Packaging device

Abstract

The invention discloses a packaging device. The packaging device comprises a first electronic component, a second electronic component, a conductive component, a packaging layer and a circuit structure, the packaging layer surrounds the first electronic component, the second electronic component and the conductive component, the circuit structure is arranged on the packaging layer, and the first connecting pad of the first electronic component is electrically connected with the second connecting pad of the second electronic component through the circuit structure and the conductive component. A first gap is arranged between the surface of the first electronic component and the first surface of the packaging layer, and a second gap is arranged between the surface of the second electronic component and the second surface of the first packaging layer.

Description

Technical Field

[0001] The present invention relates to a packaging device, and particularly to a packaging device including a conductive via structure penetrating through a packaging layer. Background Art

[0002] With the progress of semiconductor packaging technology, it has been developed to package multiple chips in the same package. In the existing packaging structure, the chips need to be sealed by packaging materials to protect the chips. However, as the thickness of the packaging materials increases, it is not easy to form through-holes in the packaging materials. For example, the quality of the formed through-holes is poor, resulting in poor quality of the conductive layer formed in the through-holes or easy generation of voids in the conductive layer, causing a low product yield. Summary of the Invention

[0003] An object of the present invention is to provide a packaging device to form a conductive element in a packaging layer and improve the product yield.

[0004] The present invention provides a packaging device, which includes a first electronic component, a second electronic component, a conductive component, a first packaging layer, and a first circuit structure. The first electronic component and the second electronic component are arranged side by side, and the conductive component is arranged on one side of the first electronic component. The first packaging layer surrounds the first electronic component, the second electronic component, and the conductive component. The first packaging layer has a first surface and a second surface opposite to the first surface. The first electronic component includes a first pad adjacent to the first surface, and the second electronic component includes a second pad adjacent to the second surface. The first circuit structure is arranged on the first packaging layer, and the first pad of the first electronic component is electrically connected to the conductive component through the first circuit structure and the second pad of the second electronic component. There is a first gap between the surface of the first electronic component and the first surface of the first packaging layer, and there is a second gap between the surface of the second electronic component and the second surface of the first packaging layer.

[0005] In the packaging device of the present invention, the pad and the conductive component can form a conductive via structure penetrating through the packaging layer. Therefore, it is not necessary to form through-holes with a high aspect ratio in the packaging layer, thereby avoiding problems such as bubbles or low product yield caused by poor quality of the through-holes, and the problem of time-consuming caused by multiple drilling, and improving the yield of the packaging device. Moreover, through the first gap and the second gap, the possibility of disconnection of the traces formed on the surface of the electronic component and the first surface of the packaging layer can be reduced. Brief Description of the Drawings

[0006] Figures 1 to 6 Shown is a cross-sectional structural schematic diagram of the manufacturing method of the packaging device according to the first embodiment of the present invention at different steps.

[0007] Figure 7The figure shows a cross-sectional schematic view of a packaging device according to a first variant embodiment of the first embodiment of the present invention.

[0008] Figure 8 The figure shows a cross-sectional schematic view of a packaging device according to a second variant embodiment of the first embodiment of the present invention.

[0009] Figure 9 The figure shows a cross-sectional schematic view of a packaging device according to a third variant embodiment of the first embodiment of the present invention.

[0010] Figure 10 The figure shows a cross-sectional schematic view of a packaging device according to a fourth variant embodiment of the first embodiment of the present invention.

[0011] Figures 11 to 13 The figure shows a cross-sectional structural schematic view of a method for manufacturing a packaging device according to the second embodiment of the present invention at different steps.

[0012] Explanation of reference numerals: 1, 1a, 1b, 1c, 1d, 2 - packaging device; 12, 36, 62, 64 - carrier plate; 14 - conductive element; 14b - conductive layer; 16, 16a, 16b, 16c, 44, 52, 58 - electronic component; 18, 16p, 54, 14a - encapsulation layer; 18R, TR - groove; 20, 30 - circuit structure; 22 - seed layer; 24, 38, 66, 68 - release layer; 26, 40, 70 - anti-warpage layer; 28 - mask pattern; 32 - semi-finished structure; 34 - conductive block; 46, 60 - bonding pad; 48 - underfill layer; 50 - heat sink; 56 - circuit element; 72 - pressing plate; BL1, BL2, BL3, 14c - buffer layer; BL1, BL2, BL3, 14c - buffer layer; C - conductive member; G1 - first interval; G2 - second interval; H - height; IN1, IN2 - insulating layer; L1, L2 - length; M - main body; ND - normal direction; OP1, OP2, OP3, OP4 - opening; P, CP1, P1, P21, P22, P31, P32, CP2, CP3, CP4, CP5 - pad; PL, PL1, PL2, PL3, PL4 - protective layer; R1, R2, R3 - depression; S1 - first surface; S2 - second surface; S3, S4, S5, 18S - surface; S6 - corner; SC - semiconductor chip; T1 - first trace; T2 - second trace; T3 - third trace; TH - thickness; VD - top view direction; W1, W2, W3, W4, W5 - width. Detailed description of the invention

[0013] The content of the present invention will be described in detail below in conjunction with specific embodiments and the accompanying drawings. In order to make the content of the present invention clearer and easier to understand, the drawings of the present invention may be schematic diagrams that are simplified, and the elements therein may not be drawn to scale. Moreover, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present invention.

[0014] Throughout the specification of the present invention and the appended claims, certain terms will be used to refer to specific elements. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same element, and the present invention does not intend to distinguish elements that have the same function but different names. In the specification and claims of the present invention, words such as "comprising" and "including" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0015] The ordinal numbers used in the specification and claims of the present invention, such as "first", "second", etc., are used to modify the elements of the claims. They do not inherently imply or represent that the claimed elements have any previous ordinal numbers, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of the ordinal numbers is only to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0016] In addition, when an element or a film layer is referred to as being connected to another element or another film layer, it should be understood that the element or the film layer is directly physically or electrically connected to the other element or the other film layer, or they can also be physically or electrically connected (indirectly) through other elements or film layers. Conversely, when an element or a film layer is referred to as "directly connected to" another element or another film layer, it should be understood that there is no physical or electrical connection between them through other elements or film layers. The term "connected" can include means of "direct contact" or "non-direct contact". In addition, the terms "electrically connected" or "coupled" include any direct and indirect means of electrical connection.

[0017] In the present invention, when an element is referred to as being "disposed on" another element, there is no limitation on the manufacturing process steps or order of forming the element and the other element.

[0018] In the present invention, terms such as "about", "substantially", "approximately" or "the same" generally represent a range within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. The given quantity is an approximate quantity, that is, even without specifically stating "about", "substantially", "approximately" or "the same", the meaning of "about", "substantially", "approximately" or "the same" can still be implied.

[0019] The term "between numerical value A and numerical value B" is interpreted to include the situation where numerical value A and numerical value B are included or at least one of numerical value A and numerical value B is included, and other numerical values between numerical value A and numerical value B.

[0020] In the present invention, the measurement methods of depth, thickness, length, width and pore diameter can be obtained by using an optical microscope (OM), an electron microscope (such as a scanning electron microscope (SEM)) or other methods, but are not limited thereto.

[0021] In the present invention, the definition of roughness judgment can be observed by SEM. On the uneven surface, the distance difference between the peaks and valleys of the surface undulation can be seen to be 0.15 micrometers (μm) to 1 μm. The measurement of roughness judgment can include using SEM, transmission electron microscope (TEM), etc. to observe the surface undulation condition at an appropriate same magnification, and the roughness range is obtained by comparing the undulation conditions of samples of a unit length (such as 10 μm). Here, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks of roughness (Rz) or average roughness (Ra) in the field of view at this magnification.

[0022] It should be understood that in the following examples, without departing from the spirit of the present invention, the features in multiple different examples can be replaced, recombined and mixed to complete other examples. As long as the features between the examples do not violate the spirit of the invention or conflict with each other, they can be arbitrarily mixed and used.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. It can be understood that these terms, for example, define the terms in a commonly used dictionary, and should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0024] The encapsulation device of the present invention can be applicable to any kind of electronic device. The electronic device can, for example, include a display device, a light-emitting device, a sensing device, an antenna device, a touch device, a splicing device, an encapsulation device, or other suitable electronic devices, but is not limited thereto. The electronic device can, for example, be a bendable, stretchable, foldable, rollable, and / or flexible electronic device, but is not limited thereto. The display device can, for example, be applied to a laptop computer, a public display, a splicing display, a vehicle display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, a military device, or an electronic device applied to the above products, but is not limited thereto. The sensing device can, for example, be a sensing device for detecting capacitance change, light, heat energy, or ultrasonic waves, but is not limited thereto. The sensing device can, for example, include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors, or a combination of the above types of sensors. The display device can, for example, include liquid crystal molecules, light-emitting diodes, fluorescent materials, phosphor materials, other suitable display media, or a combination of the foregoing, but is not limited thereto. The light-emitting diode can, for example, include an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot, QD, which can be, for example, QLED, QDLED), or other suitable materials, or any permutation and combination of the above materials, but is not limited thereto. The antenna device can, for example, be a liquid crystal antenna, a varactor diode antenna, or other types of antenna types, but is not limited thereto. The splicing device can, for example, include a splicing display device or a splicing antenna device, but is not limited thereto. In addition, the shape of the electronic device can, for example, be rectangular, circular, polygonal, a shape with curved edges, curved, or other suitable shapes. The electronic device can have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. The electronic device can include an electronic unit, where the electronic unit can include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. It should be noted that the electronic device of the present invention can be various combinations of the above devices, but is not limited thereto.The manufacturing method of the encapsulation device in the present invention can be applied, for example, in a wafer-level package (WLP) process or a panel-level package (PLP) process. The wafer-level package or panel-level package process may include a chip-first process or a chip-last process, but is not limited thereto. The encapsulation device of the present invention can be applied, for example, to a power module, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The encapsulation device may include a system-on-a-chip (SoC), a system-in-a-package (SiP), an antenna-in-package (AiP), or various combinations of the above devices, but is not limited thereto.

[0025] Figures 1 to 6 Shown is a schematic cross-sectional structure diagram at different steps of the manufacturing method of the encapsulation device according to the first embodiment of the present invention, where Figure 6 Shown is a schematic cross-sectional view of the encapsulation device according to the first embodiment of the present invention. The manufacturing method of the encapsulation device of the present invention may include the following steps, and the manufacturing method of the present invention is not limited to the following steps, and other steps may also be performed before, after, or during any of the shown steps. As Figures 1 to 6 Shown, the manufacturing method of the encapsulation device 1 of this embodiment may include forming at least one conductive element 14 on a carrier plate 12 and arranging a plurality of electronic elements 16 side by side on the carrier plate 12, forming an encapsulation layer 18 surrounding the electronic elements 16 and the conductive element 14, removing the carrier plate 12, and forming a circuit structure 20 on the encapsulation layer 18. The encapsulation layer 18 may have a first surface S1 and a second surface S2 opposite to the first surface S1. One of the electronic elements 16 (for example, the electronic element 16a in the present invention) may have a pad P adjacent to the first surface S1, and the other (for example, the electronic element 16b hereinafter) may have another pad P adjacent to the second surface S2, and the pad P may be electrically connected to the other pad P through the circuit structure 20 and the conductive element 14. By forming the conductive element 14 before forming the encapsulation layer 18, it is helpful to form a conductive via structure penetrating the encapsulation layer 18, so that the pad P of the electronic element 16 adjacent to the first surface S1 can be electrically connected to the other pad P of another electronic element 16 adjacent to the second surface S2, thereby improving the quality of the encapsulation device 1.

[0026] The present invention will be further combined with Figures 1 to 6 to detail the manufacturing method of the encapsulation device 1 of this embodiment. As Figure 1As shown, first, a carrier substrate 12 is provided. Then, a seed layer 22 is formed on the carrier substrate 12, and a plurality of pads CP1 and at least one conductive element 14 are formed on the seed layer 22. The seed layer 22 can help form the pads CP1 and the conductive element 14 on the carrier substrate 12. The carrier substrate 12 can include, for example, a steel plate, a transparent glass substrate, a silicon substrate, or other suitable substrates. The carrier substrate 12 can be used to carry a film layer, and the thickness of the carrier substrate 12 can be between 0.1 millimeter (mm) and 30 mm. According to some embodiments, the area of the carrier substrate 12 can be, for example, 310 mm * 310 mm, or 510 mm * 515 mm, or 700 mm * 700 mm, but is not limited thereto. The seed layer 22 can include, for example, copper, nickel, gold, titanium, tantalum, titanium nitride, other suitable materials, or a combination of the above. The method of forming the seed layer 22 can include, for example, a deposition process, an atomic layer deposition process, or other suitable processes.

[0027] In Figure 1 the embodiments, before forming the seed layer 22, a release layer 24 can be formed on the carrier substrate 12 to help separate the subsequently formed encapsulation layer 18, electronic component 16, and conductive element 14 from the carrier substrate 12. The dissociation method of the release layer 24 can include photo-dissociation, thermal dissociation, other suitable methods, or a combination of any two of the above. For example, depending on the dissociation method, the release layer 24 can be paired with different types of carrier substrates 12. For example, a photo-dissociation type release layer 24 can be paired with a transparent glass substrate, while a thermal dissociation type release layer 24 can be paired with a steel plate. The release layer 24 can include, for example, an ultraviolet (UV) release film, a heat release tape (HRT), other suitable materials, or a combination of any two of the above.

[0028] In some embodiments, before forming the release layer 24, a warpage-resistant layer 26 can be selectively formed on the carrier substrate 12 to reduce the warpage generated in subsequent processes, thereby improving the process yield. The setting of the warpage-resistant layer 26 can be determined according to the stress change requirements thereon or the density of the conductive layer formed thereon later (for example, the conductive layer density of the circuit structure 30 hereinafter), but is not limited thereto. The warpage-resistant layer 26 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), or other suitable materials. Further, along the normal direction ND of the carrier substrate 12, the warpage trend of the warpage-resistant layer 26 is opposite to that of the subsequently formed circuit structure 30. Therefore, the warpage generated in subsequent processes can be reduced. For example, the two sides of the warpage-resistant layer 26 bend downward, and the two sides of the circuit structure 30 bend upward, so they can cancel each other out and maintain the flatness of the overall structure.

[0029] In Figure 1In the embodiments, the pad CP1 can be formed before the conductive element 14 is formed, but is not limited thereto. The pad CP1 can be formed, for example, by forming a conductive layer on the seed layer 22 and then patterning the conductive layer to form the pad CP1, or a mask pattern can also be used, where the mask pattern exposes the seed layer 22, and then the pad CP1 is formed on the exposed seed layer 22. The pad CP1 can be used to bond with the subsequently provided electronic component 16. After the pad CP1 is formed, a mask pattern 28 can be formed on the pad CP1 and the seed layer 22, where the mask pattern 28 has an opening OP1 that exposes the seed layer 22. Then, the conductive element 14 is formed on the seed layer 22 exposed by the opening OP1. The methods of forming the conductive layer, the pad CP1, and the conductive element 14 can include, for example, evaporation, sputtering, electroplating, electroless plating, deposition, or other suitable processes. The conductive layer and the conductive element 14 can include, for example, copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), nitrides, carbides, or other suitable conductive materials or any combination of the above, but is not limited thereto. The mask pattern 28 can include, for example, a photoresist material or other suitable mask materials. The photoresist material can include, for example, a dry film photoresist or other suitable types of photoresists. The method of forming the mask pattern 28 can include, for example, exposure and development processes or other suitable processes. According to some embodiments, the seed layer 22 can be omitted, and a conductive thin film can be directly formed on the release layer 24, such as attaching a copper foil or a lead frame.

[0030] As Figure 2 shown, after the conductive element 14 is formed, the mask pattern 28 can be removed. Then, a plurality of electronic components 16 are disposed on the pad CP1 and the seed layer 22. The step of disposing the electronic components 16 can include, for example, a die bonding process, a pick-and-place process, a flipped chip process, or other suitable processes. Each electronic component 16 can at least include a semiconductor chip SC, where the semiconductor chip SC can include a body M and a plurality of pads P, and the pads P are disposed on the body M. The body M can include, for example, an integrated circuit. The pads P can be, for example, signal output / input pads of the semiconductor chip SC. In Figure 2In an embodiment, at least one electronic component 16 may include a packaging layer 16p that surrounds a semiconductor chip SC to protect the semiconductor chip SC. In other words, the semiconductor chip SC of the electronic component 16 may be protected by the packaging layer 16p before being disposed on the seed layer 22, so as to reduce the possibility of damage. In some embodiments, the electronic component 16 may not include the packaging layer 16p either. The semiconductor chip SC described in the present invention is a substance or material with conductivity between that of an insulator and a conductor. The material of the semiconductor chip SC may include silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, zinc oxide, aluminum nitride, silicon carbide, etc.

[0031] In Figure 2 an embodiment, the electronic component 16 may include an electronic component 16a and an electronic component 16b, which are arranged side by side with each other, but are not limited thereto. In one embodiment, the pads P of the electronic component 16a may include a plurality of pads P1 located on the surface of the main body M adjacent to the carrier plate 12, but are not limited thereto. In addition to including the semiconductor chip SC and the packaging layer 16p, the electronic component 16a may further include a buffer layer BL1 and a plurality of conductive members C. The buffer layer BL1 may be disposed on the semiconductor chip SC, and the buffer layer BL1 may have a plurality of openings OP2 corresponding to the pads P1 respectively. The conductive members C may be disposed in the openings OP2 and electrically connected to the corresponding pads P1. In this case, the formed packaging layer 16p may further surround the buffer layer BL1. When the electronic component 16a is disposed on the carrier plate 12, the conductive members C of the electronic component 16a may be in direct contact with the seed layer 22, but are not limited thereto. In some embodiments, the thickness TH of the electronic component 16 may be greater than or equal to the height H of the conductive component 14 to reduce damage to the conductive component 14 in subsequent processes, but are not limited thereto. The thickness of the component referred to in the present invention may be measured, for example, along the normal direction of the carrier plate 12. According to some embodiments, the material of the packaging layer 16p may include an organic or inorganic insulating material. The organic insulating material includes epoxy resin, polymer, or other suitable materials. The inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium dioxide, or other suitable materials. Further, along a direction of the normal direction ND perpendicular to the carrier plate 12, the width W5 of the packaging layer 16p on the sidewall of the semiconductor chip SC is greater than or equal to 0.1 μm and less than or equal to 5 μm. According to some embodiments, the thermal expansion coefficient of the packaging layer 16p may be greater than or equal to 0.1 ppm / °C and less than or equal to 10 ppm / °C, or the thermal expansion coefficient of the packaging layer 16p may be greater than or equal to 0.5 ppm / °C and less than or equal to 8 ppm / °C. According to some embodiments, the intrinsic stress of the packaging layer 16p may be greater than -1000 megapascals (MPa) and less than or equal to +800 MPa. When the packaging layer 16p has the foregoing specific intrinsic stress, it can compensate for the mechanical properties of the electronic component 16a, improve the stress balance, and thus improve the electronic device (such asFigure 6 The reliability of the electronic device 1) shown. Furthermore, according to some embodiments, spectroscopic reflectometry can be used to measure the thickness and refractive index of the encapsulation layer 16p, and the intrinsic stress of the encapsulation layer 16p can be judged by the difference in refractive index.

[0032] For example, before the semiconductor chip SC is disposed on the carrier 12, a buffer layer BL1 can be bonded to the semiconductor chip SC to reduce the risk of the semiconductor chip SC being chipped or cracked. And, a conductive member C can be formed in the opening OP2 of the buffer layer BL1 to serve as a pad for the electronic component 16a. The conductive member C can include, for example, a material similar to or the same as the conductive element 14, so reference can be made to the above. In some embodiments, the conductive member C may further include a seed layer, but is not limited thereto. In some embodiments, before forming the conductive member C, a cleaning process is performed on the pad P1, so that the surface of the pad P1 facing the conductive member C may have a recess R1. And, the conductive member C can be formed in the recess R1, so that the impedance between the conductive member C and the pad P1 can be reduced to improve the electrical conduction efficiency. The depth of the recess R1 can be, for example, between 0.03 μm and 5 μm, or between 0.05 μm and 3 μm. In the present embodiment, the cleaning process can include wet etching, dry etching, plasma treatment, laser treatment, or other suitable cleaning processes.

[0033] In addition, the pads P of the electronic component 16b can include at least one pad P21 and at least one pad P22, which are respectively disposed on the surface of the main body M away from the carrier 12 and the surface of the main body M adjacent to the carrier 12. In Figure 2 the embodiment, the encapsulation layer 16p may not cover the pad P22, so that the pad P22 can be exposed, and the encapsulation layer 16p can cover the pad P21 to protect the pad P21. When the electronic component 16b is disposed on the carrier 12, the pad P22 can be joined to one of the pads CP1. The number of the pads P21 can be, for example, a plurality, but is not limited thereto. In some embodiments, the electronic component 16b may also selectively include a buffer layer, such as Figure 8 the buffer layer BL2 shown.

[0034] In some embodiments, the electronic component 16 may further include an electronic component 16c, which is disposed side by side with the electronic component 16a. The pads P of the electronic component 16c may also selectively include at least one pad P31 and at least one pad P32, which are respectively disposed on the surface of the main body M away from the carrier 12 and the surface of the main body M adjacent to the carrier 12, but is not limited thereto. In Figure 2Among them, the pads P32 can be, for example, multiple, and when the electronic component 16c is disposed on the carrier 12, the pads P32 can be respectively joined to a plurality of pads CP1, but not limited thereto. In some embodiments, the electronic component 16c may also selectively include a buffer layer, such as Figure 8 the buffer layer BL3 shown. According to some embodiments, the coefficient of thermal expansion of the encapsulation layer 16p can be less than that of the buffer layer (e.g., buffer layer BL1, buffer layer BL2, and / or buffer layer BL3), so that the buffer layer can be more buffering, thereby protecting the circuit of the electronic component 16 from being damaged during the manufacturing process, but not limited thereto.

[0035] As Figure 3 shown, after the step of disposing the electronic component 16, the encapsulation layer 18 can be formed on the electronic component 16, the conductive component 14, and the seed layer 22. Specifically, the encapsulation layer 18 can be formed, for example, by a molding process or other suitable means to form and cover the encapsulation material on the electronic component 16, the conductive component 14, and the seed layer 22, and then a part of the encapsulation material can be removed by a grinding process, a sandblasting process, a plasma surface treatment process, a chemical mechanical polishing (CMP) process, an etching process, or other suitable processes to expose the encapsulation layer 16p of the electronic component 16. The encapsulation layer 18 can include, for example, a molding compound or other suitable encapsulation material. The molding compound can include, for example, an epoxy resin or other suitable materials. According to some embodiments, the coefficient of thermal expansion of the encapsulation layer 16p can be less than or equal to that of the encapsulation layer 18, thereby reducing the risk of interface cracking. Alternatively, according to some embodiments, before forming the encapsulation layer 18, a surface roughening step can be performed on the electronic component 16 or the encapsulation layer 16p to improve the bonding ability with the subsequent film layer, but not limited thereto.

[0036] In Figure 3In an embodiment, the step of forming the encapsulation layer 18 may not expose the conductive element 14. In other words, the step of removing a portion of the encapsulation material does not completely remove the encapsulation material on the conductive element 14. In this case, after forming the encapsulation layer 18, a patterning process may be performed to form an opening OP3 in the encapsulation layer 18 on the conductive element 14, and an opening OP4 in the encapsulation layer 16p of the electronic components 16b and 16c to expose the conductive element 14 and the pads P21 of the electronic component 16b and the pads P31 of the electronic component 16c. Then, a circuit structure 30 is formed on the encapsulation layer 18 to form a semi-finished structure 32. The patterning process may include, for example, a laser process, a plasma process, a lithography process, an etching process, or other suitable processes. In this embodiment, a portion of the encapsulation layer 16p of the electronic component 16b and / or the electronic component 16c may be disposed between the circuit structure 30 and the corresponding semiconductor chip SC. According to some embodiments, one of the electronic components 16 of the electronic device is a high side switch element, another one of the electronic components 16 is a low side switch element, and yet another one of the electronic components 16 is a power management chip, but not limited thereto.

[0037] The circuit structure 30 may be a redistribution structure including at least one conductive layer and at least one insulating layer. In Figure 3 an embodiment, the circuit structure 30 may include one conductive layer and one insulating layer IN1, but not limited thereto. The conductive layer of the circuit structure 30 may include a plurality of pads CP2 exposed from the surface of the circuit structure 30 away from the encapsulation layer 18.

[0038] In some embodiments, after forming the circuit structure 30, a conductive block 34 may be selectively formed on the surface of each pad CP2 away from the encapsulation layer 18 to protect the pad CP2 from oxygen or moisture before bonding with other components. The method of forming the conductive block 34 may include, for example, electroplating, electroless plating, or other suitable methods. The conductive block 34 may include gold, tin, silver, copper, nickel, gold, other suitable metal materials, or a combination of the above.

[0039] In some embodiments, the step of forming the encapsulation layer 18 may also expose at least one of the pads P21 of the electronic component 16b, the pads P31 of the electronic component 16c, and the conductive component 14. When the pads P21 of the electronic component 16b, the pads P31 of the electronic component 16c, and the conductive component 14 are all exposed, a patterning process may not be required, and the circuit structure 30 may be directly formed on the exposed pads P21, pads P31, and conductive component 14. In some embodiments, when the electronic component 16 may not include the encapsulation layer 16p, the step of removing part of the encapsulation material may be performed until the pads P21 of the electronic component 16b, the pads P31 of the electronic component 16c, and the conductive component 14 are exposed and then stopped.

[0040] As Figure 4 shown, after the circuit structure 30 is formed, the semi-finished structure 32 may be turned upside down and transferred to another carrier 36 to expose the seed layer 22. For example, before the semi-finished structure 32 is turned over, the carrier 36 may be attached to the circuit structure 30, and then the carrier 36, the semi-finished structure 32, and the carrier 12 are turned upside down. Then, by dissociating the release layer 24, the carrier 12, the release layer 24, and the anti-warpage layer 26 may be removed. After the carrier 12 and the release layer 24 are removed, the exposed seed layer 22 may be further removed to expose the pad CP1, the conductive component 14, the conductive member C of the electronic component 16a, and the first surface S1 of the encapsulation layer 18.

[0041] In some embodiments, between the step of removing the mask pattern 28 and the step of disposing the electronic component 16, an etching process may be selectively performed to remove the exposed portion of the seed layer 22 and leave the portion of the seed layer 22 overlapping with the pad CP1 and the conductive component 14. In this case, after the carrier 12 and the release layer 24 are removed, the exposed seed layer 22 may be selectively not removed, but not limited thereto.

[0042] In Figure 4In an embodiment, before attaching the carrier 36 to the circuit structure 30, a release layer 38 may be formed on the carrier 36 to facilitate separation from the subsequently formed packaging device 1. The dissociation method of the release layer 38 may include photo-dissociation, thermal dissociation, other suitable methods, or a combination of any two of the above. The release layer 38 may include, for example, an ultraviolet (UV) release film, a heat release tape (HRT), other suitable materials, or a combination of any two of the above. The dissociation method of the release layer 38 may be the same as or different from that of the release layer 24. In some embodiments, before forming the release layer 38, a warpage-resistant layer 40 may be selectively formed on the carrier 36 to reduce warpage generated in subsequent processes, thereby improving the process yield. The material of the warpage-resistant layer 40 may be similar to or the same as that of the warpage-resistant layer 26, so reference may be made to the above and will not be elaborated here. The setting of the warpage-resistant layer 40 may be determined according to the stress change thereon or the density of the conductive layer formed thereon subsequently (for example, the conductive layer density of the circuit structure 30 and the conductive layer density of the subsequently formed circuit structure 20), but is not limited thereto.

[0043] As Figure 5 shown, next, the circuit structure 20 may be formed on the first surface S1 of the encapsulation layer 18. The circuit structure 20 may be a redistribution structure including at least one conductive layer and at least one insulating layer. In Figure 5 this case, the insulating layer of the circuit structure 20 is schematically shown as a single insulating layer IN2, and the insulating layer IN2 may include a single layer or multiple layers of insulating layers. The circuit structure 20 may include multiple traces, and each trace may be formed by at least one conductive layer according to sequential requirements, but is not limited thereto.

[0044] The materials of the conductive layers of the circuit structure 30 and the circuit structure 20 may refer to the materials of the conductive layer used to form the pad CP1 above and will not be elaborated here. The insulating layer IN1 and the insulating layer IN2 may each include a molding compound, an Ajinomoto Build-up Film (ABF) material, a photosensitive polyimide (PSPI), or other suitable insulating materials. In some embodiments, by adjusting the coefficient of thermal expansion of the insulating layer IN1 (or the insulating layer IN2) and the coefficient of thermal expansion of the encapsulation layer 18, the warpage of the overall structure may be reduced or the stress difference may be alleviated. For example, during the manufacturing process, the warpage may be less than or equal to 3 mm, or less than or equal to 2 mm. In some embodiments, the insulating layer IN1 (or the insulating layer IN2) and the encapsulation layer 18 may include the same material, for example. The insulating layer IN1 and the insulating layer IN2 may include the same or different materials, for example.

[0045] As Figure 6As shown, after forming the circuit structure 20, the carrier plate 36 can be removed, thereby forming the packaging device 1 of this embodiment. It should be noted that through the above manufacturing method, the conductive element 14 can be formed before forming the packaging layer 18, and by matching the step of forming the circuit structure 30, the pad CP2 of the circuit structure 30 and the conductive element 14 can form a conductive via structure penetrating the packaging layer 18. Therefore, the probability of forming vias with a high aspect ratio in the packaging layer 18 can be reduced, thereby avoiding problems such as bubbles or low product yield caused by poor via quality, as well as the time-consuming problem caused by multiple drilling, and improving the yield of the packaging device 1. The height of the conductive element 14 can be, for example, greater than 180 microns.

[0046] As Figure 6 shown, the packaging device 1 can include electronic components 16a, electronic components 16b, at least one conductive element 14, a packaging layer 18, and a circuit structure 20. The electronic components 16a and 16b can be arranged side by side, and the conductive element 14 is disposed on one side of the electronic component 16a. The packaging layer 18 can surround the electronic components 16a, 16b, and the conductive element 14, wherein the packaging layer 18 can have a first surface S1 and a second surface S2 opposite to the first surface S1. The electronic component 16a can have a pad P1 adjacent to the first surface S1, the electronic component 16b can have a pad P21 adjacent to the second surface S2, and the pad P1 can be electrically connected to the pad P21 of the circuit structure 20 via the conductive element 14, so that the packaging device 1 can have an electrical connection effect penetrating the packaging layer 18.

[0047] In Figure 6 this embodiment, the circuit structure 20 can include a first trace T1, and a pad P1 of the electronic component 16a can be electrically connected to the pad P21 of the electronic component 16b via the first trace T1 and the conductive element 14. The packaging device 1 can further include a circuit structure 30 disposed on the second surface S2 of the packaging layer 18, and the pad P21 of the electronic component 16b adjacent to the second surface S2 of the packaging layer 18 can be electrically connected to the conductive element 14 via the circuit structure 30, and thus can be further electrically connected to the pad P1 of the electronic component 16a adjacent to the first surface S1 of the packaging layer 18. For example, one of the pads CP2 can extend into the openings OP3 and the corresponding opening OP4 of the packaging layer 18 to be electrically connected to the conductive element 14 and the corresponding pad P21. In other words, the pad CP2 can serve as a trace to electrically connect the pad P21 of the electronic component 16b to the conductive element 14. The other pads CP2 can extend into the corresponding openings OP4 to be electrically connected to the corresponding other pads P21 or pads P31. For example, in a cross-sectional schematic diagram, the total length of the path from the pad P1 of the electronic component 16a via the first trace T1, the conductive element 14, and the pad CP2 to the pad P21 of the electronic component 16b can be the length L1.

[0048] In addition, the pad P22 of the electronic component 16b adjacent to the first surface S1 of the encapsulation layer 18 can be electrically connected to the pad P32 of the electronic component 16c adjacent to the first surface S1 of the encapsulation layer 18. In Figure 6 the embodiment, the circuit structure 20 may further include a second trace T2, and the pad P22 of the electronic component 16b can be electrically connected to the pad P32 of the electronic component 16c through the second trace T2. In some embodiments, the circuit structure 20 may further include a third trace T3, and the electronic component 16a may further include another pad P1, adjacent to the first surface S1 of the encapsulation layer 18, wherein the pad P1 is electrically connected to another pad P32 of the electronic component 16c via the third trace T3. For example, in a cross-sectional schematic diagram, the total length of the path from the pad P1 to the pad P32 of the electronic component 16c via the third trace T3 may be the length L2. The pad P31 of the electronic component 16c can be adjacent to the second surface S2 of the encapsulation layer 18 and electrically connected to the circuit structure 30. For example, the pad P31 can be further electrically connected to an external component through the pad CP2 of the circuit structure 30. In some embodiments, another pad P21 of the electronic component 16b can also be further electrically connected to an external component through another pad CP2 of the circuit structure 30. In the present embodiment, the length L1 is greater than the length L2. In some embodiments, the length L1 may be greater than or equal to 0.5 times the length L2 and less than or equal to 2 times the length L2 (0.5*L2 ≤ L1 ≤ 2*L2). Through the above design, signal transmission loss can be reduced, but it is not limited thereto.

[0049] In the electronic component 16a, since the conductive member C can penetrate through the buffer layer BL1 and electrically connect the semiconductor chip SC to the circuit structure 20, the pad P1 can be electrically connected to the corresponding first trace T1 or second trace T2 through the conductive member C. The circuit structures 20 and 30 of the present invention are not limited to those shown in the drawings and may have other layout structures.

[0050] In Figure 6 it, the encapsulation device 1 may further include a conductive block 34, disposed on the surface of the pad CP2 away from the encapsulation layer 18, and the width of the conductive block 34 can be the same as the exposed surface width of the corresponding pad CP2, but is not limited thereto. In some embodiments, as Figure 8 shown, the width W1 of the conductive block 34 can be greater than the width W2 of the corresponding pad CP2, so as to improve the bonding degree between the circuit structure 30 and other components (for example, a circuit board), thereby enhancing the reliability of the bonding degree. In addition, other parts of the encapsulation device 1 can be as described above, so they will not be elaborated here.

[0051] The encapsulation device and its manufacturing method of the present invention are not limited to the above embodiments, and may have different embodiments or variant embodiments. For the sake of simplicity, the same reference numerals will be used to label the same components in different embodiments or variant embodiments of the present invention as those in the first embodiment. To clearly illustrate different embodiments or variant embodiments, the present invention will describe the differences between different embodiments or variant embodiments, and will not repeat the overlapping parts.

[0052] Please refer to Figure 7 , which shows a cross-sectional schematic view of an encapsulation device according to a first variant embodiment of the first embodiment of the present invention. As Figure 7 shown, the difference between the encapsulation device 1a provided in this embodiment and Figure 6 the encapsulation device 1 shown is that the circuit structure 20 may further include a plurality of pads CP3, which are exposed from the surface of the circuit structure 20 away from the electronic component 16 for electrical connection with other components. For example, the encapsulation device 1a further includes an electronic component 44, which is disposed on the surface of the circuit structure 20 away from the encapsulation layer 18 and is bonded to some of the pads CP3, and is thus electrically connected to the circuit structure 20. The electronic component 44 can be bonded to the corresponding pad CP3 through a bonding pad 46, for example. The bonding pad 46 may include, for example, solder balls, nickel, gold, copper, gallium or other suitable conductive materials. In some embodiments, the electronic component 44 can be selectively electrically connected to at least one of the electronic components 16. Although Figure 7The connection structure between the pad CP3 and the electronic component 16 is not shown, but the pad CP3 of the present invention can be electrically connected to the electronic component 16 through traces (not shown), for example. In some embodiments, the encapsulation device 1a may further selectively include an underfill layer 48 disposed between the electronic component 44 and the circuit structure 20 to enhance the bonding degree between the electronic component 44 and the circuit structure 20. In some embodiments, the material of the underfill layer 48 may include an organic material or an inorganic material. The inorganic material may include silicon oxide, silicon nitride, silicon oxynitride, and the organic material includes epoxy resin or polymer. Alternatively, according to some embodiments, the organic material may include double bonds or triple bond functional groups to enhance reactivity or increase the bonding ability with other film layers, but not limited thereto. In some embodiments, the material of the underfill layer 48 may further include filler particles dispersed in the organic material, such as silicon dioxide, titanium dioxide, aluminum oxide, or other suitable materials, and the average particle size of the filler particles may be between 0.01 micrometers and 5 micrometers. In some embodiments, the coefficient of thermal expansion of the underfill layer 48 may be different from that of the encapsulation layer 16b. For example, the coefficient of thermal expansion of the underfill layer 48 may be greater than that of the encapsulation layer 16b, or the coefficient of thermal expansion of the underfill layer 48 may be greater than that of the encapsulation layer 16b. When the coefficient of thermal expansion of the underfill layer 48 is different from that of the encapsulation layer 16b, the thickness of the underfill layer 48 is also different from that of the encapsulation layer 16b. In some embodiments, the underfill layer 48 may be a stack of multiple film layers, and the materials between the film layers may be the same or different.

[0053] In some embodiments, the encapsulation device 1a may further selectively include a heat sink 50 disposed on the back surface of the electronic component 44 away from the bonding pad 46. The heat sink 50 may include a metal material or other suitable materials, for example. In some embodiments, the encapsulation device 1a may further include another electronic component 52 disposed on the surface of the circuit structure 20 away from the electronic component 16 and bonded to another part of the pad CP3. According to some embodiments, the encapsulation device 1a may further selectively include an encapsulation layer 54 surrounding the electronic component 44 and the electronic component 52. The encapsulation layer 54 may surround a part of the heat sink 50, but not limited thereto. The electronic component 52 may include an active component, a passive component, or other suitable components, for example. The encapsulation layer 54 may include a molding material or other suitable encapsulation materials, for example. Other parts of the encapsulation device 1a and its manufacturing method may be the same as those of Figures 1 to 6 the embodiments, so details are not described herein.

[0054] Please refer to Figure 8 , which shows a cross-sectional schematic view of an encapsulation device according to a second variant embodiment of the first embodiment of the present invention. As Figure 8 shown, the encapsulation device 1b provided in this embodiment is the same as Figure 6The difference of the encapsulation device 1 shown is that the encapsulation device 1b may further include a circuit element 56, and the conductive block 34 may be joined to the circuit element 56. The circuit element 56 may be, for example, a circuit board or other suitable element.

[0055] In Figure 8 the embodiment of, there may be a first gap G1 between the surface S3 of the electronic component 16a and the first surface S1 of the encapsulation layer 18, and there may be a second gap G2 between the surface S4 of the electronic component 16b and the second surface S2 of the encapsulation layer 18. In other words, the surface S3 of the electronic component 16a is located outside the encapsulation layer 18, and the surface S4 of the electronic component 16b is located outside the encapsulation layer 18. For example, each of the first gap G1 and the second gap G2 may be greater than 0 and less than or equal to 10 μm to reduce the possibility of disconnection of the traces formed on the surface S3 of the electronic component 16a and the first surface S1 of the encapsulation layer 18 and on the surface S4 of the electronic component 16b and the second surface S2 of the encapsulation layer 18. The difference between the first gap G1 and the second gap G2 may be, for example, greater than or equal to 0 and less than or equal to 5 μm. In the present invention, the "gap" between one surface and another surface refers to the distance between the extended planes of the said surfaces in the top view direction VD.

[0056] In some embodiments, there may be a third gap G3 between the surface S5 of the electronic component 16c and the first surface S1 of the encapsulation layer 18. The third gap G3 may be, for example, greater than or equal to 0 and less than or equal to 10 μm. And, the difference between the first gap G1 and the third gap G3 may be, for example, greater than or equal to 0 and less than or equal to 5 μm. In some embodiments, Figure 8 at least one of the first gap G1, the second gap G2 and the third gap G3 of

[0057] In Figure 8 the embodiment of, the surface S3 of the electronic component 16a may be, for example, the surface of its buffer layer BL1 away from the semiconductor chip SC. The electronic component 16b may further include a buffer layer BL2 disposed on the surface of its semiconductor chip SC adjacent to the second surface S2 of the encapsulation layer 18, and the surface of the buffer layer BL2 away from the corresponding semiconductor chip SC may be the surface S4 of the electronic component 16b. The electronic component 16c may also further include a buffer layer BL3 disposed on the surface of its semiconductor chip SC adjacent to the first surface S1 of the encapsulation layer 18, and the surface of the buffer layer BL3 away from the corresponding semiconductor chip SC may be the surface S5 of the electronic component 16c.

[0058] In Figure 8In an embodiment, the semiconductor chip SC of the electronic component 16a may further include a protective layer PL disposed between the pad P1 and the buffer layer BL1, and the protective layer PL may have an opening corresponding to the pad P1, such that the conductive member C can be electrically connected to the pad P1 through the opening. The stiffness of the buffer layer BL1 may be less than that of the protective layer PL, for example. The semiconductor chip SC of the electronic component 16b may further include a protective layer PL1 and a protective layer PL2. The protective layer PL1 may be disposed between the pad P21 and the buffer layer BL2 and have at least one opening corresponding to the pad P21, while the protective layer PL2 may be disposed on the pad P22 and have at least one opening corresponding to the pad P22. The stiffness of the buffer layer BL2 may be less than that of the protective layer PL1 and the protective layer PL2, for example. The semiconductor chip SC of the electronic component 16c may also further include a protective layer PL3 and a protective layer PL4. The protective layer PL3 may be disposed between the pad P31 and the buffer layer BL3 and have at least one opening corresponding to the pad P31, while the protective layer PL4 may be disposed on the pad P32 and have at least one opening corresponding to the pad P32. The stiffness of the buffer layer BL3 may be less than that of the protective layer PL3 and the protective layer PL4, for example. According to some embodiments, a corner S6 of the main body M of at least one semiconductor chip SC adjacent to the buffer layer (e.g., the buffer layer BL1) may have a curved corner, which may be formed, for example, by a process of cutting the semiconductor chip SC, but is not limited thereto. The cutting process may include, for example, dicing saw cutting or laser cutting. In some embodiments, the protective layer PL, the protective layer PL1, the protective layer PL2, the protective layer PL3, and the protective layer PL4 may each have at least one opening exposing the main body M of the corresponding semiconductor chip SC, but is not limited thereto.

[0059] In Figure 8 the embodiment, the electronic component 16 may not include the encapsulation layer 16p, but is not limited thereto. In some embodiments, the electronic component 16 of the encapsulation device 1b may also selectively include Figure 6 the encapsulation layer 16p as shown.

[0060] In some embodiments, the width W1 of at least one of the conductive blocks 34 may be greater than the width W2 of the pad CP2 to improve the bonding degree between the circuit structure 30 and the circuit element 56, thereby enhancing the reliability of the bonding. In some embodiments, the sidewall of one of the pads CP2 may not be covered by the insulating layer IN1 of the circuit structure 30, such that the conductive block 34 corresponding to one of the pads CP2 can extend onto the sidewall of the pad CP2, thereby enhancing the bonding degree between the circuit structure 30 and the circuit element 56, as Figure 8As shown in the enlarged view of the sidewall portion of the corresponding circuit structure 30. According to some embodiments, the surface 18S of the encapsulation layer 18 facing the contact pad CP2 adjacent to the edge of the sidewall may have a groove 18R, and the contact pad CP2 and the conductive block 34 may extend into the groove 18R, so that the contact area between the contact pad CP2 and the conductive block 34 is increased, thereby improving the bonding degree between the circuit structure 30 and the circuit element 56. According to some embodiments, the surface of the contact pad CP2 facing the conductive block 34 may selectively have at least one groove TR, so that the conductive block 34 can extend into the groove TR, thereby improving the bonding force between the conductive block 34 and the contact pad CP2. In some embodiments, each conductive block 34 may extend to contact the sidewall of the corresponding contact pad CP2 and be located between the contact pad CP2 and the insulating layer IN1. In this case, after forming the conductive layer IN1, the part of the insulating layer IN1 in contact with the contact pad CP2 may be removed first, and then formed on the sidewall of the contact pad CP2 through an electroplating process, thereby improving the bonding force between the conductive block 34 and the contact pad CP2 and the circuit element 56.

[0061] In some embodiments, Figure 8 The relationship between the width W1 of the conductive block 34 and the width W2 of the contact pad CP2 may also be applicable to any of the above or below embodiments. Other parts of the encapsulation device 1b and its manufacturing method may be the same as Figures 1 to 6 the embodiments, so they will not be elaborated here.

[0062] Please refer to Figure 9 , which shows a cross-sectional schematic diagram of an encapsulation device according to a third variant embodiment of the first embodiment of the present invention. As Figure 9 shown, the difference between the encapsulation device 1c provided in this embodiment and Figure 8 the encapsulation device 1b shown is that the encapsulation device 1b may further include another electronic component 58 disposed on the surface of the circuit structure 30 away from the electronic component 16. The electronic component 58 may be bonded to a part of the contact pad CP2 of the circuit structure 30 through a bonding pad 60. The electronic component 58 may include, for example, an active component, a passive component, or other suitable components. The bonding pad 60 may be the same or similar to the above-mentioned bonding pad 46, so it will not be elaborated here. Other parts of the encapsulation device 1c and its manufacturing method may be the same as Figures 1 to 6 the embodiments, so they will not be elaborated here.

[0063] Please refer to Figure 10 , which shows a cross-sectional schematic diagram of an encapsulation device according to a fourth variant embodiment of the first embodiment of the present invention. As Figure 10 shown, the difference between the encapsulation device 1d provided in this embodiment and Figure 9The difference of the packaged device 1c shown is that the conductive element 14 may include a packaging layer 14a, a conductive layer 14b and a buffer layer 14c, wherein the packaging layer 14a may surround the conductive layer 14b, and the conductive layer 14b surrounds the buffer layer 14c. In other words, the conductive element 14 may be, for example, a packaged conductive element, and the conductive element 14 may be, for example, disposed on the seed layer (e.g., Figure 1 The seed layer 22 shown in FIG. Figure 1 The steps of forming the conductive element 14 and the steps of forming the mask pattern 28 are shown, thereby shortening the production time. It is worth noting that the hardness of the buffer layer 14c may be less than the hardness of the packaging layer 14a, so that the buffer layer 14c can provide a buffer for the conductive layer 14b when it expands due to heat. For example, the buffer layer 14c may include plastic, organic material or other suitable materials. In the cross-sectional view of the packaging device 1d, the ratio of the width W3 of the buffer layer 14c to the width W4 of the conductive layer 14b may be, for example, greater than or equal to 0.5 and less than 1. The width W4 of the conductive layer 14b may, for example, be the distance between two parts of the interface between the conductive layer 14b and the packaging layer 14a in the cross-sectional view. In some embodiments, Figure 10 The conductive element 14 may also be applied to any of the above or below embodiments. The other parts of the packaging device 1d and its manufacturing method may be the same as Figures 1 to 6 The embodiments of the present invention are described in detail herein.

[0064] Figures 11 to 13 FIG. 1 is a schematic cross-sectional view of a method for manufacturing a packaging device according to a second embodiment of the present invention at different steps, wherein Figure 13 FIG. 2 is a cross-sectional view of a packaging device according to a second embodiment of the present invention. Figures 11 to 13 As shown, the difference between the manufacturing method of the packaging device 2 of this embodiment and the manufacturing method of the above-mentioned embodiment is that the circuit structure 20 and the semi-finished structure 32 are respectively formed on two different carriers 62 and 64, and then the pad CP4 of the circuit structure 20 is joined with the pad of the semi-finished structure 32 through a bonding process to form the packaging device 2.

[0065] Specifically, if Figure 11 As shown, a circuit structure 20 is formed on a carrier 62 , wherein the circuit structure 20 may include a plurality of traces, a plurality of pads CP4 and an insulating layer IN2 . The pads CP4 may be exposed from the upper surface of the circuit structure 20 for bonding with the semi-finished structure 32 .

[0066] In some embodiments, before forming the circuit structure 20, a release layer 66 may be selectively formed on the carrier 62. In some embodiments, before forming the release layer 66, an anti-warping layer may be selectively formed on the carrier 62, but the present invention is not limited thereto.

[0067] In some embodiments, before the step of combining the circuit structure 20 with the semi-finished structure 32, a recess R2 may be selectively formed on the upper surface of the exposed pad CP4 to help reduce the extrusion on the circuit structure 20 and the semi-finished structure 32 during the bonding with the semi-finished structure 32. The depth of the recess R2 may be, for example, less than or equal to 15 nanometers (nm). The method of forming the recess R2 may include, for example, a CMP process, an etching process, or other suitable methods.

[0068] As Figure 12 shown, a circuit structure 30 is formed on the carrier 64. Then, a conductive element 14 is formed on the circuit structure 30, and a plurality of electronic components 16 are disposed on the circuit structure 30. The circuit structure 30 may include, for example, a plurality of pads CP2, a plurality of pads CP5, and an insulating layer IN1, wherein the pads CP2 may be electrically connected to the corresponding pads CP5. The pads CP2 are adjacent to the carrier 64, and their lower surfaces are not covered by the insulating layer IN1. The upper surfaces of the pads CP5 are not covered by the insulating layer IN1, so they can be exposed from the upper surface of the circuit structure 30. In some embodiments, the circuit structure 30 may also selectively include at least one trace for electrically connecting the pads CP2 and the corresponding pads CP5. In some embodiments, before forming the circuit structure 30, a release layer 68 may be selectively formed on the carrier 64. In some embodiments, before forming the release layer 68, a warpage-resistant layer 70 may also be selectively formed on the carrier 64, but not limited thereto. The dissociation method and material of the release layer 66 and the release layer 68 may each adopt any one of the dissociation methods and materials of the above-mentioned release layer 24, and may be the same as or different from the dissociation method and material of the above-mentioned release layer 24, so it will not be elaborated here. The warpage-resistant layer of this embodiment may adopt the material of the above-mentioned warpage-resistant layer 26, so it will not be elaborated here.

[0069] The conductive element 14 may be formed on one of the pads CP5, and the electronic component 16 may be bonded to the other pads CP5. The electronic component 16 may be bonded to the corresponding pad CP5 through, for example, a bonding pad or other suitable means. In Figure 12 the embodiments, the conductive element 14 may be directly formed on the corresponding pad CP5 through, for example, evaporation, sputtering, electroplating, electroless plating, deposition, or other suitable processes, but not limited thereto. In some embodiments, the conductive element 14 may also adopt Figure 10 the conductive element 14. In this case, the conductive element 14 may be first formed as a single independent element, and then the conductive element 14 is bonded to the pad CP5.

[0070] After the steps of forming the conductive element 14 and disposing the electronic element 16, an encapsulation layer 18 can be formed on the circuit structure 30, where the encapsulation layer 18 surrounds the electronic element 16 and the conductive element 14. At this time, the electronic element 16a and the conductive element 14 can be exposed, and the encapsulation layer 18 can cover the electronic element 16b and the electronic element 16c, but is not limited thereto. Then, openings are formed in the encapsulation layer 18 on the pad P22 of the electronic element 16b and the pad P32 of the electronic element 16c, and pads CP1 are formed in the openings, thereby forming a semi-finished structure 32. The manner of forming the encapsulation layer 18 can be the same as or similar to Figure 3 the manner of forming the encapsulation layer 18, so reference can be made to the above, and details will not be elaborated here.

[0071] After forming the pads CP1, a recess R3 can be selectively formed on the upper surfaces of the exposed pads CP1, the conductive element 14, and the conductive pad C to help reduce the extrusion of the circuit structure 20 and the semi-finished structure 32 during the bonding with the circuit structure 20. The depth of the recess R3 can be, for example, less than or equal to 15 nanometers. The manner of forming the recess R3 can include, for example, a CMP process, an etching process, or other suitable methods.

[0072] As Figure 13 shown, after forming the circuit structure 20 and the semi-finished structure 32, the circuit structure 20 can be turned upside down and bonded to the semi-finished structure 32, so that the pads CP4 can be bonded to the corresponding pads CP1, the conductive element 14, or the conductive member C. Then, by dissociating the release layer 66 and the release layer 68, the carrier plates 62, 64, the release layer 66, the release layer 68, and the anti-warpage layer 70 can be removed, thereby forming the encapsulation device 2 of this embodiment. In some embodiments, the semi-finished structure 32 can also be turned upside down and bonded to the circuit structure 20. In some embodiments, after the steps of removing the carrier plates 62, 64, the release layer 66, the release layer 68, and the anti-warpage layer 70, a conductive block (such as Figure 6 the conductive block 34 shown) can be selectively formed under the pad CP2 of the circuit structure 30.

[0073] In Figure 13 the embodiment, the manner of bonding the circuit structure 20 and the semi-finished structure 32 can include, for example, disposing a pressing plate 72 on the carrier plate 62 and under the carrier plate 64 respectively to perform a hot pressing process, so that the pads CP4 can be in direct metal-metal bonding with the corresponding pads CP1, the conductive element 14, or the conductive member C, and then an annealing process is performed. According to some embodiments, the bonding between the pads CP4 and the corresponding pads CP1, the conductive element 14, and the conductive member C can also be achieved by using bonding pads or conductive adhesives or other suitable bonding methods.

[0074] In the encapsulation device 2 of this embodiment, the electronic component 16 may not include an encapsulation layer, but is not limited thereto. In some embodiments, Figure 13 the electronic component 16 may also include Figure 6 the encapsulation layer 16p shown.

[0075] In some embodiments, Figures 11 to 13 the manufacturing method may also be applicable to the encapsulation device of any of the above embodiments. For example, Figure 7 the encapsulation device 1a to Figure 10 at least one of the encapsulation devices 1d may further include Figure 11 the pad CP4 and Figure 12 the pad CP5. Other parts of the encapsulation device 2 may be the same as Figures 1 to 6 the embodiments, so they will not be elaborated here. In some embodiments, Figure 13 the encapsulation device 2 may also selectively adopt Figure 7 the circuit structure 20 therein and the structures thereon, Figure 8 the electronic component 16, the conductive block 34 and the circuit element 56, Figure 9 the electronic component 58 and Figure 10 at least one of the conductive elements 14.

[0076] In summary, in the manufacturing method of the encapsulation device of the present invention, since the conductive element can be formed before forming the encapsulation layer surrounding the conductive element, and by matching with the step of forming the circuit structure, the pad and the conductive element can form a conductive via structure penetrating the encapsulation layer. Therefore, there is no need to form vias with a high aspect ratio in the encapsulation layer, thereby avoiding problems such as bubbles or low product yield caused by poor via quality, as well as the problem of time-consuming caused by multiple drilling, and improving the yield of the encapsulation device. And, through the first interval and the second interval, the possibility of disconnection of the traces formed on the surface of the electronic component and the first surface of the encapsulation layer can be reduced.

[0077] The above are only the embodiments of the present invention and are not intended to limit the present invention. For those of ordinary skill in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An encapsulation device, characterized in that, Comprising: A first electronic component and a second electronic component, arranged side by side; A conductive component, disposed on one side of the first electronic component; A first encapsulation layer surrounding the first electronic component, the second electronic component and the conductive component, wherein the first encapsulation layer has a first surface and a second surface opposite to the first surface, the first electronic component includes a first pad adjacent to the first surface, and the second electronic component includes a second pad adjacent to the second surface; And A first circuit structure disposed on the first encapsulation layer, wherein the first pad of the first electronic component is electrically connected to the conductive component via the first circuit structure and the second pad of the second electronic component; Wherein there is a first gap between a surface of the first electronic component and the first surface of the first encapsulation layer, and there is a second gap between a surface of the second electronic component and the second surface of the first encapsulation layer.

2. The encapsulation device according to claim 1, characterized in that, The difference between the first gap and the second gap is greater than or equal to 0 and less than or equal to 5 micrometers.

3. The encapsulation device according to claim 1, wherein The first gap and the second gap are each greater than 0 and less than or equal to 10 micrometers.

4. The encapsulation device according to claim 1, characterized in that, The first circuit structure includes a first trace, and the first pad of the first electronic component is electrically connected to the conductive component via the first trace and the second pad of the second electronic component.

5. The encapsulation device according to claim 4, wherein It further includes a second circuit structure disposed on the second surface of the first encapsulation layer, and the second pad of the second electronic component is electrically connected to the conductive component via the second circuit structure.

6. The encapsulation device according to claim 5, wherein, The second electronic component further includes a semiconductor chip and a second encapsulation layer, the second encapsulation layer surrounds the semiconductor chip, and a part of the second encapsulation layer is disposed between the second circuit structure and the semiconductor chip.

7. The encapsulation device according to claim 5, wherein, It further includes a conductive block, the second circuit structure includes a third pad, the conductive block is disposed on a surface of the third pad away from the first encapsulation layer, and the width of the conductive block is greater than the width of the third pad.

8. The encapsulation device according to claim 1, characterized in that, It further includes a third electronic component arranged side by side with the first electronic component, wherein the third electronic component includes a fourth pad adjacent to the first surface of the first encapsulation layer, and the second electronic component includes a fifth pad adjacent to the first surface of the first encapsulation layer and electrically connected to the fourth pad.

9. The encapsulation device according to claim 8, characterized in that, The first circuit structure includes a second trace, and the fifth pad is electrically connected to the fourth pad through the second trace.

10. The encapsulation device according to claim 8, characterized in that, The first circuit structure includes a third trace, and the first electronic component further includes another first pad adjacent to the first surface of the first encapsulation layer, wherein the another first pad is electrically connected to the third electronic component via the third trace.

11. The encapsulation device according to claim 8, characterized in that, It further includes a second circuit structure disposed on the second surface of the first encapsulation layer, the third electronic component further includes a sixth pad adjacent to the second surface of the first encapsulation layer and electrically connected to the second circuit structure.

12. The encapsulation device according to claim 1, wherein The first circuit structure includes an insulating layer, and the insulating layer and the first encapsulation layer are made of the same material.

13. The encapsulation device according to claim 1, wherein The conductive element includes a third encapsulation layer, a conductive layer, and a buffer layer. The third encapsulation layer surrounds the conductive layer, and the conductive layer surrounds the buffer layer.

14. The encapsulation device according to claim 13, wherein, In a cross-sectional view of the encapsulation device, the ratio of the width of the buffer layer to the width of the conductive layer is greater than or equal to 0.5 and less than 1.

15. The encapsulation device according to claim 1, characterized in that, The surface of the first electronic component is located outside the first encapsulation layer, and the surface of the second electronic component is located outside the first encapsulation layer.

16. The encapsulation device according to claim 1, wherein, The first electronic component includes a semiconductor chip, a buffer layer, and a conductive member. The buffer layer is disposed on the semiconductor chip, and the conductive member penetrates through the buffer layer and electrically connects the semiconductor chip to the first circuit structure.

17. The encapsulation device according to claim 16, wherein The first electronic component further includes a fourth encapsulation layer surrounding the semiconductor chip and the buffer layer.

18. The encapsulation device according to claim 16, characterized in that, The semiconductor chip includes a main body, a first pad, and a protective layer. The first pad is disposed on the main body, and the protective layer is disposed between the first pad and the buffer layer.

19. The encapsulation device according to claim 18, wherein, The rigidity of the buffer layer is less than the rigidity of the protective layer.

20. The encapsulation device according to claim 1, wherein, A fourth electronic component is further included, disposed on a side of the first circuit structure away from the first encapsulation layer and electrically connected to the first circuit structure.

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