Auxiliary driving circuit for reducing driving strength of internal power rail and control method

Abstract

The invention relates to the technical field of integrated circuits, in particular to an auxiliary driving circuit for reducing driving strength of an internal power rail and a control method, and the auxiliary driving circuit comprises an auxiliary switching tube with an input end connected with an input power rail and an output end connected with a grid electrode of a main switching tube; the auxiliary driving control circuit enables the auxiliary switch tube to be conducted, so that the input power rail and the internal power rail charge the input capacitor of the main switch tube at the same time, and the auxiliary switch tube is turned off when the grid charge of the main switch tube is fully charged. Aiming at the problem that the driving strength of an internal power rail is difficult to improve in the prior art, an input power rail and the internal power rail are introduced through an auxiliary switch tube to charge an input capacitor of a main switch tube together, so that the requirement on the driving strength of the internal power rail is reduced; and meanwhile, the auxiliary switch tube is controlled to be conducted by adopting the auxiliary driving control circuit, so that a relatively stable conduction effect can be realized, and application scenes such as high-voltage, high-speed and high-power switch driving and the like are met.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an auxiliary driving circuit and a control method for reducing the driving strength of an internal power supply rail. Background Art

[0002] A high-voltage driving chip is an integrated circuit chip used to drive high-voltage devices. Its main function is to convert a low-level signal into a high-voltage output, thereby achieving precise control of high-voltage devices. With the improvement of device integration, high-voltage driving chips often need to be miniaturized according to product requirements. Based on the miniaturization requirements, the most intuitive change is the reduction in the number of pins of the chip. The high-side and low-side driving power supply rail voltages inside the chip need to be generated internally, and there are no external capacitor pins. Since the voltages of the high-side and low-side driving power supply rails need to be generated from the internal circuit, their driving strengths are limited and cannot meet the requirements of high-speed high-power driving chips. For example, the charging time of the input capacitance of the power transistor is extended, and the driving frequency cannot be increased. Moreover, since the external capacitor pins are omitted, the driving ability of the power supply rail cannot be improved by introducing external capacitors.

[0003] To solve this problem, in the prior art, a scheme such as an accompanying capacitor is usually adopted to improve the driving ability of the internal power supply rail of the chip, as Figure 1 shown. The scheme of the low-side power supply rail based on the accompanying capacitor is to connect an accompanying capacitor A1 to the ground under the low-side power supply rail VCC. Among them, the drain of the NMOS transistor A2 is connected to the input power supply rail VIN, the gate is connected to the input power supply rail VIN through the pull-up resistor A3, and the gate voltage is controlled to conduct through the reversely connected zener diode A4. The source of the NMOS transistor is controlled by the source voltage through the pull-down resistor A5, and the low-side power supply rail driving is carried out in cooperation with the low-side power supply rail VCC and the accompanying capacitor A1. The driving strength of the low-side power supply rail VCC is increased by charging the accompanying capacitor A1.

[0004] However, in the actual implementation process, the inventor found that the scheme of increasing the accompanying capacitor is significantly limited by the chip area, that is, the unit capacitance value of the on-chip capacitor is low. When the switching speed and the size of the power transistor increase, the capacitance value of the accompanying capacitor to be configured also increases accordingly, which leads to an increase in chip cost and the problem of not meeting the chip miniaturization requirements. Summary of the Invention

[0005] In view of the above problems existing in the prior art, an auxiliary driving circuit for reducing the driving strength of an internal power supply rail is provided herein;

[0006] On the other hand, a control method applicable to the auxiliary driving circuit is also provided.

[0007] The specific technical solutions are as follows:

[0008] An auxiliary driving circuit for reducing the driving strength of an internal power rail, connected to the gate of a main switching transistor, the gate of the main switching transistor being connected to a driving signal terminal provided by the internal power rail and receiving a conduction signal output from the driving signal terminal, characterized by comprising an auxiliary switching transistor;

[0009] The input end of the auxiliary switching transistor is connected to an input power rail, and the output end of the auxiliary switching transistor is connected to the gate of the main switching transistor;

[0010] The gate voltage of the auxiliary switching transistor is adjusted by an auxiliary driving control circuit, so as to turn on the auxiliary switching transistor, so that the input power rail and the internal power rail charge the input capacitance of the main switching transistor at the same time, and turn off the auxiliary switching transistor when the gate charge of the main switching transistor is full.

[0011] On the other hand, the gate of the main switching transistor is also connected to the driving signal terminal through an input isolation module;

[0012] The input isolation module is turned off in the initial state to block the internal power rail from charging the input capacitance of the main switching transistor;

[0013] The input isolation module is turned on when the gate voltage of the main switching transistor reaches a predetermined voltage value, so that the input power rail and the internal power rail charge the input capacitance of the main switching transistor at the same time.

[0014] On the other hand, the input isolation module includes:

[0015] A first buffer, the input end of the first buffer being connected to the driving signal terminal;

[0016] A first AND gate, the first input end of the first AND gate being connected to the output end of the first buffer;

[0017] The second input end of the first AND gate is connected to a first logic controller and receives a first logic control signal input from the first logic controller;

[0018] A second buffer, the first end of the second buffer being connected to the output end of the first AND gate;

[0019] The output end of the second buffer serves as the output end of the input isolation module.

[0020] On the other hand, it further includes a first level shifter;

[0021] The input end of the first level shifter is connected to the driving signal terminal and receives the conduction signal, and the output end of the first level shifter is connected to the auxiliary driving control circuit;

[0022] When the first level converter outputs the conduction signal at the drive signal terminal, it performs level conversion on the level signal and inputs it to the first input terminal of the auxiliary drive control circuit, so that the auxiliary drive control circuit controls the conduction of the auxiliary switch transistor.

[0023] On the other hand, it further includes a gate voltage detection module, a second logic controller, and a second level converter;

[0024] The input terminal of the gate voltage detection module is connected to the gate of the main switch transistor;

[0025] The output terminal of the gate voltage detection module is connected to the input terminal of the second logic controller;

[0026] The output terminal of the second logic controller is connected to the second level converter;

[0027] The output terminal of the second level converter is respectively connected to the second input terminal of the auxiliary drive control circuit and the logic control terminal of the input isolation module.

[0028] On the other hand, the flip voltage of the gate voltage detection module is lower than the voltage of the internal power supply rail;

[0029] When the output level of the gate voltage detection module flips, the second logic controller generates a second logic control signal to respectively control the conduction of the input isolation module and the turn-off of the auxiliary switch transistor.

[0030] On the other hand, the auxiliary drive control circuit includes a third logic controller and a third buffer;

[0031] The output terminal of the third logic controller is connected to the input terminal of the third buffer, and the output terminal of the third buffer serves as the output terminal of the auxiliary drive control circuit;

[0032] The third logic controller controls the conduction of the auxiliary switch transistor according to the signal input at the first input terminal and controls the turn-off of the auxiliary switch transistor according to the input signal at the second input terminal.

[0033] On the other hand, the auxiliary drive control circuit includes a pulse signal generator, a fourth buffer, and a fourth logic controller;

[0034] The input terminal of the pulse signal generator serves as the input terminal of the auxiliary drive control circuit and generates a pulse signal according to the high-level signal output by the first buffer;

[0035] The pulse signal is respectively input to the fourth logic controller and the gate of the auxiliary switch transistor through the fourth buffer;

[0036] The width of the pulse signal is used to control the turn-on time of the auxiliary switch tube;

[0037] The fourth logic controller controls the conduction of the input isolation module according to the falling edge of the pulse signal.

[0038] A control method, applicable to the above-mentioned auxiliary drive circuit, includes:

[0039] Step S1: When a conduction signal of the main switch tube is received, turn on the auxiliary switch tube to charge the input capacitance of the main switch tube using both the input power supply rail and the internal power supply rail simultaneously;

[0040] Step S2: When the input capacitance of the main switch tube is fully charged, turn off the auxiliary switch tube.

[0041] On the other hand, step S1 further includes:

[0042] Step S11: Turn on the auxiliary switch tube and use the input isolation module to turn off the path between the internal power supply rail and the gate of the main switch tube;

[0043] Step S12: When the gate voltage of the main switch tube rises to a predetermined voltage, turn on the input isolation module to charge using both the input power supply rail and the internal power supply rail simultaneously.

[0044] The above technical solution has the following advantages or beneficial effects:

[0045] Aiming at the problem that it is difficult to further increase the driving strength of the power tube by the internal power supply rail of the driving chip in the prior art, in this embodiment, the input power supply rail and the internal power supply rail are introduced through the auxiliary switch tube to jointly charge the input capacitance of the main switch tube, thereby reducing the driving strength requirement for the internal power supply rail. At the same time, since the auxiliary switch tube is controlled to conduct by the auxiliary drive control circuit, a relatively stable conduction effect can be achieved, meeting application scenarios such as high-voltage, high-speed, and high-power switch driving. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Referring to the accompanying drawings, the embodiments of the present invention are described more fully. However, the accompanying drawings are only for illustration and explanation, and do not constitute a limitation on the scope of the present invention.

[0047] Figure 1 Schematic diagram of the prior art;

[0048] Figure 2 Overall schematic diagram of the embodiment of the present invention;

[0049] Figure 3 Schematic diagram of another charging scheme through the input power supply rail;

[0050] Figure 4 Schematic diagram of the input isolation module in the embodiment of the present invention;

[0051] Figure 5 Schematic diagram of the control circuit based on gate voltage detection in the embodiment of the present invention;

[0052] Figure 6 Schematic diagram of the control circuit based on pulse width length in the embodiment of the present invention;

[0053] Figure 7 Schematic diagram of the control method in the embodiment of the present invention;

[0054] Figure 8 Schematic diagram of the sub - steps of step S1 in the embodiment of the present invention. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0056] Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in one or more hardware modules or integrated circuits, or in different processor devices and / or microcontroller devices and / or in combination with control programs.

[0057] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0058] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.

[0059] The present invention includes:

[0060] An auxiliary drive circuit for reducing the drive strength of the internal power supply rail, as Figure 2 shown, is connected to the gate of the main switch tube M1. The gate of the main switch tube M1 is connected to the drive signal terminal DRV provided by the internal power supply rail (VCC) and receives the conduction signal output from the drive signal terminal DRV;

[0061] It further includes an auxiliary switch tube M2;

[0062] The input end of the auxiliary switch tube M2 is connected to the input power supply rail VIN, and the output end of the auxiliary switch tube M2 is connected to the gate of the main switch tube M1;

[0063] The gate voltage of the auxiliary switching transistor M2 is regulated by the auxiliary drive control circuit U1, which is used to turn on the auxiliary switching transistor M2, so that the input power supply rail VIN and the internal power supply rail (VCC) charge the input capacitance of the main switching transistor M1 simultaneously, and turn off the auxiliary switching transistor M2 when the gate charge of the main switching transistor M1 is full.

[0064] Specifically, for the miniaturized drive chip in the prior art, the driving strength of its internal power supply rail (VCC) is weak, resulting in a long charging time for the input capacitance of the main switching transistor M1 to reach the gate voltage for predetermined conduction. In this embodiment, a technical solution of parallel charging based on the input power supply rail VIN is introduced.

[0065] Specifically, taking the main switching transistor M1 of the NMOS type as an example, its drain is used as the input terminal and its source is used as the output terminal, then its gate-source voltage needs to meet a specific threshold voltage to conduct. To meet this conduction condition, it is necessary to charge its input capacitance through the gate so that the gate has a specific amount of charge to conduct. In the prior art, when the drive chip is a miniaturized drive chip, the driving ability of its internal power supply rail (VCC) will decrease accordingly, and then the charging process of the above-mentioned gate charge will be prolonged, which cannot meet the requirements of high-frequency drive.

[0066] To solve this problem, in this embodiment, a technical means of charging the input capacitance of the main switching transistor M1 simultaneously through the input power supply rail VIN and the internal power supply rail (VCC) is selected. Among them, the input power supply rail VIN corresponds to the power supply pin of the chip and can obtain the external input power supply, and it has significantly stronger driving ability compared with the internal power supply rail (VCC) generated by the chip through the built-in circuit. Then, by introducing the input power supply rail VIN and the internal power supply rail (VCC) to charge the input capacitance of the main switching transistor M1 simultaneously, and turning off the auxiliary switching transistor M2 when the input capacitance of the main switching transistor M1 is almost full, the charging speed of the main switching transistor M1 can be greatly increased based on the above charging method, so as to meet the requirements of high-frequency drive.

[0067] In one embodiment, the main switching transistor M1 is an NMOS transistor and is driven by a low-side power supply rail.

[0068] The auxiliary switching transistor M2 is a PMOS transistor. The source of the auxiliary switching transistor M2 is connected to the input power supply rail VIN through a pull-up resistor R1 to obtain the source voltage, and the drain of the auxiliary switching transistor M2 is connected to the main switching transistor M1 for output.

[0069] Meanwhile, considering the problem that the operating region of the auxiliary switch tube M2 affects the charging efficiency of the gate of the main switch tube M1, in this embodiment, an independent auxiliary drive control circuit U1 is provided for driving the auxiliary switch tube M2, so that the auxiliary switch tube M2 is always turned on during the process of charging the main switch tube M1.

[0070] As a comparative example, Figure 3 Another possible charging scheme through the input power supply rail VIN is shown. In this embodiment, the high-side auxiliary switch tube M2 is an NMOS device. Among them, the VCC power supply rail part receives the turn-on signal through the buffer Buf1 and then inputs it to the high-side and low-side branches respectively. The high-side branch inputs the gate of the auxiliary switch tube M2 through the buffer Buf2, and the low-side is connected to the gate of the main switch tube M1 through the buffer Buf3 and the buffer Buf4 in sequence.

[0071] Assume that the auxiliary switch tube M2 is used as an isolation switch tube, and its gate voltage is controlled by the turn-on signal on the drive signal terminal DRV. When the internal power supply rail (VCC) transmits the turn-on signal to the gate of the main switch tube M1, the auxiliary switch tube M2 is turned on at the same time. At this time, a channel from the input power supply rail VIN to the gate of the main switch tube M1 can also be constructed. During this process, the gate voltage of the auxiliary switch tube M2 is controlled by the drive signal terminal DRV, and the source is directly connected to the gate of the main switch tube M1.

[0072] Since the output terminal of the auxiliary switch tube M2 is directly connected to the main switch tube M1, and the source of the auxiliary switch tube M2 is connected to the gate of the main switch tube M1, as the gate voltage of the main switch tube M1 increases, the gate-source voltage difference of the auxiliary switch tube M2 will gradually decrease, and the operating region will retreat from the saturation region to the linear region. Moreover, as the charging process progresses, the conduction degree of the auxiliary switch tube M2 becomes weaker and weaker, and the amount of charge input on the channel from the input power supply rail VIN to the gate of the main switch tube M1 also decreases significantly.

[0073] If a schematic diagram is constructed with time as the horizontal axis and the gate charge of the main switch tube M1 as the vertical axis, it is easy to infer that as time increases, the gate charge of the main switch tube M1 will initially increase with a large slope, and then the slope will decrease as time increases. When it is close to full charge, due to the decrease in the gate-source voltage difference of the auxiliary switch tube M2, the conduction degree of the auxiliary switch tube M2 weakens, and the gate of the main switch tube M1 is mainly charged by the internal power supply rail (VCC). At this time, the charging efficiency is significantly reduced.

[0074] Accordingly, if the above-mentioned independent auxiliary drive control circuit U1 is used for driving and the auxiliary switch M2 is adjusted to a PMOS device, the auxiliary switch M2 can operate in the saturation region during the entire charging process, and the change slope of the gate charge of the main switch M1 will not decrease, thus having significantly higher charging efficiency.

[0075] The above embodiments are mainly constructed around the design where the auxiliary switch M2 is a PMOS transistor and the main switch M1 is an NMOS transistor, but the device types can also be swapped according to actual needs.

[0076] In one embodiment, the gate of the main switch M1 is also connected to the drive signal terminal DRV through the input isolation module U2;

[0077] The input isolation module U2 is turned off in the initial state to block the charging of the input capacitance of the main switch M1 by the internal power supply rail (VCC);

[0078] The input isolation module U2 is turned on when the gate voltage of the main switch M1 reaches a predetermined voltage value, so that the input power supply rail VIN and the internal power supply rail (VCC) charge the input capacitance of the main switch M1 simultaneously.

[0079] Specifically, considering that there may be other loads working simultaneously on the internal power supply rail (VCC) in the chip circuit, and the internal power supply rail (VCC) may cause the voltage of other loads to decrease when charging the gate of the main switch M1. In this embodiment, an input isolation module U2 is also provided.

[0080] The input terminal of the input isolation module U2 is connected to the drive signal terminal DRV to provide a gate voltage for the main switch M1, and at the same time, it is also used to selectively pass the conduction signal provided by the drive signal terminal DRV.

[0081] Specifically, in the initial state, the input isolation module U2 can be configured to be in the off state, and through logical control, the auxiliary drive control circuit U1 drives the auxiliary switch M2 to conduct. At this time, the channel where the internal power supply rail (VCC) corresponding to the input isolation module U2 is turned off and does not output the conduction signal of the drive signal terminal DRV, while the channel of the input power supply rail VIN corresponding to the auxiliary switch M2 is turned on, and the gate of the main switch M1 is mainly charged by the input power supply rail VIN.

[0082] When the input capacitance of the main switching transistor M1 is about to be fully charged or reaches a predetermined charge amount, the input isolation module U2 is controlled to turn on, conducting the channel where the internal power rail (VCC) is located, and the drive signal terminal DRV provides a gate voltage to the main switching transistor M1 or continues to charge; at the same time, the auxiliary drive control circuit U1 controls the auxiliary switching transistor M2 to turn off, thereby closing the channel of the input power rail VIN to the gate of the main switching transistor M1.

[0083] Through the above settings, most of the charge of the input capacitance of the main switching transistor M1 can be provided by the input power rail VIN, further reducing the demand for the internal power rail (VCC).

[0084] In one embodiment, as Figure 4 shown, the input isolation module U2 includes:

[0085] A first buffer Buffer1, the input end of the first buffer Buffer1 is connected to the drive signal terminal DRV;

[0086] A first AND gate AND, the first input end of the first AND gate AND is connected to the output end of the first buffer Buffer1;

[0087] The second input end of the first AND gate AND is connected to the first logic controller CTR1 and receives the first logic control signal input by the first logic controller CTR1;

[0088] A second buffer Buffer2, the first end of the second buffer Buffer2 is connected to the output end of the first AND gate AND;

[0089] The output end of the second buffer Buffer2 serves as the output end of the input isolation module U2.

[0090] Specifically, to achieve the above control of the conduction channel of the internal power rail (VCC), in this embodiment, a AND gate circuit constructed by the first AND gate AND is introduced in the input isolation module U2 to achieve this.

[0091] Specifically, between the first AND gate AND and the drive signal terminal DRV, matching is performed through the first buffer Buffer1, and a stronger driving ability for the first AND gate AND is provided. The first AND gate AND is a AND gate circuit, and the level of its first input end is controlled by the drive signal terminal DRV. When the drive signal terminal DRV needs to drive the main switching transistor M1 to conduct, a conduction signal is generated on the drive signal terminal DRV, and the first buffer Buffer1 performs level matching for this conduction signal and converts it to a level that meets the requirements of the first AND gate AND for input.

[0092] The level of the second input terminal of the first AND gate AND is controlled by the first logic controller CTR1. The first logic controller CTR1 controls the level output according to a pre-configured control logic or in combination with an externally input level signal, thereby controlling the conduction of the first AND gate AND. For example, in the initial state, a low level is output to block the output of the first AND gate AND, and when the input capacitance of the main switching transistor M1 is about to be fully charged, it flips to a high level to enable the first AND gate AND to output.

[0093] When the first logic controller CTR1 outputs a high level and there is a conduction signal on the drive signal terminal DRV, the first AND gate AND is opened and outputs a high level signal. At this time, the output is matched by the subsequent second buffer Buffer2.

[0094] In one embodiment, it further includes a first level converter S1;

[0095] The input terminal of the first level converter S1 is connected to the drive signal terminal DRV and receives the conduction signal, and the output terminal of the first level converter S1 is connected to the auxiliary drive control circuit U1;

[0096] When the first level converter S1 outputs a conduction signal on the drive signal terminal DRV, it converts the level signal and inputs it to the first input terminal of the auxiliary drive control circuit U1, so that the auxiliary drive control circuit U1 controls the auxiliary switching transistor M2 to conduct.

[0097] Specifically, during the process of charging the input capacitance of the main switching transistor M1, the establishment of its charging logic depends on the drive signal terminal DRV outputting a conduction signal, and on the basis that the internal power supply rail starts to charge the main switching transistor M1 and provides a conduction signal.

[0098] Therefore, in order to enable the auxiliary switching transistor M2 to establish a channel from the input power supply rail VIN to the gate of the main switching transistor M1 in a timely manner, in this embodiment, a first level converter S1 is introduced to connect the drive signal terminal DRV and the auxiliary drive control circuit U1.

[0099] The first level converter S1 is used to perform level conversion and matching on the output voltage of the drive signal terminal DRV and the input voltage of the auxiliary drive control circuit U1, so as to provide a following level signal to the auxiliary drive control circuit U1.

[0100] When the drive signal terminal DRV does not output a conduction signal, the output of the auxiliary drive control circuit U1 is also a low level signal.

[0101] After the drive signal terminal DRV outputs a conduction signal, the first level converter S1 outputs a high-level signal to the auxiliary drive control circuit U1 through level conversion. The auxiliary drive control circuit U1 controls the conduction of the auxiliary switch tube M2 according to this signal and establishes a channel from the input power supply rail VIN to the gate of the main switch tube M1 for charging. During this process, the input isolation module U2 may be conducting or non-conducting, which does not affect the operation of the auxiliary drive control circuit U1.

[0102] To implement the logical control of the first logic controller CTR1, the following provides two different control embodiments, which are controlled based on gate voltage measurement and pulse time respectively.

[0103] In one embodiment, as Figure 5 shown, it further includes a gate voltage detection module U3, a second logic controller CTR2, and a second level converter S2;

[0104] The input end of the gate voltage detection module U3 is connected to the gate of the main switch tube M1;

[0105] The output end of the gate voltage detection module U3 is connected to the input end of the second logic controller CTR2;

[0106] The output end of the second logic controller CTR2 is connected to the second level converter S2;

[0107] The output end of the second level converter S2 is respectively connected to the second input end of the auxiliary drive control circuit U1 and the logic control end of the input isolation module U2;

[0108] The flip voltage of the gate voltage detection module U3 is lower than the voltage of the internal power supply rail (VCC);

[0109] When the output level of the gate voltage detection module U3 flips, the second logic controller CTR2 generates a second logic control signal to control the input isolation module U2 to conduct and the auxiliary switch tube M2 to turn off respectively.

[0110] Specifically, to implement the logical control process based on the gate voltage, in this embodiment, a gate voltage detection module U3 is set on the low side, which mainly includes a group of voltage detection circuits that can detect the gate voltage of the main switch tube M1 and compare it with a pre-configured reference voltage through a comparator circuit, so as to provide a corresponding output level signal to indicate the charging condition of the input capacitance of the main switch tube M1. Generally speaking, this reference voltage, or the flip voltage of the gate voltage detection module U3, will be configured as a voltage slightly lower than the voltage of the internal power supply rail (VCC), that is, the voltage when the main switch tube M1 is about to complete charging.

[0111] During the charging process of the main switching transistor M1, the gate voltage detection module U3 detects that the gate voltage of the main switching transistor M1 continues to rise but always remains lower than the flip voltage. At this time, the gate voltage detection module U3 continuously outputs a low level.

[0112] When the gate voltage of the main switching transistor M1 reaches the flip voltage, the output level of the gate voltage detection module U3 flips to a high level, which causes the second logic controller CTR2 to start operating and provide a corresponding drive signal level.

[0113] For the channels on both the high side and the low side, there are two mutually related branches at this time.

[0114] First, analyze the input isolation module U2 on the low side. In the initial state, the first logic controller CTR1 in the input isolation module U2 outputs a low level signal, while the drive signal terminal DRV outputs a conduction signal. At this time, there is only one high level signal on the first AND gate AND, and the first AND gate AND outputs a low level signal, which blocks the output of the corresponding drive signal terminal DRV of the input isolation module U2.

[0115] In this state, the auxiliary drive control circuit U1 on the high side will be turned on. Specifically, the first level converter S1 outputs a high level signal with a matching amplitude to the auxiliary drive control circuit U1 through level conversion. The auxiliary drive control circuit U1 controls the conduction of the auxiliary switching transistor M2 according to this signal and establishes a charging path from the input power supply rail VIN to the gate of the main switching transistor M1.

[0116] At this time, the input capacitance of the gate of the main switching transistor M1 starts to charge, and the charging current is provided by the input power supply rail VIN. There is a high level on the drive signal terminal DRV but it does not provide charging.

[0117] As the gate voltage of the main switching transistor M1 gradually rises to the flip voltage, the output level of the gate voltage detection module U3 flips to a high level, which causes the second logic controller CTR2 to output a corresponding high level signal for control.

[0118] For the input isolation module U2 on the low side, after the logic control terminal of the first logic controller CTR1 in the input isolation module U2 receives a high level signal, the output signal of the first logic controller CTR1 also flips to a high level. At this time, the conduction signal continues to be output on the drive signal terminal DRV, so that there are two high level signals on the first AND gate AND. The first AND gate AND outputs a high level signal, which is output after the driving ability is improved by the second buffer Buffer2, and the path from the corresponding drive signal terminal DRV to the main switching transistor M1 is opened.

[0119] For the auxiliary drive control circuit U1, the auxiliary drive control circuit U1 will receive a high-level signal from the drive signal terminal DRV and a high-level signal from the second logic controller CTR2 at this time. When receiving these two high-level signals simultaneously, the auxiliary drive control circuit U1 turns off the auxiliary switch tube M2, thereby blocking the path from the input power supply rail VIN to the gate of the main switch tube M1, so that the main switch tube M1 only follows the action of the drive signal terminal DRV.

[0120] Among them, to achieve the matching of the output level of the second logic controller CTR2, a level conversion is performed by the second level converter S2 before inputting to the auxiliary drive control circuit U1.

[0121] In this embodiment, the auxiliary drive control circuit U1 includes a third logic controller CTR3 and a third buffer Buffer3;

[0122] The output terminal of the third logic controller CTR3 is connected to the input terminal of the third buffer Buffer3, and the output terminal of the third buffer Buffer3 serves as the output terminal of the auxiliary drive control circuit;

[0123] The third logic controller CTR3 controls the conduction of the auxiliary switch tube M2 according to the signal input at the first input terminal, and controls the turning off of the auxiliary switch tube M2 according to the input signal at the second input terminal.

[0124] Specifically, to implement the above control logic, in this embodiment, a third logic controller CTR3 is configured in the auxiliary drive control circuit U1. Among them, the third logic controller CTR3 controls the conduction of the auxiliary switch tube M2 according to the signal input at the first input terminal, and controls the turning off of the auxiliary switch tube M2 according to the input signal at the second input terminal.

[0125] Specifically, before the third logic controller CTR3 starts to act, both inputs are low-level signals. At this time, the third logic controller CTR3 outputs a low-level signal, and the auxiliary switch tube M2 is turned off.

[0126] When a high-level signal matched by the first level converter S1 is input to the first input terminal, the output of the third logic controller CTR3 flips to a high-level signal. At this time, the second input terminal should still be a low-level signal, and the auxiliary switch tube M2 conducts to establish a charging path from the input power supply rail VIN to the main switch tube M1.

[0127] When the first input terminal maintains a high-level signal and the second input terminal inputs a high-level signal due to the flip of the second logic controller CTR2, the output of the third logic controller CTR3 also flips and becomes a low-level signal.

[0128] When other situations occur, such as when the first input terminal is at a low level and a high level appears at the second input terminal, it indicates that the circuit may be accidentally triggered. At this time, the third logic controller CTR3 should output a low-level signal to avoid the auxiliary switch tube M2 introducing high voltage.

[0129] Similarly, during the above output process, the third buffer Buffer 3 changes following the level of the third logic controller CTR3 and provides a specific driving voltage to drive the auxiliary switch tube M2.

[0130] In another embodiment, the switching can be performed by means of the conduction time.

[0131] In this embodiment, as Figure 6 shown, the auxiliary drive control circuit U1 includes a pulse signal generator PLS, a fourth buffer Buffer 4, and a fourth logic controller CTR4;

[0132] The input terminal of the pulse signal generator PLS serves as the input terminal of the auxiliary drive control circuit U1 and generates a pulse signal in accordance with the high-level signal output by the first buffer Buffer 1;

[0133] The pulse signal is respectively input into the fourth logic controller CTR4 and the gate of the auxiliary switch tube M2 via the fourth buffer Buffer 4;

[0134] The width of the pulse signal is used to control the on-time of the auxiliary switch tube M2;

[0135] The fourth logic controller CTR4 controls the conduction of the input isolation module U2 in accordance with the falling edge of the pulse signal.

[0136] Specifically, to achieve control based on the conduction time, in this embodiment, a pulse signal generator PLS is first introduced into the auxiliary drive control circuit U1. The pulse signal generator PLS is used to generate a square wave signal with a specific pulse width, and after the amplitude is adjusted by the fourth buffer Buffer4, it can be used to drive the conduction of the auxiliary switch tube M2.

[0137] The triggering of the pulse signal generator PLS is controlled by the first buffer Buffer 1. When the drive signal terminal DRV outputs a conduction signal, the first buffer Buffer 1 performs level matching to trigger the pulse signal generator PLS, and the pulse signal generator generates a pulse signal with a specific pulse width and inputs it into the fourth buffer Buffer 4.

[0138] The fourth buffer Buffer 4 adjusts the amplitude of the pulse signal to match the gate voltage of the auxiliary switch tube M2, thereby driving the auxiliary switch tube M2 to conduct and starting to charge the main switch tube M1 through the input power supply rail VIN.

[0139] The output of the fourth buffer, Buffer 4, is adjusted by the third level converter S3 to conform to the input level of the first logic controller CTR1 of the input isolation module U2, so that the first logic controller CTR1 receives a rising edge signal. The first logic controller CTR1 triggers the detection process based on this rising edge signal and always outputs a low level during the rising edge stage to block the output on the side of the input isolation module U2.

[0140] Correspondingly, when the pulse signal output by the pulse signal generator PLS reaches the complete pulse length, the output of the fourth buffer, Buffer 4, flips to a low level, the auxiliary switch tube M2 turns off, thus blocking the conduction path on the side of the input power supply rail VIN, and a falling edge is generated in the output signal on the side of the third level converter S3.

[0141] The first logic controller CTR1 detects this falling edge signal. When the falling edge is triggered, the first logic controller CTR1 outputs a high level to control the conduction of the input isolation module U2, and further enables the path from the internal power supply rail (VCC) to the main switch tube M1 to conduct.

[0142] Based on the above settings, it can be seen that the conduction on the side of the drive signal terminal DRV is controlled by the rising edge and falling edge of the pulse signal, and the conduction time of the input power supply rail VIN is set by the pulse width of the pulse signal. By configuring a specific pulse width length, the charging process of the input capacitance of the main switch tube M1 can be matched.

[0143] A control method is applicable to the above-mentioned auxiliary drive circuit, as Figure 7 shown, including:

[0144] Step S1: When receiving the conduction signal of the main switch tube, conduct the auxiliary switch tube to charge the input capacitance of the main switch tube by using both the input power supply rail and the internal power supply rail simultaneously;

[0145] Step S2: When the input capacitance of the main switch tube is fully charged, turn off the auxiliary switch tube.

[0146] Specifically, according to the above circuit settings, in this solution, when it is necessary to conduct the main switch tube, a high-level conduction signal will be generated at the drive signal terminal. At this time, the auxiliary switch tube is first conducted, thus constructing a conduction path from the input power supply rail VIN to the gate of the main switch tube to charge the input capacitance of the main switch tube by using both the input power supply rail and the internal power supply rail simultaneously, improving the charging speed.

[0147] When the input capacitance of the main switch tube is fully charged, turn off the auxiliary switch tube, so that the gate of the main switch tube acts with the drive signal terminal, and at the same time, the charging efficiency can be greatly improved.

[0148] In one embodiment, as Figure 8 shown, step S1 further includes:

[0149] Step S11: Turn on the auxiliary switch tube and use the input isolation module to turn off the path between the internal power rail and the gate of the main switch tube;

[0150] Step S12: When the gate voltage of the main switch tube rises to a predetermined voltage, turn on the input isolation module to charge using both the input power rail and the internal power rail simultaneously.

[0151] Specifically, to further reduce the charging requirement for the internal power rail, in this embodiment, first turn on the auxiliary switch tube and use the input isolation module to turn off the path between the drive signal terminal and the gate of the main switch tube. When the gate voltage of the main switch tube rises to a predetermined voltage, turn on the input isolation module to charge using both the input power rail and the internal power rail simultaneously.

[0152] Although this application contains many specific implementation details, these should not be construed as limiting the scope of any disclosure or the scope of what is claimed, but are mainly used to describe the features of specific embodiments of a particular disclosure. Certain features described in multiple embodiments of this application can also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may operate in certain combinations as described and are even initially claimed as such, one or more features from the claimed combination can in some cases be removed from the combination, and the claimed combination can be directed to a sub-combination or a variant of a sub-combination.

[0153] Similarly, although configurations are depicted in a specific order in the drawings, this should not be construed as requiring these configurations to be arranged in the specific structures shown, or requiring all illustrated configurations to be implemented to achieve the desired result. In some cases, an integrated structure and a discrete structure may be advantageous. In addition, the separation of the various system modules and components in the described embodiments should not be construed as required in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single integrated circuit product or packaged into multiple chips.

[0154] The above are only preferred embodiments of the present invention, and thus do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be able to realize that all equivalent replacements and obvious changes made by using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. An auxiliary driving circuit for reducing the driving strength of an internal power rail, connected to the gate of a main switching transistor. The gate of the main switching transistor is connected to a driving signal terminal provided by the internal power rail and receives a conduction signal output from the driving signal terminal. It is characterized in that, including an auxiliary switching transistor; The input end of the auxiliary switching transistor is connected to the input power supply rail, and the output end of the auxiliary switching transistor is connected to the gate of the main switching transistor; The gate voltage of the auxiliary switching transistor is regulated by an auxiliary driving control circuit, which is used to turn on the auxiliary switching transistor, so that the input power supply rail and the internal power supply rail charge the input capacitance of the main switching transistor at the same time, and turn off the auxiliary switching transistor when the gate charge of the main switching transistor is full.

2. The auxiliary drive circuit according to claim 1, wherein The gate of the main switching transistor is also connected to the driving signal terminal through an input isolation module; The input isolation module is turned off in the initial state to block the internal power supply rail from charging the input capacitance of the main switching transistor; The input isolation module is turned on when the gate voltage of the main switching transistor reaches a predetermined voltage value, so that the input power supply rail and the internal power supply rail charge the input capacitance of the main switching transistor at the same time.

3. The auxiliary drive circuit according to claim 2, wherein The input isolation module includes: A first buffer, the input end of the first buffer is connected to the driving signal terminal; A first AND gate, the first input end of the first AND gate is connected to the output end of the first buffer; The second input end of the first AND gate is connected to a first logic controller and receives a first logic control signal transmitted by the first logic controller; A second buffer, the first end of the second buffer is connected to the output end of the first AND gate; The output end of the second buffer is used as the output end of the input isolation module.

4. The auxiliary drive circuit according to claim 2, wherein, It also includes a first level converter; The input end of the first level converter is connected to the driving signal terminal and receives the conduction signal, and the output end of the first level converter is connected to the auxiliary driving control circuit; When the conduction signal is output at the driving signal terminal, the first level converter performs level conversion on the level signal and inputs it to the first input end of the auxiliary driving control circuit, so that the auxiliary driving control circuit controls the auxiliary switching transistor to turn on.

5. The auxiliary drive circuit according to claim 4, characterized in that, It also includes a gate voltage detection module, a second logic controller and a second level converter; The input end of the gate voltage detection module is connected to the gate of the main switching transistor; The output end of the gate voltage detection module is connected to the input end of the second logic controller; The output end of the second logic controller is connected to the second level converter; The output end of the second level converter is respectively connected to the second input end of the auxiliary driving control circuit and the logic control end of the input isolation module.

6. The auxiliary drive circuit according to claim 5, wherein, The switching voltage of the gate voltage detection module is lower than the voltage of the internal power supply rail; When the output level of the gate voltage detection module flips, the second logic controller generates a second logic control signal to respectively control the input isolation module to turn on and the auxiliary switching transistor to turn off.

7. The auxiliary drive circuit according to claim 5, wherein The auxiliary driving control circuit includes a third logic controller and a third buffer; The output end of the third logic controller is connected to the input end of the third buffer, and the output end of the third buffer is used as the output end of the auxiliary driving control circuit; The third logic controller controls the conduction of the auxiliary switch tube according to the signal input at the first input end, and controls the turn-off of the auxiliary switch tube according to the input signal at the second input end.

8. The auxiliary drive circuit according to claim 5, wherein The auxiliary drive control circuit includes a pulse signal generator, a fourth buffer, and a fourth logic controller; The input end of the pulse signal generator serves as the input end of the auxiliary drive control circuit, and generates a pulse signal according to the high-level signal output by the first buffer; The pulse signal is respectively input into the fourth logic controller and the gate of the auxiliary switch tube via the fourth buffer; The width of the pulse signal is used to control the turn-on time of the auxiliary switch tube; The fourth logic controller controls the conduction of the input isolation module according to the falling edge of the pulse signal.

9. A control method, characterized in that, Applicable to the auxiliary drive circuit according to any one of claims 1-8, including: Step S1: When the conduction signal of the main switch tube is received, the auxiliary switch tube is turned on to charge the input capacitance of the main switch tube using both the input power rail and the internal power rail simultaneously; Step S2: When the input capacitance of the main switch tube is fully charged, the auxiliary switch tube is turned off.

10. The control method according to claim 9, wherein The step S1 further includes: Step S11: Turn on the auxiliary switch tube and turn off the path between the internal power rail and the gate of the main switch tube using the input isolation module; Step S12: After the gate voltage of the main switch tube rises to a predetermined voltage, turn on the input isolation module to charge using both the input power rail and the internal power rail simultaneously.

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