Gate driver circuit, half-bridge gate driver circuit, method for adjusting adaptive dead time, and power module

Abstract

The invention relates to a gate driver circuit, a half-bridge gate driver circuit, a method of adjusting adaptive dead time, and a power module. The gate driver circuit includes: a high side region operating in a first voltage domain; a low side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive the power switch between an on state and an off state with adaptive dead time, a capacitor cross-coupled to the high side region and the low side region; a logic circuit configured to use the capacitor to detect a voltage transient of the power switch based on a first crossing threshold and to detect an end of the voltage transient based on a second crossing threshold; and an active-passive discrimination circuit configured to indicate whether the voltage transient is active or passive. The logic circuit is configured to adjust the adaptive dead time based on the second crossing threshold and based on the voltage transient being passive.

Description

Technical Field

[0001] The present disclosure generally relates to the field of electronics and, more particularly, to a gate driver having self-adjusting and adaptive dead time. Background Art

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as driving an electric machine or motor, rely on power semiconductor devices. For example, by way of non-limiting example only, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to switching in power supplies and power converters.

[0003] A transistor typically includes a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the transistor. Additionally, the load current can be controlled by a control electrode (sometimes referred to as a gate electrode) of the transistor. For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of an on state or an off state. Thus, the semiconductor structure behaves like a switch having on and off states (i.e., on and off states, respectively).

[0004] Typically, a power converter includes two complementary transistors (e.g., a high-side transistor and a low-side transistor) for each motor phase, where the two complementary transistors form a half-bridge to drive an output pad connected to a motor winding. A gate driver for driving the two complementary transistors can be supplied with a fixed positive voltage from a positive supply rail and a fixed negative voltage from a negative supply rail. The positive supply rail can be connected to the output pad via the high-side transistor of the two complementary transistors to supply a load current to the motor winding, and the negative supply rail can be connected to the output pad via the low-side transistor of the two complementary transistors to absorb the load current from the motor winding. The two complementary transistors can be turned on and off complementarily to avoid cross-conduction.

[0005] Thus, the load current (also referred to as the motor phase current) can be controlled by driving the two complementary transistors. The amplitude of the control signal received from the gate driver for each transistor can vary to drive the two complementary transistors between switching states. This in turn drives the motor. For example, the gate-source voltage Vgs of a MOSFET is typically driven down to approximately zero to turn off the MOSFET and is typically driven to a maximum value to fully turn on the MOSFET. Thus, the gate-source voltage Vgs can be referred to as a control voltage.

[0006] During operation, the motor can be driven according to a motor control algorithm to achieve a desired motor speed corresponding to the electrical frequency of the control signal. Summary of the Invention

[0007] In some implementations, a gate driver circuit includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state with an adaptive dead time, where the adaptive dead time is a delay between a turn-off event of a complementary power switch and a turn-on event of the power switch, at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensed value representative of a rate of change of a voltage present at a load terminal of the power switch; a comparator circuit configured to compare the sensed value with a threshold and further configured to generate a comparison result based on whether the sensed value meets the threshold; a logic circuit configured to receive the comparison result, detect a voltage transient of the voltage based on the comparison result indicating a first crossing of the threshold, and detect an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, where the second crossing occurs after the first crossing and in a direction opposite to the first crossing; and an active-passive discrimination circuit configured to detect a switching state of the power switch, including whether the power switch is in an on state or an off state, where the active-passive discrimination circuit is configured to indicate to the logic circuit whether the voltage transient is an active voltage transient or a passive voltage transient based on the switching state of the power switch, and where the logic circuit is configured to adjust the adaptive dead time of the power switch based on the comparison result indicating a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0008] In some implementations, a half-bridge gate driver circuit includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a first gate driver disposed in the high-side region and configured to drive a high-side power switch between an on state and an off state using a first adaptive dead time provided during an off-state interval of the high-side power switch; a second gate driver disposed in the low-side region and configured to drive a low-side power switch between an on state and an off state using a second adaptive dead time provided during an off-state interval of the low-side power switch, wherein the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, and wherein the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; a phase node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit disposed in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and configured to provide a first sensed value representing a rate of change of a phase voltage present at the phase node terminal; a second sensing circuit disposed in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and configured to provide a second sensed value representing a rate of change of the phase voltage present at the phase node terminal; a first comparator circuit configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; a second comparator circuit configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; a first logic circuit configured to receive the first comparison result, detect a first voltage transient of the phase node terminal based on the first comparison result indicating a first crossing of the first threshold, and detect an end of the first voltage transient based on the first comparison result indicating a second crossing of the first threshold, wherein the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold;The first active - passive discrimination circuit, which is configured to detect a first switching state of a high - side power switch, including whether the high - side power switch is in an on state or an off state. Wherein, the first active - passive discrimination circuit is configured to indicate to a first logic circuit whether a first voltage transient is an active voltage transient or a passive voltage transient based on the first switching state of the high - side power switch, and wherein the first logic circuit is configured to indicate a second crossing of a first threshold based on a first comparison result and adjust a first adaptive dead - time of the high - side power switch based on the first voltage transient being a passive voltage transient; A second logic circuit, which is configured to receive a second comparison result, detect a second voltage transient of a phase - node terminal based on the second comparison result indicating a first crossing of a second threshold, and detect the end of the second voltage transient based on the second comparison result indicating a second crossing of the second threshold, wherein the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold; And a second active - passive discrimination circuit, which is configured to detect a second switching state of a low - side power switch, including whether the low - side power switch is in an on state or an off state. Wherein, the second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switching state of the low - side power switch, wherein the second logic circuit is configured to indicate a second crossing of the second threshold based on the second comparison result and adjust a second adaptive dead - time of the low - side power switch based on the second voltage transient being a passive voltage transient, and wherein the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.;

[0009] In some implementations, a method for adjusting an adaptive dead time includes: generating, by a gate driver of a gate driver circuit, a drive signal configured to drive a power switch between an on state and an off state; sensing, by a capacitor, a voltage transient across the power switch, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to a slope of the voltage transient; generating, at a sense node coupled to the capacitor, a sensed value based on the capacitor current, wherein the sensed value is proportional to the slope of the voltage transient; comparing, by a comparator circuit, the sensed value with a threshold to generate a comparison result indicating whether the sensed value satisfies the threshold; detecting, by a logic circuit, a voltage transient based on the comparison result indicating a first crossing of the threshold; detecting, by the logic circuit, an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; generating, by an active-passive discrimination circuit, a status signal indicating whether the voltage transient is an active voltage transient or a passive voltage transient based on a switching state of the power switch; and adjusting, by the logic circuit, an adaptive dead time of the power switch based on the comparison result indicating a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0010] In some implementations, a power module includes: a high-side region that operates in a first voltage domain; a high-side power switch coupled to the high-side region, where the high-side power switch includes a first control terminal; a low-side region that operates in a second voltage domain lower than the first voltage domain; a low-side power switch coupled to the low-side region, where the low-side power switch includes a second control terminal; a first gate driver disposed in the high-side region and coupled to the first control terminal, where the first gate driver is configured to drive the high-side power switch between an on state and an off state using a first adaptive dead time provided during an off-state interval of the high-side power switch; a second gate driver disposed in the low-side region and coupled to the second control terminal, where the second gate driver is configured to drive the low-side power switch between an on state and an off state using a second adaptive dead time provided during an off-state interval of the low-side power switch, where the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, and where the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; a phase node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit disposed in the high-side region, where the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value representing a rate of change of a phase voltage present at the phase node terminal; a second sensing circuit disposed in the low-side region, where the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value representing a rate of change of the phase voltage present at the phase node terminal; a first comparator circuit configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; a second comparator circuit configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; a first logic circuit configured to receive the first comparison result, detect a first voltage transient of the phase node terminal based on the first comparison result indicating a first crossing of the first threshold, and detect an end of the first voltage transient based on the first comparison result indicating a second crossing of the first threshold, where the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold;A first active - passive discrimination circuit configured to detect a first switch state of a high - side power switch, including whether the high - side power switch is in an on state or an off state. The first active - passive discrimination circuit is configured to indicate to a first logic circuit whether a first voltage transient is an active voltage transient or a passive voltage transient based on the first switch state of the high - side power switch. And the first logic circuit is configured to indicate a second crossing of a first threshold based on a first comparison result and adjust a first adaptive dead - time of the high - side power switch based on the first voltage transient being a passive voltage transient. A second logic circuit configured to receive a second comparison result, detect a second voltage transient of a phase - node terminal based on the second comparison result indicating a first crossing of a second threshold, and detect an end of the second voltage transient based on the second comparison result indicating a second crossing of the second threshold, where the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold. And a second active - passive discrimination circuit configured to detect a second switch state of a low - side power switch, including whether the low - side power switch is in an on state or an off state. The second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switch state of the low - side power switch. The second logic circuit is configured to indicate a second crossing of the second threshold based on the second comparison result and adjust a second adaptive dead - time of the low - side power switch based on the second voltage transient being a passive voltage transient, and where the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Implementations are described herein with reference to the drawings.

[0012] Figure 1 A schematic block diagram of a motor control system according to one or more implementations is shown.

[0013] Figure 2 A schematic block diagram of a gate driver system according to one or more implementations is shown.

[0014] Figure 3A A circuit system according to one or more implementations is shown.

[0015] Figure 3B A circuit system according to one or more implementations is shown.

[0016] Figure 4A and Figure 4B A signal diagram corresponding to an adaptive dead - time for a low - side power switch according to one or more implementations is shown.

[0017] Figure 5 Shows a signal diagram corresponding to an adaptive dead time for a high-side power switch according to one or more implementations.

[0018] Figure 6 Shows a signal diagram corresponding to a dV / dt event corresponding to the turn-off of a high-side power switch according to one or more implementations.

[0019] Figure 7 Is a schematic block diagram of a dV / dt sensing and gate drive system according to one or more embodiments.

[0020] Figure 8 Is a schematic block diagram of a dV / dt sensing and gate drive system according to one or more embodiments. Detailed implementation

[0021] In the following, details are set forth to provide a more thorough description of example implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form or in schematic form rather than in detail, so as to avoid obscuring the implementations. Additionally, unless otherwise specifically noted, the features of the different implementations described below may be combined with each other.

[0022] Furthermore, in the following description, equivalent or similar elements or elements having equivalent or similar functions are denoted by equivalent or similar reference numerals. Since the same or functionally equivalent elements are given the same reference numerals in the drawings, the repeated description of the elements provided with the same reference numerals may be omitted. Therefore, the descriptions provided for elements having the same or similar reference numerals are interchangeable.

[0023] The orientations of the various elements in the drawings are shown by way of example, and the examples shown may be rotated relative to the depicted orientations. The description provided herein and the appended claims relate to any structure having the described relationships between the various features, regardless of whether the structure is in a particular orientation in the drawings or rotated relative to such an orientation. Similarly, for ease of description, the spatial relative terms such as "top", "bottom", "lower", "below", "under", "upper", "above", "middle", "left", and "right" are used herein to describe the relationship of one element to one or more other elements as shown in the drawings. The spatial relative terms are intended to cover different orientations of the element, structure, and / or component in use or operation in addition to the orientation depicted in the drawings. The structure and / or component may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In addition, for simplicity of the drawings, the cross-sectional views in the drawings only show the features within the cross-sectional plane and do not show the material behind the cross-sectional plane unless otherwise indicated.

[0024] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" relative to "directly between", "adjacent" relative to "directly adjacent", etc.).

[0025] In the implementations described or shown in the drawings herein, any direct electrical connection or coupling (e.g., any connection or coupling without additional intervening elements) can also be achieved by an indirect connection or coupling (e.g., a connection or coupling having one or more additional intervening elements), and vice versa, as long as the general purpose of the connection or coupling (e.g., transmitting a certain signal or transmitting a certain information) is substantially maintained. Features from different implementations can be combined to form additional implementations. For example, unless otherwise stated, the variations or modifications described with respect to one of the implementations can also be applied to other implementations.

[0026] As used herein, the terms "substantially" and "about" mean "within reasonable tolerances of manufacturing and measurement". For example, without departing from the aspects of the implementations described herein, the terms "substantially" and "about" can be used herein to account for small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry. For example, a resistor having an approximate resistance value can actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value can actually have a signal value within 5% of the approximate signal value.

[0027] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. may modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of the elements. Instead, such expressions are only for the purpose of distinguishing an element from other elements. For example, a first box and a second box indicate different boxes, although both are boxes. As another example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0028] A transistor may be referred to as a power switch, a logic switch, or a transistor switch that can be used to drive a current such as a load current. In particular, a power transistor is a power semiconductor device that can be used to drive a load current. The power transistor includes a first load terminal (e.g., source or emitter) and a second load terminal (e.g., drain or collector). Additionally, the load current path of the power transistor can be controlled by a control electrode (sometimes referred to as a gate) connected to the control terminal of the power transistor. The load current path of the power transistor is a gate-controlled conduction channel, the conductivity of which can be controlled by a control voltage applied to the control electrode of the power transistor. For example, the power transistor can be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage across the gate and source of a MOSFET will keep the MOSFET in its "on" state, while applying an approximately zero or slightly negative voltage across the gate and source of the MOSFET will turn the MOSFET "off".

[0029] There are turn-on and turn-off processes for turning on and off a transistor. During the turn-on process of an n-channel transistor, a gate driver can be used to supply (provide) a gate current (e.g., a turn-on current) to the gate of the n-channel transistor in order to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. Conversely, during the turn-off process of the n-channel transistor, the gate driver is used to draw (absorb) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor in order to sufficiently discharge the gate voltage to turn off the n-channel transistor. A voltage pulse can be output from the gate driver as a control signal according to a pulse width modulation (PWM) scheme. Thus, the control signal can switch between an on voltage level and an off voltage level during a PWM period for controlling the n-channel transistor. This in turn charges and discharges the gate capacitance to correspondingly modulate the gate voltage to turn on and off the n-channel transistor, respectively.

[0030] For a p-channel transistor, the situation is exactly the opposite. A gate driver can be used to sink (absorb) gate current (e.g., turn-on current) from the gate of the p-channel transistor in order to discharge the gate voltage to a voltage sufficient to turn on the p-channel transistor. Conversely, during the turn-off process of the p-channel transistor, the gate driver is used to source (supply) gate current (e.g., turn-off current) to the gate of the p-channel transistor in order to fully charge the gate voltage of the p-channel transistor to turn off the p-channel transistor. The control signal applied to the gate of the p-channel transistor can switch between a turn-on voltage level and a turn-off voltage level during a PWM period used to control the p-channel transistor. This in turn charges and discharges the gate voltage to turn on and turn off the p-channel transistor, respectively.

[0031] For both n-channel and p-channel transistors, the n-channel and p-channel transistors are turned off when the gate-source voltage Vgs is approximately zero or below the threshold voltage, and the n-channel and p-channel transistors are turned on when the gate-source voltage Vgs is equal to or greater than the threshold voltage.

[0032] To drive a load in this manner, two transistors are typically arranged in a half-bridge configuration and can form a converter leg of a power converter. The two transistors can include a high-side transistor and a low-side transistor coupled together at a phase node, at which a phase voltage (e.g., phase node voltage) is generated based on the switching states of the two transistors. The phase voltage is used to generate a phase current. The high-side transistor can be a p-channel transistor connected to a high-side supply potential, and the low-side transistor can be an n-channel transistor connected to a low-side supply potential. In some implementations, the high-side transistor and the low-side transistor can be of the same transistor type (e.g., both are n-channel type or both are p-channel type).

[0033] When the load current (e.g., phase current) flows from the half-bridge towards the load (e.g., from the phase node towards the load), the load current is referred to as a positive load current, and when the load current flows away from the load towards the half-bridge (e.g., from the load towards the phase node), the load current is referred to as a negative load current. When the high-side transistor is turned on, the high-side transistor is responsible for conducting the positive load current in order to supply the load current to the load while its complementary low-side transistor is turned off (e.g., the low-side transistor is in a blocking or high-impedance mode). To sink the load current from the load, the roles of the high-side transistor and the low-side transistor are reversed. Here, the low-side transistor is responsible for conducting the negative load current when turned on in order to sink the load current from the load while its complementary high-side transistor is turned off (e.g., the high-side transistor is in a blocking or high-impedance mode). The two complementary transistors are typically switched such that they are not turned on simultaneously.

[0034] The transistor may include an IGBT and a MOSFET (e.g., Si MOSFET or SiC MOSFET), among other examples. It should be understood that one type of transistor may replace another type of transistor. In this context, when a MOSFET replaces an IGBT, in any of the examples described herein, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, the drain-source voltage Vds of the MOSFET may replace the collector-emitter voltage Vce of the IGBT, and the gate-source voltage Vgs of the MOSFET may replace the gate-emitter voltage Vge of the IGBT, or vice versa.

[0035] Some implementations described in the present disclosure relate to, but are not limited to, a half-bridge for driving a motor. For example, a multiphase converter, as a type of power converter, is configured to provide multiphase power by supplying power to a multiphase load (e.g., a three-phase motor). For example, three-phase power involves three symmetric sine waves that are out of phase with each other by 120 electrical degrees. In a symmetric three-phase power supply system, three conductors each carry an alternating current (AC) having the same frequency and voltage amplitude with respect to a common reference but a phase difference of one-third of the drive period. Due to the phase difference, the voltage on any one of the three conductors reaches its voltage peak at one-third of the drive period, where the voltage peaks of the three conductors are distributed with a substantially equal phase delay from each other within the drive period. This phase delay gives a constant power transfer to a balanced linear load. This also makes it possible to generate a rotating magnetic field in a motor.

[0036] The three-phase converter includes three converter legs, one for each of the three phases, and each converter leg is connected in parallel with the other converter legs to a direct current (DC) voltage source. As described above, each converter leg includes a pair of transistors arranged in a half-bridge configuration for converting DC to AC to drive a phase load. However, the multiphase converter is not limited to three phases and may include two phases or more than three phases, each phase having a converter leg. In some instances, two half-bridges may be connected as an H-bridge circuit, where a load (e.g., a motor) is connected as a cross-switch between the two half-bridges as a single-phase load.

[0037] Dead time is typically implemented in gate driver technology to ensure that two complementary transistors in a half-bridge circuit do not conduct simultaneously. Thus, dead time is the delay between the turn-off event of one of the two complementary transistors and the turn-on event of the other of the two complementary transistors. Reverse conduction losses caused by excessive dead time can significantly affect the efficiency of a power converter. Wide bandgap (WBG) devices, such as silicon carbide (SiC) and gallium nitride (GaN) transistors, suffer higher reverse conduction losses and current handling capabilities compared to their channel conduction. Additionally, GaN devices exhibit a low threshold voltage of 1V compared to SiC devices with a threshold voltage of approximately 3.5V. Thus, negative gate voltage is used to increase noise immunity (e.g., immunity to spurious power switch turn-on caused by current injection from the Miller capacitance on the gate). However, the source-drain voltage (VSD) of GaN devices increases with the magnitude of the negative gate voltage, which results in increased reverse conduction of GaN devices. VSD is the negative voltage drop between the drain and source of a GaN transistor device. Thus, a shorter dead time can reduce reverse conduction losses that lead to system power losses and lower power efficiency. However, dead time is typically pre-programmed and fixed, or requires a complex control system.

[0038] Some implementations disclosed herein relate to an adaptive dead time circuit and method that adjusts (e.g., tunes) an adaptive dead time based on an evaluation of the rate of change of a voltage transient dV / dt present at the load end of a power switch (e.g., a power transistor), including detecting two threshold crossings of the voltage transient dV / dt in opposite directions, and determining whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on whether the power switch is off at the start of the voltage transient dV / dt. The voltage transient dV / dt can correspond to the voltage across the power switch or the voltage at a phase node terminal (e.g., a phase voltage). For example, the voltage transient dV / dt can be the drain-source voltage V of the power switch DS transient. A voltage transient dV / dt measurement can be obtained and compared to a threshold to detect the two threshold crossings. Thus, the adaptive dead time circuit can include dV / dt sensing for quickly detecting threshold crossings. The adaptive dead time circuit can implement a low-cost design. Thus, the adaptive dead time circuit can adjust the adaptive dead time within the same switching cycle as the voltage transient dV / dt to provide an optimized (e.g., shortest) dead time that minimizes reverse conduction losses. Additionally, the adaptive dead time circuit can perform an evaluation for each switching cycle and perform an adjustment of the adaptive dead time for each switching cycle. Thus, each dead time interval of the switching scheme can be optimized.

[0039] Figure 1FIG. 0 shows a schematic block diagram of a motor control system 100 according to one or more implementations. In particular, the motor control system 100 includes a power converter 102, a controller 104, and a gate driver system 106. The controller 104 and the gate driver system 106 may work together as a motor control unit. In some implementations, the motor control unit may be a monolithic integrated circuit (IC), where the controller 104 and the gate driver system 106 are arranged on a single IC. "Monolithic" refers to an IC or semiconductor device fabricated on a single chip of a single material (usually silicon). The IC is called "monolithic" because all active and passive components of the circuit, such as transistors, resistors, capacitors, and interconnects, are integrated onto a single piece or material substrate. In some implementations, the motor control unit may be divided into two or more ICs. For example, where the controller 104 is arranged on a first IC, and the gate driver system 106 is arranged on one or more second ICs. Thus, the gate driver system 106 may be a monolithic gate driver. It should be understood that although the implementations described herein relate to driving a motor, the concepts described herein may be extended to other types of inductive loads and are not limited to motors.

[0040] The motor control system 100 is also coupled to a motor M (e.g., a permanent magnet synchronous motor (PMSM) as an AC motor) including three phases U, V, and W. The power converter 102 in this example is a three-phase voltage generator configured to supply three-phase power by supplying three-phase voltages to drive the motor M.

[0041] Deviations in amplitude and phase may result in power and torque losses in the motor M. Thus, the controller 104 may be configured to monitor and control in real time the amplitude and phase of the voltage supplied to the motor M to ensure an appropriate current balance is maintained based on a feedback control loop.

[0042] The power converter 102 for the electric machine M includes a switch array of six transistors 108u, 108v, 108w, 109u, 109v, and 109w arranged in complementary pairs. Each complementary pair forms a half-bridge circuit and constitutes one converter leg for supplying a phase voltage to the electric machine M. Thus, each converter leg includes a high-side transistor 108u, 108v, or 108w and a low-side transistor 109u, 109v, or 109w. Additionally, each of the transistors 108u, 108v, 108w, 109u, 109v, and 109w may be anti-parallel connected to a corresponding freewheeling diode D1 to D6. The freewheeling diodes D1 to D6 provide an alternative current path for the load current for current commutation during the turn-off of the respective transistors 108u, 108v, 108w, 109u, 109v, and 109w. For example, the freewheeling diode D1 provides an alternative current path with respect to the low-side transistor 109u during the turn-off of the low-side transistor 109u. Similarly, the freewheeling diode D2 provides an alternative current path with respect to the high-side transistor 108u during the turn-off of the high-side transistor 108u.

[0043] Load current paths U, V, and W extend from output disks Uout, Vout, or Wout of each converter leg (e.g., the output of each half-bridge circuit) located between complementary transistors and are configured to be coupled to a load, such as the electric machine M. Each load current path U, V, and W carries a corresponding phase current Iu, Iv, and Iw. Each phase current Iu, Iv, and Iw has an AC electrical frequency that directly corresponds to the actual motor speed of the electric machine M.

[0044] The power converter 102 is coupled to a DC power source (e.g., a battery or a diode bridge rectifier) and is coupled to a gate driver system 106.

[0045] The controller 104 can be a microcontroller or other hardware-based controller that executes the motor control functions of the motor control system 100 in real time (or near real time) and transmits PWM control signals to the gate driver system 106. The controller 104 can adopt a PWM scheme to control the states of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V, and W. The gate driver system 106 generates driver signals for controlling the switching states (e.g., on and off states) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w based on the PWM control signals. Therefore, the load current paths U, V, and W can be controlled by the controller 104 and the gate driver system 106 by controlling the control electrodes (e.g., gate electrodes) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. For example, when receiving the PWM control signal from the controller 104, the gate driver system 106 can set the corresponding transistor 108u, 108v, 108w, 109u, 109v, or 109w to one of the on states (e.g., conducting state) or off states (e.g., blocking state).

[0046] The gate driver system 106 can include one or more gate drivers for driving the transistors 108u, 108v, 108w, 109u, 109v, and 109w between switching states. For example, the gate driver system 106 can include gate drivers for each half-bridge circuit. The gate driver system 106 can be configured to receive instructions including PWM control signals from the controller 104 and turn on and off the transistors 108u, 108v, 108w, 109u, 109v, and 109w respectively according to the received instructions and control signals. For example, during the conduction process of the transistors 108u, 108v, 108w, 109u, 109v, or 109w, the gate driver system 106 can be used to supply gate current to the gates of the transistors 108u, 108v, 108w, 109u, 109v, or 109w to charge the gates. Conversely, during the turn-off process, the gate driver system 106 can be used to draw gate current from the gates of the transistors 108u, 108v, 108w, 109u, 109v, or 109w to discharge the gates.

[0047] In addition, the transistors 108u, 108v, 108w, 109u, 109v, and 109w of the power converter 102 are controlled such that the high-side and low-side transistors in the same converter leg are not simultaneously turned on at any time; otherwise, the DC power supply would be short-circuited. This requirement can be met by complementary operation of the transistors 108u, 108v, 108w, 109u, 109v, and 109w within the converter leg according to the motor control algorithm. For example, during operation, the motor M can be driven according to the motor control algorithm to achieve a desired motor speed corresponding to the electrical frequency of the control signal. A dead time can be imposed by the controller 104, during which both the high-side and low-side transistors of the same converter leg are turned off simultaneously.

[0048] As indicated above, Figure 1 is provided only as an example. Other examples may be different from the example described with respect to Figure 1 For example, in some implementations, the multiple motor phases may be different, or two half-bridges may be connected as an H-bridge circuit. In some implementations, additional circuit components may be added without departing from the disclosure provided above.

[0049] Figure 2 FIG. shows a schematic block diagram of a gate driver system 200 according to one or more implementations. The gate driver system 200 may correspond to Figure 1 the gate driver system 106 of. As Figure 2 shown, the gate driver system 200 includes a single-phase motor drive stage 201 (e.g., a converter leg or a half-bridge circuit) and a gate driver 206 electrically coupled to the single-phase motor drive stage 201. The gate driver system 200 may be a half-bridge gate driver circuit and may be replicated for each converter leg in the gate driver system 200. Additionally, the gate driver system 200 may be integrated with power switches (e.g., high-side power transistors and low-side power transistors) into an intelligent power module (IPM). In other words, the gate driver system 200 and the power switches may be disposed in a housing and may be arranged on an application circuit board. The housing may include external pins for providing external connections to the gate driver system 200 and the power switches, including power connections, control connections, and / or data connections.

[0050] The single-phase motor drive stage 201 includes a high-side transistor 208u and a low-side transistor 209u, which are controlled to supply a load current I to the motor M LOAD . In other words, the single-phase motor drive stage 201 in this example corresponds to the U-phase converter leg of the motor M described with respect to Figure 1 . However, the single-phase motor drive stage 201 may correspond to any converter leg in the motor control system 100.

[0051] The gate driver 206 is a monolithic gate driver that includes a low-side gate driver 210 for driving the low-side transistor 209u and a high-side gate driver 220 for driving the high-side transistor 208u. Both the low-side gate driver 210 and the high-side gate driver 220 perform gate driving of their respective low-side transistor 209u and high-side transistor 208u based on the PWM control signals LIN and HIN received from a controller such as the controller 104.

[0052] The PWM control signals are received from the controller 104 at the PWM logic unit 225 of the gate driver 206. The PWM logic unit 225 receives the PWM control signals LIN and HIN from the controller 104 and ensures that a minimum dead time is achieved during which both the high-side transistor 208u and the low-side transistor 209u are turned off simultaneously. Finally, the PWM control signals LIN and HIN are passed to the respective low-side gate driver 210 and high-side gate driver 220. In some implementations, the PWM control signal HIN provided to the high-side gate driver 220 may pass through a level converter 230. The level converter 230 is used to convert (e.g., level-shift) the PWM control signal HIN and thus transfer control information from the low-voltage power domain of the gate driver 206 to the high-voltage power domain. Thereafter, the low-side gate driver 210 and the high-side gate driver 220 perform gate driving.

[0053] The low-side gate driver 210 and the high-side gate driver 220 respectively include separate pre-driver circuitry 240 and 250 and buffers 245 and 255. The pre-driver circuitry 240 and 250 are configured to receive the PWM control signals LIN and HIN signals and, based on the PWM control signals LIN and HIN signals, control the on / off states of the respective first current sources (such as supply field effect transistors (FETs)) for generating the current Io+. Additionally, the pre-driver circuitry 240 and 250 are configured to receive the PWM control signals LIN and HIN and, based on the PWM control signals LIN and HIN, control the on / off states of the respective second current sources (such as sink FETs) for generating the current Io-. The respective current sources are provided in the buffers 245 and 255. Thus, the buffers 245 and 255 may each include a pair of complementary FETs for generating the turn-on current Io+ and the turn-off current Io- for the respective low-side transistor 209u and high-side transistor 208u.

[0054] Each of the pre-driver circuitry systems 240 and 250 may also include a regulator configured to control the magnitudes of the turn-on current Io+ and the turn-off current Io- by controlling current sources in the buffers 245 and 255. In other words, each regulator commands the corresponding buffers 245 and 255 to use a specific current capability.

[0055] The gate driver 206 may be configured to receive a PWM control signal from the controller 104 and turn on or off the corresponding high-side transistor 208u and low-side transistor 209u according to the received PWM control signal. For example, during the turn-on process of the high-side transistor 208u and the low-side transistor 209u, the gate driver 206 may be used to supply a gate current Io+ to the gate of one of the high-side transistor 208u or the low-side transistor 209u to charge the gate. Conversely, during the turn-off process, the gate driver 206 may be used to draw a gate current Io- from the gate of one of the high-side transistor 208u or the low-side transistor 209u to discharge the gate.

[0056] Therefore, the controller 104 is electrically coupled to the gate driver 206 to transmit information and control signals therebetween, and the gate driver 206 is electrically coupled to the single-phase motor drive stage 201 to drive the high-side transistor 208u and the low-side transistor 209u.

[0057] The gate driver 206 may include a high-side circuitry disposed in the high-voltage power domain and configured to monitor and detect a short-circuit event corresponding to the high-side transistor 208u. The high-side circuitry may be used to trigger the high-side transistor 208u to turn off based on the detected short-circuit event corresponding to the high-side transistor 208u. Additionally, the gate driver 206 may include a low-side circuitry disposed in the low-voltage power domain and configured to monitor and detect a short-circuit event corresponding to the low-side transistor 209u. The low-side circuitry may be used to trigger the low-side transistor 209u to turn off based on the detected short-circuit event corresponding to the low-side transistor 209u.

[0058] The gate driver system 200 may also include a bootstrap diode 260 to charge the voltage charging device 270. In this case, the voltage charging device 270 is a bootstrap capacitor. However, the voltage charging device 270 may be a rechargeable battery or other types of voltage charging devices.

[0059] Additionally, in Figure 2Here, VB refers to the high-side floating power supply voltage; VS refers to the high-side floating ground voltage, which can also be referred to as the phase voltage or phase node voltage; VCC refers to the low-side fixed power supply voltage; VSS refers to the low-side ground voltage; HO refers to the output terminal for the high-side floating output voltage; LO refers to the output terminal for the low-side output voltage; DC+ refers to the positive power supply of the DC link; DC- refers to the negative power supply of the DC link; and HIN and LIN refer to the PWM control signals (e.g., logic input voltages) received from the controller 104. The low-side fixed power supply voltage VCC also supplies power to certain logic components of the gate driver 206 that operate using the fixed power supply voltage, and can be used to charge the voltage charging device 270 when the bootstrap diode 260 is forward-biased.

[0060] Generally, VB = VCC - VS - VD, where VD is the forward bias voltage drop across the bootstrap diode 260. As an example implementation, when the low-side fixed power supply voltage VCC is equal to 15V, the high-side floating ground voltage VS is equal to 0V, and the bootstrap diode 260 is forward-biased and has a forward bias voltage drop VD = 0.5V, then VB = 15V - 0V - 0.5V = 14.5V. That is, during normal operation, since the voltage charging device 270 supplies power to the high side of the gate driver 206, the high-side floating power supply voltage VB is approximately 15V higher than the high-side floating ground voltage VS. For example, the positive power supply rail that provides the DC link positive power supply DC+ can be in the range of 200V to 1200V, but is not limited thereto. In addition, when the low-side transistor 209u is conducting (and the high-side transistor 208u is off), the high-side floating ground voltage VS is equal to DC- (e.g., VSS or 0V). As shown, the negative power supply rail provides the DC link negative power supply DC-, and can be shorted to VSS, but is not required to be. In this case, the high-side floating power supply voltage VB is close to 15V, and the voltage charging device 270 is charged by the low-side fixed power supply voltage VCC through the bootstrap diode 260. Otherwise, when the high-side transistor 208u is conducting (and the low-side transistor 209u is off) and the bootstrap diode 260 is reverse-biased and non-conducting, the high-side floating ground voltage VS is equal to the DC link positive power supply DC+. In the case where the bootstrap diode 260 is reverse-biased, the high-side floating power supply voltage VB is 15V higher than the DC link positive power supply DC+, and the voltage charging device 270 discharges slowly. It should be understood that certain circuit values and device parameters used herein are examples for illustrative purposes of one or more possible implementations among many possible implementations, and should not be considered to limit or require in any way unless explicitly stated.

[0061] The above voltage is set such that the high-side voltage domain of the gate driver 206 operates in a higher voltage or power domain than the voltage or power domain of the low-side voltage domain of the gate driver 206. For example, when the DC link positive power supply DC+ is 1200V, the low-side fixed power supply voltage VCC can be set to 15V, and the high-side floating power supply voltage VB can operate at a maximum voltage of 1215V.

[0062] The gate driver 206 is configured to receive instructions from the controller 104 to drive a motor phase (e.g., single-phase motor drive stage 201) connected to the high-side floating ground voltage VS using PWM control signals. These PWM control signals, depicted as PWM control signals HIN and LIN, are received by the gate driver 206 and transmitted to the high-side gate driver 220 and the low-side gate driver 210 via appropriate logic (e.g., PWM logic unit 225 for the low-side gate driver 210 and level converter 230 for the high-side gate driver 220). The low-side gate driver 210 is configured to receive the PWM control signal LIN, and the high-side gate driver 220 is configured to receive the PWM control signal HIN, and drive the low-side transistor 209u and the high-side transistor 208u using the output terminals HO and LO of the gate driver 206, respectively.

[0063] As indicated above, Figure 2 is provided only as an example. Other examples may be different from the example described with respect to Figure 2 For example, in some implementations, the high-side gate driver 220 may receive the PWM control signal directly from the controller 104. In some implementations, the bootstrap diode 260 may be located outside the gate driver 206. In some implementations, the low-side ground voltage VSS may be connected to a power supply potential different from the ground potential. In some implementations, additional circuit components may be added without departing from the disclosure provided above.

[0064] Figure 3A A circuit system 300A according to one or more implementations is shown. The circuit system 300A may be integrated in a half-bridge gate driver circuit. For example, the circuit system 300A may be integrated into a half-bridge gate driver circuit similar to the gate driver system 200 described in connection with Figure 2 Additionally or alternatively, the circuit system 300A may be integrated into an IPM together with a power switch. In Figure 3A a high-side circuit system and a low-side circuit system for adjusting the adaptive dead time of the high-side power switch and the adaptive dead time of the low-side power switch are shown.

[0065] The circuit system 300A may include a phase node terminal 302, which is coupled to or configured to be coupled to a phase node (e.g., output disk Uout), and a high-side transistor 208u and a low-side transistor 209u are coupled to the phase node. A phase voltage Vs may be generated at the phase node according to the switching operations of the high-side transistor 208u and the low-side transistor 209u. If the high-side transistor 208u is turned on by the high-side gate driver 220, the phase node terminal 302 may be connected to the high-side power potential (e.g., DC+) through the high-side transistor 208u, and if the low-side transistor 209u is turned on by the low-side gate driver 210, the phase node terminal 302 may be connected to the low-side power potential (e.g., DC-) through the low-side transistor 209u.

[0066] The low-side transistor 209u is a complementary transistor of the high-side transistor 208u. The dead time applied to the high-side transistor 208u is the delay or time interval between the turn-off event of the low-side transistor 209u and the turn-on event of the high-side transistor 208u. The delay can be adjusted or tuned to optimize (e.g., minimize) the dead time and minimize the reverse conduction loss. A turn-off event is the transition of a transistor from an on state to an off state, and a turn-on event is the transition of a transistor from an off state to an on state.

[0067] Additionally, the high-side transistor 208u is a complementary transistor of the low-side transistor 209u. The dead time applied to the low-side transistor 209u is the delay or time interval between the turn-off event of the high-side transistor 208u and the turn-on event of the low-side transistor 209u. The delay can be adjusted or tuned to optimize (e.g., minimize) the dead time and minimize the reverse conduction loss.

[0068] The circuit system 300A may include a capacitor HVC cross-coupled to the high-side region and the low-side region of the circuit system 300A. The capacitor HVC may be a high-voltage capacitor. In some implementations, more than one capacitor may be cross-coupled to the high-side region and the low-side region. Thus, at least one capacitor cross-coupled to the high-side region and the low-side region is provided. The capacitor HVC may provide a capacitor current Icap that is proportional to the magnitude of the voltage slope of the phase voltage VS. In other words, the capacitor current Icap is proportional to the steepness or rate of change of the voltage transient dV / dt of the phase voltage VS. Since the DC link voltages DC+ and DC- are fixed, the voltage transient dV / dt of the phase voltage also corresponds to the corresponding voltage transients of the high-side transistor 208u and the low-side transistor 209u. For example, the voltage transient across the high-side transistor 208u DS is proportional to or equal to the voltage transient dV / dt of the phase voltage VS. Additionally, the voltage across the low-side transistor 209u DSis proportional to or equal to the voltage transient dV / dt of the phase voltage VS.

[0069] Therefore, the capacitor current Icap can be based on the rate of change of the voltage V across the high-side transistor 208u and / or can be based on the rate of change of the voltage V across the low-side transistor 209u. DS For example, the capacitor current Icap can be proportional to the magnitude of the voltage slope of the voltage V across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u. DS Therefore, the capacitor HVC can be used to sense and measure the voltage transient of the phase voltage VS, the voltage transient of the voltage V across the high-side transistor 208u, and / or the voltage transient of the voltage V across the low-side transistor 209u. DS across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u. DS across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u. DS across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u. DS across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u.

[0070] The circuit system 300A can include a first adaptive dead-time circuit 304 disposed in the high-side region of the circuit system 300A and a second adaptive dead-time circuit 306 disposed in the low-side region of the circuit system 300A. The first adaptive dead-time circuit 304 is coupled to a first corresponding capacitor among at least one capacitor and is configured to provide a first sensed value representing the voltage transient of the phase voltage VS present at the phase node. Alternatively, the first sensed value can represent the voltage transient of the voltage V across the high-side transistor 208u. In this example, the first corresponding capacitor is the capacitor HVC. The first sensed value can be a first sensed voltage HVsense provided at the first sensing node 308. Alternatively, the first sensed value can be a first sensed current corresponding to (e.g., proportional to) the capacitor current Icap. In some implementations, the first sensed current can be the same current as the capacitor current Icap. The capacitor HVC can sense the voltage transient dV / dt of the phase voltage VS and provide a capacitor current Icap proportional to the slope of the voltage transient, and the capacitor current Icap can be configured to generate a first sensed value at the first sensing node 308. DS across the high-side transistor 208u and can be proportional to the magnitude of the voltage slope of the voltage V across the low-side transistor 209u.

[0071] The second adaptive dead-time circuit 306 can be coupled to a second corresponding capacitor among at least one capacitor and is configured to provide a second sensed value representing the voltage transient of the phase voltage VS present at the phase node. Alternatively, the second sensed value can represent the voltage transient of the voltage V across the low-side transistor 209u. DSVoltage transients. In this example, the second corresponding capacitor is capacitor HVC. The second sensed value can be the second sensed voltage LVsense provided at the second sensing node 310. Alternatively, the second sensed value can be a second sensed current corresponding to (e.g., proportional to) the capacitor current Icap. In some implementations, the second sensed current can be the same current as the capacitor current Icap.

[0072] Although the first corresponding capacitor and the second corresponding capacitor are shown as the same capacitor (e.g., capacitor HVC) in this example, the first corresponding capacitor and the second corresponding capacitor can be different capacitors that are serially coupled or coupled to different sensing paths. The first adaptive dead time circuit 304 can include a first Zener diode 312 and a first sense resistor 314 that are coupled in parallel between the first internal positive power supply voltage Vdd_HS (e.g., provided by the first local voltage supply) and the first sensing node 308. The first sense resistor 314 can be configured to receive at least a portion of the capacitor current Icap and generate a first sensed voltage HVsense at the first sensing node 308 based on the portion of the capacitor current Icap flowing through the first sense resistor 314. The first sense resistor 314 can be a single resistor or multiple resistors arranged in different ways.

[0073] The first Zener diode 312 and the first sense resistor 314 can form a first sensing circuit that is coupled to the capacitor HVC and is configured to provide a first sensed voltage HVsense at the first sensing node 308, where the first sensed voltage HVsense represents the rate of change of the voltage present at the load end of the high-side transistor 208u (e.g., at the phase node terminal 302).

[0074] The high-side gate driver 220 can be configured to be coupled to the first internal positive power supply voltage Vdd_HS and the first internal ground voltage. For example, the high-side gate driver 220 can use the first internal positive power supply voltage Vdd_HS and the first internal ground voltage to drive the high-side transistor 208u between an on state and an off state. In some implementations, the first internal positive power supply voltage Vdd_HS can be derived from the high-side floating power supply voltage VB, and the first internal ground voltage can be derived from the phase voltage VS (e.g., the high-side floating ground voltage).

[0075] The first adaptive dead-time circuit 304 may further include a first reference source 316 and a first comparator circuit 318 (e.g., a voltage comparator or a current comparator). The first reference source 316 may generate a first threshold Th1 as a threshold voltage. In some implementations, the first threshold Th1 may be generated to be a predetermined amount smaller or higher than the first internal positive supply voltage Vdd_HS according to the first internal positive supply voltage Vdd_HS. In an implementation where the first comparator circuit 318 is a current comparator, the first reference source 316 may be a current source for providing the first threshold Th1 as a threshold current to the first comparator circuit 318.

[0076] When the phase voltage VS is in a steady state, the first sensing circuit may generate a first sensed value (e.g., a first sensed voltage HVsense or a first sensed current) at a steady-state value. For example, when the phase voltage VS is in a steady state, the rate of change of the phase voltage VS (e.g., the rate of change of dV / dt) is zero. Therefore, the first sensed voltage HVsense is also at a steady-state value, which may be set to the first internal positive supply voltage Vdd_HS. In some implementations, the steady-state value of the first sensed voltage HVsense may be a predetermined amount larger than the first threshold Th1. For example, the steady-state value of the first sensed voltage HVsense may be 5V (e.g., Vdd_HS = 5V), and the first threshold Th1 may be set to 4.8V. In some implementations, the steady-state value of the first sensed voltage HVsense may be a predetermined amount smaller than the first threshold Th1. For example, the steady-state value of the first sensed voltage HVsense may be 5V (e.g., Vdd_HS = 5V), and the first threshold Th1 may be set to 5.2V.

[0077] The first comparator circuit 318 may compare the first sensed value (e.g., the first sensed voltage HVsense or the first sensed current) with the first threshold Th1, and may generate a first comparison result based on whether the first sensed value satisfies the first threshold Th1. For example, the first comparator circuit 318 may generate a logic high output when the first sensed value is equal to or greater than the first threshold Th1, and may generate a logic low output when the first sensed value is less than the first threshold Th1.

[0078] The first adaptive dead-time circuit 304 may further include a first active-passive discrimination circuit 320 and a first logic circuit 322. The first adaptive dead-time circuit 304 may detect the occurrence of a dV / dt event corresponding to the turn-off of the low-side transistor 209u, and may also detect the moment when the dV / dt event ends. Thus, the first adaptive dead-time circuit 304 may detect the start and the end of the dV / dt event. The first adaptive dead-time circuit 304 may trigger the end of the adaptive dead-time of the high-side transistor 208u based on (e.g., in response to) detecting the end of the dV / dt event of the low-side transistor 209u.

[0079] A change in the output state of the first comparator circuit 318 may indicate a threshold crossing of the first threshold Th1. During the turn-off event of the low-side transistor 209u, the first sense voltage HVsense deviates from the steady-state value. For example, at the start of the dV / dt event, the first sense voltage HVsense may undergo a falling transition and cross the first threshold Th1. Crossing the first threshold Th1 during the falling transition may cause the output of the first comparator circuit 318 to change from a logic high value to a logic low value, thereby indicating the start of the dV / dt event. When the phase voltage VS enters the steady state, the dV / dt event ends. Thus, at the end of the dV / dt event, the first sense voltage HVsense may return to the steady-state value. In other words, at the end of the dV / dt event, the first sense voltage HVsense may undergo a rising transition and cross the first threshold Th1 again - this time from the opposite direction. Crossing the first threshold Th1 during the rising transition may cause the output of the first comparator circuit 318 to change from a logic low value to a logic high value, thereby indicating the end of the dV / dt event. In some implementations, the start of the dV / dt event may be indicated by a rising transition of the first sense voltage HVsense, and the end of the dV / dt event may be indicated by a falling transition of the first sense voltage HVsense.

[0080] The first logic circuit 322 may include one or more logic gates, one or more processors, or a combination of one or more logic gates and one or more processors. The first logic circuit 322 may detect that a dV / dt event (e.g., a voltage transient dV / dt) is occurring based on the first comparison result indicating that the first sensed voltage HVsense satisfies the first threshold Th1, and may detect that a dV / dt event (e.g., a voltage transient dV / dt) is not occurring based on the first comparison result indicating that the first sensed voltage HVsense does not satisfy the first threshold Th1. The first logic circuit 322 may receive the first comparison result of the first comparator circuit 318 for monitoring and detecting a dV / dt event corresponding to the turn-off of the low-side transistor 209u. For example, the first logic circuit 322 may detect a voltage transient dV / dt of the phase voltage VS (or the voltage at the load end) based on the first comparison result indicating a first crossing of the first threshold Th1, and may detect the end of the voltage transient dV / dt of the phase voltage VS (or the voltage at the load end) based on the first comparison result indicating a second crossing of the first threshold Th1. Here, the second crossing occurs after the first crossing and in the opposite direction to the first crossing. Thus, the first logic circuit 322 may detect the start of the dV / dt event based on the first crossing of the first threshold Th1, and may detect the end of the dV / dt event based on the second crossing of the first threshold Th1.

[0081] In some implementations, the first comparator circuit 318 may directly detect the start and end of the voltage transient dV / dt and pass the information to the first logic circuit 322. For example, the first logic circuit 322 may process the first comparison result (e.g., the comparator output) of the first comparator circuit 318 and detect the start and end of the voltage transient dV / dt according to the first comparison result of the first comparator circuit 318. Thus, the first comparison result of the first comparator circuit 318 may indicate the start of the voltage transient dV / dt and may also indicate the end of the voltage transient dV / dt.

[0082] When the first threshold Th1 is less than the steady-state value of the first sensed voltage HVsense, the first crossing of the first threshold Th1 may correspond to the falling edge of the first sensed voltage HVsense, and the second crossing of the first threshold Th1 may correspond to the rising edge of the first sensed voltage HVsense. Turning off a complementary transistor (e.g., the low-side transistor 209u) coupled to the load end of the high-side transistor 208u may cause a voltage transient dV / dt and cause the first sensed voltage HVsense to satisfy the first threshold Th1 by making the first sensed voltage HVsense less than the first threshold Th1.

[0083] Alternatively, when the first threshold Th1 is greater than the steady-state value of the first sense voltage HVsense, the first crossing of the first threshold Th1 may correspond to the rising edge of the first sense voltage HVsense, and the second crossing of the first threshold Th1 may correspond to the falling edge of the first sense voltage HVsense. Turning off the complementary transistor (e.g., the low-side transistor 209u) coupled to the load terminal of the high-side transistor 208u may cause a voltage transient dV / dt and cause the first sense voltage HVsense to satisfy the first threshold Th1 by making the first sense voltage HVsense greater than the first threshold Th1.

[0084] In addition, the first active-passive discrimination circuit 320 may detect the switching state of the high-side transistor 208u, including whether the high-side transistor 208u is in the on state or the off state. For example, the first active-passive discrimination circuit 320 may monitor the gate voltage of the high-side transistor 208u, the PWM control signal HIN, or the output terminal HO of the high-side transistor 208u to determine the switching state of the high-side transistor 208u. The first active-passive discrimination circuit 320 may indicate to the first logic circuit 322 whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the high-side transistor 208u. For example, if the high-side transistor 208u is in the on state at the start of the voltage transient dV / dt, the first active-passive discrimination circuit 320 may determine that the voltage transient dV / dt is an active voltage transient, and if the high-side transistor 208u is in the off state at the start of the voltage transient dV / dt, the first active-passive discrimination circuit 320 may determine that the voltage transient dV / dt is a passive voltage transient. In some implementations, the first active-passive discrimination circuit 320 may receive the first comparison result of the first comparator circuit 318 and detect the first crossing of the first threshold Th1 as an indication of the start of the voltage transient dV / dt. Based on (e.g., in response to) detecting the start of the voltage transient dV / dt, the first active-passive discrimination circuit 320 may evaluate the switching state of the high-side transistor 208u and determine whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the high-side transistor 208u. In other words, the first active-passive discrimination circuit 320 may receive the first comparison result, detect the voltage transient dV / dt based on the first comparison result indicating the first crossing of the first threshold Th1, and determine whether the voltage transient dV / dt corresponding to the first crossing of the first threshold Th1 is an active voltage transient or a passive voltage transient based on the switching state of the high-side transistor 208u. The first active-passive discrimination circuit 320 may indicate to the first logic circuit 322 with a logic high output that the voltage transient dV / dt is an active voltage transient and with a logic low output that the voltage transient dV / dt is a passive voltage transient, and vice versa.

[0085] Therefore, the first active - passive discrimination circuit 320 can determine the active / passive nature of the voltage transient dV / dt by monitoring the state of the power switch (e.g., by monitoring PWM, HIN, or HO) and by monitoring the comparator output of the first comparator circuit 318 (e.g., the first comparison result). The first comparator circuit 318 can detect the presence of the voltage transient dV / dt and generate a square pulse representing the voltage transient dV / dt. The first active - passive discrimination circuit 320 can check whether the voltage transient dV / dt occurs during the dead - time period by checking the conduction state via PWM, HIN, or HO. Finally, the first active - passive discrimination circuit 320 can discriminate whether the voltage transient dV / dt is active or passive.

[0086] The first logic circuit 322 can adjust the adaptive dead - time of the high - side transistor 208u based on the first comparison result of the first comparator circuit 318 indicating a second crossing of the first threshold Th1 and based on the first active - passive discrimination circuit 320 indicating that the voltage transient is a passive voltage transient - which occurs when the high - side transistor 208u is in the off state at the start of the voltage transient dV / dt (e.g., at the first crossing of the first threshold Th1).

[0087] Based on the first active - passive discrimination circuit 320 indicating that the voltage transient dV / dt is a passive voltage transient and in response to the first comparison result of the first comparator circuit 318 indicating a second crossing of the first threshold Th1, the first logic circuit 322 can trigger the high - side transistor 208u to switch from the off state to the on state, thus ending the current dead - time of the high - side transistor 208u. Therefore, the first logic circuit 322 can trigger the end of the current dead - time only when the voltage transient dV / dt is a passive voltage transient. If the voltage transient dV / dt is an active voltage transient, the default duration can be used for the current dead - time. The first logic circuit 322 can trigger the end of the current dead - time by generating a trigger signal ADTtrigger_HS. The first logic circuit 322 can provide the trigger signal ADTtrigger_HS to the driver stage of the high - side gate driver 220. Additionally or alternatively, the first logic circuit 322 can provide the trigger signal ADTtrigger_HS to the controller 104 to initiate the switch of the high - side transistor 208u from the off state to the on state.

[0088] Accordingly, the first logic circuit 322 can adjust the adaptive dead time of the high-side transistor 208u based on detecting a second crossing of the first threshold Th1 and based on the voltage transient dV / dt being a passive voltage transient. The adaptive dead time can be adjusted based on the timing of the second crossing of the first threshold Th1. For example, the first logic circuit 322 can trigger the end of the current dead time in response to detecting the second crossing of the first threshold Th1. Accordingly, since the second crossing of the first threshold Th1 can fluctuate for each switching cycle, the first logic circuit 322 can adjust the adaptive dead time for each switching cycle. By triggering the end of the current dead time in response to detecting the second crossing of the first threshold Th1, the first logic circuit 322 can minimize the adaptive dead time.

[0089] For the low-side transistor 209u, the second adaptive dead time circuit 306 can operate similarly to the first adaptive dead time circuit 304. The second adaptive dead time circuit 306 can include a second Zener diode 324 and a second sense resistor 326 coupled in parallel between a second internal positive supply voltage Vdd_LS (e.g., provided by a second local voltage supply) and a second sense node 310. The second sense resistor 326 can be configured to receive at least a portion of the capacitor current Icap and generate a second sense voltage LVsense at the second sense node 310 based on the portion of the capacitor current Icap flowing through the second sense resistor 326. The second sense resistor 326 can be a single resistor or multiple resistors arranged in different ways.

[0090] The second Zener diode 324 and the second sense resistor 326 can form a second sense circuit that is coupled to the capacitor HVC and configured to provide the second sense voltage LVsense at the second sense node 310, where the second sense voltage LVsense represents the rate of change of the voltage present at the load end of the low-side transistor 209u (e.g., at the phase node terminal 302).

[0091] The low-side gate driver 210 can be configured to be coupled to the second internal positive supply voltage Vdd_LS and the second internal ground voltage. For example, the low-side gate driver 210 can use the second internal positive supply voltage Vdd_LS and the second internal ground voltage to drive the low-side transistor 209u between an on state and an off state. In some implementations, the second internal positive supply voltage Vdd_LS can be derived from a low-side fixed supply voltage VCC, and the second internal ground voltage can be derived from ground (e.g., a low-side fixed ground voltage).

[0092] The second adaptive dead time circuit 306 may further include a second reference source 328 and a second comparator circuit 330 (e.g., a voltage comparator or a current comparator). The second reference source 328 may generate a second threshold Th2 as a threshold voltage. In some implementations, the second threshold Th2 may be generated to be a predetermined amount smaller or higher than the second internal positive supply voltage Vdd_LS according to the second internal positive supply voltage Vdd_LS. In an implementation where the second comparator circuit 330 is a current comparator, the second reference source 328 may be a current source for providing the second threshold Th2 as a threshold current to the second comparator circuit 330.

[0093] When the phase voltage VS is in a steady state, the first sensing circuit may generate a second sensed value (e.g., a second sensed voltage LVsense or a second sensed current) at a steady state value. For example, when the phase voltage VS is in a steady state, the change rate of the phase voltage VS (e.g., the change rate of dV / dt) is zero. Therefore, the second sensed voltage LVsense is also at a steady state value, which may be set to the second internal positive supply voltage Vdd_LS. In some implementations, the steady state value of the second sensed voltage LVsense may be a predetermined amount larger than the second threshold Th2. For example, the steady state value of the second sensed voltage LVsense may be 5V (e.g., Vdd_LS = 5V), and the second threshold Th2 may be set to 4.8V. In some implementations, the steady state value of the second sensed voltage LVsense may be a predetermined amount smaller than the second threshold Th2. For example, the steady state value of the second sensed voltage LVsense may be 5V (e.g., Vdd_LS = 5V), and the second threshold Th2 may be set to 5.2V.

[0094] The second comparator circuit 330 may compare the second sensed value (e.g., the second sensed voltage LVsense or the second sensed current) with the second threshold Th2, and may generate a second comparison result based on whether the second sensed value meets the second threshold Th2. For example, the second comparator circuit 330 may generate a logic high output when the second sensed value is equal to or greater than the second threshold Th2, and may generate a logic low output when the second sensed value is less than the second threshold Th2.

[0095] The second adaptive dead time circuit 306 may further include a second active-passive discrimination circuit 332 and a second logic circuit 334. The second adaptive dead time circuit 306 may detect the occurrence of a dV / dt event corresponding to the turn-off of the high-side transistor 208u, and may also detect the moment when the dV / dt event ends. Thus, the second adaptive dead time circuit 306 may detect the start and the end of the dV / dt event. The second adaptive dead time circuit 306 may trigger the end of the adaptive dead time of the low-side transistor 209u based on (e.g., in response to) detecting the end of the dV / dt event of the high-side transistor 208u.

[0096] A change in the output state of the second comparator circuit 330 may indicate a threshold crossing of the second threshold Th2. During the turn-off event of the high-side transistor 208u, the second sensed voltage LVsense deviates from the steady-state value. For example, at the start of the dV / dt event, the second sensed voltage LVsense may undergo a falling transition and cross the second threshold Th2. Crossing the second threshold Th2 during the falling transition may cause the output of the second comparator circuit 330 to change from a logic high value to a logic low value, thereby indicating the start of the dV / dt event. When the phase voltage VS enters the steady state, the dV / dt event ends. Thus, at the end of the dV / dt event, the second sensed voltage LVsense may return to the steady-state value. In other words, at the end of the dV / dt event, the second sensed voltage LVsense may undergo a rising transition and cross the second threshold Th2 again - this time from the opposite direction. Crossing the second threshold Th2 during the rising transition may cause the output of the second comparator circuit 330 to change from a logic low value to a logic high value, thereby indicating the end of the dV / dt event. In some implementations, the start of the dV / dt event may be indicated by a rising transition of the second sensed voltage LVsense, and the end of the dV / dt event may be indicated by a falling transition of the second sensed voltage LVsense.

[0097] Thus, the second comparator circuit 330 may detect the voltage transient dV / dt (e.g., the start of the dV / dt event) based on the first crossing of the second threshold Th2, and may detect the end of the voltage transient dV / dt based on the second crossing of the second threshold Th2. The second crossing occurs after the first crossing and in the opposite direction to the first crossing. Thus, the second comparison result (e.g., the comparator output) of the second comparator circuit 330 may indicate the start of the voltage transient dV / dt, and may also indicate the end of the voltage transient dV / dt.

[0098] The second logic circuit 334 may include one or more logic gates, one or more processors, or a combination of one or more logic gates and one or more processors. The second logic circuit 334 may detect that a dV / dt event (e.g., a voltage transient dV / dt) is occurring based on the second comparison result indicating that the second sensed voltage LVsense meets the second threshold Th2, and may detect that a dV / dt event (e.g., a voltage transient dV / dt) is not occurring based on the second comparison result indicating that the second sensed voltage LVsense does not meet the second threshold Th2. The second logic circuit 334 may receive the second comparison result of the second comparator circuit 330 for monitoring and detecting a dV / dt event corresponding to the turn-off of the high-side transistor 208u. For example, the second logic circuit 334 may detect a voltage transient dV / dt of the phase voltage VS (or the voltage at the load terminal) based on the second comparison result indicating a first crossing of the second threshold Th2, and may detect the end of the voltage transient dV / dt of the phase voltage VS (or the voltage at the load terminal) based on the second comparison result indicating a second crossing of the second threshold Th2. Here, the second crossing occurs after the first crossing and in the opposite direction to the first crossing. Thus, the second logic circuit 334 may detect the start of the dV / dt event based on the first crossing of the second threshold Th2, and may detect the end of the dV / dt event based on the second crossing of the second threshold Th2. In some implementations, the second comparator circuit 330 may directly detect the start and end of the voltage transient dV / dt and pass this information to the second logic circuit 334. For example, the second logic circuit 334 may process the second comparison result (e.g., the comparator output) of the second comparator circuit 330 and detect the start and end of the voltage transient dV / dt according to the second comparison result of the second comparator circuit 330. Thus, the second comparison result of the second comparator circuit 330 may indicate the start of the voltage transient dV / dt and may also indicate the end of the voltage transient dV / dt.

[0099] When the second threshold Th2 is less than the steady-state value of the second sensed voltage LVsense, the first crossing of the second threshold Th2 may correspond to the falling edge of the second sensed voltage LVsense, and the second crossing of the second threshold Th2 may correspond to the rising edge of the second sensed voltage LVsense. Turning off a complementary transistor (e.g., the high-side transistor 208u) coupled to the load terminal of the low-side transistor 209u may cause a voltage transient dV / dt and cause the second sensed voltage LVsense to meet the second threshold Th2 by making the second sensed voltage LVsense less than the second threshold Th2.

[0100] Alternatively, when the second threshold Th2 is greater than the steady-state value of the second sense voltage LVsense, the first crossing of the second threshold Th2 may correspond to the rising edge of the second sense voltage LVsense, and the second crossing of the second threshold Th2 may correspond to the falling edge of the second sense voltage LVsense. Turning off the complementary transistor (e.g., the high-side transistor 208u) coupled to the load terminal of the low-side transistor 209u may cause a voltage transient dV / dt and cause the second sense voltage LVsense to satisfy the second threshold Th2 by making the second sense voltage LVsense greater than the second threshold Th2.

[0101] In addition, the second active-passive discrimination circuit 332 may detect the switching state of the low-side transistor 209u, including whether the low-side transistor 209u is in an on state or an off state. For example, the second active-passive discrimination circuit 332 may monitor the gate voltage of the low-side transistor 209u, the PWM control signal LIN, or the output terminal LO of the low-side transistor 209u to determine the switching state of the low-side transistor 209u. The second active-passive discrimination circuit 332 may indicate to the second logic circuit 334 whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the low-side transistor 209u. For example, if the low-side transistor 209u is in an on state at the start of the voltage transient dV / dt, the second active-passive discrimination circuit 332 may determine that the voltage transient dV / dt is an active voltage transient, and if the low-side transistor 209u is in an off state at the start of the voltage transient dV / dt, the second active-passive discrimination circuit 332 may determine that the voltage transient dV / dt is a passive voltage transient. In some implementations, the second active-passive discrimination circuit 332 may receive the second comparison result of the second comparator circuit 330 and detect the first crossing of the second threshold Th2 as an indication of the start of the voltage transient dV / dt. Based on (e.g., in response to) detecting the start of the voltage transient dV / dt, the second active-passive discrimination circuit 332 may evaluate the switching state of the low-side transistor 209u and determine whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the low-side transistor 209u. In other words, the second active-passive discrimination circuit 332 may receive the second comparison result, detect the voltage transient dV / dt based on the second comparison result indicating the first crossing of the second threshold Th2, and determine whether the voltage transient dV / dt corresponding to the first crossing of the second threshold Th2 is an active voltage transient or a passive voltage transient based on the switching state of the low-side transistor 209u. The second active-passive discrimination circuit 332 may indicate to the second logic circuit 334 with a logic-high output that the voltage transient dV / dt is an active voltage transient and with a logic-low output that the voltage transient dV / dt is a passive voltage transient, and vice versa.

[0102] Therefore, the second active - passive discrimination circuit 332 can determine the active / passive nature of the voltage transient dV / dt by monitoring the state of the power switch (e.g., by monitoring PWM, LIN, or LO) and by monitoring the comparator output of the second comparator circuit 330 (e.g., the second comparison result). The second comparator circuit 330 can detect the presence of the voltage transient dV / dt and generate a square pulse representing the voltage transient dV / dt. The second active - passive discrimination circuit 332 can check whether the voltage transient dV / dt occurs during the dead - time by checking the conduction state via PWM, LIN, or LO. Finally, the second active - passive discrimination circuit 332 can discriminate whether the voltage transient dV / dt is active or passive.

[0103] The second logic circuit 334 can indicate a second crossing of the second threshold Th2 based on the second comparison result of the second comparator circuit 330 and can adjust the adaptive dead - time of the low - side transistor 209u based on the second active - passive discrimination circuit 332 indicating that the voltage transient is a passive voltage transient, which occurs when the low - side transistor 209u is in the off state at the start of the voltage transient dV / dt (e.g., at the first crossing of the second threshold Th2).

[0104] Based on the second active - passive discrimination circuit 332 indicating that the voltage transient dV / dt is a passive voltage transient and in response to the second comparison result of the second comparator circuit 330 indicating a second crossing of the second threshold Th2, the second logic circuit 334 can trigger the low - side transistor 209u to switch from the off state to the on state, thus ending the current dead - time of the low - side transistor 209u. Therefore, the second logic circuit 334 can trigger the end of the current dead - time only when the voltage transient dV / dt is a passive voltage transient. If the voltage transient dV / dt is an active voltage transient, the default duration can be used for the current dead - time. The second logic circuit 334 can trigger the end of the current dead - time by generating a trigger signal ADTtrigger_LS. The second logic circuit 334 can provide the trigger signal ADTtrigger_LS to the driver stage of the low - side gate driver 210. Additionally or alternatively, the second logic circuit 334 can provide the trigger signal ADTtrigger_LS to the controller 104 to initiate the switch of the low - side transistor 209u from the off state to the on state.

[0105] Accordingly, the second logic circuit 334 can adjust the adaptive dead time of the low-side transistor 209u based on detecting a second crossing of the second threshold Th2 and based on the voltage transient dV / dt being a passive voltage transient. The adaptive dead time can be adjusted based on the timing of the second crossing of the second threshold Th2. For example, the second logic circuit 334 can trigger the end of the current dead time in response to detecting the second crossing of the second threshold Th2. Accordingly, since the second crossing of the second threshold Th2 can fluctuate for each switching cycle, the second logic circuit 334 can adjust the adaptive dead time for each switching cycle. By triggering the end of the current dead time in response to detecting the second crossing of the second threshold Th2, the second logic circuit 334 can minimize the adaptive dead time.

[0106] As indicated above, Figure 3A is provided as an example. Other examples can be different from the example regarding Figure 3A described. Figure 3A The number and arrangement of the components shown in Figure 3A are provided as an example. In practice, the circuit system 300A can include additional components, fewer components, different components, or components arranged differently compared to those shown in Figure 3A Two or more of the components shown in Figure 3A can be implemented within a single component, or a single component shown in

[0107] Figure 3B A circuit system 300B is shown in accordance with one or more implementations. The circuit system 300B can be similar to the circuit system 300A described in connection with Figure 3A except that the first comparator circuit 318 and the second comparator circuit 330 are current comparators. Accordingly, the first reference source 316 and the second reference source 328 can be current sources instead of voltage sources. For example, the first reference source 316 and the second reference source 328 can provide reference currents as the thresholds Th1 and Th2, respectively. Additionally, the first comparator circuit 318 and the second comparator circuit 330 are configured to receive a sense current Isense corresponding to the capacitor current Icap.

[0108] When the first threshold Th1 is less than the steady-state value of the first sense current Isense_HS, the first crossing of the first threshold Th1 can correspond to the falling edge of the first sense current Isense_HS, and the second crossing of the first threshold Th1 can correspond to the rising edge of the first sense current Isense_HS. Turning off the complementary transistor (e.g., the low-side transistor 209u) coupled to the load terminal of the high-side transistor 208u can cause a voltage transient dV / dt and cause the first sense current Isense_HS to satisfy the first threshold Th1 by making the first sense current Isense_HS less than the first threshold Th1. Alternatively, when the first threshold Th1 is greater than the steady-state value of the first sense current Isense_HS, the first crossing of the first threshold Th1 can correspond to the rising edge of the first sense current Isense_HS, and the second crossing of the first threshold Th1 can correspond to the falling edge of the first sense current Isense_HS. Turning off the complementary transistor (e.g., the low-side transistor 209u) coupled to the load terminal of the high-side transistor 208u can cause a voltage transient dV / dt and cause the first sense current Isense_HS to satisfy the first threshold Th1 by making the first sense current Isense_HS greater than the first threshold Th1.

[0109] When the second threshold Th2 is less than the steady-state value of the second sense current Isense_LS, the first crossing of the second threshold Th2 can correspond to the falling edge of the second sense current Isense_LS, and the second crossing of the second threshold Th2 can correspond to the rising edge of the second sense current Isense_LS. Turning off the complementary transistor (e.g., the high-side transistor 208u) coupled to the load terminal of the low-side transistor 209u can cause a voltage transient dV / dt and cause the second sense current Isense_LS to satisfy the second threshold Th2 by making the second sense current Isense_LS less than the second threshold Th2. Alternatively, when the second threshold Th2 is greater than the steady-state value of the second sense current Isense_LS, the first crossing of the second threshold Th2 can correspond to the rising edge of the second sense current Isense_LS, and the second crossing of the second threshold Th2 can correspond to the falling edge of the second sense current Isense_LS. Turning off the complementary transistor (e.g., the high-side transistor 208u) coupled to the load terminal of the low-side transistor 209u can cause a voltage transient dV / dt and cause the second sense current Isense_LS to satisfy the second threshold Th2 by making the second sense current Isense_LS greater than the second threshold Th2.

[0110] As described above, the first adaptive dead-time circuit 304 can detect the occurrence of a dV / dt event corresponding to the turn-off of the low-side transistor 209u, and can also detect the moment when the dV / dt event ends. As described above, the second adaptive dead-time circuit 306 can detect the occurrence of a dV / dt event corresponding to the turn-off of the high-side transistor 208u, and can also detect the moment when the dV / dt event ends.

[0111] As described above, the first active-passive discrimination circuit 320 can indicate to the first logic circuit 322 whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the high-side transistor 208u. As described above, the second active-passive discrimination circuit 332 can indicate to the second logic circuit 334 whether the voltage transient dV / dt is an active voltage transient or a passive voltage transient based on the switching state of the low-side transistor 209u.

[0112] The first logic circuit 322 can adjust the adaptive dead time of the high-side transistor 208u based on detecting a second crossing of the first threshold Th1 and based on the voltage transient dV / dt being a passive voltage transient. The adaptive dead time can be adjusted based on the timing of the second crossing of the first threshold Th1. For example, the first logic circuit 322 can trigger the end of the current dead time in response to detecting a second crossing of the first threshold Th1. Thus, since the second crossing of the first threshold Th1 may fluctuate for each switching cycle, the first logic circuit 322 can adjust the adaptive dead time for each switching cycle. By triggering the end of the current dead time in response to detecting a second crossing of the first threshold Th1, the first logic circuit 322 can minimize the adaptive dead time.

[0113] The second logic circuit 334 can adjust the adaptive dead time of the low-side transistor 209u based on detecting a second crossing of the second threshold Th2 and based on the voltage transient dV / dt being a passive voltage transient. The adaptive dead time can be adjusted based on the timing of the second crossing of the second threshold Th2. For example, the second logic circuit 334 can trigger the end of the current dead time in response to detecting a second crossing of the second threshold Th2. Thus, since the second crossing of the second threshold Th2 may fluctuate for each switching cycle, the second logic circuit 334 can adjust the adaptive dead time for each switching cycle. By triggering the end of the current dead time in response to detecting a second crossing of the second threshold Th2, the second logic circuit 334 can minimize the adaptive dead time.

[0114] As indicated above, Figure 3B is provided as an example. Other examples may be different from the example regarding Figure 3B described. Figure 3BThe number and arrangement of the components shown are provided as an example. In practice, the circuitry 300B may include additional components, fewer components, different components, or components in a different arrangement compared to those shown in Figure 3B Two or more of the components shown in. Figure 3B may be implemented within a single component, or Figure 3B a single component shown in may be implemented as multiple distributed components. Additionally or alternatively, a set of components (e.g., one or more components) of the circuitry 300B may perform one or more functions described as being performed by another set of components of the circuitry 300B.

[0115] Figure 4A and Figure 4B show signal diagrams 400A and 400B corresponding to an adaptive dead time for a low-side power switch according to one or more implementations. Figure 4B The signal diagram 400B shown in shows Figure 4A an enlarged portion of the signal diagram 400A shown in. The adaptive dead time may be a delay between the turn-off event of the high-side power transistor 208u and the turn-on event of the low-side power transistor 209u.

[0116] When the high-side transistor 208u is turned on, the high-side floating output voltage at the output terminal HO is high, and when the high-side transistor 208u is turned off, the high-side floating output voltage at the output terminal HO is low. When the low-side transistor 209u is turned on, the low-side output voltage at the output terminal LO is high, and when the low-side transistor 209u is turned off, the low-side output voltage at the output terminal LO is low. The turn-off event of the high-side power transistor 208u causes a voltage transient dV / dt at the phase node terminal 302 (e.g., a voltage transient dV / dt of the phase voltage VS). For example, the turn-off event of the high-side power transistor 208u may cause the phase voltage VS to decrease from the DC link positive power supply DC+ to the DC link negative power supply DC- (e.g., to ground), which causes the second sense voltage LVsense to initially cross the second threshold Th2 on the falling edge and then cross the second threshold Th2 on the rising edge. In other words, the voltage transient dV / dt causes a deviation (e.g., a negative spike) from the steady-state value of the second sense voltage LVsense. Once the voltage transient dV / dt is complete, the second sense voltage LVsense returns to the steady-state value. Thus, as described above, the turn-off event of the high-side power transistor 208u causes the second adaptive dead time circuit 306 to detect two threshold crossings of the second threshold Th2.

[0117] Based on the second active - passive discrimination circuit 332 indicating that the voltage transient dV / dt is a passive voltage transient, and in response to the second comparison result of the second comparator circuit 330 indicating a second crossing of the second threshold Th2, the second logic circuit 334 can trigger the low - side transistor 209u to switch from the off state to the on state, thereby ending the current dead - time of the low - side transistor 209u. The second logic circuit 334 can trigger the end of the current dead - time by generating a trigger signal ADTtrigger_LS. Based on the trigger signal ADTtrigger_LS, the low - side transistor 209u conducts.

[0118] As indicated above, Figure 4A and Figure 4B are provided as examples. Other examples may be different from the examples regarding Figure 4A and Figure 4B described.

[0119] Figure 5 FIG. 500 shows a signal diagram corresponding to an adaptive dead - time for a high - side power switch according to one or more implementations. The adaptive dead - time can be the delay between the turn - off event of the low - side power transistor 209u and the turn - on event of the high - side power transistor 208u.

[0120] The turn - off event of the low - side power transistor 209u causes a voltage transient dV / dt at the phase - node terminal 302 (e.g., the voltage transient dV / dt of the phase voltage VS). For example, the turn - off event of the low - side power transistor 209u can cause the phase voltage VS to increase from the DC - link negative power supply DC - to the DC - link positive power supply DC +, which causes the first sensed voltage HVsense to initially cross the first threshold Th1 on the falling edge and then cross the first threshold Th1 on the rising edge. In other words, the voltage transient dV / dt causes a deviation (e.g., a negative spike) from the steady - state value of the first sensed voltage HVsense. Once the voltage transient dV / dt is complete, the first sensed voltage HVsense returns to the steady - state value. Thus, as described above, the turn - off event of the low - side power transistor 209u enables two threshold crossings of the first threshold Th1 to be detected by the first adaptive dead - time circuit 304.

[0121] Based on the first active - passive discrimination circuit 320 indicating that the voltage transient dV / dt is a passive voltage transient and in response to the first comparison result of the first comparator circuit 318 indicating a second crossing of the first threshold Th1, the first logic circuit 322 can trigger the high - side transistor 208u to switch from the off state to the on state, thereby ending the current dead - time of the high - side transistor 208u. The first logic circuit 322 can trigger the end of the current dead - time by generating a trigger signal ADTtrigger_HS. Based on the trigger signal ADTtrigger_HS, the high - side transistor 208u conducts.

[0122] As indicated above, Figure 5 is provided as an example. Other examples may be different from those Figure 5 described.

[0123] Figure 6 Signal diagrams 600A and 600B corresponding to dV / dt events corresponding to the turn - off of a high - side power switch according to one or more implementations are shown. Signal diagram 600A shows a non - adaptive dead - time or a fixed dead - time, while signal diagram 600B shows an adaptive dead - time. The duration of the adaptive dead - time is shorter than the duration of the non - adaptive dead - time, such that the reverse - conduction loss of a system implementing the adaptive dead - time is smaller.

[0124] As indicated above, Figure 6 is provided as an example. Other examples may be different from those Figure 6 described.

[0125] Figure 7 is a schematic block diagram of a dV / dt sensing and gate - driving system 700 according to one or more embodiments. The dV / dt sensing and gate - driving system 700 may include a monolithic gate - driver IC 702 having two separate voltage islands corresponding to two isolated voltage domains. The dV / dt sensing and gate - driving system 700 may be similar to the gate - driver system 200 described in connection with Figure 2 but also includes circuitry configured to monitor the voltage transient dV / dt at the phase - node terminal and detect short - circuit events in more detail. For example, a first adaptive dead - time circuit 304 may be provided in the high - side gate driver 220, and a second adaptive dead - time circuit 306 may be provided in the low - side gate driver 210. Additionally, a sensing capacitor 704 may be connected between the first adaptive dead - time circuit 304 and the second adaptive dead - time circuit 306 such that the sensing capacitor 704 is cross - coupled to the high - side region and the low - side region of the monolithic gate - driver IC 702. The sensing capacitor 704 may correspond to the capacitor HVC of the circuit system 300A described in connection with Figure 3A described or the capacitor in connection withFigure 3B The capacitor HVC of the described circuit system 300B. In some implementations, an optional sense capacitor 706 may be arranged in series with the sense capacitor 704. Accordingly, the monolithic gate driver IC 702 includes at least one of the sense capacitors 704 and / or 706 coupled to the input node (e.g., the first sense node 308) of the first adaptive dead-time circuit 304 and the input node (e.g., the second sense node 310) of the second adaptive dead-time circuit 306.

[0126] The first adaptive dead-time circuit 304 and the second adaptive dead-time circuit 306 may be configured to sense the voltage transient dV / dt of the phase voltage VS at the phase node terminal 302 for adjusting the respective adaptive dead-time.

[0127] Specifically, the first adaptive dead-time circuit 304 and the second adaptive dead-time circuit 306 may sense the dV / dt event in an analog manner using the sense capacitor 704. Then the respective adaptive dead-time may be adjusted using a threshold crossing.

[0128] The dV / dt sensing and gate drive system 700 may further include a DC link power supply 708 (VDC), a low-side gate driver power supply 710 (VL), a high-side gate driver power supply 712 (VH), a decoupling capacitor 714 (e.g., a bootstrap capacitor) coupled in parallel to the low-side gate driver power supply 710, a decoupling capacitor 716 (e.g., a bootstrap capacitor) coupled in parallel to the high-side gate driver power supply 712, and a resistor R providing a path for current flow. The voltage VH may be equal to VB - VS, and the voltage VL may be equal to VCC - VSS (e.g., VCC - GND).

[0129] The monolithic gate driver IC 702 may include a PWM logic unit 225 that includes circuitry for processing signals received from a microcontroller via pins HIN and LIN and also forwards the PWM control signals from the microcontroller to the low-side gate driver 210 and the high-side gate driver 220. The PWM control signal to the high-side gate driver 220 may be transmitted through a level shifter 230 across an isolation region that isolates the high-side region and the low-side region.

[0130] The sense capacitor 704 and the optional sense capacitor 706 are substantially linear such that the voltage is proportional to the charge stored therein. The sense capacitor 704 and the optional sense capacitor 706 may be placed across two voltage domains and may be external to or integrated within the monolithic gate driver IC 702 to sense the voltage slope of the voltage transient dV / dt.

[0131] Both the first adaptive dead-time circuit 304 and the second adaptive dead-time circuit 306 can use the sense capacitor 704 to sense dV / dt events for adjusting the respective adaptive dead-times. The sense capacitor 704 can be arranged in two sense paths, including a first sense path and a second sense path. The first sense path can include a first end and a second end. The first sense path can be coupled at the first end to the collector or drain of the high-side transistor 208u and at the second end to the emitter or source of the high-side transistor 208u. The first sense path can enable the sense capacitor 704 to sense a voltage transient of the high-side transistor 208u (e.g., V DS ) that is proportional to the phase voltage VS.

[0132] The first sense path from the source to the drain of the high-side transistor 208u can include starting at the source of the high-side transistor 208u (e.g., at the phase node), continuing through the high-side gate driver power supply 712 or the decoupling capacitor 716 to VB, continuing from VB to the first sense node 308, and continuing through the sense capacitor 704 to the second sense node 310. From the second sense node 310, the first sense path continues through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VSS, and continues through the DC link power supply 708 to DC+, where DC+ is equivalent to the drain of the high-side transistor 208u.

[0133] The second sense path can include a third end and a fourth end. The third end can be coupled to the collector or drain of the low-side transistor 209u, and the fourth end can be coupled to the emitter or source of the low-side transistor 209u. The second sense path can enable the sense capacitor 704 to sense a voltage transient of the low-side transistor 209u (e.g., V DS ) that is proportional to the phase voltage VS. The second sense path from the source to the drain of the low-side transistor 209u can include starting at the source of the low-side transistor 209u (DC- or VSS), continuing through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VCC, continuing from VCC to the second sense node 310, and continuing through the sense capacitor 704 to the first sense node 308. From the first sense node 308, the second sense path continues through the high-side gate driver power supply 712 or the decoupling capacitor 716 to VS, where VS is equivalent to the drain of the low-side transistor 209u. Thus, the sense capacitor 704 can be indirectly coupled to the collector or drain and the emitter or source of the high-side transistor 208u, and can be indirectly coupled to the collector or drain and the emitter or source of the low-side transistor 209u.

[0134] As indicated above, Figure 7Provided as an example. Other examples may be different from the example regarding Figure 7 the described example.

[0135] Figure 8 is a schematic block diagram of a dV / dt sensing and gate drive system 800 according to one or more embodiments. The dV / dt sensing and gate drive system 800 may include a monolithic gate driver IC 802 having two separate voltage islands corresponding to two isolated voltage domains. The dV / dt sensing and gate drive system 800 may be similar to the dV / dt sensing and gate drive system 700 described in conjunction with Figure 7 except that the sense capacitors 704 and 706 are arranged in different paths. For example, the sense capacitor 704 may correspond to the first adaptive dead time circuit 304, and the sense capacitor 706 may correspond to the second adaptive dead time circuit 306. The sense capacitor 704 may be coupled to the input node (e.g., the first sense node 308) of the first adaptive dead time circuit 304 and the reference node (e.g., VSS) of the low side region. The sense capacitor 706 may be coupled to the input node (e.g., the second sense node 310) of the second adaptive dead time circuit 306 and the floating reference node (e.g., VS) of the high side region.

[0136] The sense capacitor 704 may be arranged in the first sense path, and the sense capacitor 706 may be arranged in the second sense path. The first sense path may include a first end and a second end. The first sense path may be coupled to the collector or drain of the high side transistor 208u at the first end and to the emitter or source of the high side transistor 208u at the second end. The first sense path may enable the sense capacitor 704 to sense the voltage transient (e.g., V DS ) of the high side transistor 208u proportional to the phase voltage VS. The first sense path from the source to the drain of the high side transistor 208u may include starting at the source of the high side transistor 208u (e.g., at the phase node), continuing through the high side gate driver power supply 712 or the decoupling capacitor 716 to VB, continuing from VB to the first sense node 308, continuing through the sense capacitor 704 to VSS, and continuing through the DC link power supply 708 to DC+, where DC+ is equivalent to the drain of the high side transistor 208u. Thus, the sense capacitor 704 may be indirectly coupled to the collector or drain and the emitter or source of the high side transistor 208u.

[0137] The second sensing path may include a third terminal and a fourth terminal. The third terminal may be coupled to the collector or drain of the low-side transistor 209u, and the fourth terminal may be coupled to the emitter or source of the low-side transistor 209u. The second sensing path may enable the sense capacitor 706 to sense the voltage transient of the low-side transistor 209u that is proportional to the phase voltage VS (e.g., the V DS ) of the low-side transistor 209u. The second sensing path from the source to the drain of the low-side transistor 209u may include starting at the source (DC- or VSS) of the low-side transistor 209u, continuing through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VCC, continuing from VCC to the second sensing node 310, continuing through the sense capacitor 706 to VS, where VS is equivalent to the drain of the low-side transistor 209u. Thus, the sense capacitor 706 may be indirectly coupled to the collector or drain and the emitter or source of the low-side transistor 209u.

[0138] As indicated above, Figure 8 is provided as an example. Other examples may be different from the examples described with respect to Figure 8 the description.

[0139] An overview of some aspects of the present disclosure is provided below:

[0140] Aspect 1: A gate driver circuit, comprising: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state using an adaptive dead time, wherein the adaptive dead time is a delay between an off event of a complementary power switch and an on event of the power switch, at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensed value representing a rate of change of a voltage present at a load terminal of the power switch; a comparator circuit configured to compare the sensed value with a threshold and further configured to generate a comparison result based on whether the sensed value meets the threshold; a logic circuit configured to receive the comparison result, detect a voltage transient of the voltage based on the comparison result indicating a first crossing of the threshold, and detect an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; and an active-passive discrimination circuit configured to detect a switching state of the power switch, including whether the power switch is in an on state or an off state, wherein the active-passive discrimination circuit is configured to indicate to the logic circuit whether the voltage transient is an active voltage transient or a passive voltage transient based on the switching state of the power switch, and wherein the logic circuit is configured to adjust the adaptive dead time of the power switch based on the comparison result indicating a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0141] Aspect 2: The gate driver circuit according to Aspect 1, wherein the logic circuit is configured to trigger the power switch to switch from an off state to an on state based on the active-passive discrimination circuit indicating that the voltage transient is a passive voltage transient and in response to the comparison result indicating a second crossing of the threshold.

[0142] Aspect 3: The gate driver circuit according to any one of Aspects 1 to 2, wherein the logic circuit is configured to optimize the adaptive dead time based on detecting a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0143] Aspect 4: The gate driver circuit according to any one of Aspects 1 to 3, wherein the logic circuit is configured to minimize the adaptive dead time based on detecting a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0144] Aspect 5: The gate driver circuit according to any one of Aspects 1 to 4, wherein the active-passive discrimination circuit is configured to receive the comparison result, detect a voltage transient based on the comparison result indicating a first crossing of a threshold, and determine whether the voltage transient corresponding to the first crossing of the threshold is an active voltage transient or a passive voltage transient based on the switching state of the power switch.

[0145] Aspect 6: The gate driver circuit according to Aspect 5, wherein the active-passive discrimination circuit is configured to: determine that the voltage transient is an active voltage transient if the power switch is in the on state at the start of the voltage transient, and determine that the voltage transient is a passive voltage transient if the power switch is in the off state at the start of the voltage transient.

[0146] Aspect 7: The gate driver circuit according to any one of Aspects 1 to 6, wherein the first crossing of the threshold corresponds to the start of the voltage transient.

[0147] Aspect 8: The gate driver circuit according to any one of Aspects 1 to 7, wherein the logic circuit is configured to detect that a voltage transient is occurring based on the comparison result indicating that the sensed value satisfies a threshold, wherein the start of the voltage transient corresponds to the first crossing of the threshold, and wherein the logic circuit is configured to detect that a voltage transient has not occurred based on the comparison result indicating that the sensed value does not satisfy the threshold, wherein the end of the voltage transient corresponds to a second crossing of the threshold.

[0148] Aspect 9: The gate driver circuit according to any one of Aspects 1 to 8, wherein the sensing circuit is configured to generate a sensed value at a steady-state value when the voltage is in a steady state, and the steady-state value is greater than the threshold by a predetermined amount.

[0149] Aspect 10: The gate driver circuit according to any one of Aspects 1 to 9, wherein the first crossing of the threshold corresponds to the falling edge of the sensed value, and the second crossing of the threshold corresponds to the rising edge of the sensed value, or wherein the first crossing of the threshold corresponds to the rising edge of the sensed value, and the second crossing of the threshold corresponds to the falling edge of the sensed value.

[0150] Aspect 11: The gate driver circuit according to any one of Aspects 1 to 10, wherein turning off the complementary power switch coupled to the load terminal is configured to cause a voltage transient and cause the sensed value to satisfy the threshold by making the sensed value less than the threshold, or wherein turning off the complementary power switch coupled to the load terminal is configured to cause a voltage transient and cause the sensed value to satisfy the threshold by making the sensed value greater than the threshold.

[0151] Aspect 12: The gate driver circuit according to any one of Aspects 1 to 11, wherein the gate driver is configured to be coupled to an internal positive supply voltage and an internal ground voltage, wherein the gate driver is configured to drive a power switch between an on state and an off state using the internal positive supply voltage and the internal ground voltage, and wherein the threshold is less than the internal positive supply voltage.

[0152] Aspect 13: The gate driver circuit according to any one of Aspects 1 to 12, wherein at least one capacitor is configured to sense a voltage transient and provide a capacitor current proportional to the slope of the voltage transient, and wherein the capacitor current is configured to generate a sensed value at a sensing node of the sensing circuit.

[0153] Aspect 14: The gate driver circuit according to Aspect 13, wherein the voltage transient corresponds to a voltage across the power switch, wherein the voltage across the power switch is a drain-source voltage or a collector-emitter voltage, and wherein the capacitor current is based on the rate of change of the voltage across the power switch.

[0154] Aspect 15: The gate driver circuit according to any one of Aspects 1 to 14, wherein: the power switch is a high-side power switch, the gate driver and the sensing circuit are disposed in a high-side region, and at least one capacitor is coupled to an input node of the sensing circuit and a reference node of a low-side region.

[0155] Aspect 16: The gate driver circuit according to any one of Aspects 1 to 15, further comprising: a sensing path including a first end and a second end, wherein the sensing path is coupled to a collector or a drain of the power switch at the first end and to an emitter or a source of the power switch at the second end, and wherein at least one capacitor is disposed in the sensing path.

[0156] Aspect 17: The gate driver circuit according to any one of Aspects 1 to 16, wherein: the power switch is a low-side power switch, the gate driver and the sensing circuit are disposed in a low-side region, and at least one capacitor is coupled to an input node of the sensing circuit and a floating reference node of a high-side region.

[0157] Aspect 18: A half-bridge gate driver circuit includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a first gate driver that is disposed in the high-side region and is configured to drive a high-side power switch between an on state and an off state using a first adaptive dead time provided during an off-state interval of the high-side power switch; a second gate driver that is disposed in the low-side region and is configured to drive a low-side power switch between an on state and an off state using a second adaptive dead time provided during an off-state interval of the low-side power switch, wherein the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, and wherein the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; a phase node terminal that is coupled to or is configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor that is cross-coupled to the high-side region and the low-side region; a first sensing circuit that is disposed in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value representing a rate of change of a phase voltage present at the phase node terminal; a second sensing circuit that is disposed in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value representing a rate of change of the phase voltage present at the phase node terminal; a first comparator circuit that is configured to compare the first sensed value with a first threshold and is further configured to generate a first comparison result based on whether the first sensed value satisfies the first threshold; a second comparator circuit that is configured to compare the second sensed value with a second threshold and is further configured to generate a second comparison result based on whether the second sensed value satisfies the second threshold; a first logic circuit that is configured to receive the first comparison result, detect a first voltage transient of the phase node terminal based on the first comparison result indicating a first crossing of the first threshold, and detect an end of the first voltage transient based on the first comparison result indicating a second crossing of the first threshold, wherein the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold;The first active - passive discrimination circuit, which is configured to detect a first switching state of a high - side power switch, including whether the high - side power switch is in an on state or an off state. Wherein, the first active - passive discrimination circuit is configured to indicate to a first logic circuit whether a first voltage transient is an active voltage transient or a passive voltage transient based on the first switching state of the high - side power switch, and wherein, the first logic circuit is configured to indicate a second crossing of a first threshold based on a first comparison result and adjust a first adaptive dead - time of the high - side power switch based on the first voltage transient being a passive voltage transient; A second logic circuit, which is configured to receive a second comparison result, detect a second voltage transient of a phase - node terminal based on the second comparison result indicating a first crossing of a second threshold, and detect an end of the second voltage transient based on the second comparison result indicating a second crossing of the second threshold, wherein, the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold; And a second active - passive discrimination circuit, which is configured to detect a second switching state of a low - side power switch, including whether the low - side power switch is in an on state or an off state. Wherein, the second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switching state of the low - side power switch, wherein, the second logic circuit is configured to indicate a second crossing of the second threshold based on the second comparison result and adjust a second adaptive dead - time of the low - side power switch based on the second voltage transient being a passive voltage transient, and wherein, the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.;

[0158] Aspect 19: The half - bridge gate driver circuit according to aspect 18, wherein, turning off the high - side power switch is configured to cause a second voltage transient and make a second sensed value satisfy a second threshold by making the second sensed value less than the second threshold, and wherein, turning off the low - side power switch is configured to cause a first voltage transient and make a first sensed value satisfy a first threshold by making the first sensed value less than the first threshold.

[0159] Aspect 20: A method for adjusting an adaptive dead time, comprising: generating, by a gate driver of a gate driver circuit, a drive signal configured to drive a power switch between an on state and an off state; sensing, by a capacitor, a voltage transient across the power switch, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to a slope of the voltage transient; generating, at a sense node coupled to the capacitor, a sense value based on the capacitor current, wherein the sense value is proportional to the slope of the voltage transient; comparing, by a comparator circuit, the sense value with a threshold to generate a comparison result indicating whether the sense value meets the threshold; detecting, by a logic circuit, a voltage transient based on the comparison result indicating a first crossing of the threshold; detecting, by the logic circuit, an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; generating, by an active-passive discrimination circuit, a status signal indicating whether the voltage transient is an active voltage transient or a passive voltage transient based on a switching state of the power switch; and adjusting, by the logic circuit, an adaptive dead time of the power switch based on the comparison result indicating the second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0160] Aspect 21: A gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state with an adaptive dead time, wherein the adaptive dead time is a delay between a turn-off event of a complementary power switch and a turn-on event of the power switch; at least one capacitor cross-coupled to the high-side region and the low-side region such that the at least one capacitor is configured to sense a voltage transient across the power switch and provide a capacitor current proportional to the slope of the voltage transient; a sensing circuit configured to receive the capacitor current and provide a sensed value corresponding to the capacitor current; a comparator circuit configured to compare the sensed value with a threshold and further configured to generate a comparison result based on whether the sensed value meets the threshold; a logic circuit configured to receive the comparison result, detect a voltage transient based on the comparison result indicating a first crossing of the threshold, and detect an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; and an active-passive discrimination circuit configured to detect a switching state of the power switch, including whether the power switch is in an on state or an off state, wherein the active-passive discrimination circuit is configured to indicate to the logic circuit whether the voltage transient is an active voltage transient or a passive voltage transient based on the switching state of the power switch, and wherein the logic circuit is configured to adjust the adaptive dead time of the power switch based on the comparison result indicating a second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0161] Aspect 22: A power module, comprising: a high-side region operating in a first voltage domain; a high-side power switch coupled to the high-side region, wherein the high-side power switch includes a first control terminal; a low-side region operating in a second voltage domain lower than the first voltage domain; a low-side power switch coupled to the low-side region, wherein the low-side power switch includes a second control terminal; a first gate driver arranged in the high-side region and coupled to the first control terminal, wherein the first gate driver is configured to drive the high-side power switch between an on state and an off state using a first adaptive dead time provided during an off-state interval of the high-side power switch; a second gate driver arranged in the low-side region and coupled to the second control terminal, wherein the second gate driver is configured to drive the low-side power switch between an on state and an off state using a second adaptive dead time provided during an off-state interval of the low-side power switch, wherein the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, and wherein the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; a phase node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit arranged in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value representing a rate of change of a phase voltage present at the phase node terminal; a second sensing circuit arranged in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value representing a rate of change of the phase voltage present at the phase node terminal; a first comparator circuit configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; a second comparator circuit configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; a first logic circuit configured to receive the first comparison result, detect a first voltage transient of the phase node terminal based on the first comparison result indicating a first crossing of the first threshold, and detect an end of the first voltage transient based on the first comparison result indicating a second crossing of the first threshold, wherein the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold;A first active - passive discrimination circuit configured to detect a first switching state of a high - side power switch, including whether the high - side power switch is in an on state or an off state. The first active - passive discrimination circuit is configured to indicate to a first logic circuit whether a first voltage transient is an active voltage transient or a passive voltage transient based on the first switching state of the high - side power switch. And the first logic circuit is configured to indicate a second crossing of a first threshold based on a first comparison result and adjust a first adaptive dead - time of the high - side power switch based on the first voltage transient being a passive voltage transient; A second logic circuit configured to receive a second comparison result, detect a second voltage transient of a phase - node terminal based on the second comparison result indicating a first crossing of a second threshold, and detect an end of the second voltage transient based on the second comparison result indicating a second crossing of the second threshold, where the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold; And a second active - passive discrimination circuit configured to detect a second switching state of a low - side power switch, including whether the low - side power switch is in an on state or an off state. The second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switching state of the low - side power switch. The second logic circuit is configured to indicate a second crossing of the second threshold based on the second comparison result and adjust a second adaptive dead - time of the low - side power switch based on the second voltage transient being a passive voltage transient, and where the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.;

[0162] Aspect 23: A gate driver circuit, comprising: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state with an adaptive dead time, wherein the adaptive dead time is a delay between a turn-off event of a complementary power switch and a turn-on event of the power switch, at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensed value representative of a rate of change of a voltage present at a load terminal of the power switch; a comparator circuit configured to compare the sensed value with a threshold and further configured to generate a comparison result based on whether the sensed value meets the threshold, wherein the comparison result indicates the presence of a voltage transient corresponding to a first crossing of the threshold and indicates the end of the voltage transient using a second crossing of the threshold, and wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; a logic circuit configured to process the comparison result; and an active-passive discrimination circuit configured to detect a switching state of the power switch, including whether the power switch is in an on state or an off state, wherein the active-passive discrimination circuit is configured to indicate to the logic circuit whether the voltage transient is an active voltage transient or a passive voltage transient based on the switching state of the power switch, and wherein the logic circuit is configured to adjust the adaptive dead time of the power switch based on the comparison result indicating the second crossing of the threshold and based on the voltage transient being a passive voltage transient.

[0163] Aspect 24: A system configured to perform one or more operations described in one or more of Aspects 1 to 23.

[0164] Aspect 25: An apparatus comprising means for performing one or more operations described in one or more of Aspects 1 to 23.

[0165] Aspect 26: A non-transitory computer-readable medium storing an instruction set, the instruction set including one or more instructions that, when executed by an apparatus, cause the apparatus to perform one or more operations described in one or more of Aspects 1 to 23.

[0166] Aspect 27: A computer program product including instructions or code for performing one or more operations described in one or more of Aspects 1 to 23.

[0167] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the exact forms disclosed. Modifications and variations may be made in light of the above disclosure, or may be acquired from practice of the implementations.

[0168] Some implementations may be described herein in connection with thresholds. As used herein, "meeting" a threshold may mean that a value is greater than, more than, higher than, greater than or equal to, less than, fewer than, lower than, less than or equal to, equal to, etc., the threshold.

[0169] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual specific control hardware or software code used to implement these systems and / or methods is not a limitation on the implementations. Thus, the operations and behaviors of the systems and / or methods are described herein without reference to specific software code, and it should be understood that the software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0170] Any processing component may be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transitory computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions may be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. The software may be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes program code or program algorithms stored thereon that, when executed, cause the processor to perform the steps of a method via a computer program.

[0171] A controller that includes hardware may also perform one or more of the techniques of the present disclosure. A controller that includes one or more processors may use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may also include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in the present disclosure.

[0172] A signal processing circuit and / or a signal conditioning circuit may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive further information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal in a manner such that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, transformation, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0173] Even if particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementations described herein. Many of these features may be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, the present disclosure includes combinations of each dependent claim in a claim set with each other individual claim in the claim set and with each combination of multiple claims in the claim set. As used herein, the phrase referring to "at least one" of a list of items means any combination of these items, including a single member. As an example, "at least one of a, b, or c" is intended to cover a, b, c, a and b, a and c, b and c, and a, b, and c, as well as any combination with multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0174] Furthermore, it should be understood that the disclosure of multiple acts or functions in the specification or claims may not be construed as being in a particular order. Thus, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Additionally, in some implementations, a single act may include or may be divided into multiple sub-acts. Such sub-acts may be included and are part of the disclosure of the single act unless explicitly excluded.

[0175] Unless so explicitly described, any element, act, or instruction used herein should not be construed as critical or essential. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Additionally, as used herein, the article "the" is intended to include one or more items referred to in conjunction with the article "the" and may be used interchangeably with "one or more." In the only meaning Figure 1In the case of one item, use the phrases "only one", "single", or similar language. Additionally, as used herein, the terms "has", "having", "owns", etc. are intended to be open-ended terms that do not limit the elements they modify (e.g., an element "having" A may also have B). Further, unless otherwise expressly stated, the phrase "based on" is intended to mean "at least partially based on". As used herein, the term "multiple" may be replaced with "a plurality of", and vice versa. Additionally, as used herein, the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or", unless otherwise expressly stated (e.g., when used in combination with "either" or "only one").

Claims

1. A gate driver circuit, comprising: A high-side region that operates in a first voltage domain; A low-side region that operates in a second voltage domain lower than the first voltage domain; A gate driver configured to drive a power switch between an on state and an off state with an adaptive dead time, wherein the adaptive dead time is a delay between a turn-off event of a complementary power switch and a turn-on event of the power switch, At least one capacitor cross-coupled to the high-side region and the low-side region; A sensing circuit coupled to the at least one capacitor and configured to provide a sensed value representing a rate of change of a voltage present at a load terminal of the power switch; A comparator circuit configured to compare the sensed value with a threshold and further configured to generate a comparison result based on whether the sensed value meets the threshold; A logic circuit configured to receive the comparison result, detect a voltage transient of the voltage based on the comparison result indicating a first crossing of the threshold, and detect an end of the voltage transient based on the comparison result indicating a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; and An active-passive discrimination circuit configured to detect a switching state of the power switch, including whether the power switch is in the on state or the off state, wherein the active-passive discrimination circuit is configured to indicate to the logic circuit whether the voltage transient is an active voltage transient or a passive voltage transient based on the switching state of the power switch, and wherein the logic circuit is configured to adjust the adaptive dead time of the power switch based on the comparison result indicating a second crossing of the threshold and based on the voltage transient being the passive voltage transient.

2. The gate driver circuit according to claim 1, wherein The logic circuit is configured to trigger the power switch to switch from the off state to the on state based on the active-passive discrimination circuit indicating that the voltage transient is the passive voltage transient and in response to the comparison result indicating a second crossing of the threshold.

3. The gate driver circuit according to claim 1, wherein, The logic circuit is configured to optimize the adaptive dead time based on detecting a second crossing of the threshold and based on the voltage transient being the passive voltage transient.

4. The gate driver circuit according to claim 1, wherein The logic circuit is configured to minimize the adaptive dead time based on detecting a second crossing of the threshold and based on the voltage transient being the passive voltage transient.

5. The gate driver circuit according to claim 1, wherein, The active-passive discrimination circuit is configured to receive the comparison result, detect the voltage transient based on the comparison result indicating a first crossing of the threshold, and determine whether the voltage transient corresponding to the first crossing of the threshold is the active voltage transient or the passive voltage transient based on the switching state of the power switch.

6. The gate driver circuit according to claim 5, wherein, The active - passive discrimination circuit is configured to: determine that the voltage transient is the active voltage transient when the power switch is in the on - state at the start of the voltage transient, and determine that the voltage transient is the passive voltage transient when the power switch is in the off - state at the start of the voltage transient.

7. The gate driver circuit according to claim 1, wherein, The first crossing of the threshold corresponds to the start of the voltage transient.

8. The gate driver circuit according to claim 1, wherein, The logic circuit is configured to detect that the voltage transient is occurring based on the comparison result indicating that the sensed value satisfies the threshold, wherein the start of the voltage transient corresponds to the first crossing of the threshold, and wherein the logic circuit is configured to detect that the voltage transient does not occur based on the comparison result indicating that the sensed value does not satisfy the threshold, wherein the end of the voltage transient corresponds to the second crossing of the threshold.

9. The gate driver circuit according to claim 1, wherein, The sensing circuit is configured to generate the sensed value at a steady - state value when the voltage is in a steady state, wherein the steady - state value is greater than the threshold by a predetermined amount.

10. The gate driver circuit according to claim 1, wherein The first crossing of the threshold corresponds to the falling edge of the sensed value, and wherein the second crossing of the threshold corresponds to the rising edge of the sensed value, or wherein the first crossing of the threshold corresponds to the rising edge of the sensed value, and wherein the second crossing of the threshold corresponds to the falling edge of the sensed value.

11. The gate driver circuit according to claim 1, wherein, Turning off the complementary power switch coupled to the load terminal is configured to cause the voltage transient and cause the sensed value to satisfy the threshold by making the sensed value less than the threshold, or wherein turning off the complementary power switch coupled to the load terminal is configured to cause the voltage transient and cause the sensed value to satisfy the threshold by making the sensed value greater than the threshold.

12. The gate driver circuit according to claim 1, wherein, The gate driver is configured to be coupled to an internal positive power supply voltage and an internal ground voltage, wherein the gate driver is configured to drive the power switch between the on - state and the off - state using the internal positive power supply voltage and the internal ground voltage, and wherein the threshold is less than the internal positive power supply voltage.

13. The gate driver circuit according to claim 1, wherein, The at least one capacitor is configured to sense the voltage transient and provide a capacitor current proportional to the slope of the voltage transient, and wherein the capacitor current is configured to generate the sensed value at a sensing node of the sensing circuit.

14. The gate driver circuit according to claim 13, wherein, The voltage transient corresponds to the voltage across the power switch, wherein the voltage across the power switch is the drain - source voltage or the collector - emitter voltage, and wherein the capacitor current is based on the rate of change of the voltage across the power switch.

15. The gate driver circuit according to claim 1, wherein: The power switch is a high - side power switch, The gate driver and the sensing circuit are disposed in the high - side region, and The at least one capacitor is coupled to an input node of the sensing circuit and a reference node of the low - side region.

16. The gate driver circuit according to claim 1, further comprising: A sensing path, the sensing path including a first end and a second end, wherein the sensing path is coupled to the collector or drain of the power switch at the first end and is coupled to the emitter or source of the power switch at the second end, and wherein at least one capacitor is arranged in the sensing path.

17. The gate driver circuit according to claim 1, wherein: the power switch is a low-side power switch, the gate driver and the sensing circuit are arranged in the low-side region, and the at least one capacitor is coupled to an input node of the sensing circuit and a floating reference node of the high-side region.

18. A half-bridge gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a first gate driver arranged in the high-side region and configured to drive the high-side power switch between an on state and an off state using a first adaptive dead time provided during an off-state interval of the high-side power switch; a second gate driver arranged in the low-side region and configured to drive the low-side power switch between an on state and an off state using a second adaptive dead time provided during an off-state interval of the low-side power switch, wherein the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, wherein the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; a phase node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit arranged in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value representing a rate of change of a phase voltage present at the phase node terminal; a second sensing circuit arranged in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value representing a rate of change of a phase voltage present at the phase node terminal; a first comparator circuit configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; a second comparator circuit configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; A first logic circuit configured to receive the first comparison result, indicate a first voltage transient of the phase node terminal based on the first comparison result detecting a first crossing of the first threshold, and indicate an end of the first voltage transient based on the first comparison result detecting a second crossing of the first threshold, wherein the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold; A first active - passive discrimination circuit configured to detect a first switching state of the high - side power switch, including whether the high - side power switch is in an on state or an off state, wherein the first active - passive discrimination circuit is configured to indicate to the first logic circuit whether the first voltage transient is an active voltage transient or a passive voltage transient based on the first switching state of the high - side power switch, and wherein the first logic circuit is configured to adjust the first adaptive dead - time of the high - side power switch based on the first comparison result indicating a second crossing of the first threshold and based on the first voltage transient being the passive voltage transient; A second logic circuit configured to receive the second comparison result, indicate a second voltage transient of the phase node terminal based on the second comparison result detecting a first crossing of the second threshold, and indicate an end of the second voltage transient based on the second comparison result detecting a second crossing of the second threshold, wherein the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold; and A second active - passive discrimination circuit configured to detect a second switching state of the low - side power switch, including whether the low - side power switch is in an on state or an off state, wherein the second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switching state of the low - side power switch, wherein the second logic circuit is configured to adjust the second adaptive dead - time of the low - side power switch based on the second comparison result indicating a second crossing of the second threshold and based on the second voltage transient being the passive voltage transient, and wherein the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.

19. The half-bridge gate driver circuit according to claim 18, wherein, Turning off the high - side power switch is configured to cause the second voltage transient and cause the second sensed value to satisfy the second threshold by making the second sensed value less than the second threshold, and wherein turning off the low - side power switch is configured to cause the first voltage transient and cause the first sensed value to satisfy the first threshold by making the first sensed value less than the first threshold.

20. A method for adjusting an adaptive dead - time, comprising: A drive signal is generated by a gate driver of a gate driver circuit, the drive signal being configured to drive a power switch between an on state and an off state; A voltage transient across the power switch is sensed by a capacitor, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to the slope of the voltage transient; A sensed value is generated at a sense node coupled to the capacitor based on the capacitor current, wherein the sensed value is proportional to the slope of the voltage transient; The sensed value is compared with a threshold by a comparator circuit to generate a comparison result indicating whether the sensed value satisfies the threshold; The logic circuit indicates detection of the voltage transient based on the comparison result for a first crossing of the threshold; The logic circuit indicates an end of the voltage transient based on the comparison result for a second crossing of the threshold, wherein the second crossing occurs after the first crossing and in a direction opposite to the first crossing; A state signal indicating whether the voltage transient is an active voltage transient or a passive voltage transient is generated by an active-passive discrimination circuit based on the switching state of the power switch; and The logic circuit indicates a second crossing of the threshold based on the comparison result and adjusts the adaptive dead time of the power switch based on the voltage transient being the passive voltage transient.

21. A power module, comprising: A high-side region operating in a first voltage domain; A high-side power switch coupled to the high-side region, wherein the high-side power switch includes a first control terminal; A low-side region operating in a second voltage domain lower than the first voltage domain; A low-side power switch coupled to the low-side region, wherein the low-side power switch includes a second control terminal; A first gate driver disposed in the high-side region and coupled to the first control terminal, wherein the first gate driver is configured to drive the high-side power switch between an on state and an off state with a first adaptive dead time provided during an off-state interval of the high-side power switch; A second gate driver disposed in the low-side region and coupled to the second control terminal, wherein the second gate driver is configured to drive the low-side power switch between an on state and an off state with a second adaptive dead time provided during an off-state interval of the low-side power switch, wherein the first adaptive dead time is a delay between an off event of the low-side power switch and an on event of the high-side power switch, wherein the second adaptive dead time is a delay between an off event of the high-side power switch and an on event of the low-side power switch; A phase node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; At least one capacitor, the at least one capacitor being cross-coupled to the high-side region and the low-side region; A first sensing circuit, the first sensing circuit being disposed in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value indicative of a rate of change of a phase voltage present at the phase node terminal; A second sensing circuit, the second sensing circuit being disposed in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value indicative of a rate of change of the phase voltage present at the phase node terminal; A first comparator circuit, the first comparator circuit being configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; A second comparator circuit, the second comparator circuit being configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; A first logic circuit, the first logic circuit being configured to receive the first comparison result, detect a first voltage transient of the phase node terminal based on the first comparison result indicating a first crossing of the first threshold, and detect an end of the first voltage transient based on the first comparison result indicating a second crossing of the first threshold, wherein the second crossing of the first threshold occurs after the first crossing of the first threshold and in a direction opposite to the first crossing of the first threshold; A first active-passive discrimination circuit, the first active-passive discrimination circuit being configured to detect a first switching state of the high-side power switch, including whether the high-side power switch is in an on state or an off state, wherein the first active-passive discrimination circuit is configured to indicate to the first logic circuit whether the first voltage transient is an active voltage transient or a passive voltage transient based on the first switching state of the high-side power switch, and wherein the first logic circuit is configured to adjust the first adaptive dead time of the high-side power switch based on the first comparison result indicating a second crossing of the first threshold and based on the first voltage transient being the passive voltage transient; A second logic circuit, the second logic circuit being configured to receive the second comparison result, detect a second voltage transient of the phase node terminal based on the second comparison result indicating a first crossing of the second threshold, and detect an end of the second voltage transient based on the second comparison result indicating a second crossing of the second threshold, wherein the second crossing of the second threshold occurs after the first crossing of the second threshold and in a direction opposite to the first crossing of the second threshold; and Second active - passive discrimination circuit, the second active - passive discrimination circuit being configured to detect a second switching state of the low - side power switch, including whether the low - side power switch is in an on state or an off state, wherein, the second active - passive discrimination circuit is configured to indicate to the second logic circuit whether the second voltage transient is an active voltage transient or a passive voltage transient based on the second switching state of the low - side power switch, wherein, the second logic circuit is configured to indicate a second crossing of the second threshold based on the second comparison result and to adjust the second adaptive dead - time of the low - side power switch based on the second voltage transient being the passive voltage transient, and wherein, the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.

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