Two-way interlaced BUCK circuit, neutral-point potential balance control method thereof and electric appliance

Abstract

The invention discloses a two-way interlaced BUCK circuit, a neutral-point potential equalization control method thereof and an electric appliance. The neutral-point potential equalization control method comprises the following steps: acquiring and comparing voltage parameters of an upper voltage-dividing capacitor and a lower voltage-dividing capacitor; correcting the initial modulation wave signals of the first switch and the second switch according to the comparison result of the voltage parameters of the upper voltage dividing capacitor and the lower voltage dividing capacitor; and inputting the corrected initial modulation wave signal into a PWM generation circuit to generate a double-path staggered PWM signal for controlling the working states of the first switch and the second switch. Compared with the prior art, the two-way interlaced PWM signal generated by the invention does not influence the voltage reduction stability of the two-way interlaced BUCK circuit, can also realize the balance control of the direct-current bus capacitors, and avoids the problem that the service life of a device is influenced because the voltage difference on the two direct-current bus capacitors is too large.

Description

Technical Field

[0001] The present invention relates to the field of power management, and particularly to a dual-channel interleaved BUCK circuit, a midpoint potential equalization control method thereof, and an electrical appliance. Background Art

[0002] Dual-channel interleaved BUCK circuits have shown significant advantages and potential in the field of modern power management, especially in high-power and high-density application scenarios. Through the dual-channel interleaved design, the ripple current can be effectively reduced, the conversion efficiency can be improved, electromagnetic interference can be reduced, and at the same time, the dynamic response ability of the system can be enhanced. Although its design complexity and cost are relatively high, with the progress of semiconductor technology and the development of digital power management, dual-channel interleaved BUCK circuits are expected to be widely used in more fields and become an important part of efficient power solutions.

[0003] In the topology of a dual-channel interleaved BUCK circuit, the reverse voltage borne by each diode and IGBT is half of the DC bus voltage. Compared with traditional BUCK DC converters, switches with smaller breakdown voltages can be selected at the same voltage level. However, due to the process reasons of the DC-side electrolytic capacitor components themselves and the instantaneous change of the load, the voltage division of the DC-side capacitors is uneven, which in turn leads to an unbalanced reverse voltage bearing of other switching devices. If the midpoint potential equalization control of the DC side is not carried out, it may occur that the voltage on one DC capacitor is the DC input voltage while the voltage on the other DC capacitor is zero, seriously affecting the device life.

[0004] Therefore, how to design a dual-channel interleaved BUCK circuit, a midpoint potential equalization control method thereof, and an electrical appliance that can achieve the midpoint potential equalization control of the DC side is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] Aiming at the problem in the prior art that in a dual-channel interleaved BUCK circuit, due to the process reasons of the DC-side electrolytic capacitor components themselves and the instantaneous change of the load, the voltage division of the DC-side capacitors is uneven, which in turn leads to an unbalanced reverse voltage bearing of other switching devices, the present invention proposes a dual-channel interleaved BUCK circuit, a midpoint potential equalization control method thereof, and an electrical appliance.

[0006] The technical solution of the present invention is to propose a midpoint potential equalization control method for a dual-channel interleaved BUCK circuit, including:

[0007] Collect and compare the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor;

[0008] According to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, correct the initial modulation wave signals of the first switch and the second switch;

[0009] Input the corrected initial modulation wave signal into the PWM generation circuit to generate a dual-channel interleaved PWM signal for controlling the operating states of the first switch and the second switch.

[0010] Further, generating a dual-channel interleaved PWM wave for controlling the operating states of the first switch and the second switch includes:

[0011] Configure the circuit parameters of the timer connected to the PWM generation circuit so that the timer outputs a square wave signal with a preset period;

[0012] Input the square wave signal into an integration circuit to obtain a triangular wave carrier signal with a preset period;

[0013] Compare the corrected initial modulation wave signal with the triangular wave carrier signal in the PWM generation circuit, and output the dual-channel interleaved PWM signal according to the comparison result of the PWM generation circuit.

[0014] Further, before correcting the initial modulation wave signal of the first switch and the second switch, it also includes:

[0015] Collect the output parameters of the dual-channel interleaved BUCK circuit;

[0016] Perform current-voltage double closed-loop control on the output parameters of the dual-channel interleaved BUCK circuit, and perform normalization processing on the output result of the current-voltage double closed-loop control to obtain a normalized signal;

[0017] Perform phase shift processing on the normalized signal, and output the phase-shifted normalized signal and the non-phase-shifted normalized signal through a DAC converter;

[0018] Use the output signal of the DAC converter as the initial modulation wave signal of the first switch and the second switch.

[0019] Further, performing current-voltage double closed-loop control on the output parameters of the dual-channel interleaved BUCK circuit includes:

[0020] Obtain the output voltage of the dual-channel interleaved BUCK circuit, subtract the output voltage from the target voltage, and output the difference to a voltage loop PI controller to generate a target current;

[0021] Obtain the output current of the dual-channel interleaved BUCK circuit, subtract the output current from the target current, and output the difference to a current loop PI controller to generate the output result of the current-voltage double closed-loop control.

[0022] Further, performing phase shift processing on the normalized signal includes:

[0023] Perform a hysteresis process on the normalized signal, where the amplitude of the hysteresis of the normalized signal is half of the carrier period, and the carrier period is the preset period of the square wave signal output by the timer.

[0024] The present invention also proposes a dual-channel interleaved BUCK circuit, including an upper voltage-dividing capacitor and a lower voltage-dividing capacitor connected in series at both ends of the DC input side, and a first switch and a second switch connected across both ends of the output-side capacitor and capable of adjusting the output voltage of the dual-channel interleaved BUCK circuit;

[0025] The dual-channel interleaved BUCK circuit collects and compares the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor;

[0026] According to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, correct the initial modulation wave signals of the first switch and the second switch;

[0027] Input the corrected initial modulation wave signals into a PWM generating circuit to generate dual-channel interleaved PWM signals for controlling the operating states of the first switch and the second switch.

[0028] Further, it includes: resistor R1, resistor R2, switch S1, switch S2, capacitor C1, capacitor C2, output-side capacitor C3, diode D1, diode D2, output-side inductor L;

[0029] The first end of the switch S1 is connected to the positive terminal of the DC-side input voltage, and the second end of the switch S1 is connected to the first end of the output-side capacitor C3 in series through the output-side inductor L;

[0030] The first end of the switch S2 is connected to the negative terminal of the DC-side input voltage, and the second end of the switch S2 is connected to the second end of the output-side capacitor C3;

[0031] The first end of the capacitor C1 is connected between the first end of the switch S1 and the positive terminal of the DC-side input voltage, the first end of the capacitor C1 is connected to the first end of the capacitor C2, and the second end of the capacitor C2 is connected between the first end of the switch S2 and the negative terminal of the DC-side input voltage;

[0032] The first end of the resistor R1 is connected between the first end of the switch S1 and the positive terminal of the DC-side input voltage, the first end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected between the first end of the switch S2 and the negative terminal of the DC-side input voltage;

[0033] The negative electrode of the diode D1 is connected between the second terminal of the switch S1 and the output-side inductor L, the positive electrode of the diode D1 is connected to the negative electrode of the diode D2, and the positive electrode of the diode D2 is connected between the second terminal of the switch S2 and the second terminal of the output-side capacitor C3;

[0034] Between the capacitor C1 and the capacitor C2, between the resistor R1 and the resistor R2, and between the diode D1 and the diode D2 are connected in sequence;

[0035] The switch S1 is the first switch, the switch S2 is the second switch, the capacitor C1 is the upper voltage-dividing capacitor, and the capacitor C2 is the lower voltage-dividing capacitor.

[0036] Further, the dual interleaved BUCK circuit has a first operating mode, a second operating mode, a third operating mode, and a fourth operating mode;

[0037] When the switch S1 and the switch S2 are both turned on, the dual interleaved BUCK circuit operates in the first operating mode, and in the first operating mode, the voltage on the output-side capacitor C3 increases;

[0038] When the switch S1 and the switch S2 are both turned off, the dual interleaved BUCK circuit operates in the second operating mode, and in the second operating mode, the voltage on the output-side capacitor C3 decreases;

[0039] When the switch S1 is turned on and the switch S2 is turned off, the dual interleaved BUCK circuit operates in the third operating mode, and in the third operating mode, the voltage on the output-side capacitor C3 increases;

[0040] When the switch S1 is turned off and the switch S2 is turned on, the dual interleaved BUCK circuit operates in the fourth operating mode, and in the fourth operating mode, the voltage on the output-side capacitor C3 increases.

[0041] Further, the switch S1 and the switch S2 adopt fully controlled switch devices, and the diode D1 and the diode D2 adopt power diodes.

[0042] The present invention also proposes an electrical appliance having the above dual interleaved BUCK circuit.

[0043] Compared with the prior art, the present invention has at least the following beneficial effects:

[0044] In the present invention, a voltage-sharing resistor is added to the input DC side of the dual-channel interleaved BUCK circuit, and the voltage of the DC bus capacitor is sampled. The obtained voltage of the DC bus capacitor is compared through a voltage comparator, and the output result of the comparator is limited by a Schmitt trigger to reduce the influence of the introduction of the DC bus midpoint potential equalization control method on the buck stability. By analyzing the current flow directions of the dual-channel interleaved BUCK circuit in different switching states, the control mechanism of the DC bus capacitor voltage can be obtained. An in-phase addition and subtraction circuit is designed to correct the two PWM modulation waves output by the microprocessor, and the corrected signal is compared with the triangular wave output by the RC integration circuit. The shifted PWM modulation wave lags behind the unshifted modulation wave by half of the carrier frequency period. Therefore, a dual-channel interleaved PWM drive signal can be generated, and then the drive circuit is used to improve the driving ability of the PWM. The generated PWM wave neither affects its buck stability nor can achieve the DC bus capacitor voltage equalization control. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] Figure 1 It is the control schematic diagram of the dual-channel interleaved BUCK circuit in the present invention;

[0047] Figure 2 It is the current schematic diagram of the dual-channel interleaved BUCK circuit in the first working mode of the present invention;

[0048] Figure 3 It is the current schematic diagram of the dual-channel interleaved BUCK circuit in the second working mode of the present invention;

[0049] Figure 4 It is the current schematic diagram of the dual-channel interleaved BUCK circuit in the third working mode of the present invention;

[0050] Figure 5 It is the current schematic diagram of the dual-channel interleaved BUCK circuit in the fourth working mode of the present invention;

[0051] Figure 6 It is the overall control flow chart of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] Therefore, a feature pointed out in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the illustrated feature. In addition, it should be noted that this specification describes many features. Although some features may be combined to show possible system designs, these features may also be used in other combinations not explicitly described. Therefore, unless otherwise stated, the illustrated combination is not intended to be limiting.

[0054] The principle and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0055] In a dual interleaved BUCK circuit topology, the reverse voltage borne by each diode and IGBT is half of the DC bus voltage. Compared with the traditional BUCK DC converter, at the same voltage level, switching devices with a smaller breakdown voltage can be selected. However, due to the process reasons of the DC side electrolytic capacitor device itself and the instantaneous change of the load, the voltage division of the DC side capacitor is uneven, which in turn leads to the imbalance of the reverse voltage borne by other switching devices. If the midpoint potential equalization control of the DC side is not carried out, it may occur that the voltage on one DC capacitor is the DC input voltage while the voltage on the other DC capacitor is zero, seriously affecting the device life.

[0056] In view of the above problems, the present invention proposes a method for midpoint potential equalization control of a dual interleaved BUCK circuit, which includes the following steps:

[0057] Collect and compare the voltage parameters of the upper voltage dividing capacitor and the lower voltage dividing capacitor;

[0058] According to the comparison result of the voltage parameters of the upper voltage dividing capacitor and the lower voltage dividing capacitor, correct the initial modulation wave signals of the first switch and the second switch;

[0059] Input the corrected initial modulation wave signals into the PWM generating circuit to generate dual interleaved PWM signals for controlling the working states of the first switch and the second switch.

[0060] Here, the upper voltage-dividing capacitor and the lower voltage-dividing capacitor are also the two bus capacitors on the DC side in the present invention. In the present invention, by sampling and comparing the voltages of the two bus capacitors, and then correcting the initial modulation wave signal through an in-phase addition and subtraction circuit, the fusion of the error information of the bus capacitors and the initial modulation wave signal can be achieved. Then, by cooperating with the PWM generation circuit to generate the corresponding dual-channel interleaved PWM signal, the balanced control of the bus capacitor voltage can be realized without affecting the buck stability of the dual-channel interleaved BUCK circuit.

[0061] Further, the generation of the dual-channel interleaved PWM wave for controlling the working states of the first switch and the second switch includes:

[0062] Configuring the circuit parameters of the timer connected to the PWM generation circuit to make the timer output a square wave signal with a preset period;

[0063] Inputting the square wave signal into an integration circuit to obtain a triangular wave carrier signal with a preset period;

[0064] Comparing the corrected initial modulation wave signal with the triangular wave carrier signal in the PWM generation circuit, and outputting a dual-channel interleaved PWM signal according to the comparison result of the PWM generation circuit.

[0065] In the present invention, the 555 timer is adopted for the timer, and the above-mentioned circuit parameters are also the parameters such as resistors and capacitors on the peripheral circuit of the 555 timer. The specific principle of this part is as follows:

[0066] By configuring the resistors and capacitors on the peripheral circuit of the 555 timer, the period of the square wave signal output by the 555 timer can be modified (because the output frequency of the 555 timer is f = (R3 + 2R4) * C * 1.44, where R3, R4, and C are the resistors and capacitors used in the peripheral circuit of the 555 timer, and the output frequency can be adjusted by changing the ratio. Since the output frequency and the period are reciprocal to each other, the period of the output square wave signal can be adjusted to be in the preset period);

[0067] Then, the square wave signal is input into the integration circuit, and the integration circuit will integrate the input signal. Therefore, when the output signal of the 555 timer is input into the integration circuit, a triangular wave can be obtained. This triangular wave can be used as the carrier signal required for the modulation link. By comparing the obtained carrier signal with the corrected initial modulation wave signal, a dual-channel interleaved PWM signal can be obtained;

[0068] The general voltage of this dual-channel interleaved PWM signal is only about 5V, which is too low to directly drive an IGBT (the driving voltage of a conventional IGBT is basically around 12V - 15V). In the present invention, a driving chip is connected at the output of the dual-channel interleaved PWM signal, which is used to input the dual-channel interleaved PWM signal into the driving circuit in the driving chip. The driving circuit will not change the duty cycle of the dual-channel interleaved PWM signal, but will increase the high-level voltage of the dual-channel interleaved PWM signal and improve the driving ability of the dual-channel interleaved PWM signal, so that the driving of the IGBT can be realized (the switches S1 and S2 in the present invention are actually IGBTs).

[0069] That is to say, through the above configuration of the 555 timer, the present invention can generate a dual-channel interleaved PWM signal, and improve the driving ability of the dual-channel interleaved PWM signal through the driving circuit, so as to realize the current-voltage double closed-loop control of the dual-channel interleaved BUCK circuit while ensuring the balanced control of the midpoint potential of the DC bus capacitor.

[0070] Further, before correcting the initial modulation wave signals of the first switch and the second switch, the present invention further includes:

[0071] Collecting the output parameters of the dual-channel interleaved BUCK circuit;

[0072] Performing current-voltage double closed-loop control on the output parameters of the dual-channel interleaved BUCK circuit, and performing normalization processing on the output result of the current-voltage double closed-loop control to obtain a normalized signal;

[0073] Performing phase-shifting processing on the normalized signal, and outputting the phase-shifted normalized signal and the non-phase-shifted normalized signal through a DAC converter;

[0074] Using the output signal of the DAC converter as the initial modulation wave signals of the first switch and the second switch.

[0075] This part of the control is also the process of the current-voltage double closed-loop control in the present invention, which is used to obtain the above initial modulation wave signals. Under the logic of this current-voltage double closed-loop control, the stability of the entire dual-channel interleaved BUCK circuit can be taken into account, and at the same time, the accurate control of the output voltage can be realized.

[0076] In addition, the phase-shifting processing of the above normalized signal includes:

[0077] Performing lag processing on the normalized signal, and the lag amplitude of the normalized signal is half of the carrier period, and the carrier period is the preset period of the square wave signal output by the timer.

[0078] The phase shift processing of the normalized signal here is used to generate a two-way interleaved signal. This setting is because the two-way interleaved signal can reduce the inductor current ripple, and the output of the current-voltage double closed-loop control is essentially only one PWM signal. Therefore, the above-mentioned phase shift processing needs to be performed to obtain two interleaved signals, and the interleaved amplitude is the phase shift amplitude, that is, the amplitude by which the normalized signal lags here.

[0079] In the present invention, the amplitude by which the normalized signal lags is half a carrier period. At this time, the PWM signals of the first switch and the second switch differ by half a carrier period. At this time, when the first switch is turned on, the second switch is turned off, and when the first switch is turned off, the second switch is turned on, realizing the switching between the third working mode and the fourth working mode. The circuit has high symmetry and it is easier to achieve the voltage balance of the two bus capacitors.

[0080] Further, the above-mentioned current-voltage double closed-loop control of the output parameters of the two-way interleaved BUCK circuit specifically includes the following steps:

[0081] Obtain the output voltage of the two-way interleaved BUCK circuit, subtract the output voltage from the target voltage, and output the difference to the voltage loop PI controller to generate a target current;

[0082] Obtain the output current of the two-way interleaved BUCK circuit, subtract the output current from the target current, and output the difference to the current loop PI controller to generate the output result of the current-voltage double closed-loop control.

[0083] The current-voltage double closed-loop control has the following advantages:

[0084] 1. Improve control accuracy: By independently controlling the current and voltage, higher control accuracy can be achieved. Each loop has its own PID controller, which can automatically adjust the output signal according to the set value to achieve the desired control effect;

[0085] 2. Enhance system stability: The current-voltage double closed-loop control is an unconditional first-order stable system, so the system has good stability;

[0086] 3. Fast response: Since the feedback of the current and voltage is immediate, the system can quickly respond to changes and improve the response speed of the system.

[0087] Please refer to Figure 1 and Figure 6 , which points out the overall control flow of the present invention, Figure 6 in which the sampled current IL and voltage VOUT are subjected to current-voltage double closed-loop control; that is, the output parameters of the two-way interleaved BUCK circuit are collected as described above, such as Figure 1As shown, the current IL here is the current on the output-side inductor L, that is, the output current in the current-voltage double closed-loop control. The voltage VOUT is the voltage on the output-side capacitor C3, that is, the output voltage in the current-voltage double closed-loop control, and it is collected through the collector in the microprocessor TMS320F28003X. Figure 1 The VREF in it is also the target voltage, which is input to the voltage-loop PI controller together with the collected output voltage for performing voltage-loop control. The signal IREF output by this voltage-loop PI controller is also the target current, which is input to the current-loop PI controller together with the collected output current. The output of this current-loop PI controller is also the output result of the entire current-voltage double closed-loop control;

[0088] Figure 6 The per-unit transformation and phase-shifting processing of the output of the PI controller in it, corresponding to the attachment Figure 1 The per-unit transformation in it, that is, the phase-shifting processing is performed after the above-mentioned normalization processing;

[0089] Figure 6 The DAC output in it is also to output the above-mentioned initial modulation wave signal, and the initial modulation wave signal it outputs is also the attachment Figure 1 The two signals DACOUT1 and DACOUT2 in it;

[0090] Figure 6 The voltage comparison of the DC capacitor voltages V1 and V2 in it, that is, the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor collected and compared in the previous text. It can be clearly seen from the attachment Figure 1 that the voltage on the upper voltage-dividing capacitor here is the DC capacitor voltage V1, and the voltage on the lower voltage-dividing capacitor is the DC capacitor voltage V2. In the present invention, after comparing the above-mentioned DC capacitor voltages V1 and V2 through a voltage comparator, they are also input to a Schmitt trigger for output limitation. This is because the primary index of the dual-channel interleaved BUCK circuit is to ensure buck stability. Therefore, the output of the voltage comparator is limited by the Schmitt trigger to prevent the output of the voltage comparator from adjusting DACOUT1 and DACOUT2 too much and reducing the reliability of the dual-channel interleaved BUCK circuit;

[0091] Figure 6 The result of the comparator in it corrects the DAC result through an in-phase addition and subtraction circuit, that is, the initial modulation wave signals of the first switch and the second switch are corrected according to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor in the previous text. It can be clearly seen from the attachment Figure 1 that the output of the above-mentioned voltage comparator is respectively input to the in-phase addition circuit and the in-phase subtraction circuit through the Schmitt trigger, that is, the DAC result is corrected through the in-phase addition and subtraction circuit as above;

[0092] Figure 6 The corrected signal is input into the PWM generation circuit to generate a dual-channel interleaved PWM wave, that is, the corrected initial modulation wave signal is input into the PWM generation circuit as described above to generate a dual-channel interleaved PWM signal for controlling the operating states of the first switch and the second switch, as Figure 1 shown. The above PWM generation circuit is also a voltage comparator for outputting PWM1 signal and PWM2 signal, and this voltage comparator is also connected to the output terminal of the 555 timer. After configuring the 555 timer, a dual-channel interleaved PWM signal with a preset period can be output.

[0093] The above is the overall control flow of the present invention. Based on the above control method, the present invention also proposes a dual-channel interleaved BUCK circuit, which includes an upper voltage-dividing capacitor and a lower voltage-dividing capacitor connected in series at both ends of the DC input side, and a first switch and a second switch connected to both ends of the output-side capacitor and used to adjust the output voltage of the dual-channel interleaved BUCK circuit;

[0094] The dual-channel interleaved BUCK circuit collects and compares the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor;

[0095] According to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, the initial modulation wave signals of the first switch and the second switch are corrected;

[0096] The corrected initial modulation wave signal is input into the PWM generation circuit to generate a dual-channel interleaved PWM signal for controlling the operating states of the first switch and the second switch.

[0097] As described above, in the present invention, by sampling and comparing the voltages of the two bus capacitors, and then correcting the initial modulation wave signal through a common-phase addition and subtraction circuit, the error information of the bus capacitors can be fused with the initial modulation wave signal. Then, by cooperating with the PWM generation circuit to generate the corresponding dual-channel interleaved PWM signal, the voltage balance control of the bus capacitors can be achieved without affecting the buck stability of the dual-channel interleaved BUCK circuit.

[0098] Please refer to Figure 1 , the dual-channel interleaved BUCK circuit in the present invention specifically includes: resistor R1, resistor R2, switch S1, switch S2, capacitor C1, capacitor C2, output-side capacitor C3, diode D1, diode D2, output-side inductor L;

[0099] The first end of switch S1 is connected to the positive end of the DC-side input voltage, and the second end of switch S1 is connected to the first end of output-side inductor L in series and then to the first end of output-side capacitor C3;

[0100] The first end of switch S2 is connected to the negative end of the DC-side input voltage, and the second end of switch S2 is connected to the second end of output-side capacitor C3;

[0101] The first terminal of capacitor C1 is connected between the first terminal of switch S1 and the positive terminal of the DC-side input voltage. The first terminal of capacitor C1 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected between the first terminal of switch S2 and the negative terminal of the DC-side input voltage.

[0102] The first terminal of resistor R1 is connected between the first terminal of switch S1 and the positive terminal of the DC-side input voltage. The first terminal of resistor R1 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected between the first terminal of switch S2 and the negative terminal of the DC-side input voltage.

[0103] The cathode of diode D1 is connected between the second terminal of switch S1 and the output-side inductor L. The anode of diode D1 is connected to the cathode of diode D2. The anode of diode D2 is connected between the second terminal of switch S2 and the second terminal of the output-side capacitor C3.

[0104] Between capacitor C1 and capacitor C2, between resistor R1 and resistor R2, and between diode D1 and diode D2 are connected in sequence.

[0105] Among them, C1 is the upper voltage-dividing capacitor on the DC side of the dual-path interleaved BUCK circuit, C2 is the lower voltage-dividing capacitor on the DC side of the dual-path interleaved BUCK circuit, C3 is the output-side capacitor of the dual-path interleaved BUCK circuit, V1 is the voltage on the upper voltage-dividing capacitor C1, V2 is the voltage on the lower voltage-dividing capacitor C2, VOUT is the voltage on the output-side capacitor C3, that is, the output voltage of the dual-path interleaved BUCK circuit.

[0106] O is the midpoint of the DC bus of the NPC-type three-level inverter, that is, the cathode of the voltage-dividing capacitor C1 and the anode of the voltage-dividing capacitor C2.

[0107] R1 and R2 are DC bus voltage-sharing resistors, and L is the output-side inductor.

[0108] VIN is the DC-side input voltage of the dual-path interleaved BUCK circuit.

[0109] S1 and S2 are fully controlled switch devices (IGBTs). Among them, S1 is the first switch, S2 is the second switch, g1 and g2 are the drive signals of the first switch S1 and the second switch S2, and D1 and D2 are power diodes.

[0110] In the microprocessor, current-voltage double closed-loop control is performed to output dual-channel drive modulation wave signals DACOUT1 and DACOUT2. The designed DC bus capacitor voltage equalization control circuit includes a 555 timer, an integration circuit, a non-inverting addition and subtraction circuit, a voltage comparison circuit, and a drive circuit.

[0111] The above-mentioned dual-channel interleaved BUCK circuit, through the dual-channel interleaved design, can effectively reduce the ripple current, improve the conversion efficiency, reduce electromagnetic interference, and at the same time enhance the dynamic response ability of the system.

[0112] Furthermore, the dual-channel interleaved BUCK circuit in the present invention has a first operating mode, a second operating mode, a third operating mode, and a fourth operating mode;

[0113] When switches S1 and S2 are turned on simultaneously, the dual-channel interleaved BUCK circuit operates in the first operating mode, and in the first operating mode, the voltage on the output-side capacitor C3 increases;

[0114] When switches S1 and S2 are turned off simultaneously, the dual-channel interleaved BUCK circuit operates in the second operating mode, and in the second operating mode, the voltage on the output-side capacitor C3 decreases;

[0115] When switch S1 is turned on and switch S2 is turned off, the dual-channel interleaved BUCK circuit operates in the third operating mode, and in the third operating mode, the voltage on the output-side capacitor C3 increases;

[0116] When switch S1 is turned off and switch S2 is turned on, the dual-channel interleaved BUCK circuit operates in the fourth operating mode, and in the fourth operating mode, the voltage on the output-side capacitor C3 increases.

[0117] Please refer to Figure 2 , in the first operating mode, the DC input voltage VIN forms a loop through the output-side inductor L, the output-side capacitor C3, and the load, and the current flows into the output-side capacitor C3 for charging, and at this time the output voltage VOUT gradually increases;

[0118] Please refer to Figure 3 , in the second operating mode, assuming that the freewheeling of the output-side inductor L has been completed at this time, the output-side capacitor C3 and the load form a loop, and the current flows out from the output-side capacitor C3 to supply power to the load, and at this time the output voltage VOUT gradually decreases;

[0119] Please refer to Figure 4 , in the third operating mode, the voltage V1 on the upper voltage-dividing capacitor C1 forms a loop through the output-side inductor L, the power diode D2, the output-side capacitor C3, and the load, and the current flows into the output-side capacitor C3 for charging, and at this time the output voltage VOUT gradually increases;

[0120] Please refer to Figure 5 , in the fourth operating mode, the voltage V2 on the lower voltage-dividing capacitor C2 forms a loop through the output-side inductor L, the power diode D1, the output-side capacitor C3, and the load, and the current flows into the output-side capacitor C3 for charging, and at this time the output voltage VOUT gradually increases;

[0121] As can be seen from the four operating modes of the above-mentioned dual-path interleaved BUCK circuit, by controlling the first switch S1 and the second switch S2, the control of the output voltage can be achieved. That is to say, in the present invention, the operating mode of the dual-path interleaved BUCK circuit can be switched by the first switch and the second switch, so as to adapt to the actual needs and adjust the magnitude of the output voltage.

[0122] Furthermore, in the present invention, the switch S1 and the switch S2 adopt fully controlled switch devices, and the diodes D1 and D2 adopt power diodes.

[0123] Among them, the fully controlled switch device is namely IGBT, which has the advantages of high voltage and current handling capabilities, high input impedance, low on-resistance, and high power gain.

[0124] The diodes D1 and D2 adopt power diodes, which have the advantages of high voltage and large current bearing capabilities, fast recovery, and high efficiency.

[0125] Based on the above-mentioned dual-path interleaved BUCK circuit, the present invention also proposes an electrical appliance, which has the above-mentioned dual-path interleaved BUCK circuit.

[0126] To sum up, compared with the prior art, the present invention has at least the following beneficial effects:

[0127] In the present invention, a voltage-sharing resistor is added to the input DC side of the dual-path interleaved BUCK circuit, and the voltage of the DC bus capacitor is sampled. The obtained voltage of the DC bus capacitor is compared by a voltage comparator, and the output result of the comparator is limited by a Schmitt trigger to reduce the influence of the introduction of the DC bus midpoint potential balancing control method on the buck stability. By analyzing the current flow direction of the dual-path interleaved BUCK circuit under different switch states, the control mechanism of the DC bus capacitor voltage can be obtained. An in-phase addition and subtraction circuit is designed to correct the two-way PWM modulation waves output by the microprocessor, and the corrected signal is compared with the triangular wave output by the RC integration circuit. The shifted PWM modulation wave lags behind the unshifted modulation wave by half a carrier cycle. Therefore, a dual-path interleaved PWM drive signal can be generated, and then the drive circuit is used to improve the driving ability of the PWM. The generated PWM wave neither affects its buck stability nor can achieve the DC bus capacitor voltage balancing control.

[0128] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for controlling the midpoint potential balance of a dual-path interleaved BUCK circuit. The dual-path interleaved BUCK circuit includes an upper voltage-dividing capacitor and a lower voltage-dividing capacitor connected in series at both ends of the DC input side, and a first switch and a second switch connected across the output side capacitor and capable of adjusting the output voltage of the dual-path interleaved BUCK circuit. It is characterized in that, The described midpoint potential balancing control method includes: Collect and compare the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor; According to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, correct the initial modulation wave signals of the first switch and the second switch; Input the corrected initial modulation wave signals into a PWM generating circuit to generate a dual-channel interleaved PWM signal for controlling the working states of the first switch and the second switch.

2. The method for controlling the midpoint potential balance of the dual-path interleaved BUCK circuit according to claim 1, wherein, Generating a dual-channel interleaved PWM wave for controlling the working states of the first switch and the second switch includes: Configure the circuit parameters of the timer connected to the PWM generating circuit to make the timer output a square wave signal with a preset period; Input the square wave signal into an integration circuit to obtain a triangular wave carrier signal with a preset period; Compare the corrected initial modulation wave signal with the triangular wave carrier signal in the PWM generating circuit, and output the dual-channel interleaved PWM signal according to the comparison result of the PWM generating circuit.

3. The method for balancing the midpoint potential of the dual-channel interleaved BUCK circuit according to claim 1, characterized in that Before correcting the initial modulation wave signals of the first switch and the second switch, it further includes: Collect the output parameters of the dual-channel interleaved BUCK circuit; Perform current-voltage dual-loop control on the output parameters of the dual-channel interleaved BUCK circuit, and perform normalization processing on the output result of the current-voltage dual-loop control to obtain a normalized signal; Perform phase-shifting processing on the normalized signal, and output the phase-shifted normalized signal and the non-phase-shifted normalized signal through a DAC converter; Use the output signal of the DAC converter as the initial modulation wave signals of the first switch and the second switch.

4. The method for controlling the midpoint potential balance of the dual-path interleaved BUCK circuit according to claim 3, characterized in that, Performing current-voltage dual-loop control on the output parameters of the dual-channel interleaved BUCK circuit includes: Obtain the output voltage of the dual-channel interleaved BUCK circuit, subtract the output voltage from the target voltage, and output the difference to a voltage-loop PI controller to generate a target current; Obtain the output current of the dual-channel interleaved BUCK circuit, subtract the output current from the target current, and output the difference to a current-loop PI controller to generate the output result of the current-voltage dual-loop control.

5. The method for controlling the midpoint potential balance of the dual-channel interleaved BUCK circuit according to claim 3, characterized in that Performing phase-shifting processing on the normalized signal includes: Perform lag processing on the normalized signal, and the lag amplitude of the normalized signal is half of the carrier period, and the carrier period is the preset period of the square wave signal output by the timer.

6. A dual-channel interleaved BUCK circuit, characterized in that, It includes an upper voltage-dividing capacitor and a lower voltage-dividing capacitor connected in series at both ends of the DC input side, and a first switch and a second switch connected to both ends of the output-side capacitor and capable of adjusting the output voltage of the dual-channel interleaved BUCK circuit; The dual-channel interleaved BUCK circuit collects and compares the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor; According to the comparison result of the voltage parameters of the upper voltage-dividing capacitor and the lower voltage-dividing capacitor, correct the initial modulation wave signals of the first switch and the second switch; Input the corrected initial modulation wave signals into a PWM generating circuit to generate a dual-channel interleaved PWM signal for controlling the working states of the first switch and the second switch.

7. The dual-path interleaved BUCK circuit according to claim 6, wherein It includes: Resistor R1, resistor R2, switch S1, switch S2, capacitor C1, capacitor C2, output-side capacitor C3, diode D1, diode D2, output-side inductor L; The first terminal of the switch S1 is connected to the positive terminal of the DC-side input voltage, and the second terminal of the switch S1 is connected to the first terminal of the output-side capacitor C3 in series with the output-side inductor L; The first terminal of the switch S2 is connected to the negative terminal of the DC-side input voltage, and the second terminal of the switch S2 is connected to the second terminal of the output-side capacitor C3; The first terminal of the capacitor C1 is connected between the first terminal of the switch S1 and the positive terminal of the DC-side input voltage. The first terminal of the capacitor C1 is connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is connected between the first terminal of the switch S2 and the negative terminal of the DC-side input voltage; The first terminal of the resistor R1 is connected between the first terminal of the switch S1 and the positive terminal of the DC-side input voltage. The first terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected between the first terminal of the switch S2 and the negative terminal of the DC-side input voltage; The negative electrode of the diode D1 is connected between the second terminal of the switch S1 and the output-side inductor L. The positive electrode of the diode D1 is connected to the negative electrode of the diode D2, and the positive electrode of the diode D2 is connected between the second terminal of the switch S2 and the second terminal of the output-side capacitor C3; Between the capacitor C1 and the capacitor C2, between the resistor R1 and the resistor R2, and between the diode D1 and the diode D2 are connected in sequence; The switch S1 is the first switch, the switch S2 is the second switch, the capacitor C1 is the upper voltage-dividing capacitor, and the capacitor C2 is the lower voltage-dividing capacitor.

8. The dual-path interleaved BUCK circuit according to claim 7, characterized in that, The dual-path interleaved BUCK circuit has a first operating mode, a second operating mode, a third operating mode, and a fourth operating mode; When the switch S1 and the switch S2 are both turned on, the dual-path interleaved BUCK circuit operates in the first operating mode, and in the first operating mode, the voltage on the output-side capacitor C3 increases; When the switch S1 and the switch S2 are both turned off, the dual-path interleaved BUCK circuit operates in the second operating mode, and in the second operating mode, the voltage on the output-side capacitor C3 decreases; When the switch S1 is turned on and the switch S2 is turned off, the dual-path interleaved BUCK circuit operates in the third operating mode, and in the third operating mode, the voltage on the output-side capacitor C3 increases; When the switch S1 is turned off and the switch S2 is turned on, the dual-path interleaved BUCK circuit operates in the fourth operating mode, and in the fourth operating mode, the voltage on the output-side capacitor C3 increases.

9. The dual-path interleaved BUCK circuit according to claim 8, wherein The switch S1 and the switch S2 use fully controlled switch devices, and the diode D1 and the diode D2 use power diodes.

10. An electrical appliance, characterized in that, The electrical appliance has the dual-path interleaved BUCK circuit according to any one of claims 6 to 9.

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