Seven-level clamped converter topology and voltage balance modulation method thereof

Abstract

The invention discloses a seven-level clamping type converter topology and a voltage balance modulation method thereof, and relates to the field of converter voltage modulation. The seven-level clamping type converter topology comprises a direct-current bus capacitor, three-phase circuits and a direct-current input source, carrier signals and modulation signals are logically compared, a preset switch state table and the voltage deviation of each flying capacitor in each phase of circuit are combined, and the voltage deviation of each flying capacitor in each phase of circuit is calculated. And a switch tube of the seven-level clamping type converter topology is regulated and controlled, so that the voltage balance of the seven-level clamping type converter topology is ensured. Through the switch state table, the power conversion efficiency can be optimized, and the voltage stress of devices in the converter can be reduced, so that the voltage stress distribution balance of the devices in the converter is ensured, the unbalanced heat loss and overlarge heat loss of the converter devices caused by the unbalanced voltage stress distribution are avoided, the converter can adapt to different working conditions, and the service life of the converter is prolonged. And the applicability and the practicability of the converter are improved.

Description

Technical Field

[0001] The present invention relates to the field of converter voltage modulation, and particularly to a seven-level clamped converter topology and its voltage balance modulation method. Background Art

[0002] As a new type of multilevel converter, the seven-level converter has broad application prospects. For example, it plays a crucial role in fields such as high-voltage direct current transmission and flexible direct current transmission in power systems. The seven-level converter converts the DC voltage into AC voltages of different levels by controlling the on and off of switching devices.

[0003] During the operation of the seven-level converter, the devices in the converter need to withstand large voltage stresses, and the number of devices in the seven-level converter is numerous. This also leads to the technical defects of serious imbalance in the voltage stress distribution of the existing devices in the seven-level converter and excessive total voltage stress of the converter. These technical defects will cause uneven distribution of device heat losses in the converter, resulting in the converter malfunctioning or not meeting the working standards. Therefore, there is an urgent need for a new seven-level clamped converter topology to solve the defects in the existing technology. Summary of the Invention

[0004] The present invention provides a seven-level clamped converter topology and its voltage balance modulation method to solve the technical problem of uneven distribution of device heat losses in the existing seven-level converter.

[0005] To solve the above technical problem, an embodiment of the present invention provides a seven-level clamped converter topology, including: a DC input source, a DC bus capacitor, and a three-phase circuit; wherein, the DC bus capacitor and the three-phase circuit are connected in parallel to the DC input source;

[0006] The three-phase circuit includes a first-phase circuit, a second-phase circuit, and a third-phase circuit, and the structure of each phase circuit is the same;

[0007] Each phase circuit of the three-phase circuit includes: twelve switching tubes and three flying capacitors; among them, the first switching tube, the second switching tube, the third switching tube, the seventh switching tube, the eighth switching tube, and the sixth switching tube are connected in series in sequence; the first H-bridge composed of the fourth switching tube, the fifth switching tube, the tenth switching tube, and the ninth switching tube is connected between the third switching tube and the seventh switching tube; the second H-bridge composed of the first flying capacitor, the second flying capacitor, the eleventh switching tube, and the twelfth switching tube is connected across the first switching tube, the second switching tube, the third switching tube, the seventh switching tube, the eighth switching tube, and the sixth switching tube connected in series in sequence; the third flying capacitor is connected to the first H-bridge.

[0008] It can be understood that, compared with the prior art, the seven-level clamped converter topology of the present invention has a DC bus capacitor and a three-phase circuit connected in parallel to the DC input source. Through the first switch tube, the second switch tube, the third switch tube, the seventh switch tube, the eighth switch tube and the sixth switch tube connected in series in sequence, and the first H-bridge composed of the fourth switch tube, the fifth switch tube, the tenth switch tube and the ninth switch tube, the first flying capacitor, the second flying capacitor, the second H-bridge composed of the eleventh switch tube and the twelfth switch tube, and the third flying capacitor connected to the first H-bridge circuit, through the coordinated opening and closing of multiple switch tubes and the working characteristics of the H-bridge circuit, the voltage regulation of the converter is optimized. While reducing the voltage stress of each switch tube in the converter, the voltage balance of the flying capacitors in the converter is maintained, thereby reducing the total device voltage stress of the converter, ensuring the balanced distribution of the voltage stress of the devices in the converter, avoiding the uneven thermal loss and excessive thermal loss of the converter devices caused by the uneven voltage stress distribution, and ensuring the working performance and stable operation of the converter.

[0009] As a preferred solution, in each phase circuit of the three-phase circuit, the drain of the first switch tube is connected to the positive terminal of the DC input source and the anode of the DC bus capacitor, the source of the first switch tube is connected to the drain of the second switch tube and the anode of the first flying capacitor, the source of the second switch tube is connected to the drain of the third switch tube and the drain of the eleventh switch tube, the source of the eleventh switch tube is connected to the cathode of the first flying capacitor, the anode of the second flying capacitor and the drain of the twelfth switch tube, the source of the twelfth switch tube is connected to the drain of the eighth switch tube and the source of the seventh switch tube, the source of the eighth switch tube is connected to the drain of the sixth switch tube and the cathode of the second flying capacitor, the source of the third switch tube is connected to the drain of the seventh switch tube, the drain of the ninth switch tube and the source of the fourth switch tube, the drain of the fourth switch tube is connected to the anode of the third flying capacitor and the drain of the fifth switch tube, the source of the ninth switch tube is connected to the cathode of the third flying capacitor and the source of the tenth switch tube, and the source of the fifth switch tube is connected to the drain of the tenth switch tube.

[0010] As a preferred solution, the source of the fifth switch tube in each phase circuit of the three-phase circuit is used as the output terminal of the corresponding phase circuit.

[0011] As a preferred solution, in the three-phase circuit, the carrier waves between the first phase circuit, the second phase circuit and the third phase circuit are the same, and the modulation waves are phase-shifted by 120°; the corresponding switch tubes in the first phase circuit, the second phase circuit and the third phase circuit are controlled by the same control method.

[0012] As a preferred solution, in each phase circuit of the three-phase circuit, the driving signal of the sixth switching tube is complementary to the driving signal of the first switching tube, the driving signal of the seventh switching tube is complementary to the driving signal of the second switching tube, the driving signal of the eighth switching tube is complementary to the driving signal of the third switching tube, the driving signal of the ninth switching tube is complementary to the driving signal of the fourth switching tube, the driving signal of the tenth switching tube is complementary to the driving signal of the fifth switching tube, the driving signal of the eleventh switching tube is the same as the driving signal of the seventh switching tube, and the driving signal of the twelfth switching tube is the same as the driving signal of the third switching tube.

[0013] As a preferred solution, in the three-phase circuit, the voltage stresses of the corresponding switching tubes and flying capacitors between the first-phase circuit, the second-phase circuit, and the third-phase circuit are the same.

[0014] As a preferred solution, the voltage stresses of the first switching tube, the second switching tube, the third switching tube, the sixth switching tube, the seventh switching tube, the eighth switching tube, the eleventh switching tube, the twelfth switching tube, the first flying capacitor, and the second flying capacitor are one-third of the power supply input by the DC input source, and the voltage stresses of the fourth switching tube, the fifth switching tube, the ninth switching tube, the tenth switching tube, and the third flying capacitor are one-sixth of the power supply input by the DC input source.

[0015] Correspondingly, the embodiment of the present invention provides a voltage balance modulation method for a seven-level clamped converter topology, including:

[0016] Obtain a seven-level clamped converter topology as described above, and obtain a modulation signal, a carrier signal, and the voltage deviation of each flying capacitor in each phase circuit input to the seven-level clamped converter topology, where the modulation signal includes: a first-phase modulation signal, a second-phase modulation signal, and a third-phase modulation signal, and the carrier signal includes: a first carrier signal, a second carrier signal, a third carrier signal, a fourth carrier signal, a fifth carrier signal, and a sixth carrier signal;

[0017] Logically compare the carrier signal and the modulation signal, and combine the preset switch state table and the voltage deviation of each flying capacitor in each phase circuit to control the switching tubes of the seven-level clamped converter topology to keep the voltage of the seven-level clamped converter topology balanced.

[0018] It can be understood that, compared with the prior art, the present invention controls the switching tubes of the seven-level clamped converter topology by logically comparing the carrier signal and the modulation signal, and combining the preset switching state table and the voltage deviation of each flying capacitor in each phase circuit, thereby ensuring the voltage balance of the seven-level clamped converter topology. Through the switching state table, the power conversion efficiency can be optimized, the voltage stress of the devices in the converter can be reduced, so as to ensure the balanced distribution of the voltage stress of the devices in the converter, avoid the uneven thermal loss and excessive thermal loss of the converter devices caused by the uneven distribution of the voltage stress, and also enable the converter to adapt to different working conditions, improving the applicability and practicality of the converter.

[0019] As a preferred solution, the obtaining of the modulation signal and the carrier signal input to the seven-level clamped converter topology specifically includes:

[0020] Obtaining the modulation signal of the seven-level clamped converter topology:

[0021]

[0022] where m is the modulation ratio of the converter, u refa is the modulation signal of the first phase, u refb is the modulation signal of the second phase, u refc is the modulation signal of the third phase;

[0023] Respectively obtaining the voltage deviations of the three flying capacitors in each phase circuit of the seven-level clamped converter topology:

[0024]

[0025] where ΔU fx1 is the voltage deviation of the first flying capacitor in each phase circuit, ΔU fx2 is the voltage deviation of the first flying capacitor in the second phase circuit, ΔU fx3 is the voltage deviation of the third flying capacitor in each phase circuit; when x = a, it represents the first phase circuit, when x = b, it represents the second phase circuit, and when x = c, it represents the third phase circuit.

[0026] As a preferred solution, the logically comparing the carrier signal and the modulation signal, and combining the preset switching state table and the voltage deviation of each flying capacitor in each phase circuit to control the switching tubes of the seven-level clamped converter topology specifically includes: obtaining the modulation signal of one or any number of phase circuits and the corresponding phase circuit output current value, numerically comparing the modulation signal with each carrier signal in turn; according to the comparison result, combining the voltage deviation of each flying capacitor in the corresponding phase circuit and the phase circuit output current value, and selecting the corresponding switching tubes in the seven-level clamped converter topology to conduct according to the preset switching state table. Description of the Drawings

[0027] Figure 1 : A topological schematic diagram of a seven-level clamped converter topology provided by an embodiment of the present invention;

[0028] Figure 2 : A flowchart of the steps of a voltage balance modulation method for a seven-level clamped converter topology provided by an embodiment of the present invention

[0029] Figure 3 : An equivalent circuit diagram of the first operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0030] Figure 4 : An equivalent circuit diagram of the second operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0031] Figure 5 : An equivalent circuit diagram of the third operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0032] Figure 6 : An equivalent circuit diagram of the fourth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0033] Figure 7 : An equivalent circuit diagram of the fifth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0034] Figure 8 : An equivalent circuit diagram of the sixth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0035] Figure 9 : An equivalent circuit diagram of the seventh operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0036] Figure 10 : An equivalent circuit diagram of the eighth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0037] Figure 11 : An equivalent circuit diagram of the ninth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0038] Figure 12 : An equivalent circuit diagram of the tenth operating state of any phase circuit of a seven-level clamped converter provided by an embodiment of the present invention;

[0039] Figure 13 : It is the equivalent circuit diagram of the eleventh working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0040] Figure 14 : It is the equivalent circuit diagram of the twelfth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0041] Figure 15 : It is the equivalent circuit diagram of the thirteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0042] Figure 16 : It is the equivalent circuit diagram of the fourteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0043] Figure 17 : It is the equivalent circuit diagram of the fifteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0044] Figure 18 : It is the equivalent circuit diagram of the sixteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention;

[0045] Figure 19 : It is the voltage balance modulation classification diagram of a seven-level clamped converter topology provided by the embodiment of the present invention;

[0046] Figure 20 : It is the schematic diagram of the switching tube drive signal corresponding to the voltage balance modulation strategy provided by the embodiment of the present invention. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0048] When the seven-level converter topology appears, it provides a new way to achieve high conversion efficiency, high power density and other indicators of medium-voltage high-power converters. However, the existing seven-level converter topologies have the disadvantages of serious imbalance in the device voltage stress distribution, large number of power devices and uneven device loss distribution. Specifically, during the operation of the seven-level converter, the devices in the converter need to bear a large voltage stress, and the number of devices in the seven-level converter is numerous, which also leads to the technical defects of serious imbalance in the device voltage stress distribution and excessive total voltage stress in the existing seven-level converters. These technical defects will cause uneven distribution of device thermal losses in the converter, resulting in converter failure or inability to meet the working standards.

[0049] Embodiment 1

[0050] Please refer to Figure 1 , which is a topological schematic diagram of a seven-level clamped converter topology provided by an embodiment of the present invention, including: a DC input source U dc , a DC bus capacitor C dc and a three-phase circuit; wherein, the DC bus capacitor C dc is connected in parallel with the three-phase circuit to the DC input source U dc ;

[0051] The three-phase circuit includes a first-phase circuit (phase A circuit), a second-phase circuit (phase B circuit) and a third-phase circuit (phase C circuit), and the structure of each phase circuit is the same;

[0052] Each phase circuit of the three-phase circuit includes: twelve switching tubes and three flying capacitors; among them, the first switching tube S x1 , the second switching tube S x2 , the third switching tube S x3 , the seventh switching tube S x2 ', the eighth switching tube S x3 ' and the sixth switching tube S x1 ' are connected in series in sequence; the first H-bridge composed of the fourth switching tube S x4 , the fifth switching tube S x5 , the tenth switching tube S x5 ' and the ninth switching tube S x4 ' is connected between the third switching tube S x3 and the seventh switching tube S x2 '; the first flying capacitor C fx1 , the second flying capacitor C fx2 , the eleventh switching tube S x6 and the twelfth switching tube S x7 form a second H-bridge that is bridged across the first switching tube S x1 , the second switching tube S x2 , the third switching tube Sx3 and the seventh switching transistor S x2 ′, the eighth switching transistor S x3 ′, and the sixth switching transistor S x1 ′; The third flying capacitor C fx3 is connected to the first H-bridge.

[0053] It should be noted that in the description of each phase circuit of the three-phase circuit above, x can be a, b, or c. When x is a, it represents the A-phase circuit of the first phase circuit; when x is b, it represents the B-phase circuit of the second phase circuit; when x is c, it represents the C-phase circuit of the third phase circuit.

[0054] In this embodiment, in each phase circuit of the three-phase circuit, the drain of the first switching transistor is connected to the positive terminal of the DC input source and the anode of the DC bus capacitor. The source of the first switching transistor is connected to the drain of the second switching transistor and the anode of the first flying capacitor. The source of the second switching transistor is connected to the drain of the third switching transistor and the drain of the eleventh switching transistor. The source of the eleventh switching transistor is connected to the cathode of the first flying capacitor, the anode of the second flying capacitor, and the drain of the twelfth switching transistor. The source of the twelfth switching transistor is connected to the drain of the eighth switching transistor and the source of the seventh switching transistor. The source of the eighth switching transistor is connected to the drain of the sixth switching transistor and the cathode of the second flying capacitor. The source of the third switching transistor is connected to the drain of the seventh switching transistor, the drain of the ninth switching transistor, and the source of the fourth switching transistor. The drain of the fourth switching transistor is connected to the anode of the third flying capacitor and the drain of the fifth switching transistor. The source of the ninth switching transistor is connected to the cathode of the third flying capacitor and the source of the tenth switching transistor. The source of the fifth switching transistor is connected to the drain of the tenth switching transistor.

[0055] By connecting each switching transistor and the flying capacitor, combined with the structural characteristics of the H-bridge, the voltage stress of each switching transistor in the converter is maintained not to exceed the preset standard, reducing the total voltage stress of the converter.

[0056] In an alternative embodiment, the A-phase circuit of the first phase circuit of the three-phase circuit includes: the first switching transistor S a1 , the second switching transistor S a2 , the third switching transistor S a3 , the fourth switching transistor S a4 , the fifth switching transistor S a5 , the sixth switching transistor S a1 ′, the seventh switching transistor S a2 ′, the eighth switching transistor S a3 ′, the ninth switching transistor S a4 ′, the tenth switching transistor S a5 ′, the eleventh switching transistor S a6 , the twelfth switching transistor S a7 , the first flying capacitor C fα1 , the second flying capacitor Cfα2 and the third flying capacitor C fα3 .

[0057] In an alternative embodiment, the connection mode of the first-phase circuit A-phase circuit of the three-phase circuit includes: the drain of the first switching transistor S a1 is connected to the positive terminal of the DC input source U dc and the anode of the DC bus capacitor C dc , the source of the first switching transistor S a1 is connected to the drain of the second switching transistor S a2 and the anode of the first flying capacitor C fα1 , the source of the second switching transistor S a2 is connected to the drain of the third switching transistor S a3 and the drain of the eleventh switching transistor S a6 , the source of the eleventh switching transistor S a6 is connected to the cathode of the first flying capacitor C fα1 , the anode of the second flying capacitor C fα2 and the drain of the twelfth switching transistor S a7 , the source of the twelfth switching transistor S a7 is connected to the drain of the eighth switching transistor S a3 ' and the source of the seventh switching transistor S a2 ', the source of the eighth switching transistor S a3 ' is connected to the drain of the sixth switching transistor S a1 ' and the cathode of the second flying capacitor C fα2 , the source of the third switching transistor S a3 is connected to the drain of the seventh switching transistor S a2 ', the drain of the ninth switching transistor S a4 ' and the source of the fourth switching transistor S a4 , the drain of the fourth switching transistor S a4 is connected to the anode of the third flying capacitor C fα3 and the drain of the fifth switching transistor S a5 , the source of the ninth switching transistor S a4 ' is connected to the cathode of the third flying capacitor C fα3 and the source of the tenth switching transistor S a5 ', the source of the fifth switching transistor S a5 is connected to the drain of the tenth switching transistor S a5 .

[0058] In an alternative embodiment, the second-phase circuit B-phase circuit of the three-phase circuit includes: the first switching transistor S b1 , the second switching transistor S b2 , the third switching transistor S b3 , the fourth switching transistor S b4 , the fifth switching transistor S b5, the sixth switching transistor S b1 ′, the seventh switching transistor S b2 ′, the eighth switching transistor S b3 ′, the ninth switching transistor S b4 ′, the tenth switching transistor S b5 ′, the eleventh switching transistor S b6 , the twelfth switching transistor S b7 , the first flying capacitor C fb1 , the second flying capacitor C fb2 and the third flying capacitor C fb3 .

[0059] In an optional embodiment, the connection mode of the second-phase circuit (B-phase circuit) of the three-phase circuit includes: the drain of the first switching transistor S b1 is connected to the positive terminal of the DC input source U dc and the anode of the DC bus capacitor C dc , the source of the first switching transistor S b1 is connected to the drain of the second switching transistor S b2 and the anode of the first flying capacitor C fb1 , the source of the second switching transistor S b2 is connected to the drain of the third switching transistor S b3 and the drain of the eleventh switching transistor S b6 , the source of the eleventh switching transistor S b6 is connected to the cathode of the first flying capacitor C fb1 , the anode of the second flying capacitor C fb2 and the drain of the twelfth switching transistor S b7 , the source of the twelfth switching transistor S b7 is connected to the drain of the eighth switching transistor S b3 ′ and the source of the seventh switching transistor S b2 ′, the source of the eighth switching transistor S b3 ′ is connected to the drain of the sixth switching transistor S b1 ′ and the cathode of the second flying capacitor C fb2 , the source of the third switching transistor S b3 is connected to the drain of the seventh switching transistor S b2 ′, the drain of the ninth switching transistor S b4 ′ and the source of the fourth switching transistor S b4 , the drain of the fourth switching transistor S b4 is connected to the anode of the third flying capacitor C fb3 and the drain of the fifth switching transistor S b5 , the source of the ninth switching transistor S b4 ′ is connected to the cathode of the third flying capacitor C fb3 and the source of the tenth switching transistor S b5 ′, the source of the fifth switching transistor S b5The source of is connected to the tenth switch S b5 ′s drain.

[0060] In an alternative embodiment, the C-phase circuit of the third-phase circuit of the three-phase circuit includes: the first switch S c1 , the second switch S c2 , the third switch S c3 , the fourth switch S c4 , the fifth switch S c5 , the sixth switch S c1 ′, the seventh switch S c2 ′, the eighth switch S c3 ′, the ninth switch S c4 ′, the tenth switch S c5 ′, the eleventh switch S c6 , the twelfth switch S c7 , the first flying capacitor C fc1 , the second flying capacitor C fc2 and the third flying capacitor C fc3 .

[0061] In an alternative embodiment, the connection mode of the C-phase circuit of the third-phase circuit of the three-phase circuit includes: the drain of the first switch S c1 is connected to the positive terminal of the DC input source U dc and the anode of the DC bus capacitor C dc , the source of the first switch S c1 is connected to the drain of the second switch S c2 and the anode of the first flying capacitor C fc1 , the source of the second switch S c2 is connected to the drain of the third switch S c3 and the drain of the eleventh switch S c6 , the source of the eleventh switch S c6 is connected to the cathode of the first flying capacitor C fc1 , the anode of the second flying capacitor C fc2 and the drain of the twelfth switch S c7 , the source of the twelfth switch S c7 is connected to the drain of the eighth switch S c3 ′ and the source of the seventh switch S c2 ′, the source of the eighth switch S c3 ′ is connected to the drain of the sixth switch S c1 ′ and the cathode of the second flying capacitor C fc2 , the source of the third switch S c3 is connected to the drain of the seventh switch S c2 ′, the drain of the ninth switch S c4 ′ and the fourth switch Sc4 the source electrode of c4 is connected to the third flying capacitor C at the drain electrode of the fourth switching transistor S fc3 the anode of c5 is connected to the drain electrode of the fifth switching transistor S c4 the source electrode of the ninth switching transistor S' is connected to the third flying capacitor C fc3 the cathode of c5 the source electrode of the tenth switching transistor S' c5 the source electrode of the fifth switching transistor S is connected to the drain electrode of the tenth switching transistor S' c5 .

[0062] In this embodiment, the source electrode of the fifth switching transistor in each phase circuit of the three-phase circuit serves as the output terminal of the corresponding phase circuit.

[0063] By selecting the source electrode of the corresponding switching transistor as the output of the converter, the working performance of the converter is improved.

[0064] In an alternative embodiment, the fifth switching transistor S of the first phase circuit (A-phase circuit) of the three-phase circuit a5 serves as the output terminal of the first phase circuit (A-phase circuit); the fifth switching transistor S of the second phase circuit (B-phase circuit) of the three-phase circuit b5 serves as the output terminal of the second phase circuit (B-phase circuit); the fifth switching transistor S of the third phase circuit (C-phase circuit) of the three-phase circuit c5 serves as the output terminal of the third phase circuit (C-phase circuit).

[0065] In this embodiment, in the three-phase circuit, the carrier waves between the first phase circuit, the second phase circuit, and the third phase circuit are the same, and the modulation waves are phase-shifted by 120°; the corresponding switching transistors in the first phase circuit, the second phase circuit, and the third phase circuit are controlled by the same control method.

[0066] By using the same control method to regulate the driving signals of the switching transistors in each phase circuit, the control logic of the converter can be simplified, the current distribution balance degree and the system stability of the converter are improved, and the loss of the switching transistors is reduced.

[0067] In this embodiment, in each phase circuit of the three-phase circuit, the driving signal of the sixth switching transistor is complementary to the driving signal of the first switching transistor, the driving signal of the seventh switching transistor is complementary to the driving signal of the second switching transistor, the driving signal of the eighth switching transistor is complementary to the driving signal of the third switching transistor, the driving signal of the ninth switching transistor is complementary to the driving signal of the fourth switching transistor, the driving signal of the tenth switching transistor is complementary to the driving signal of the fifth switching transistor, the driving signal of the eleventh switching transistor is the same as the driving signal of the seventh switching transistor, and the driving signal of the twelfth switching transistor is the same as the driving signal of the third switching transistor.

[0068] By making the drive signals between the switching tubes complementary, the computational load of the controller in the converter and the number of pins occupied can be reduced, the design difficulty of the drive circuit is lowered, the stability and reliability of the circuit are improved, and thus the working efficiency of the converter is enhanced.

[0069] In an alternative embodiment, in the first-phase circuit (A-phase circuit) of the three-phase circuit, the drive signal S of the sixth switching tube a1 ′ is complementary to the drive signal of the first switching tube S a1 , the drive signal of the seventh switching tube S a2 ′ is complementary to the drive signal of the second switching tube S a2 , the drive signal of the eighth switching tube S a3 ′ is complementary to the drive signal of the third switching tube S a3 , the drive signal of the ninth switching tube S a4 ′ is complementary to the drive signal of the fourth switching tube S a4 , the drive signal of the tenth switching tube S a5 ′ is complementary to the drive signal of the fifth switching tube S a5 , the drive signal of the eleventh switching tube S a6 is the same as the drive signal of the seventh switching tube S a2 ′, and the drive signal of the twelfth switching tube S a7 is the same as the drive signal of the third switching tube S a3 .

[0070] In an alternative embodiment, in the second-phase circuit (B-phase circuit) of the three-phase circuit, the drive signal S of the sixth switching tube b1 ′ is complementary to the drive signal of the first switching tube S b1 , the drive signal of the seventh switching tube S b2 ′ is complementary to the drive signal of the second switching tube S b2 , the drive signal of the eighth switching tube S b3 ′ is complementary to the drive signal of the third switching tube S b3 , the drive signal of the ninth switching tube S b4 ′ is complementary to the drive signal of the fourth switching tube S b4 , the drive signal of the tenth switching tube S b5 ′ is complementary to the drive signal of the fifth switching tube S b5 , the drive signal of the eleventh switching tube S b6 is the same as the drive signal of the seventh switching tube S b2 ′, and the drive signal of the twelfth switching tube S b7 is the same as the drive signal of the third switching tube S b3 .

[0071] In an alternative embodiment, in the third-phase circuit (C-phase circuit) of the three-phase circuit, the drive signal S of the sixth switching tubec1 ' is complementary to the driving signal of the first switching transistor S c1 , and the driving signal of the seventh switching transistor S c2 ' is complementary to the driving signal of the second switching transistor S c2 , and the driving signal of the eighth switching transistor S c3 ' is complementary to the driving signal of the third switching transistor S c3 , and the driving signal of the ninth switching transistor S c4 ' is complementary to the driving signal of the fourth switching transistor S c4 , and the driving signal of the tenth switching transistor S c5 ' is complementary to the driving signal of the fifth switching transistor S c5 , and the driving signal of the eleventh switching transistor S c6 is the same as the driving signal of the seventh switching transistor S c2 ', and the driving signal of the twelfth switching transistor S c7 is the same as the driving signal of the third switching transistor S c3 .

[0072] In this embodiment, in the three-phase circuit, the voltage stresses of the corresponding switching transistors and flying capacitors between the first-phase circuit, the second-phase circuit, and the third-phase circuit are the same.

[0073] By ensuring that the voltage stresses of the corresponding switching transistors and flying capacitors are the same, the device selection can be optimized, thereby simplifying the design of the circuit control system and improving the reliability of the converter.

[0074] In this embodiment, the voltage stresses of the first switching transistor, the second switching transistor, the third switching transistor, the sixth switching transistor, the seventh switching transistor, the eighth switching transistor, the eleventh switching transistor, the twelfth switching transistor, the first flying capacitor, and the second flying capacitor are one-third of the power supply input by the DC input source, and the voltage stresses of the fourth switching transistor, the fifth switching transistor, the ninth switching transistor, the tenth switching transistor, and the third flying capacitor are one-sixth of the power supply input by the DC input source.

[0075] By controlling the voltage stresses of the corresponding switching transistors and flying capacitors, the voltage stress of each device can be effectively reduced, thereby reducing the voltage stress of the converter and ensuring the working efficiency of the converter.

[0076] In an alternative embodiment, in the A-phase circuit of the first-phase circuit of the three-phase circuit, the first switching transistor S a1 , the second switching transistor S a2 , the third switching transistor S a3 , the sixth switching transistor S a1 ', the seventh switching transistor S a2 ', the eighth switching transistor S a3 ', the eleventh switching transistor S a6 , the twelfth switching transistor S a7, the voltage stress of the first flying capacitor C fα1 and the second flying capacitor C fα2 is one-third of the DC input source U dc input power supply. The voltage stress of the fourth switching transistor S a4 , the fifth switching transistor S a5 , the ninth switching transistor S a4 ′, the tenth switching transistor S a5 ′ and the third flying capacitor C fα3 is one-sixth of the DC input source U dc input power supply.

[0077] In an alternative embodiment, in the second-phase circuit (B-phase circuit) of the three-phase circuit, the voltage stress of the first switching transistor S b1 , the second switching transistor S b2 , the third switching transistor S b3 , the sixth switching transistor S b1 ′, the seventh switching transistor S b2 ′, the eighth switching transistor S b3 ′, the eleventh switching transistor S b6 , the twelfth switching transistor S b7 , the first flying capacitor C fb1 and the second flying capacitor C fb2 is one-third of the DC input source U dc input power supply. The voltage stress of the fourth switching transistor S b4 , the fifth switching transistor S b5 , the ninth switching transistor S b4 ′, the tenth switching transistor S b5 ′ and the third flying capacitor C fb3 is one-sixth of the DC input source U dc input power supply.

[0078] In an alternative embodiment, in the third-phase circuit (C-phase circuit) of the three-phase circuit, the voltage stress of the first switching transistor S c1 , the second switching transistor S c2 , the third switching transistor S c3 , the sixth switching transistor S c1 ′, the seventh switching transistor S c2 , the eighth switching transistor S c3 ′, the eleventh switching transistor S c6 , the twelfth switching transistor S c7 , the first flying capacitor C fc1 and the second flying capacitor C fc2 is one-third of the DC input source U dc input power supply. The voltage stress of the fourth switching transistor S c4 , the fifth switching transistor S c5 , the ninth switching transistor S c4′, the tenth switch tube S c5 ′ and the third flying capacitor C fc3 The voltage stress of is one-sixth of the DC input source U dc of the input power supply.

[0079] The seven-level clamped converter topology of this embodiment is connected to the DC input source in parallel through a DC bus capacitor and a three-phase circuit. Through the first switch tube, the second switch tube, the third switch tube, the seventh switch tube, the eighth switch tube, and the sixth switch tube connected in series in sequence, and the first H-bridge composed of the fourth switch tube, the fifth switch tube, the tenth switch tube, and the ninth switch tube, the first flying capacitor, the second flying capacitor, the second H-bridge composed of the eleventh switch tube and the twelfth switch tube, and the third flying capacitor connected to the first H-bridge circuit, through the coordinated opening and closing of multiple switch tubes and the working characteristics of the H-bridge circuit, the voltage regulation of the converter is optimized. While reducing the voltage stress of each switch tube in the converter, the voltage balance of the flying capacitors in the converter is maintained, thereby reducing the total device voltage stress in the converter, ensuring the balanced distribution of the voltage stress of the devices in the converter, avoiding the uneven thermal loss and excessive thermal loss of the converter devices caused by the uneven distribution of the voltage stress, and ensuring the working performance and stable operation of the converter.

[0080] Embodiment 2

[0081] Please refer to Figure 2 , which is a step flowchart of a voltage balance modulation method for a seven-level clamped converter topology provided by an embodiment of the present invention, including steps S101 - S102.

[0082] Step S101: Obtain a seven-level clamped converter topology as described in Embodiment 1, and obtain the modulation signal, carrier signal, and voltage deviation of each flying capacitor in each phase circuit input to the seven-level clamped converter topology. Among them, the modulation signal includes: the first-phase modulation signal, the second-phase modulation signal, and the third-phase modulation signal, and the carrier signal includes: the first carrier signal, the second carrier signal, the third carrier signal, the fourth carrier signal, the fifth carrier signal, and the sixth carrier signal.

[0083] In this embodiment, the obtaining of the modulation signal and carrier signal input to the seven-level clamped converter topology specifically includes:

[0084] Obtain the modulation signal of the seven-level clamped converter topology:

[0085]

[0086] Among them, m is the modulation ratio of the converter, u refa is the first-phase modulation signal, u refb is the second-phase modulation signal, urefc is the third-phase modulation signal;

[0087] Obtain the voltage deviations of the three flying capacitors in each phase circuit of the seven-level clamped converter topology respectively:

[0088]

[0089] where, ΔU fx1 is the voltage deviation of the first flying capacitor in each phase circuit, ΔU fx2 is the voltage deviation of the first flying capacitor in the second phase circuit, ΔU fx3 is the voltage deviation of the third flying capacitor in each phase circuit; when x = a, it represents the first phase circuit, when x = b, it represents the second phase circuit, and when x = c, it represents the third phase circuit.

[0090] By defining the carrier signal, modulation signal and voltage deviation of the flying capacitor of the converter, and in the form of digital quantization, the control effect of the switching state of the converter is improved.

[0091] Step S102: Logically compare the carrier signal and the modulation signal, and in combination with the preset switching state table and the voltage deviation of each flying capacitor in each phase circuit, control the switching tubes of the seven-level clamped converter topology so that the voltage of the seven-level clamped converter topology remains balanced.

[0092] In this embodiment, the logically comparing the carrier signal and the modulation signal, and in combination with the preset switching state table and the voltage deviation of each flying capacitor in each phase circuit to control the switching tubes of the seven-level clamped converter topology specifically includes: obtaining the modulation signal of one or any number of phase circuits and the corresponding phase circuit output current value, numerically comparing the modulation signal with each carrier signal in turn; according to the comparison result, in combination with the voltage deviation of each flying capacitor of the corresponding phase circuit and the phase circuit output current value, and according to the preset switching state table, select the corresponding switching tubes in the seven-level clamped converter topology to conduct.

[0093] By comparing the carrier signal and the modulation signal, and in combination with the voltage deviation of the flying capacitor in the circuit and the phase circuit output current value, the voltage balance modulation effect of the converter is improved.

[0094] In an optional embodiment, please refer to Table 1, which is a table showing the influence of different switching states on the charging and discharging of the flying capacitor provided by the embodiment of the present invention. Wherein, when x is a, it represents the first phase circuit, when x is b, it represents the second phase circuit, and when x is c, it represents the third phase circuit; Figures 3 to 18 is the equivalent circuit corresponding to any one phase circuit of the seven-level clamped converter under different switching states.

[0095] Table 1

[0096]

[0097]

[0098]

[0099] It should be noted that in the following description of the equivalent circuit diagram of the converter topology, x can be a, b, or c. When x is a, it represents the first-phase circuit; when x is b, it represents the second-phase circuit; when x is c, it represents the third-phase circuit.

[0100] In an alternative embodiment, please refer to Figure 3 , which is the equivalent circuit diagram of the first operating state of any one phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the second switch tube S x2 , the third switch tube S x3 , the fourth switch tube S x4 , the fifth switch tube S x5 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is U dc . Whether the current i x flows out (i x ≥ 0), or the current i x flows in (i x < 0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 are not affected.

[0101] In an alternative embodiment, please refer to Figure 4 , which is the equivalent circuit diagram of the second operating state of any one phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the second switch tube S x2 , the third switch tube S x3 , the fourth switch tube S x4 , the tenth switch tube S x5 ' and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 5 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are not affected, and the third flying capacitor C fx3 is charged; when the current ix When flowing in (i x <0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are not affected, and the third flying capacitor C fx3 discharges.

[0102] In an optional embodiment, please refer to Figure 5 , which is the equivalent circuit diagram of the third working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the second switch tube S x2 , the third switch tube S x3 , the ninth switch tube S x4 ′, the fifth switch tube S x5 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 5 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 all discharge; when the current i x flows in (i x <0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 all charge.

[0103] In an optional embodiment, please refer to Figure 6 , which is the equivalent circuit diagram of the fourth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the seventh switch tube S x2 ′, the third switch tube S x3 , the ninth switch tube S x4 ′, the fifth switch tube S x5 , the eleventh switch tube S x6 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 5 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 charges, the second flying capacitor C fx2 is not affected, and the third flying capacitor C fx3 discharges; when the current i x flows in (i xWhen t < 0, the first flying capacitor C fx1 discharges, and the second flying capacitor C fx2 is not affected. The third flying capacitor C fx3 charges.

[0104] In an alternative embodiment, please refer to Figure 7 , which is the equivalent circuit diagram of the fifth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switching tube S x1 , the seventh switching tube S x2 ′, the third switching tube S x3 , the fourth switching tube S x4 , the fifth switching tube S x5 , the eleventh switching tube S x6 and the twelfth switching tube S x7 conduct, and the magnitude of the output voltage u x is 4 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 charges, and the second flying capacitor C fx2 and the third flying capacitor C fx3 are not affected; when the current i x flows in (i x <0), the first flying capacitor C fx1 discharges, and the second flying capacitor C fx2 and the third flying capacitor C fx3 are not affected.

[0105] In an alternative embodiment, please refer to Figure 8 , which is the equivalent circuit diagram of the sixth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switching tube S x1 ′, the second switching tube S x2 , the third switching tube S x3 , the fourth switching tube S x4 , the fifth switching tube S x5 and the twelfth switching tube S x7 conduct, and the magnitude of the output voltage u x is 4 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 and the second flying capacitor C fx2 discharge, and the third flying capacitor C fx3 is not affected; when the current i x flows in (i x <0), the first flying capacitor C fx1and the second flying capacitor C fx2 is charged, and the third flying capacitor C fx3 is not affected.

[0106] In an alternative embodiment, please refer to Figure 9 , which is the equivalent circuit diagram of the seventh working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the second switch tube S x2 , the third switch tube S x3 , the fourth switch tube S x4 , the tenth switch tube S x5 ′ and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 3 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 and the second flying capacitor C fx2 discharge, and the third flying capacitor C fx3 is charged; when the current i x flows in (i x <0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are charged, and the third flying capacitor C fx3 discharges.

[0107] In an alternative embodiment, please refer to Figure 10 , which is the equivalent circuit diagram of the eighth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the seventh switch tube S x2 ′, the third switch tube S x3 , the fourth switch tube S x4 , the tenth switch tube S x5 ′, the eleventh switch tube S x6 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 3 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 is charged, the second flying capacitor C fx2 is not affected, and the third flying capacitor C fx3 is charged; when the current i x flows in (i x <0), the first flying capacitor C fx1 discharges, and the second flying capacitor C fx2Unaffected, the third flying capacitor C fx3 discharges.

[0108] In an alternative embodiment, refer to Figure 11 , which is the equivalent circuit diagram of the ninth operating state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switching tube S x1 , the seventh switching tube S x2 ′, the eighth switching tube S x3 ′, the ninth switching tube S x4 ′, the fifth switching tube S x5 and the eleventh switching tube S x6 conduct, and the magnitude of the output voltage u x is 3 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are charged, and the third flying capacitor C fx3 discharges; when the current i x flows in (i x <0), the first flying capacitor C fx1 and the second flying capacitor C fx2 discharge, and the third flying capacitor C fx3 is charged.

[0109] In an alternative embodiment, refer to Figure 12 , which is the equivalent circuit diagram of the tenth operating state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switching tube S x1 ′, the seventh switching tube S x2 ′, the third switching tube S x3 , the ninth switching tube S x4 ′, the fifth switching tube S x5 , the eleventh switching tube S x6 and the twelfth switching tube S x7 conduct, and the magnitude of the output voltage u x is 3 / 6U dc . When the current i x flows out (i x ≥0), the first flying capacitor C fx1 is unaffected, the second flying capacitor C fx2 and the third flying capacitor C fx3 discharge; when the current i x flows in (i x <0), the first flying capacitor C fx1 is unaffected, the second flying capacitor C fx2 and the third flying capacitor C fx3 are charged.

[0110] In an alternative embodiment, please refer to Figure 13 , which is the equivalent circuit diagram of the eleventh operating state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the seventh switch tube S x2 ′, the eighth switch tube S x3 ′, the ninth switch tube S x4 ′, the tenth switch tube S x5 ′ and the eleventh switch tube S x6 are turned on, and the magnitude of the output voltage u x is 2 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are charged, and the third flying capacitor C fx3 is not affected; when the current i x flows in (i x < 0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are discharged, and the third flying capacitor C fx3 is not affected.

[0111] In an alternative embodiment, please refer to Figure 14 , which is the equivalent circuit diagram of the twelfth operating state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the seventh switch tube S x2 ′, the third switch tube S x3 , the ninth switch tube S x4 ′, the tenth switch tube S x5 ′, the eleventh switch tube S x6 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 2 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 is not affected, the second flying capacitor C fx2 is discharged, and the third flying capacitor C fx3 is not affected; when the current i x flows in (i x < 0), the first flying capacitor C fx1 is not affected, the second flying capacitor C fx2 is charged, and the third flying capacitor C fx3 is not affected.

[0112] In an alternative embodiment, please refer to Figure 15 , which is the equivalent circuit diagram of the thirteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the seventh switch tube S x2 ′, the third switch tube S x3 , the fourth switch tube S x4 , the tenth switch tube S x5 ′, the eleventh switch tube S x6 and the twelfth switch tube S x7 are turned on, and the magnitude of the output voltage u x is 1 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 is not affected, the second flying capacitor C fx2 discharges, and the third flying capacitor C fx3 charges; when the current i x flows in (i x < 0), the first flying capacitor C fx1 is not affected, the second flying capacitor C fx2 charges, and the third flying capacitor C fx3 discharges.

[0113] In an alternative embodiment, please refer to Figure 16 , which is the equivalent circuit diagram of the fourteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the first switch tube S x1 , the seventh switch tube S x2 ′, the eighth switch tube S x3 ′, the fourth switch tube S x4 , the tenth switch tube S x5 ′ and the eleventh switch tube S x6 are turned on, and the magnitude of the output voltage u x is 1 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 charge; when the current i x flows in (i x < 0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 discharge.

[0114] In an alternative embodiment, please refer toFigure 17 , which is the equivalent circuit diagram of the fifteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the seventh switch tube S x2 ′, the eighth switch tube S x3 ′, the ninth switch tube S x4 ′, the fifth switch tube S x5 and the eleventh switch tube S x6 are turned on, and the magnitude of the output voltage u x is 1 / 6U dc . When the current i x flows out (i x ≥ 0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are not affected, and the third flying capacitor C fx3 discharges; when the current i x flows in (i x < 0), the first flying capacitor C fx1 and the second flying capacitor C fx2 are not affected, and the third flying capacitor C fx3 charges.

[0115] In an alternative embodiment, please refer to Figure 18 , which is the equivalent circuit diagram of the sixteenth working state of any phase circuit of the seven-level clamped converter provided by the embodiment of the present invention. Among them, the sixth switch tube S x1 ′, the seventh switch tube S x2 ′, the eighth switch tube S x3 ′, the ninth switch tube S x4 ′, the tenth switch tube S x5 ′ and the eleventh switch tube S x6 are turned on, and the magnitude of the output voltage u x is 0. Whether the current i x flows out (i x ≥ 0), or the current i x flows in (i x < 0), the first flying capacitor C fx1 , the second flying capacitor C fx2 and the third flying capacitor C fx3 are not affected.

[0116] In an alternative embodiment, please refer to Figure 19 , which is a voltage balance modulation classification diagram of a seven-level clamped converter topology provided by the embodiment of the present invention. Among them, the carrier signals include: the first carrier signal V carr1 , the second carrier signal V carr2 , the third carrier signal V carr3, the fourth carrier signal V carr4 , the fifth carrier signal V carr5 and the sixth carrier signal V carr6 ; the modulation signal u refx includes: the first phase modulation signal u refa , the second phase modulation signal u refb and the third phase modulation signal u refc , when x in u refx is a, it represents the first phase modulation signal u refa , when x is b, the second phase modulation signal u refb , when x is c, it represents the third phase modulation signal u refc .

[0117] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the first carrier signal V carr1 , the switching state A1 described in Table 1 is selected to modulate the voltage balance of the converter topology; when the modulation signal u refx is less than the sixth carrier signal V carr6 , the switching state G1 described in Table 1 is selected to modulate the voltage balance of the converter topology.

[0118] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the second carrier signal V carr2 and less than the first carrier signal V carr1 , if the output phase current i x flows out (i x ≥ 0) and ΔU fx3 ≥ 0, when satisfying one of the two conditions of ΔU fx1 > 0 or ΔU fx1 < 0, ΔU fx2 > 0, |ΔU fx1 | < |ΔU fx2 |, the switching state B2 described in Table 1 is selected to modulate the voltage balance of the converter topology, otherwise the switching state B3 is selected; if the output phase current i x flows out (i x ≥ 0) and ΔU fx3 < 0, the switching state B1 is selected. If the output phase current i x flows in (i x < 0) and when ΔU fx3 < 0, when satisfying ΔU fx1 < 0 or ΔU fx1 > 0, ΔU fx2 < 0, |ΔU fx1 | < |ΔU fx2When one of the two conditions is met, select switch state B2; otherwise, select switch state B3. If the output phase current i x flows in (i x <0) and ΔU fx3 ≥0, select switch state B1.

[0119] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the third carrier signal V carr3 and less than the second carrier signal V carr2 If the output phase current i x flows out (i x ≥0), when the following conditions are met: or ΔU fx1 <0, ΔU fx2 >0, |ΔU fx1 |<|ΔU fx2 When one of the two conditions is met, select switch state C2; otherwise, select switch state C1. If the output phase current i x flows in (i x <0), when the following conditions are met: ΔU fx1 <0 or ΔU fx1 >0, ΔU fx2 <0, |ΔU fx1 |<|ΔU fx2 When one of the two conditions is met, select switch state C2; otherwise, select switch state C1.

[0120] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the fourth carrier signal V carr4 and less than the third carrier signal V carr3 If the output phase current i x flows out (i x ≥0) and ΔU fx3 ≥0, when the following conditions are met: ΔU fx2 >0 or ΔU fx1 <0, ΔU fx2 >0, |ΔU fx1 |>|ΔU fx2 When one of the two conditions is met, select switch state D3; otherwise, select switch state D4. If the output phase current i x flows out (i x ≥0) and ΔU fx3 <0, when the following conditions are met: ΔU fx1 >0 or ΔU fx1 <0, ΔU fx2 >0, |ΔU fx1 |<|ΔU fx2When one of the two conditions is met, select the switch state D1; otherwise, select the switch state D2. If the output phase current i x flows in (i x < 0) and ΔU fx3 ≥ 0, when ΔU fx1 < 0 or ΔU fx1 > 0, ΔU fx2 < 0, |ΔU fx1 | < |ΔU fx2 When one of the two conditions is met, select the switch state D1; otherwise, select the switch state D2; if the output phase current i x flows in (i x < 0) and ΔU fx3 < 0, when ΔU fx2 > 0 or ΔU fx1 < 0, ΔU fx2 > 0, |ΔU fx1 | > |ΔU fx2 When one of the two conditions is met, select the switch state D3; otherwise, select the switch state D4.

[0121] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the fifth carrier signal V carr5 and less than the fourth carrier signal V carr4 , if the output phase current i x flows out (i x ≥ 0), when ΔU fx2 < 0 or ΔU fx1 < 0, ΔU fx2 > 0, |ΔU fx1 | > |ΔU fx2 When one of the two conditions is met, select the switch state E1; otherwise, select the switch state E2; if the output phase current i x flows in (i x < 0), when ΔU fx2 > 0 or ΔU fx1 > 0, ΔU fx2 < 0, |ΔU fx1 | > |ΔU fx2 When one of the two conditions is met, select the switch state E1; otherwise, select the switch state E2.

[0122] In an alternative embodiment, when the modulation signal u refx is greater than or equal to the sixth carrier signal V carr6 and less than the fifth carrier signal V carr5 , if the output phase current i x flows out (i x ≥ 0) and ΔU fx3When <0, satisfy ΔU fχ2 <0 or ΔU fx1 <0, ΔU fx2 >0, |ΔU fx1 | > |ΔU fx2 |When one of the two conditions is met, select the switch state F2, otherwise select the switch state F1; if the output phase current i x flows out (i x ≥0) and ΔU fx3 ≥0, select the switch state F3. If the output phase current i x flows in (i x <0) and ΔU fx3 ≥0, satisfy ΔU fx2 >0 or ΔU fx1 >0, ΔU fx2 <0, |ΔU fx1 | > |ΔU fx2 |When one of the two conditions is met, select the switch state F2, otherwise select the switch state F1. If the output phase current i x flows in (i x <0) and ΔU fx3 <0, select the switch state F3.

[0123] In an alternative embodiment, please refer to Figure 20 , which is a schematic diagram of the drive signal of the switch tube corresponding to the voltage balance modulation strategy provided by the embodiment of the present invention. Among them, the schematic diagram includes: the drive signals of the three-phase circuit, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, and the drive signal of the output voltage.

[0124] In this embodiment, by logically comparing the carrier signal and the modulation signal, and combining the preset switch state table and the voltage deviation of each flying capacitor in each phase circuit, the switch tubes of the seven-level clamped converter topology are regulated, thereby ensuring the voltage balance of the seven-level clamped converter topology. Through the switch state table, the power conversion efficiency can be optimized, the voltage stress of the devices in the converter can be reduced, thereby ensuring the balanced distribution of the voltage stress of the devices in the converter, avoiding the uneven thermal loss and excessive thermal loss of the converter devices caused by the uneven distribution of the voltage stress, and also enabling the converter to adapt to different working conditions, improving the applicability and practicality of the converter.

[0125] In summary, the embodiment of the present invention provides a seven-level clamped converter topology. The DC bus capacitor and the three-phase circuit are connected in parallel to the DC input source. The first switch tube, the second switch tube, the third switch tube, the seventh switch tube, the eighth switch tube and the sixth switch tube are connected in series in sequence, and the first H-bridge composed of the fourth switch tube, the fifth switch tube, the tenth switch tube and the ninth switch tube, the first flying capacitor, the second flying capacitor, the second H-bridge composed of the eleventh switch tube and the twelfth switch tube, and the third flying capacitor connected to the first H-bridge circuit. Through the coordinated opening and closing of multiple switch tubes and the working characteristics of the H-bridge circuit, the voltage regulation of the converter is optimized. While reducing the voltage stress of each switch tube in the converter, the voltage balance of the flying capacitors in the converter is maintained, thereby reducing the total device voltage stress of the converter, ensuring the balanced distribution of the voltage stress of the devices in the converter, avoiding the uneven thermal loss and excessive thermal loss of the converter devices caused by the uneven voltage stress distribution, and ensuring the working performance and stable operation of the converter.

[0126] The specific embodiments described above further elaborate on the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. In particular, it is pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0127] In addition, in the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined by the terms "first" and "second" etc. may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

Claims

1. A seven-level clamped converter topology, characterized in that, Comprising: A DC input source, a DC bus capacitor, and a three-phase circuit; wherein, the DC bus capacitor and the three-phase circuit are connected in parallel to the DC input source; The three-phase circuit includes a first-phase circuit, a second-phase circuit, and a third-phase circuit, and the structure and connection of each phase circuit are the same; Each phase circuit of the three-phase circuit includes: twelve switching tubes and three flying capacitors; wherein, the first switching tube, the second switching tube, the third switching tube, the seventh switching tube, the eighth switching tube, and the sixth switching tube are connected in series in sequence; the first H-bridge composed of the fourth switching tube, the fifth switching tube, the tenth switching tube, and the ninth switching tube is connected between the third switching tube and the seventh switching tube; the second H-bridge composed of the first flying capacitor, the second flying capacitor, the eleventh switching tube, and the twelfth switching tube is connected across the first switching tube, the second switching tube, the third switching tube, the seventh switching tube, the eighth switching tube, and the sixth switching tube connected in series in sequence; the third flying capacitor is connected to the first H-bridge.

2. The seven-level clamped converter topology according to claim 1, characterized in that, In each phase circuit of the three-phase circuit, the drain of the first switching tube is connected to the positive terminal of the DC input source and the anode of the DC bus capacitor, the source of the first switching tube is connected to the drain of the second switching tube and the anode of the first flying capacitor, the source of the second switching tube is connected to the drain of the third switching tube and the drain of the eleventh switching tube, the source of the eleventh switching tube is connected to the cathode of the first flying capacitor, the anode of the second flying capacitor, and the drain of the twelfth switching tube, the source of the twelfth switching tube is connected to the drain of the eighth switching tube and the source of the seventh switching tube, the source of the eighth switching tube is connected to the drain of the sixth switching tube and the cathode of the second flying capacitor, the source of the third switching tube is connected to the drain of the seventh switching tube, the drain of the ninth switching tube, and the source of the fourth switching tube, the drain of the fourth switching tube is connected to the anode of the third flying capacitor and the drain of the fifth switching tube, the source of the ninth switching tube is connected to the cathode of the third flying capacitor and the source of the tenth switching tube, and the source of the fifth switching tube is connected to the drain of the tenth switching tube.

3. A seven-level clamped converter topology as claimed in claim 1, wherein The source of the fifth switching tube in each phase circuit of the three-phase circuit serves as the output terminal of the corresponding phase circuit.

4. A seven-level clamped converter topology according to claim 1, characterized in that, In the three-phase circuit, the carrier waves between the first-phase circuit, the second-phase circuit, and the third-phase circuit are the same, and the modulation waves are phase-shifted by 120°; the corresponding switching tubes in the first-phase circuit, the second-phase circuit, and the third-phase circuit are controlled by the same control method.

5. A seven-level clamped converter topology according to claim 4, characterized in that In each phase circuit of the three-phase circuit, the driving signal of the sixth switching tube is complementary to the driving signal of the first switching tube, the driving signal of the seventh switching tube is complementary to the driving signal of the second switching tube, the driving signal of the eighth switching tube is complementary to the driving signal of the third switching tube, the driving signal of the ninth switching tube is complementary to the driving signal of the fourth switching tube, the driving signal of the tenth switching tube is complementary to the driving signal of the fifth switching tube, the driving signal of the eleventh switching tube is the same as the driving signal of the seventh switching tube, and the driving signal of the twelfth switching tube is the same as the driving signal of the third switching tube.

6. A seven-level clamped converter topology as claimed in claim 1, characterized in that, In the three-phase circuit, the voltage stresses of the corresponding switching tubes and flying capacitors between the first-phase circuit, the second-phase circuit, and the third-phase circuit are the same.

7. A seven-level clamped converter topology according to claim 6, characterized in that, The voltage stresses of the first switch tube, the second switch tube, the third switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube, the eleventh switch tube, the twelfth switch tube, the first flying capacitor and the second flying capacitor are one-third of the power supply input by the DC input source, and the voltage stresses of the fourth switch tube, the fifth switch tube, the ninth switch tube, the tenth switch tube and the third flying capacitor are one-sixth of the power supply input by the DC input source.

8. A voltage balancing modulation method for a seven-level clamped converter topology, characterized in that, Including: Obtain a seven-level clamped converter topology according to any one of claims 1 to 7, and obtain a modulation signal, a carrier signal input to the seven-level clamped converter topology, and the voltage deviation of each flying capacitor in each phase circuit, wherein the modulation signal includes: a first-phase modulation signal, a second-phase modulation signal, and a third-phase modulation signal, and the carrier signal includes: a first carrier signal, a second carrier signal, a third carrier signal, a fourth carrier signal, a fifth carrier signal, and a sixth carrier signal; Logically compare the carrier signal and the modulation signal, and combine a preset switch state table and the voltage deviation of each flying capacitor in each phase circuit to control the switch tubes of the seven-level clamped converter topology to keep the voltage of the seven-level clamped converter topology balanced.

9. A voltage balance modulation method for a seven-level clamped converter topology according to claim 8, characterized in that, The obtaining of the modulation signal and the carrier signal input to the seven-level clamped converter topology specifically includes: Obtain the modulation signal of the seven-level clamped converter topology: where m is the modulation ratio of the converter, u refa is the modulation signal of the first phase, u refb is the modulation signal of the second phase, u refc is the modulation signal of the third phase; Respectively obtain the voltage deviations of the three flying capacitors in each phase circuit of the seven-level clamped converter topology: Among them, ΔU fx1 is the voltage deviation of the first flying capacitor in each phase circuit, and ΔU fx2 is the voltage deviation of the first flying capacitor in the second phase circuit, and ΔU fx3 is the voltage deviation of the third flying capacitor in each phase circuit; when x = a, it represents the first phase circuit, when x = b, it represents the second phase circuit, and when x = c, it represents the third phase circuit.

10. A voltage balance modulation method for a seven-level clamped converter topology as claimed in claim 8, characterized in that, The logically comparing the carrier signal and the modulation signal, and combining a preset switch state table and the voltage deviation of each flying capacitor in each phase circuit to control the switch tubes of the seven-level clamped converter topology specifically includes: Obtain the modulation signal of one or any number of phase circuits and the corresponding phase circuit output current value, and numerically compare the modulation signal with each carrier signal in turn; According to the comparison result, combine the voltage deviation of each flying capacitor in the corresponding phase circuit and the phase circuit output current value, and select the corresponding switch tube in the seven-level clamped converter topology to conduct according to the preset switch state table.

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