Bias circuit and power amplifier circuit

Abstract

The invention provides a biasing circuit and a power amplification circuit wherein the biasing circuit comprises a first active device, a second active device, a first capacitor, a third active device, a second capacitor and a feedback circuit; the feedback circuit is used for reducing the impedance of the bias circuit. After the biasing circuit is applied to the power amplifier, the linearity of the power amplifier circuit under a large-bandwidth modulation signal can be improved, and the efficiency of the power amplifier circuit cannot be reduced.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and particularly to a bias circuit and a power amplifier circuit. Background Art

[0002] As Figure 1 shown, it is a schematic diagram of a power amplifier provided by the prior art. The power amplifier 100 in the prior art mainly includes an input matching module 101, a driver stage module 102, an inter-stage matching module 103, a power amplification stage module 104, an output matching module 105 connected in sequence, and a driver stage bias module 106 and a power amplification stage bias module 107 respectively connected to the driver stage module 102 and the power amplification stage module 104. At the same time, there are also an input resistor R1 connected to the input end of the input matching module 101 and an output resistor R2 connected to the output end of the output matching module 105 at both ends of the power amplifier 100.

[0003] Among them, the input matching module 101 is mainly used to convert the external 50 ohms into the input impedance of the input stage. The inter-stage matching module 103 is used to improve the driving ability of the driver stage module 102. The output matching module 105 is used to convert the optimal output impedance of the power amplifier 100 into a 50-ohm impedance. The driver stage bias module 106 and the power amplification stage bias module 107 are mainly used to provide a suitable DC operating point for the power amplifier 100.

[0004] With the development of communication protocols, the debugging bandwidth of the power amplifier 100 has developed from 40M to 100MHz. Its main consideration is the fundamental frequency impedance. Therefore, the linearity under a large-bandwidth modulation signal will deteriorate sharply due to the memory effect of the power amplifier 100.

[0005] In the prior art, in order to improve the linearity of the power amplifier 100 under a large-bandwidth modulation signal, the common method is to increase the saturation power of the power amplifier 100. Although this method will improve the linearity of the power amplifier 100 under a large-bandwidth modulation signal, it will also bring the problem of low efficiency at the same time. Summary of the Invention

[0006] Aiming at the above deficiencies of the prior art, the present invention proposes a bias circuit and a power amplifier circuit to solve the problem that the method used by the power amplifier in the prior art to improve its linearity will lead to low efficiency of the power amplifier.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a bias circuit, which includes a first active device, a second active device, a first capacitor, a third active device, a second capacitor, and a feedback circuit; The input end of the first active device is used to connect to a power supply; The input terminal of the second active device is connected to the first output terminal of the first active device, and the first output terminal of the second active device is grounded; The first terminal of the first capacitor is connected to the second output terminal of the first active device, and the second terminal of the first capacitor is grounded; The first input terminal of the third active device is connected to the first terminal of the first capacitor. The second input terminal of the third active device is for accessing a supply voltage, and the output terminal of the third active device is for outputting a bias signal. The first active device, the second active device, and the third active device together form a current mirror circuit for outputting a stable bias current or bias voltage according to the accessed power supply; The first terminal of the second capacitor is connected to the second output terminal of the second active device, and the second terminal of the second capacitor is grounded; The input terminal of the feedback circuit is connected to the first terminal of the second capacitor, and the output terminal of the feedback circuit is connected to the output terminal of the third active device. The feedback circuit is used to reduce the impedance of the bias circuit.

[0008] Preferably, the first active device is a first triode, the second active device is a second triode, and the third active device is a third triode; The collector of the first triode serves as the input terminal of the first active device, the emitter of the first triode serves as the first output terminal of the first active device, and the base of the first triode serves as the second output terminal of the first active device. The collector of the first triode is connected to the base of the first triode; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second active device; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

[0009] Preferably, the first active device is a first triode, the second active device is a second triode, and the third active device is a third triode; The collector of the first triode serves as the input terminal of the first active device, the emitter of the first triode serves as the first output terminal of the first active device, and the base of the first triode serves as the second output terminal of the first active device. The collector of the first triode is connected to the base of the first triode; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second triode; the collector of the second triode is connected to the base of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

[0010] Preferably, the first active device is a first diode, the second active device is a second triode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal of the first active device and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

[0011] Preferably, the first active device is a first diode, the second active device is a second triode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal of the first active device and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second triode; the collector of the second triode is connected to the base of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

[0012] Preferably, the first active device is a first diode, the second active device is a second diode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal of the first active device and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The positive electrode of the second diode serves as both the input terminal of the second active device and the second output terminal of the second active device, and the negative electrode of the second diode serves as the first output terminal of the second active device; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

[0013] Preferably, the feedback circuit includes a first resistor; the first end of the first resistor serves as the input terminal of the feedback circuit, and the second end of the first resistor serves as the output terminal of the feedback circuit.

[0014] Preferably, the feedback circuit further includes a third capacitor; the first end of the third capacitor is connected to the first end of the first resistor, and the second end of the third capacitor is connected to the second end of the first resistor.

[0015] Preferably, the feedback circuit further includes an inductor; the first end of the inductor is connected to the first end of the third capacitor, and the second end of the inductor is connected to the second end of the third capacitor.

[0016] Preferably, the feedback circuit includes an inductor; the first end of the inductor is connected to the first end of the first resistor, and the second end of the inductor is connected to the second end of the first resistor.

[0017] In a second aspect, the present invention provides a power amplifier circuit, which includes an input matching circuit, a driver stage circuit, a first bias circuit, an inter-stage matching circuit, an amplifier stage circuit, a second bias circuit, and an output matching circuit; the first bias circuit and the second bias circuit are both the bias circuits as described above; The input terminal of the input matching circuit is used to access a radio frequency signal; The first input terminal of the driver stage circuit is connected to the output terminal of the input matching circuit; The output terminal of the first bias circuit is connected to the second input terminal of the driver stage circuit; The input terminal of the inter-stage matching circuit is connected to the output terminal of the driver stage circuit; The first input terminal of the amplifier stage circuit is connected to the output terminal of the inter-stage matching circuit; The output terminal of the second bias circuit is connected to the second input terminal of the amplifier stage circuit; The input end of the output matching circuit is connected to the output end of the amplification stage circuit, and the output end of the output matching circuit is used to output a radio frequency signal.

[0018] Compared with the prior art, in the bias circuit of the present invention, by designing the first active device, the second active device, the first capacitor, the third active device, the second capacitor and the feedback circuit, and defining the connection modes of the devices, and further defining that the feedback circuit is used to reduce the impedance of the bias circuit, when the bias circuit is applied to a power amplification circuit, the linearity of the power amplification circuit under a large bandwidth modulation signal can be improved, and the efficiency of the power amplification circuit will not be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be described in detail below with reference to the drawings. Through the detailed description in conjunction with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings: Figure 1 is a schematic diagram of a power amplifier provided by the prior art; Figure 2 is a circuit diagram of the bias circuit provided in the first embodiment of the present invention, which includes a first feedback circuit; Figure 3 is a circuit diagram of the bias circuit provided in the second embodiment of the present invention, which includes a first feedback circuit; Figure 4 is a circuit diagram of the bias circuit provided in the third embodiment of the present invention, which includes a first feedback circuit; Figure 5 is a circuit diagram of the bias circuit provided in the fourth embodiment of the present invention, which includes a first feedback circuit; Figure 6 is a circuit diagram of the bias circuit provided in the fifth embodiment of the present invention, which includes a first feedback circuit; Figure 7 is a circuit diagram of the second feedback circuit in the bias circuits provided in the first to fifth embodiments of the present invention; Figure 8 is a circuit diagram of the third feedback circuit in the bias circuits provided in the first to fifth embodiments of the present invention; Figure 9 is a circuit diagram of the fourth feedback circuit in the bias circuits provided in the first to fifth embodiments of the present invention; Figure 10 is a baseband impedance simulation diagram of the bias circuit provided in the first embodiment of the present invention; Figure 11 is a schematic diagram of a power amplification circuit provided in the sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "comprising" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification, claims or drawings of this application are used to distinguish different objects and not to describe a specific order.

[0021] Reference herein to "embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] Embodiment 1 The embodiment of the present invention provides a bias circuit 200, as combined with Figure 2 、 Figures 7 - 10 shown, which includes a first active device H1, a second active device H2, a first capacitor C1, a third active device H3, a second capacitor C2, and a feedback circuit 201.

[0024] Among them, the input end of the first active device H1 is used to connect to a power supply.

[0025] The input end of the second active device H2 is connected to the first output end of the first active device H1, and the first output end of the second active device H2 is grounded.

[0026] The first end of the first capacitor C1 is connected to the second output end of the first active device H1, and the second end of the first capacitor C1 is grounded.

[0027] The first input end of the third active device H3 is connected to the first end of the first capacitor C1, the second input end of the third active device H3 is used to connect to a supply voltage VBAT, and the output end of the third active device H3 is used to output a bias signal.

[0028] The first terminal of the second capacitor C2 is connected to the second output terminal of the second active device H2, and the second terminal of the second capacitor C2 is grounded.

[0029] The input terminal of the feedback circuit 201 is connected to the first terminal of the second capacitor C2, and the output terminal of the feedback circuit 201 is connected to the output terminal of the third active device H3. The feedback circuit 201 is used to reduce the impedance of the bias circuit 200.

[0030] When an external power supply inputs a current Iin to the bias circuit 200, that is, the first active device H1 is used to access the current Iin, the output bias signal is the bias current Iout, that is, the output terminal of the third active device H3 is used to output the bias current Iout; when an external power supply inputs a voltage Vin to the bias circuit 200, that is, the first active device H1 is used to access the voltage Vin, the output bias signal is the bias voltage Vout, that is, the output terminal of the third active device H3 is used to output the bias voltage Vout.

[0031] In the bias circuit 200 of this embodiment, the first active device H1, the second active device H2, and the third active device H3 form a current mirror circuit to output or provide a stable bias current Iout or bias voltage Vout according to the accessed power supply; the first capacitor C1 and the second capacitor C2 are used as RF filtering capacitors to provide a path from RF to ground, so that the RF signal will not affect the DC-biased first active device H1 and second active device H2 to stabilize the DC operating point; the existence of the feedback circuit 201 can reduce the impedance of the bias circuit 200, that is, the baseband impedance and harmonic impedance of the bias circuit 200. In this way, when the bias circuit 200 is applied to a power amplifier circuit, the baseband impedance and harmonic impedance of the bias signal input terminals of the driver stage circuit and the power stage circuit can be reduced, thereby improving the linearity of the power amplifier circuit under a large-bandwidth modulation signal and without reducing its efficiency.

[0032] The impedance relationship of the bias circuit 200 in this embodiment is as follows: ; Wherein, Z is the impedance of the bias circuit 200; g m2 is the transconductance of the second active device H2; ω is the angular frequency; C be2 is the parasitic capacitance of the be junction of the second active device H2, and the be junction is the junction region between the base and the emitter of the corresponding triode; g m3 is the transconductance of the third active device H3; C be3 is the parasitic capacitance of the be junction of the third active device H3; βis the current amplification factor of the second active device H2; C 1 is the capacitance value of the first capacitor C1.

[0033] If only the baseband impedance is considered, the baseband impedance has a relatively low frequency, so the parameters of some parasitic capacitors can be removed, and the above impedance relationship can be simplified as: ; Through the derivation of the simplified impedance relationship, it can be obtained that the baseband impedance is very low and close to a short circuit.

[0034] As Figure 10 shown, the abscissa in the figure is the frequency from 10.00 MHz to 100.00 MHz, and the ordinate is the baseband impedance of the bias circuit 200; the frequency freq of the m1 point is 10.00 MHz, and R.S(1,1) is 0.55 / 178.578; the baseband impedance is 6.332 + j0.610.

[0035] In this embodiment, as Figure 2 shown, the first active device H1 is the first triode, the second active device H2 is the second triode, and the third active device H3 is the third triode.

[0036] The collector of the first triode serves as the input end of the first active device H1, the emitter of the first triode serves as the first output end of the first active device H1, and the base of the first triode serves as the second output end of the first active device H1; the collector of the first triode is connected to the base of the first triode.

[0037] The collector of the second triode serves as the input end of the second active device H2, the emitter of the second triode serves as the first output end of the second active device H2, and the base of the second triode serves as the second output end of the second triode.

[0038] The base of the third triode serves as the first input end of the third active device H3, the collector of the third triode serves as the second input end of the third active device H3, and the emitter of the third triode serves as the output end of the third triode.

[0039] In this embodiment, as Figures 2 - 6 shown, the feedback circuit 201 includes a first resistor R1; the first end of the first resistor R1 serves as the input end of the feedback circuit 201, and the second end of the first resistor R1 serves as the output end of the feedback circuit 201.

[0040] As the second alternative embodiment of the feedback circuit 201, as Figure 7As shown, based on the first alternative embodiment, the feedback circuit 201 further includes a third capacitor C3; a first end of the third capacitor C3 is connected to a first end of the first resistor R1, and a second end of the third capacitor C3 is connected to a second end of the first resistor R1.

[0041] As a third alternative embodiment of the feedback circuit 201, as Figure 8 shown, based on the second alternative embodiment, the feedback circuit 201 further includes an inductor L; a first end of the inductor L is connected to a first end of the third capacitor C3, and a second end of the inductor L is connected to a second end of the third capacitor C3.

[0042] As a fourth alternative embodiment of the feedback circuit 201, as Figure 9 shown, based on the first alternative embodiment, the feedback circuit 201 includes an inductor L; a first end of the inductor L is connected to a first end of the first resistor R1, and a second end of the inductor L is connected to a second end of the first resistor R1.

[0043] The feedback circuit 201 can be selected according to different frequency bands and the required harmonic impedance, and any one of the first alternative embodiment, the second alternative embodiment, the third alternative embodiment, and the fourth alternative embodiment can be selected.

[0044] Compared with the prior art, in the bias circuit 200 of the present invention, by designing the first active device H1, the second active device H2, the first capacitor C1, the third active device H3, the second capacitor C2, and the feedback circuit 201, and defining the connection modes of the devices, and at the same time defining that the feedback circuit 201 is used to reduce the impedance of the bias circuit 200, when the bias circuit 200 is applied to a power amplifier circuit, the linearity of the power amplifier circuit under a large bandwidth modulation signal can be improved, and the efficiency of the power amplifier circuit will not be reduced.

[0045] Embodiment 2 The difference between the bias circuit 300 in this embodiment and the bias circuit 200 in Embodiment 1 is that, as Figure 3 shown, the collector of the second triode is also connected to the base of the second triode.

[0046] Embodiment 3 The difference between the bias circuit 400 in this embodiment and the bias circuit 200 in Embodiment 1 is that, as Figure 4 shown, the first active device H41 is a first diode, the second active device H2 is still a second triode, and the third active device H3 is still a third triode.

[0047] Wherein, the positive electrode of the diode serves as both the input end and the second output end of the first active device H41, and the negative electrode of the diode serves as the first output end of the first active device H41; The collector of the second triode serves as the input terminal of the second active device H2, the emitter of the second triode serves as the first output terminal of the second active device H2, and the base of the second triode serves as the second output terminal of the second triode.

[0048] The base of the third triode serves as the first input terminal of the third active device H3, the collector of the third triode serves as the second input terminal of the third active device H3, and the emitter of the third triode serves as the output terminal of the third triode.

[0049] Embodiment 4 The difference between the bias circuit 500 in this embodiment and the bias circuit 400 in Embodiment 3 is that, as Figure 5 shown, the collector of the second triode is also connected to the base of the second triode.

[0050] Embodiment 5 The difference between the bias circuit 600 in this embodiment and the bias circuit 200 in Embodiment 3 is that, as Figure 6 shown, the first active device H61 is a first diode, the second active device H62 is a second diode, and the third active device H3 is also a third triode.

[0051] The positive electrode of the diode serves as both the input terminal and the second output terminal of the first active device H61, and the negative electrode of the diode serves as the first output terminal of the first active device H61.

[0052] The positive electrode of the second diode serves as both the input terminal and the second output terminal of the second active device H62, and the negative electrode of the second diode serves as the first output terminal of the second active device H62.

[0053] The base of the third triode serves as the first input terminal of the third active device H3, the collector of the third triode serves as the second input terminal of the third active device H3, and the emitter of the third triode serves as the output terminal of the third triode.

[0054] Embodiment 6 An embodiment of the present invention provides a power amplifier circuit 700, as combined with Figure 11 shown, which includes an input matching circuit 701, a driver stage circuit 702, a first bias circuit 703, an inter-stage matching circuit 704, an amplification stage circuit 705, a second bias circuit 706, and an output matching circuit 707; both the first bias circuit 703 and the second bias circuit 706 are bias circuits of any one of Embodiments 1 to 5 above.

[0055] The input terminal of the input matching circuit 701 is used to access a radio frequency signal.

[0056] The first input terminal of the driver stage circuit 702 is connected to the output terminal of the input matching circuit 701.

[0057] The output terminal of the first bias circuit 703 is connected to the second input terminal of the driver stage circuit 702.

[0058] The input terminal of the inter-stage matching circuit 704 is connected to the output terminal of the driver stage circuit 702.

[0059] The first input terminal of the amplifier stage circuit 705 is connected to the output terminal of the inter-stage matching circuit 704.

[0060] The output terminal of the second bias circuit 706 is connected to the second input terminal of the amplifier stage circuit 705.

[0061] The input terminal of the output matching circuit 707 is connected to the output terminal of the amplifier stage circuit 705, and the output terminal of the output matching circuit 707 is used to output a radio frequency signal.

[0062] In addition, a second resistor R2 and a third resistor R3 are provided at both ends of the power amplifier circuit 700.

[0063] The first end of the second resistor R2 is connected to the input terminal of the input matching circuit 701, and the second end of the second resistor R2 is grounded.

[0064] The first end of the third resistor R3 is connected to the output terminal of the output matching circuit 707, and the second end of the third resistor R3 is grounded.

[0065] Since the bias circuit of any one of the first to fifth embodiments is adopted in the power amplifier circuit 700 in this embodiment, the nonlinear components generated by the power transistor and the driver transistor due to the second, third, and higher-order nonlinear parameters inside the transistors can be effectively reduced through the bias circuit of any one of the first to fifth embodiments, thereby improving its linearity under large-bandwidth modulation signals and without reducing the efficiency of the power amplifier circuit 700.

[0066] Since the bias circuit of any one of the first to fifth embodiments is adopted in the power amplifier circuit 700 in this embodiment, it can also achieve the technical effects achieved by the bias circuit of any one of the first to fifth embodiments, which will not be elaborated here.

[0067] It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the present invention and not to limit the scope of the present invention. Those of ordinary skill in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the present invention. In addition, unless otherwise indicated by the context, words in the singular form include the plural form and vice versa. Additionally, unless otherwise specified, all or part of any embodiment can be used in combination with all or part of any other embodiment.

Claims

1. A bias circuit, characterized in that, The bias circuit includes a first active device, a second active device, a first capacitor, a third active device, a second capacitor, and a feedback circuit; The input terminal of the first active device is used to connect to a power supply; The input terminal of the second active device is connected to the first output terminal of the first active device, and the first output terminal of the second active device is grounded; The first end of the first capacitor is connected to the second output terminal of the first active device, and the second end of the first capacitor is grounded; The first input terminal of the third active device is connected to the first end of the first capacitor, the second input terminal of the third active device is used to connect to a supply voltage, and the output terminal of the third active device is used to output a bias signal; The first active device, the second active device, and the third active device together form a current mirror circuit and are used to output a stable bias current or bias voltage according to the connected power supply; The first end of the second capacitor is connected to the second output terminal of the second active device, and the second end of the second capacitor is grounded; The input terminal of the feedback circuit is connected to the first end of the second capacitor, and the output terminal of the feedback circuit is connected to the output terminal of the third active device. The feedback circuit is used to reduce the impedance of the bias circuit.

2. The offset circuit according to claim 1, wherein The first active device is a first triode, the second active device is a second triode, and the third active device is a third triode; The collector of the first triode serves as the input terminal of the first active device, the emitter of the first triode serves as the first output terminal of the first active device, and the base of the first triode serves as the second output terminal of the first active device; the collector of the first triode is connected to the base of the first triode; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second active device; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

3. The bias circuit according to claim 1, characterized in that, The first active device is a first triode, the second active device is a second triode, and the third active device is a third triode; The collector of the first triode serves as the input terminal of the first active device, the emitter of the first triode serves as the first output terminal of the first active device, and the base of the first triode serves as the second output terminal of the first active device; the collector of the first triode is connected to the base of the first triode; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second active device; the collector of the second triode is connected to the base of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

4. The bias circuit according to claim 1, wherein The first active device is a first diode, the second active device is a second triode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

5. The offset circuit according to claim 1, wherein The first active device is a first diode, the second active device is a second triode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The collector of the second triode serves as the input terminal of the second active device, the emitter of the second triode serves as the first output terminal of the second active device, and the base of the second triode serves as the second output terminal of the second triode; The collector of the second triode is connected to the base of the second triode; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

6. The bias circuit according to claim 1, wherein The first active device is a first diode, the second active device is a second diode, and the third active device is a third triode; The positive electrode of the diode serves as both the input terminal and the second output terminal of the first active device, and the negative electrode of the diode serves as the first output terminal of the first active device; The positive electrode of the second diode serves as both the input terminal and the second output terminal of the second active device, and the negative electrode of the second diode serves as the first output terminal of the second active device; The base of the third triode serves as the first input terminal of the third active device, the collector of the third triode serves as the second input terminal of the third active device, and the emitter of the third triode serves as the output terminal of the third triode.

7. The bias circuit according to any one of claims 1 to 6, characterized in that The feedback circuit includes a first resistor; The first end of the first resistor serves as the input terminal of the feedback circuit, and the second end of the first resistor serves as the output terminal of the feedback circuit.

8. The bias circuit according to claim 7, wherein The feedback circuit further includes a third capacitor; a first end of the third capacitor is connected to a first end of the first resistor, and a second end of the third capacitor is connected to a second end of the first resistor.

9. The bias circuit according to claim 8, wherein The feedback circuit further includes an inductor; a first end of the inductor is connected to a first end of the third capacitor, and a second end of the inductor is connected to a second end of the third capacitor.

10. The bias circuit according to claim 7, wherein The feedback circuit includes an inductor; a first end of the inductor is connected to a first end of the first resistor, and a second end of the inductor is connected to a second end of the first resistor.

11. A power amplifier circuit, characterized in that, The power amplifier circuit includes an input matching circuit, a driver stage circuit, a first bias circuit, an inter-stage matching circuit, an amplification stage circuit, a second bias circuit, and an output matching circuit; the first bias circuit and the second bias circuit are both the bias circuits as described in any one of claims 1 to 10. An input end of the input matching circuit is used for accessing a radio frequency signal. A first input end of the driver stage circuit is connected to an output end of the input matching circuit. An output end of the first bias circuit is connected to a second input end of the driver stage circuit. An input end of the inter-stage matching circuit is connected to an output end of the driver stage circuit. A first input end of the amplification stage circuit is connected to an output end of the inter-stage matching circuit. An output end of the second bias circuit is connected to a second input end of the amplification stage circuit. An input end of the output matching circuit is connected to an output end of the amplification stage circuit, and an output end of the output matching circuit is used for outputting a radio frequency signal.

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