Signal processing device, method and system, signal receiver, equipment and chip

Abstract

The invention relates to a signal processing device, method and system, a signal receiver, equipment and a chip, the signal processing device comprises a preprocessing module used for receiving a first signal sequence and processing the first signal sequence to obtain m groups of second signal sequences, the first signal sequence comprises a plurality of first signals, and the m groups of second signal sequences comprise m groups of second signals; the preprocessing module is used for outputting m groups of second signal sequences, each group of second signal sequences comprises n second signals, the operation module is used for receiving a third signal sequence and m groups of second signal sequences output by the preprocessing module and obtaining a correlation result of the third signal sequence and each group of second signal sequences, and the third signal sequence comprises n third signals, the sampling frequency of the first signal sequence is m times of the sampling frequency of the third signal sequence. The signal processing device can reduce power consumption and save storage resources.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a signal processing apparatus, method, system, signal receiver, device, and chip. Background Art

[0002] For a signal receiver, since it is necessary to process the Doppler time delay and code phase offset caused by the relative motion between the target and the signal receiver, it is necessary to perform correlation operations of multiple phases and multiple Doppler frequencies through a correlator. However, the correlation calculation in the related art has a large amount of calculation, which increases the power consumption of the correlator. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a signal processing apparatus, method, system, signal receiver, device, and chip, which can use the signal processed by the first signal enhancement module and the second signal enhancement module as the input signal of the clock recovery module to recover clock information, thereby improving the quality of the recovered clock information and reducing the bit error rate of the receiving circuit.

[0004] To achieve the above purpose, the first aspect of the embodiments of the present disclosure provides a signal processing apparatus, including: A preprocessing module, configured to receive a first signal sequence, process the first signal sequence, and obtain m groups of second signal sequences, where the first signal sequence includes multiple first signals, and each group of second signal sequences includes n second signals; An operation module, configured to receive a third signal sequence and the m groups of second signal sequences output by the preprocessing module, and obtain the correlation results between the third signal sequence and each group of second signal sequences, where the third signal sequence includes n third signals, and the sampling frequency of the first signal sequence is m times the sampling frequency of the third signal sequence.

[0005] Optionally, each second signal in the second signal sequence is obtained by superimposing the specified signal corresponding to the second signal in the multiple first signals and m - 1 consecutive first signals after the specified signal, the specified signals corresponding to adjacent two second signals are separated by m - 1 sampling points, the specified signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals in the multiple first signals, and the specified signals corresponding to different starting signals are different.

[0006] Optionally, the operation module includes m correlation calculation modules. Each correlation calculation module includes a multiplication unit and an addition unit. The multiplication unit is configured to multiply a second signal in the second signal sequence by a third signal with the same sequence number as the second signal in the third signal sequence, obtaining n multiplication results. The addition unit is configured to add the n multiplication results to obtain an addition result, and the addition result serves as the correlation result between the second signal sequence and the third signal sequence.

[0007] Optionally, the multiplication unit includes n multipliers, and the addition unit includes n - 1 adders connected in sequence. The input of the kth multiplier is the kth second signal and the kth third signal. The input of the first adder is the multiplication result output by the first multiplier and the multiplication result output by the second multiplier. The input of the jth adder is the multiplication result output by the (j + 1)th multiplier and the addition result output by the (j - 1)th adder, where k is greater than or equal to 1 and less than or equal to n, and j is greater than 1 and less than or equal to n - 1.

[0008] Optionally, the signal processing device further includes n storage units, and each storage unit is configured to store one third signal in the third signal sequence.

[0009] Optionally, the third signal sequence is a coarse acquisition code sequence in the L1 frequency band of the Global Positioning System.

[0010] A second aspect of the embodiments of the present disclosure provides a signal processing method, including: Receiving a first signal sequence and a third signal sequence, where the first signal sequence includes multiple first signals, the third signal sequence includes n third signals, and the sampling frequency of the first signal sequence is m times the sampling frequency of the third signal sequence; Processing the first signal sequence to obtain m groups of second signal sequences, and each group of second signal sequences includes n second signals; Obtaining the correlation result between the third signal sequence and each group of second signal sequences.

[0011] Optionally, each second signal in the second signal sequence is obtained by superimposing a specified signal corresponding to the second signal among the multiple first signals and m - 1 consecutive first signals sampled after the specified signal. The specified signals corresponding to adjacent second signals are separated by m - 1 sampling points. The specified signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals among the multiple first signals, and the specified signals corresponding to different starting signals are different.

[0012] A third aspect of the embodiments of the present disclosure provides a signal processing system, including the signal processing device according to any one of the first aspects and a code generator; an output end of the code generator is coupled to an input end of the operation module, and the code generator is configured to generate the third signal sequence and send the third signal sequence to the operation module.

[0013] A fourth aspect of the embodiments of the present disclosure provides a signal receiver, including the signal processing system according to the third aspect and a first signal sequence generation module; an output end of the first signal sequence generation module is coupled to an input end of the preprocessing module, and the first signal sequence generation module is configured to generate the first signal sequence according to the received satellite signal and send the first signal sequence to the preprocessing module.

[0014] A fifth aspect of the embodiments of the present disclosure provides an electronic device, including the signal receiver according to the fourth aspect.

[0015] Another aspect of the embodiments of the present disclosure provides a chip, including one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal and send the signal to the processor, and the signal includes computer instructions; when the processor executes the computer instructions, the chip is caused to execute the method according to the second aspect.

[0016] Through the above technical solutions, the preprocessing module in the signal processing device processes the received first signal sequence to obtain m groups of second signal sequences, and then the operation module in the signal processing device can receive the third signal sequence and the m groups of second signal sequences output by the preprocessing module, and obtain the correlation results of the received third signal sequence and each group of second signal sequences. Since the sampling frequency of the first signal sequence is m times that of the third signal sequence, and each group of second signal sequences and the third signal sequence each include n second signals, by processing the received first signal sequence to obtain m groups of second signal sequences and obtaining the correlation results of the third signal sequence and each group of second signal sequences, when the signal processing module performs the correlation result calculation once, the number of multiplications remains unchanged, still being m×n, but m correlation results of time offsets can be obtained, thereby reducing the number of times of performing the correlation result calculation in a loop and reducing power consumption. In addition, since only n third signals need to be stored, storage resources can be saved.

[0017] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the accompanying drawings: Figure 1 It is a schematic structural diagram of a correlator in the related art.

[0019] Figures 2 - 3 It is a schematic structural diagram of a signal processing device provided by some embodiments of the present disclosure.

[0020] Figure 4 It is a schematic flowchart of a signal processing method shown in an exemplary embodiment of the present disclosure.

[0021] Figure 5 It is a schematic structural diagram of a signal processing system shown in an exemplary embodiment of the present disclosure.

[0022] Figure 6 It is a schematic structural diagram of a signal receiver shown in an exemplary embodiment of the present disclosure.

[0023] Figure 7 It is a schematic structural diagram of an electronic device shown in an exemplary embodiment of the present disclosure.

[0024] Explanation of reference numerals 200, signal processing device; 21, preprocessing module; 22, operation module; 221, multiplication unit; 222, addition unit; 500, signal processing system; 51, code generator; 600, signal receiver; 61, first signal sequence generation module; 700, electronic device. Specific embodiments

[0025] The following will explain in detail the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.

[0026] In the related art, the correlator performs serial sliding correlation calculations on multiple phases and multiple Doppler frequencies. The low degree of multiplexing of the serial sliding correlation calculations results in a large amount of correlation calculations, increasing the power consumption of the correlator and unable to meet the requirements of ultra-low power consumption of the signal receiver.

[0027] Referring to Figure 1 , Figure 1 It is a schematic structural diagram of a correlator implemented based on a matched filter shown in an exemplary embodiment of the present disclosure, as Figure 1As shown, the correlator has two input signals, namely signal sequence Dmn and signal sequence Cmn. Among them, the signal sequence Dmn is the output of the previous stage decision feedback equalizer (DFE) module, and its resolution is m times the baseband frequency. Taking the coarse acquisition code sequence (GPS L1 CA) system in the L1 frequency band of the global positioning system as an example, the sampling frequency fs of the signal sequence Dmn is m×1.023 MHz, where m can take three optional values of 2 / 4 / 8, corresponding to three different engineering application scenarios, and n is taken as 1023 in this scenario. The signal sequence Cmn is the output of the previous stage code generator, and its resolution is also m times the baseband frequency. The numerically controlled oscillator (CodeNCO) module controls the output rhythm of the code generator to match the sampling frequency of the signal sequence Dmn.

[0028] In the above example, the calculation of the correlation result by the correlator can be expressed by the following formula: Y(t) =∑C(t+i)×D(i), i = 0~m×n - 1, t = 0~m×n - 1; It can be seen that for each time offset in the range of 0 to mn - 1, the calculation of the correlation result Y(t) is performed once. From the perspective of the amount of calculation, for each calculation of y(t), it is necessary to perform the calculations of D0×C0, D1×C1, ……, Dmn - 1×Cmn - 1, obtaining m×n multiplication results, and further adding the m×n multiplication results to finally obtain one y(t). Therefore, for each calculation of y(t), the number of multiplications is m×n, and the number of additions is m×n - 1. Furthermore, for m×n time offsets, the total number of multiplications is m×n×m×n, and the number of additions is m×n×(m×n - 1).

[0029] Therefore, if m or n is relatively large, the amount of calculation for the correlator to calculate the correlation result Y(t) will increase exponentially, increasing the power consumption of the correlator.

[0030] In addition, in Figure 1 the correlator with the architecture shown, storing the signal sequence Cmn requires m×n storage units, and the demand for storage units is large.

[0031] In view of this, embodiments of the present disclosure provide a signal processing apparatus, method, system, signal receiver, device, and chip. The preprocessing module in the signal processing apparatus processes the received first signal sequence to obtain m groups of second signal sequences. Then, the operation module in the signal processing apparatus can receive the third signal sequence and the m groups of second signal sequences output by the preprocessing module, and obtain the correlation results between the received third signal sequence and each group of second signal sequences. Since the sampling frequency of the first signal sequence is m times that of the third signal sequence, and each group of second signal sequences and the third signal sequence each include n second signals, by processing the received first signal sequence to obtain m groups of second signal sequences and obtaining the correlation results between the third signal sequence and each group of second signal sequences, each time the signal processing module performs a correlation result calculation, the number of multiplications remains unchanged, still being m×n, but m correlation results with time offsets can be obtained, thereby reducing the number of times of performing the correlation result calculation in a loop and reducing power consumption. In addition, since only n third signals need to be stored, storage resources can be saved.

[0032] It should be noted that in subsequent embodiments, in order to reduce the redundancy of the drawings without affecting the understanding of the technical solutions, the case of m = 2 is used for the illustration of the drawings.

[0033] Reference Figure 2 , Figure 2 is a schematic structural diagram of a signal processing apparatus 200 according to an exemplary embodiment of the present disclosure. As Figure 2 shown, in an exemplary embodiment of the present disclosure, the signal processing apparatus 200 may include a preprocessing module 21, configured to receive the first signal sequence and process the first signal sequence to obtain m groups of second signal sequences, the first signal sequence including a plurality of first signals, and each group of second signal sequences including n second signals; an operation module 22, configured to receive the third signal sequence and the m groups of second signal sequences output by the preprocessing module 21, and obtain the correlation results between the third signal sequence and each group of second signal sequences, the third signal sequence including n third signals, and the sampling frequency of the first signal sequence being m times that of the third signal sequence.

[0034] During the working process of the signal processing apparatus 200 according to the embodiments of the present disclosure, the first signal sequence including a plurality of first signals may be input into the preprocessing module 21. Then, the preprocessing module 21 may process the received first signal sequence to obtain m groups of second signal sequences, and input the m groups of second signal sequences into the operation module 22. In addition, the third signal sequence including n third signals may also be input into the operation module 22. Thus, the operation module 22 can obtain the correlation results between the third signal sequence and each group of second signal sequences.

[0035] Since the sampling frequency of the first signal sequence is m times that of the third signal sequence, for the m sampling points of one chip, the local codes used for correlation operation are the same. Continuing with the previous example, C0 to Cm-1 are the same, Cm to C2m-1 are the same, and so on, which is equivalent to repeating the 1023 local codes m times. Therefore, by processing the received first signal sequence, m groups of second signal sequences are obtained, and it is set that each group of second signal sequences and the third signal sequence both include n second signals, so that each time the signal processing module performs a correlation result calculation, the number of multiplications remains unchanged, still m×n, but m correlation results with time offsets can be obtained. Compared with the need to perform a total of m×n correlation result calculations in the related art, the number of times of circularly performing correlation result calculations is greatly reduced, and thus the power consumption can be reduced. In addition, since only n third signals need to be stored, compared with the need to store a total of m×n local code signals in the related art, storage resources can be saved.

[0036] In some embodiments, as Figure 3 shown, on the basis of Figure 2 , the operation module 22 includes m correlation calculation modules. The correlation calculation module includes a multiplication unit 221 and an addition unit 222. The multiplication unit 221 is used to multiply the second signal in the second signal sequence by the third signal with the same serial number as the second signal in the third signal sequence to obtain n multiplication results; the addition unit 222 is used to add the n multiplication results to obtain an addition result, and the addition result is used as the correlation result of the second signal sequence and the third signal sequence.

[0037] In the embodiments of the present disclosure, the correlation result of the third signal sequence and the second signal sequence can be obtained through the correlation calculation module provided in the operation module 22. One correlation calculation module can calculate the correlation result of the input third signal sequence and a group of second signal sequences. Then, by setting m correlation calculation modules, the correlation results of the third signal sequence and each group of second signal sequences can be obtained.

[0038] Specifically, in any one correlation calculation module, the multiplication unit 221 can multiply the second signal in the second signal sequence by the third signal with the same serial number as the second signal in the third signal sequence to obtain n multiplication results, and the addition unit 222 can add the n multiplication results to obtain an addition result, and this addition result can be output as the correlation result of a group of second signal sequences and the third signal sequence.

[0039] In some embodiments, the correlation result can be output to a Random Access Memory (RAM) coupled to the signal processing device for storage.

[0040] In some embodiments, continuing as Figure 3 shown, the multiplication unit 221 includes n multipliers, the addition unit 222 includes n - 1 adders connected in sequence. The input of the kth multiplier is the kth second signal and the kth third signal. The input of the first adder is the multiplication result output by the first multiplier and the multiplication result output by the second multiplier. The input of the jth adder is the multiplication result output by the (j + 1)th multiplier and the addition result output by the (j - 1)th adder, where k is greater than or equal to 1 and less than or equal to n, and j is greater than 1 and less than or equal to n - 1.

[0041] In some embodiments, the calculation process of the correlation calculation module can also be represented by the following formula: When m = 2, Y(2*t) = ∑C(t + i)*D’(2*i), i = 0~n - 1, t = 0~n - 1; Y(2*t + 1) = ∑C(t + i)*D’(2*i + 1), i = 0~n - 1, t = 0~n - 1; When m = 4, Y(4*t) = ∑C(t + i)*D’(4*i), i = 0~n - 1, t = 0~n - 1; Y(4*t + 1) = ∑C(t + i)*D’(4*i + 1), i = 0~n - 1, t = 0~n - 1; Y(4*t + 2) = ∑C(t + i)*D’(4*i + 2), i = 0~n - 1, t = 0~n - 1; Y(4*t + 3) = ∑C(t + i)*D’(4*i + 3), i = 0~n - 1, t = 0~n - 1; When m = 8, Y(8*t) = ∑C(t + i)*D’(8*i), i = 0~n - 1, t = 0~n - 1; Y(8*t + 1) = ∑C(t + i)*D’(8*i + 1), i = 0~n - 1, t = 0~n - 1; Y(8*t + 2) = ∑C(t + i)*D’(8*i + 2), i = 0~n - 1, t = 0~n - 1; Y(8*t + 3) = ∑C(t + i)*D’(8*i + 3), i = 0~n - 1, t = 0~n - 1; Y(8*t + 4) = ∑C(t + i)*D’(8*i + 4), i = 0~n - 1, t = 0~n - 1; Y(8*t + 5) = ∑C(t + i)*D’(8*i + 5), where i = 0 to n - 1 and t = 0 to n - 1; Y(8*t + 6) = ∑C(t + i)*D’(8*i + 6), where i = 0 to n - 1 and t = 0 to n - 1; Y(8*t + 7) = ∑C(t + i)*D’(8*i + 7), where i = 0 to n - 1 and t = 0 to n - 1.

[0042] In addition, further considering that during the multiplication and accumulation process of the correlation operation, for the superimposed result of one chip, it is ∑D(j)C(j), where j = 0 to m - 1; ∑D(j)C(j) = {∑D(j)} × Cr; Cr = C(0) = C(1) = … = C(m - 1). Therefore, in some embodiments, each second signal in the second signal sequence can be set to be obtained by superimposing the specified signal corresponding to the second signal among the multiple first signals and the m - 1 first signals sampled continuously after the specified signal. The specified signals corresponding to adjacent two second signals are separated by m - 1 sampling points. The specified signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals among the multiple first signals, and the specified signals corresponding to different starting signals are different.

[0043] Exemplarily, continuing with the foregoing example, taking m = 2 as an example: The second signals included in the first group of second signal sequences are in sequence: D’(0), D’(2), ……, D’(2n - 2); The second signals included in the second group of second signal sequences are in sequence: D’(1), D’(3), ……, D’(2n - 1); where D’(0) = D(0) + D(1); D’(1) = D(1) + D(2); D’(2) = D(2) + D(3); …… D’(2n - 2) = D(2n - 2) + D(2n - 1); D’(2n - 1) = D(2n - 1) + D(2n).

[0044] where D’(0) is the starting signal of the first group of second signal sequences, D’(1) is the starting signal of the second group of second signal sequences. The specified signal corresponding to the second signal D’(0) among the multiple first signals is D(0), the specified signal corresponding to the second signal D’(2) among the multiple first signals is D(2), and so on.

[0045] Taking m = 4 as an example: The second signals included in the first group of second signal sequences are successively: D’(0), D’(4), ……, D’(4n - 4); The second signals included in the second group of second signal sequences are successively: D’(1), D’(5), ……, D’(4n - 3); The second signals included in the third group of second signal sequences are successively: D’(2), D’(6), ……, D’(4n - 2); The second signals included in the fourth group of second signal sequences are successively: D’(3), D’(7), ……, D’(4n - 1).

[0046] Among them, D’(0) = D(0) + D(1) + D(2) + D(3); D’(1) = D(1) + D(2) + D(3) + D(4); D’(2) = D(2) + D(3) + D(4) + D(5); …… D’(4n - 1) = D(4n - 1) + D(4n) + D(4n + 1) + D(4n + 2).

[0047] Taking m = 8 as an example: The second signals included in the first group of second signal sequences are successively: D’(0), D’(8), ……, D’(8n - 8); The second signals included in the second group of second signal sequences are successively: D’(1), D’(9), ……, D’(8n - 7); The second signals included in the third group of second signal sequences are successively: D’(2), D’(10), ……, D’(8n - 6); …… The second signals included in the eighth group of second signal sequences are successively: D’(7), D’(15), ……, D’(8n - 1).

[0048] Among them, D’(0) = D(0) + D(1) + D(2) + D(3) + D(4) + D(5) + D(6) + D(7); D’(1) = D(1) + D(2) + D(3) + D(4) + D(5) + D(6) + D(7) + D(8); D’(2) = D(2) + D(3) + D(4) + D(5) + D(6) + D(7) + D(8) + D(9); …… D’(8n - 1) = D(8n - 1) + D(8n) + D(8n + 1) + D(8n + 2) + D(8n + 3) + D(8n + 4) + D(8n + 5) + D(8n + 6).

[0049] Thus, it can be seen from the above formula that for each time offset in the range of 0 to n-1, the calculation of the correlation result Y(t) is performed in parallel. In terms of the amount of calculation, when the operation module 22 calculates the correlation result y(t) between the third signal sequence and a set of second signal sequences, it needs to perform n multiplication calculations to obtain n multiplication results, and further add the n multiplication results to finally obtain one y(t). Therefore, for one time offset, the number of multiplication operations is m×n, and the number of addition operations is m×(n-1). Furthermore, for n time offsets, the total number of multiplication operations is m×n×n, and the number of addition operations is m×(n-1)×n. In addition, each time the preprocessing module 21 generates m sets of second signal sequences, it needs to perform (m-1)×n×m addition calculations. Therefore, when the signal processing device 200 obtains the correlation results between the third signal sequence and each set of second signal sequences, the total number of multiplication operations is m×n×n, and the number of addition operations is m×(n-1)×n+(m-1)×n×m.

[0050] Therefore, by comparing the amount of calculation for the signal processing device 200 in the embodiment of the present disclosure to perform the correlation result calculation with the amount of calculation for the correlator in the related art to perform the correlation result calculation, it can be known that when generating the same m×n correlation results, the number of multiplication operations is only 1 / m of that in the related art, and the number of addition operations is only (m+n-2) / (m×n-1) of that in the related art.

[0051] In some embodiments, in order to obtain m sets of second signal sequences, the preprocessing module 21 may superimpose the first signals in the first signal sequence according to a preset sliding window to obtain a second signal, and send the processed second signal to the operation module 22 at intervals of every m second signals, where the sliding step of the preset sliding window is 1 and the window size is m.

[0052] In some embodiments, the signal processing device 200 further includes n storage units, and each storage unit is used to store one third signal in the third signal sequence. Furthermore, in the embodiment of the present disclosure, the number of storage units for storing the third signal sequence is only 1 / m of that in the related art, greatly reducing the number of storage units and saving resources.

[0053] In some embodiments, the storage unit may be a register, for example.

[0054] In some embodiments, the input end of the preprocessing module 21 is coupled to the output end of the first signal sequence generation module, and the first signal sequence generation module is used to generate a first signal sequence and send the first signal sequence to the preprocessing module 21.

[0055] In some embodiments, the first signal sequence generation module is configured to generate a first signal sequence based on the received satellite signal, and send the first signal sequence to the preprocessing module 21.

[0056] In some embodiments, the first signal sequence generation module includes a decision feedback equalizer.

[0057] In some embodiments, the input end of the operation module 22 is coupled to the output end of the code generator. The code generator is configured to generate a third signal sequence and send the third signal sequence to the operation module 22.

[0058] In some embodiments, the third signal sequence generated by the code generator is a coarse acquisition code sequence in the L1 frequency band of the Global Positioning System.

[0059] Reference Figure 4 , Figure 4 is a schematic flow chart of a signal processing method provided according to an exemplary embodiment of the present disclosure. The signal processing method can be implemented by software or hardware. As Figure 4 shown, in an exemplary embodiment of the present disclosure, the signal processing method includes: Step S401: Receive a first signal sequence and a third signal sequence. The first signal sequence includes a plurality of first signals, the third signal sequence includes n third signals, and the sampling frequency of the first signal sequence is m times the sampling frequency of the third signal sequence; Step S402: Process the first signal sequence to obtain m groups of second signal sequences, and each group of second signal sequences includes n second signals; Step S403: Obtain the correlation results between the third signal sequence and each group of second signal sequences.

[0060] Using the above method, since the sampling frequency of the first signal sequence is m times the sampling frequency of the third signal sequence, and each group of second signal sequences and the third signal sequence both include n second signals, by processing the received first signal sequence to obtain m groups of second signal sequences and obtaining the correlation results between the third signal sequence and each group of second signal sequences, the number of multiplications remains unchanged at m×n each time the signal processing module performs the correlation result calculation, but m correlation results with time offsets can be obtained, thereby reducing the number of times of performing the correlation result calculation in a loop and reducing power consumption. In addition, since only n third signals need to be stored, storage resources can be saved.

[0061] In some embodiments, each second signal in the second signal sequence is obtained by superimposing the specified signal corresponding to the second signal among the multiple first signals and m - 1 consecutive first signals after the specified signal. There is an interval of m - 1 sampling points between the specified signals corresponding to two adjacent second signals. The specified signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals among the multiple first signals, and the specified signals corresponding to different starting signals are different.

[0062] Among them, for a detailed description of the above signal processing method, reference can be made to the foregoing embodiments, which will not be elaborated herein.

[0063] It should be noted that the signal processing method or signal processing device in the embodiments of the present disclosure can be implemented by software or a hardware circuit.

[0064] Reference Figure 5 , Figure 5 FIG. is a schematic structural diagram of a signal processing system 500 provided according to an exemplary embodiment of the present disclosure. As Figure 5 shown, in an exemplary embodiment of the present disclosure, the signal processing system 500 may include a signal processing device 200 and a code generator 51.

[0065] Among them, the output end of the code generator 51 is coupled to the input end of the operation module 22. The code generator 51 is configured to generate the third signal sequence and send the third signal sequence to the operation module 22.

[0066] Reference Figure 6 , Figure 6 FIG. is a schematic structural diagram of a signal receiver 600 provided according to an exemplary embodiment of the present disclosure. As Figure 6 shown, in an exemplary embodiment of the present disclosure, the signal receiver 600 may include a signal processing system 500 and a first signal sequence generation module 61.

[0067] Among them, the output end of the first signal sequence generation module 61 is coupled to the input end of the preprocessing module 21. The first signal sequence generation module 61 is configured to generate the first signal sequence according to the received satellite signal and send the first signal sequence to the preprocessing module 21.

[0068] Reference Figure 7 , Figure 7 FIG. is a schematic structural diagram of an electronic device 700 provided according to an exemplary embodiment of the present disclosure. As Figure 7 shown, in an exemplary embodiment of the present disclosure, the electronic device 700 may include a signal receiver 600.

[0069] Embodiments of the present disclosure further provide a chip, including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals and send signals to the processors, and the signals include computer instructions; when the processors execute the computer instructions, the chip is caused to execute the signal processing method of the embodiments of the present disclosure.

[0070] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0071] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, they can be combined in any appropriate manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination manners.

[0072] In addition, any combination can be made among various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.

[0073] It should be noted that in the present disclosure, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0074] Each embodiment in the present disclosure is described in a related manner. The same or similar parts among the embodiments can be referred to each other. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts can be referred to the partial description of the method embodiments.

Claims

1. A signal processing device (200), characterized in that, Comprising: A preprocessing module (21) for receiving a first signal sequence, processing the first signal sequence to obtain m groups of second signal sequences, the first signal sequence including a plurality of first signals, and each group of second signal sequences including n second signals; An operation module (22) for receiving a third signal sequence and the m groups of second signal sequences output by the preprocessing module (21), and obtaining a correlation result between the third signal sequence and each group of second signal sequences, the third signal sequence including n third signals, and the sampling frequency of the first signal sequence being m times the sampling frequency of the third signal sequence.

2. The signal processing device (200) according to claim 1, characterized in that, Each second signal in the second signal sequence is obtained by superimposing the designated signal corresponding to the second signal among the plurality of first signals and m - 1 consecutive first signals sampled after the designated signal. The designated signals corresponding to adjacent second signals are separated by m - 1 sampling points. The designated signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals among the plurality of first signals, and the designated signals corresponding to different starting signals are different.

3. The signal processing device (200) according to claim 1, wherein, The operation module (22) includes m correlation calculation modules. The correlation calculation module includes a multiplication unit (221) and an addition unit (222). The multiplication unit (221) is configured to multiply the second signal in the second signal sequence by the third signal having the same sequence number as the second signal in the third signal sequence to obtain n multiplication results; the addition unit (222) is configured to add the n multiplication results to obtain an addition result, and the addition result is used as the correlation result between the second signal sequence and the third signal sequence.

4. The signal processing device (200) according to claim 3, characterized in that, The multiplication unit (221) includes n multipliers, and the addition unit (222) includes n - 1 adders connected in sequence. The input of the kth multiplier is the kth second signal and the kth third signal. The input of the first adder is the multiplication result output by the first multiplier and the multiplication result output by the second multiplier. The input of the jth adder is the multiplication result output by the (j + 1)th multiplier and the addition result output by the (j - 1)th adder, where k is greater than or equal to 1 and less than or equal to n, and j is greater than 1 and less than or equal to n - 1.

5. The signal processing device (200) according to claim 1, characterized in that, The signal processing device (200) further includes n storage units, and each storage unit is configured to store one third signal in the third signal sequence.

6. The signal processing device (200) according to claim 1, characterized in that The third signal sequence is a coarse acquisition code sequence in the L1 frequency band of the global positioning system.

7. A signal processing method, characterized in that, Comprising: Receiving a first signal sequence and a third signal sequence, the first signal sequence including a plurality of first signals, the third signal sequence including n third signals, and the sampling frequency of the first signal sequence being m times the sampling frequency of the third signal sequence; Processing the first signal sequence to obtain m groups of second signal sequences, each group of second signal sequences including n second signals; Obtaining a correlation result between the third signal sequence and each group of second signal sequences.

8. The signal processing method according to claim 7, wherein Each second signal in the second signal sequence is obtained by superimposing the specified signal corresponding to the second signal among the multiple first signals and m-1 consecutive first signals sampled after the specified signal. There is an interval of m-1 sampling points between the specified signals corresponding to two adjacent second signals. The specified signal corresponding to the starting signal in each group of second signal sequences is any one of the first m first signals among the multiple first signals, and the specified signals corresponding to different starting signals are different.

9. A signal processing system (500), characterized in that, Comprising: The signal processing device (200) and the code generator (51) according to any one of claims 1-6; The output end of the code generator (51) is coupled to the input end of the operation module (22). The code generator (51) is used to generate the third signal sequence and send the third signal sequence to the operation module (22).

10. A signal receiver (600), characterized in that, Comprising: The signal processing system (500) and the first signal sequence generation module (61) according to claim 9; The output end of the first signal sequence generation module (61) is coupled to the input end of the preprocessing module (21). The first signal sequence generation module (61) is used to generate the first signal sequence according to the received satellite signal and send the first signal sequence to the preprocessing module (21).

11. An electronic device (700), comprising the signal receiver (600) according to claim 10.

12. A chip, comprising one or more interface circuits and one or more processors; the interface circuit is used to receive a signal and send the signal to the processor, and the signal includes computer instructions; when the processor executes the computer instructions, the chip executes the method according to any one of claims 7 to 8.

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