Fractional delay analysis method and system of digital pre-distortion model, storage medium and equipment
Through the method of correlation first and then interpolation, combined with integer and fraction delay adjustment, the problem of poor robustness and large calculation amount in the prior art is solved, and accurate signal synchronization and low computational complexity are achieved in multi-carrier communication scenarios.
Patent Information
- Application Number
- CN202510298939.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2025-07-18
AI Technical Summary
In the prior art, the fractional-order delay estimation method has poor robustness and large calculation amount in multi-carrier communication scenarios, so it is impossible to accurately estimate signal delay, which affects the performance of the digital predistortion model.
The correlation and then interpolation method is adopted. By synchronous sampling and fixed-float conversion, the correlation operation is performed, the maximum peak value is found, the correlation operation segment is intercepted for interpolation, combined with integer and fraction delay adjustment, and signal alignment is used to use serial registers and Nyquist interpolation filters.
Accurate fractional-level delay estimation in multi-carrier communication scenarios is realized, which reduces the computational amount and memory requirements, and improves the robustness and synchronization accuracy of the digital predistortion model.
Smart Images
Figure CN120342912A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wireless communication technologies, and in particular, to a fractional delay analysis method, system, storage medium, and device for a digital predistortion model. Background Art
[0002] Digital predistortion (DPD) is used to improve the linearity and efficiency indicators of radio frequency power amplifiers and is widely applied in radio frequency transceiver chips. Its basic principle is to insert a predistorter in the transmit channel, perform predistortion processing on the baseband signal, and then output it to the power amplifier through digital-to-analog conversion, etc. Since the predistorter contains the inverse model of the power amplifier's behavior, the purpose of compensating for the power amplifier's nonlinearity is achieved. Before using an adaptive algorithm to solve the model coefficients of the predistorter, it is necessary to align the PA input and output signals. The alignment accuracy of the signals is an important factor affecting the DPD performance, and sub-sampling level signal alignment requires accurate fractional delay estimation. In addition, since the delay of the transmit link varies with temperature, it is necessary to periodically estimate the signal delay during the operation of the system. Therefore, higher requirements are imposed on the efficiency of the delay estimation algorithm. In the prior art, there are mainly two fractional delay estimation methods:
[0003] 1) Parabolic fitting method: This method first needs to perform a correlation operation on the N-point signals of the PA input and output, and then find the maximum value and two sub-maximum values of the correlation function. The envelope near the correlation peak can be fitted with a parabola, as Figure 1 shown. Therefore, the "three-point quadratic" algorithm can be used for curve fitting. After obtaining the positions of the maximum peak and the two sub-maximum peaks, substitute them into the parabola equation to calculate the vertex coordinates, and then obtain the fractional delay. This method has the advantages of small computational complexity and easy digital implementation, but poor robustness. However, in a real multi-carrier communication application scenario, the relevant results do not have only a single peak. If the position estimation of the maximum value of the correlation peak is deviated, the fractional delay estimation will obtain an incorrect result or no solution. As Figure 2 shown, in the application scenario of a dual-carrier signal, perform a correlation operation on the original signal (red circle), and the found maximum peak P1 is located in the sidelobe, rather than the real maximum peak P0 (the interpolated correlation is required to see). Then, use the parabolic fitting method to estimate the delay, and the obtained result differs from the real integer delay by 3 sample points, and the fractional delay estimation is also inaccurate. Moreover, based on the synchronized signal adjusted by the incorrect delay estimation, the training effect of the DPD model will deteriorate the ACLR index and even cause the model to diverge.
[0004] 2) Interpolation first and correlation later method: To implement fractional delay estimation using this method, it is first necessary to perform high-magnitude interpolation on the PA input signal or output signal, extract samples at the interval before interpolation, form multiple channels, and then perform correlation operations separately with the PA output signal that has not been interpolated. Then, compare the peaks of the correlation results of each channel to find the maximum peak, and thus obtain the fractional delay. As Figure 2 shown, after interpolating the original signal by 10 times and then performing correlation operations, the true peak can be found, and thus an accurate delay estimation can be obtained. However, the disadvantage of this method is that the computational complexity is too high and it will occupy too much memory overhead. Summary of the Invention
[0005] One of the objectives of the present invention is to provide a fractional-level delay analysis method for a digital pre-distortion model, which adopts the method of correlation first and interpolation later, can take into account the accuracy and general applicability of the interpolation first and correlation later method, and at the same time has the advantage of small computational complexity of the parabolic fitting method. Moreover, it overcomes the problem that the parabolic fitting method has poor robustness and cannot handle the delay estimation in a multi-carrier scenario, and reduces the computational complexity and memory requirements for the original signal with interpolation first and correlation later.
[0006] To achieve the above objective, a fractional-level delay analysis method for a digital pre-distortion model is provided, including the following steps:
[0007] S1. Synchronously sample the PA input and output signals of the digital pre-distortion model to obtain sampling data, and the length of the sampling points is N;
[0008] S2. Perform fixed-point to floating-point conversion on the sampling data and save them to arrays x[N] and y[N] respectively;
[0009] S3. Perform correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y);
[0010] S4. Find the maximum peak of abs(z) and record the lag corresponding to the peak as intLag;
[0011] S5. Intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp;
[0012] S6. Find the maximum peak of abs(zp) and record the lag corresponding to the peak as fracLag;
[0013] S7. Convert intLag and fracLag to integer delay intDelay and fractional delay fracDelay respectively.
[0014] Furthermore, it further includes the following steps:
[0015] S8. Split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically, it includes the following sub-steps:
[0016] S801. Insert a serial register bank as an integer delay unit on the PA input signal path of the digital pre-distortion model. The length of the register bank depends on the size of the integer delay;
[0017] S802. Insert a Nyquist interpolation filter as a fractional delay unit on the feedback path of the digital pre-distortion model. The filter coefficients corresponding to different fractional delays are stored in an array and indexed by the calculated fractional delay.
[0018] The second object of the present invention is to provide a fractional-level delay analysis system for a digital pre-distortion model, including the following modules:
[0019] Sampling module: used to synchronously sample the PA input and output signals of the digital pre-distortion model to obtain sampling data, and the length of the sampling points is N;
[0020] Fixed-point to floating-point conversion module: used to perform fixed-point to floating-point conversion on the sampling data and save them into arrays x[N] and y[N] respectively;
[0021] Correlation operation module: used to perform correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y);
[0022] First peak search module: used to find the maximum peak of abs(z) and record the lag corresponding to the peak as intLag;
[0023] Interpolation module: used to intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp;
[0024] Second peak search module: used to find the maximum peak of abs(zp) and record the lag corresponding to the peak as fracLag;
[0025] Delay analysis module: used to convert intLag and fracLag into integer delay intDelay and fractional delay fracDelay respectively.
[0026] Furthermore, it further includes the following modules:
[0027] Signal alignment module: used to split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically, it includes the following sub-modules:
[0028] Integer delay alignment sub-module: used to insert a serial register bank as an integer delay unit on the PA input signal path of the digital pre-distortion model. The length of the register bank depends on the size of the integer delay;
[0029] Fractional delay alignment sub-module: It is used to insert a Nyquist interpolation filter as a fractional delay unit in the feedback path of the digital pre-distortion model. The filter coefficients corresponding to different fractional delays are stored in an array and indexed by the calculated fractional delay.
[0030] The third object of the present invention is to provide a computer-readable storage medium, which includes a fractional delay analysis program of a digital pre-distortion model. When the fractional delay analysis program of the digital pre-distortion model is executed by a processor, the steps of a fractional delay analysis method of a digital pre-distortion model as described above are implemented.
[0031] The fourth object of the present invention is to provide a computer device, which includes the storage medium as described above and a processor for executing the fractional delay analysis program of the digital pre-distortion model in the storage medium.
[0032] Principle and advantages:
[0033] The present invention proposes an optimized implementation method for fractional delay estimation that first correlates and then interpolates. Briefly, first perform a correlation operation on the original signal, find the position of the maximum peak to estimate the integer delay, then intercept the segments before and after the correlation peak for R-fold interpolation, find the position of the maximum peak, and then estimate the fractional delay and correct the integer delay. This corresponds to the core steps S4, S5, and S6 of this solution.
[0034] The innovation of the present invention lies in taking into account the accuracy and general applicability of the method of interpolating first and then correlating, and at the same time having the advantage of small computational complexity of the parabola fitting method. Moreover, it not only overcomes the poor robustness of the parabola fitting method, but also solves the problem that the parabola fitting method cannot be applied to the multi-carrier communication application scenario, and reduces the computational amount and memory requirements for interpolating first and then correlating the original signal, which has high application value in engineering implementation.
[0035] In addition, in the specific engineering implementation of the present invention, signal alignment is divided into integer alignment and fractional alignment. The number of sample points to be adjusted for integer alignment depends on the integer delay value, and fractional alignment can be implemented based on a Nyquist interpolation filter. The filter coefficients for different fractional delays are pre-calculated and saved to an array, and the array is indexed by the fractional delay and the coefficients of the interpolation filter are updated, thereby achieving signal alignment. Description of the drawings
[0036] Figure 1 It is a schematic diagram of the correlation peak approximating a parabola in the prior art;
[0037] Figure 2 It is a schematic diagram of the non-uniqueness of the correlation peak of a two-carrier signal;
[0038] Figure 3 It is a flowchart of a fractional delay analysis method for a digital predistortion model according to an embodiment of the present invention;
[0039] Figure 4 It is a schematic diagram of signal alignment;
[0040] Figure 5 It is an envelope schematic diagram of two unaligned signals;
[0041] Figure 6 It is a schematic diagram of the correlation operation peak value of the original signal;
[0042] Figure 7 It is an interpolation schematic diagram of the correlation result near the peak value;
[0043] Figure 8 It is a group delay schematic diagram of a delay filter with a resolution of 1 / 64 sample;
[0044] Figure 9 It is an envelope schematic diagram of two aligned signals. Detailed implementation manners
[0045] The following is a further detailed description through specific implementation manners:
[0046] Embodiment
[0047] A fractional delay analysis method for a digital predistortion model is basically as Figure 3 shown, and includes the following steps:
[0048] S1. Synchronously sample the PA input and output signals of the digital predistortion model to obtain sampling data, and the length of the sampling points is N; in this embodiment, the length of the sampling points is N = 4096.
[0049] S2. Perform fixed-point to floating-point conversion on the sampling data and save them to arrays x[N] and y[N] respectively; as Figure 5 shown, the two signals are not aligned.
[0050] S3. Perform a correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y);
[0051] S4. Find the peak with the largest abs(z) and record the lag corresponding to the peak value as intLag; as Figure 6 shown, the lag corresponding to the correlation peak is lag = 4103.
[0052] S5. Intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp; where intLag = 4103, M = 32, and R = 16.
[0053] S6. Locate the peak with the largest abs(zp) and record the lag corresponding to the peak value as fracLag, as shown in Figure 7 as follows.
[0054] S7. Convert intLag and fracLag to integer delay intDelay and fractional delay fracDelay respectively.
[0055] intDelay = 7, fracDelay = 8 / 16. In some examples, the resolution of fractional delay estimation is 1 / 64. Software such as Matlab can be used to design the corresponding interpolation filter, as shown in Figure 8 as follows. The group delay of 64 sets of fractional interpolation filters is noted. Note that FIR Taps = 17, and the delay introduced by the filter is (Taps - 1) / 2 = 8. Apply the calculated integer delay and fractional delay to the signal synchronization circuit. The envelopes of the two signals are shown in Figure 9 as follows.
[0056] In some examples, the loop delay range can be roughly estimated according to the hardware environment such as the transmission channel path and the length of the RF cable. Therefore, the relevant peak search range can be pre - reduced to a reasonable range. In step S3, only the correlation results corresponding to the lags within this small range need to be calculated, which reduces the search range for the largest peak in step S4, and significantly reduces the computational amount and memory overhead.
[0057] If the method of interpolation first and then correlation is adopted and the resolution requirement of fractional delay estimation is 1 / 64, one of the signals needs to be interpolated 64 times, and the memory consumption of the correlation result after interpolation will also increase. Since the search range for the maximum value is reduced, the corresponding search computational amount will also be significantly reduced, as shown in Table 1.
[0058] Table 1
[0059] Variable name Interpolation first then correlation method Correlation first then interpolation method x(P A In) 4k x 64 = 256k 4k y(P A Out) 4k 4k <![CDATA[C xy = xcorr(x,y)]]> 256k + 4k = 260k 4k + 4k = 8k
[0060] S8. Split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically including the following sub - steps:
[0061] S801. Insert a serial register bank (including several integer delay registers) as an integer delay unit on the PA input signal path of the digital predistortion model. The integer delay intDelay is input to the integer delay unit. The length of the register bank depends on the size of the integer delay; the length of the register bank also represents the number of serial registers. For a simple example: x is the input signal, y is the output, n is the integer - multiple delay, and y(i) = x(i + n) means that the input signal is delayed by n samples and then output, which requires n registers in series. That is, the length of the register bank depends on the size of the integer delay.
[0062] S802. Insert a Nyquist interpolation filter as a fractional delay unit in the feedback path of the digital predistortion model. The filter coefficients corresponding to different fractional delays are stored in an array (fractional delay filter coefficient array) and are indexed by the calculated fractional delay fracDelay. The signal alignment is as follows Figure 4 shown.
[0063] A fractional delay analysis method and system for a digital predistortion model uses the above method and includes the following modules:
[0064] Sampling module: Used to synchronously sample the PA input and output signals of the digital predistortion model to obtain sampling data, and the sampling point length is N;
[0065] Fixed-point to floating-point conversion module: Used to perform fixed-point to floating-point conversion on the sampling data and store them in arrays x[N] and y[N] respectively;
[0066] Correlation operation module: Used to perform a correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y);
[0067] First peak search module: Used to search for the maximum peak of abs(z) and record the lag corresponding to the peak as intLag;
[0068] Interpolation module: Used to intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp;
[0069] Second peak search module: Used to search for the maximum peak of abs(zp) and record the lag corresponding to the peak as fracLag;
[0070] Delay analysis module: Used to convert intLag and fracLag into integer delay intDelay and fractional delay fracDelay respectively.
[0071] Signal alignment module: Used to split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically includes the following sub-modules:
[0072] Integer delay alignment sub-module: Used to insert a serial register group as an integer delay unit in the PA input signal path of the digital predistortion model, and the length of the register group depends on the size of the integer delay;
[0073] Fractional delay alignment sub-module: Used to insert a Nyquist interpolation filter as a fractional delay unit in the feedback path of the digital predistortion model. The filter coefficients corresponding to different fractional delays are stored in an array and are indexed by the calculated fractional delay.
[0074] A computer-readable storage medium includes a fractional delay analysis program for a digital predistortion model. When the fractional delay analysis program for the digital predistortion model is executed by a processor, the steps of a fractional delay analysis method for a digital predistortion model as described above are implemented.
[0075] Those of ordinary skill in the art can understand that all or part of the process of implementing the above-mentioned fractional delay analysis method for a digital predistortion model can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of various embodiments of the above-mentioned fractional delay analysis method for a digital predistortion model. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.
[0076] A computer device includes the above-mentioned storage medium and a processor. The processor is used to execute the fractional delay analysis program in the storage medium. The computer device can be implemented as various types of devices, such as a personal computer (PC), a server device, a mobile device, etc. The processor controls all functions of the electronic device by executing the program stored in the storage medium of the electronic device.
[0077] The above are only embodiments of the present invention. Specific structures and characteristics that are well-known in the art are not described in detail here. Those of ordinary skill in the art know all the common general technical knowledge in the technical field to which the invention pertains before the filing date or the priority date, can learn all the prior art in this field, and have the ability to apply conventional experimental means before this date. Those of ordinary skill in the art can, under the inspiration given in this application, complete and implement this solution in combination with their own abilities. Some typical well-known structures or well-known methods should not be an obstacle for those of ordinary skill in the art to implement this application. It should be noted that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, and these should also be regarded as the protection scope of the present invention, and these will not affect the implementation effect of the present invention and the practicality of the patent. The protection scope required by this application should be based on the content of its claims, and the specific implementation manners and the like described in the specification can be used to interpret the content of the claims.
Claims
1. A fractional delay analysis method for a digital predistortion model, characterized in that, It includes the following steps: S1. Synchronously sample the PA input and output signals of the digital predistortion model to obtain sampling data, and the length of the sampling points is N; S2. Perform fixed-point to floating-point conversion on the sampling data and save them into arrays x[N] and y[N] respectively; S3. Perform a correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y); S4. Find the maximum peak of abs(z) and record the lag corresponding to the peak as intLag; S5. Intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp; S6. Find the maximum peak of abs(zp) and record the lag corresponding to the peak as fracLag; S7. Convert intLag and fracLag into integer delay intDelay and fractional delay fracDelay respectively.
2. The fractional delay analysis method of a digital predistortion model according to claim 1, wherein: It also includes the following steps: S8. Split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically, it includes the following sub-steps: S801. Insert a serial register bank as an integer delay unit on the PA input signal path of the digital predistortion model, and the length of the register bank depends on the size of the integer delay; S802. Insert a Nyquist interpolation filter as a fractional delay unit on the feedback path of the digital predistortion model. The filter coefficients corresponding to different fractional delays are saved in an array and indexed by the calculated fractional delay.
3. A fractional delay analysis method and system for a digital pre-distortion model, characterized in that: It includes the following modules: Sampling module: used to synchronously sample the PA input and output signals of the digital predistortion model to obtain sampling data, and the length of the sampling points is N; Fixed-point to floating-point conversion module: used to perform fixed-point to floating-point conversion on the sampling data and save them into arrays x[N] and y[N] respectively; Correlation operation module: used to perform a correlation operation on the original signals x[N] and y[N] to obtain z = xcorr(x, y); First peak search module: used to find the maximum peak of abs(z) and record the lag corresponding to the peak as intLag; Interpolation module: used to intercept the result segment z(intLag - M, intLag + M) of the correlation operation and perform R-fold interpolation to obtain zp; Second peak search module: used to find the maximum peak of abs(zp) and record the lag corresponding to the peak as fracLag; Delay analysis module: used to convert intLag and fracLag into integer delay intDelay and fractional delay fracDelay respectively.
4. The fractional delay analysis system of a digital predistortion model according to claim 3, wherein: It also includes the following modules: Signal alignment module: used to split the signal alignment into two parts: integer delay adjustment and fractional delay adjustment; specifically, it includes the following sub-modules: Integer delay alignment sub-module: used to insert a serial register bank as an integer delay unit on the PA input signal path of the digital predistortion model, and the length of the register bank depends on the size of the integer delay; Fractional delay alignment sub-module: used to insert a Nyquist interpolation filter as a fractional delay unit on the feedback path of the digital predistortion model. The filter coefficients corresponding to different fractional delays are saved in an array and indexed by the calculated fractional delay.
5. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a fractional delay analysis program for a digital pre-distortion model. When the fractional delay analysis program for the digital pre-distortion model is executed by a processor, the steps of a method for analyzing the fractional delay of a digital pre-distortion model as described in claim 1 or 2 are implemented.
6. A computer device, characterized in that: The computer device includes the storage medium as described in claim 5, and a processor configured to execute the fractional delay analysis program for the digital pre-distortion model in the storage medium.