Switch cross-device link aggregation method supporting load balancing
By determining the master and standby status and synchronous address table in the switch system, the cross-device link aggregation problem under the dual-chip FPGA switching architecture is solved, the system reliability and communication efficiency are improved, and load balancing is achieved.
Patent Information
- Application Number
- CN202510531689.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-07-18
AI Technical Summary
Under the dual-chip FPGA switching architecture, there is a lack of effective cross-device link aggregation method, which causes the switch system to fail to operate normally in the event of a failure, affecting network stability and reliability.
By determining the main and standby status of the switch, establishing a communication link, and configuring member ports for isolation, synchronizing the FPGA address table inside the switch and the address table of the external switch, cross-device link aggregation is realized.
Link aggregation is realized under the dual FPGA architecture, improving the reliability and communication efficiency of the switch system, preventing overloading of a single channel aggregation port, and achieving load balancing.
Smart Images
Figure CN120342944A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of communication technology, and in particular relates to a switch cross-device link aggregation method supporting load balancing. Background Art
[0002] With the rapid evolution of communication technology, satellite Internet has become an indispensable supplement to ground communication systems with its significant advantages such as wide coverage, flexible networking, and rapid response, and conforms to the development trend of 6G mobile communications, which integrates the earth and the sky, interconnects everything, and intelligent perception. Aerospace systems usually operate in high-risk environments, and any failure may lead to serious consequences. As a key node in the satellite Internet system, once the core switch in the onboard networking fails, the entire network or part of the network will not operate normally. Therefore, for the key equipment in these network nodes, redundant design is required to provide backup components or systems to ensure that when the main equipment fails, the backup equipment can take over, thereby maintaining the normal operation of the system.
[0003] To ensure stable operation in the harsh space environment, onboard switching equipment must use space-grade Field-Programmable Gate Array (FPGA) devices. However, the storage resources of space-grade FPGA chips are limited. If redundant backup resources are reserved for key modules, the capacity of onboard switching equipment built with a single FPGA will be greatly limited. For this reason, using two FPGAs to jointly share resource overhead has become an effective solution. By collaboratively implementing the functions of the onboard switch on two FPGAs, the number of ports can be expanded and the switching capacity can be increased.
[0004] MultiChassis Link Aggregation Group (MC-LAG) is a cross-device link aggregation mechanism. By negotiating link aggregation between two switches and the connected device, the two switches at the other end are virtualized into one switch from the perspective of the connected device, thereby improving reliability from the link level to the device level. How to implement a cross-device link aggregation system and method for space-grade reliability switches under a dual-chip FPGA switching architecture has become a key problem that needs to be solved in the current technical field. Summary of the invention
[0005] The embodiment of the present invention provides a switch cross-device link aggregation method supporting load balancing, which can solve the problem of the current lack of a method for cross-device link aggregation in a dual-chip FPGA switching architecture.
[0006] In a first aspect, an embodiment of the present invention provides a method for cross-device link aggregation of a switch supporting load balancing, the method comprising:
[0007] Determine the primary and standby status of the switch, and establish a communication link between the switch and other switches;
[0008] Configure member ports according to the primary and standby status of the switch, and perform port isolation on the member ports connected to the standby cross-device aggregation ports. The member devices include multiple cross-device aggregation ports, which are respectively mounted on different switches in the system, and the standby cross-device aggregation ports are mounted on the standby switch;
[0009] Synchronize the address tables of two FPGAs inside the switch through the cross-chip channel, and through the channel aggregation end.
[0010] In a second aspect, an embodiment of the present invention provides a switch with a dual-FPGA architecture, including a CPU and two FPGAs; the CPU is used for:
[0011] Determine the primary and standby status of the switch, and establish a communication link between the switch and other switches;
[0012] Configure member ports according to the primary and standby status of the switch, and perform port isolation on the member ports connected to the standby cross-device aggregation ports. The member devices include multiple cross-device aggregation ports, which are respectively mounted on different switches in the system, and the standby cross-device aggregation ports are mounted on the standby switch;
[0013] Synchronize the address tables of two FPGAs inside the switch through the cross-chip channel, and synchronize the address tables with other switches through the channel aggregation ports to complete the link aggregation operation.
[0014] In a third aspect, an embodiment of the present invention provides a link aggregation system, which includes multiple switches as described in the second aspect, and the switches are used to execute the method described in the first aspect.
[0015] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The present invention can realize the synchronization of the address tables of two FPGAs inside the switch through the cross-chip aggregation channel, and can realize the synchronization of the address tables between different switches through the channel aggregation ports; in addition, through operations such as clarifying the primary and standby status, establishing a communication link, and configuring cross-device aggregation ports, the present invention can complete the link aggregation operation on a switch with a dual-FPGA architecture. Description of the Drawings
[0016] Figure 1 It is a schematic diagram of the communication link of a link aggregation system provided by an embodiment of the present invention;
[0017] Figure 2 It is a schematic diagram of the structure of a switch with a dual-FPGA architecture provided by an embodiment of the present invention;
[0018] Figure 3 It is a flowchart of the implementation of a method for cross-device link aggregation in a switch supporting load balancing. Specific implementation manners
[0019] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures and technologies are presented to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.
[0020] It should be understood that when used in the specification and claims of the present invention, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.
[0021] It should also be understood that the term "and / or" as used in the specification and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0022] As used in the specification and claims of the present invention, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detecting [the described condition or event]" can be interpreted as meaning "once determined", "in response to determining", "once detecting [the described condition or event]", or "in response to detecting [the described condition or event]" depending on the context.
[0023] In addition, in the description of the specification and claims of the present invention, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.
[0024] References to "one embodiment" or "some embodiments" in the description of the present invention mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of the present invention. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc., which appear at different places in this specification, do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants mean "including but not limited to", unless otherwise specifically emphasized.
[0025] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.
[0026] Embodiment 1
[0027] Figure 1 The figure shows a schematic diagram of a communication link of a link aggregation system provided by an embodiment of the present invention.
[0028] As an example, refer to Figure 1 , the system may include multiple switches, and each switch can be connected to multiple member devices. Among them, Network Device 1 is a sending member, which sends information to be received to the switches in the system, and the MC-LAG member device is a receiving member, which receives the information to be received forwarded by the switch. The switches in the system are further divided into a primary switch and a standby switch. Refer to Figure 1 the brown-red sending path in Figure 1 . When the communication link between the primary switch and the receiving member is normal, the primary switch can directly forward the information to be forwarded to the receiving member. Refer to
[0029] Embodiment 2
[0030] Figure 2 The figure shows a schematic diagram of the structure of a switch with a dual-FPGA architecture provided by an embodiment of the present invention. As an example but not a limitation, refer to Figure 2 , the switch 200 may include a CPU 210, and two FPGAs 221 and 222.
[0031] Specifically, the CPU 210 is used to: determine the primary / standby status of the switch, and establish a communication link between the switch and other switches; configure member ports according to the primary / standby status of the switch, and perform port isolation on the member ports connected to the standby cross-device aggregated ports. Synchronize the address tables of the two FPGAs 221 and 222 inside the switch through the cross-chip channel, and synchronize the address tables with other switches through the channel aggregation ports.
[0032] In a possible implementation, a cross-chip channel (see the cross-chip aurora channel in Figure 2 ) is also provided between the two FPGAs. Each FPGA is provided with a PCIE interface for communicating with the CPU 210, a channel aggregation port for communicating with other switches (see the peerlink port in Figure 2 ), member ports for communicating with member devices, and ordinary ports for communicating with ordinary devices.
[0033] For example, the LACP packets received by the switch from the channel aggregation port on the FPGA can be reported to the CPU through the capture channel inserted by the CPU of the FPGA. The FPGA 221 / 222 can also transmit the LACP packets received by the channel aggregation port to the other FPGA 222 / 221 through the cross-chip channel.
[0034] In an example, the FPGA 221 / 222 may include an address table management module, a port configuration module, and a CPU insertion capture channel.
[0035] The address table management module can be used to update and maintain the layer-2 address tables inside the FPGA 221 / 222. The CPU 210 can read and write the address table entries inside this module through the PCIE interface, and configure the current port to enable / disable address self-learning.
[0036] The port configuration module can parse the configuration information sent by the CPU 210, and configure the port status according to the configuration information. For example, configure the status of the channel aggregation port, member ports, and ordinary ports. The port configuration module can also configure port isolation for each port to prevent network topologies from forming loops; detect the status of the port and send the port status information to the CPU 210.
[0037] The CPU insertion capture module can be used to report LACP packets from the channel aggregation port, and at the same time insert and forward the LACP packets sent by the CPU 210.
[0038] For example, the CPU can send an LACP packet, and the CPU insertion capture module captures the packet, thereby causing the port configuration module to perform port configuration and port isolation operations, and the address table management module to perform address table synchronization operations.
[0039] Embodiment 3
[0040] Figure 3 The figure shows a flowchart of the implementation of a method for cross-device link aggregation of a switch supporting load balancing. By way of example and not limitation, this method can be applied to the switch with a dual-FPGA architecture provided in the above Embodiment 2. This method may include steps S301-S305, and each step will be described below.
[0041] S301. Determine the primary and standby status of each switch.
[0042] In a possible implementation, the switch can first determine its own primary and standby status, and then configure its channel aggregation ports with other switches to complete the initialization of MC-LAG.
[0043] In an example, the switch can compare its own IPv4 address with that of other switches. If its own IPv4 address is the largest, it determines itself as the primary switch; otherwise, it determines itself as the standby switch.
[0044] Optionally, if the switch is a standby switch, it also needs to modify its MAC address to the MAC address of the primary switch during the initialization of MC-LAG.
[0045] In an example, the switch can select one on each of the two internal FPGAs as the channel aggregation port (see the peerlink port in Figure 2 ) to complete the configuration of the channel aggregation port.
[0046] Exemplarily, when the switch selects the channel aggregation port, it can also turn off the address learning function of the channel aggregation port and perform port isolation operations on the channel aggregation port to prohibit the member ports from broadcasting services to the channel aggregation port to prevent topological loops in the network.
[0047] S302. Establish a communication link between the switch and other switches.
[0048] In an example, the switch can establish a communication link with other switches through peerlink.
[0049] Exemplarily, the switch and other switches can establish a connection relationship based on the Inter-Control Center Communications Protocol (ICCP) protocol using TCP, and then send heartbeat messages to other switches at fixed intervals. If no heartbeat message sent by the other party is received after a certain period of time, it is considered that peerlink is disconnected.
[0050] S303. Configure member ports based on the primary / backup status of the switch, and perform port isolation on the member ports connected to the backup cross-device aggregated port.
[0051] Exemplarily, the switch can select some ports from the ports of two FPGAs as member ports, and the rest as ordinary ports to complete the port configuration. The connection and communication between the switch and the member devices are realized through the member ports on the switch and the cross-device aggregated ports on the member devices.
[0052] Exemplarily, each member device in the link aggregation system can include multiple cross-device aggregated ports, and these ports are respectively connected to different switches and mounted on different switches.
[0053] In one example, the switch can first send its primary / backup status to the member device. The member device can regard the ports mounted on the primary switch as primary ports, and the ports mounted on the backup switch as backup ports, and perform port isolation on the backup ports.
[0054] For example, only the traffic (i.e., the information to be forwarded) received from the primary port of the member device will be forwarded by the switch. If the switch is a backup switch, it may receive tasks from the backup port of the member device, and the switch will prohibit the tasks received from the backup port from being forwarded by the switch to prevent multiple identical packets from appearing in the network.
[0055] Optionally, the primary / backup relationship of the cross-device aggregated ports in the member device is not fixed. When the port link of the member device connected to the primary switch fails, the member device can change the port status of the original backup port to the primary port.
[0056] S304. Synchronize the address tables of the two FPGAs inside the switch through the cross-chip channel.
[0057] In one example, the two FPGAs inside the switch respectively maintain the address tables learned on the ports of their own chips, and can also send the address table entries learned on their own FPGAs to the other FPGA through the cross-chip channel (see the cross-chip aurora channel in Figure 3 . After that, the CPU 210 also needs to scan and compare the differences between the two address tables, unify the read identical results, and re-configure the wrong address table entries; then the synchronization of the address tables of the two FPGAs inside the switch can be completed.
[0058] S305. Synchronize the address table with other switches through the channel aggregated port.
[0059] In one example, after the switch completes the synchronization of the internal address table, it can send LACP packets to switches with different master-slave states to exchange address table information. For example, if this switch is the master switch, it sends LACP packets to the standby switch; if this switch is the standby switch, it sends LACP packets to the master switch. The switch maintains the address table information of this switch and the peer switch (i.e., the switch with a different master-slave state from itself). In this way, when a link fails between the switch and the member device, a request to modify the address table can be issued in a timely manner according to the address table entries of the two switches, and the traffic sent to the faulty link port can be transferred to the link aggregation port for forwarding in a timely manner.
[0060] Exemplarily, in addition to the address table, the switch and the peer switch can also exchange ARP entries learned by the MC-LAG member ports and MC-LAG member port status change information.
[0061] In some embodiments, after the link aggregation operation is completed through the above steps S301 - S305, if the switch is the master switch, it can also perform the data forwarding function through the following steps S306 - S309.
[0062] S306, Receive the information to be forwarded from the sending member.
[0063] Exemplarily, the sending member is one of the member devices.
[0064] S307, Determine whether the communication link between the switch and the receiving member is normal.
[0065] In one example, if the communication link between the two is normal, the switch can proceed to step S308 and directly send the information to be forwarded to the receiving member through the member port corresponding to the receiving member on it.
[0066] Exemplarily, the switch can be provided with member ports corresponding to the member devices one by one, and communicate with the cross-device aggregation ports of the corresponding member devices through these member ports.
[0067] In another example, if the communication link between the two is abnormal, such as a communication link failure, step S309 can be performed at this time. First, send the information to be forwarded to another standby switch through the link aggregation port of the switch, and let the standby switch send the information to be forwarded to the receiving member.
[0068] Exemplarily, the receiving member is also one of the member devices.
[0069] S308, Send the information to be forwarded to the receiving member through the member port corresponding to the receiving member on the switch.
[0070] S309. Send the information to be forwarded to another standby switch through the link aggregation port of the switch, so that the other standby switch sends the information to be forwarded to the receiving member.
[0071] In one example, when the communication links between the switch and multiple member devices are all disconnected, a large amount of traffic may gather on the same link aggregation port in the switch. If it exceeds the preset load threshold of the port, the switch can evenly disperse the different information to be forwarded of the receiving members to two link aggregation ports inside it by configuring the address table of the faulty member port, so as to achieve load balancing.
[0072] Exemplarily, when the communication link between the primary switch and the receiving member returns to normal, the primary switch and the peer switch can update the status of the MC-LAG member ports under their own devices through the peerlink, and at the same time modify the address table entries and port isolation status of the MC-LAG member devices in the switch respectively. Refer to Figure 1 , at this time, the data sending path can be restored from "Network Device 1 (sending member) → primary switch → standby switch → MC-LAG member port (receiving member)" to "Network Device 1 → primary switch → MC-LAG member".
[0073] Exemplarily, when the peerlink link between the primary switch and the standby switch is disconnected, the standby switch can modify its own MAC address to its original MAC address. When the MC-LAG member device finds that the MAC addresses for interacting with multiple switches are inconsistent, it can no longer perform the aggregation operation and can only select one port for successful negotiation. At this time, the cross-device link aggregation port of the member device will only maintain normal negotiation with the primary switch, and its traffic reception and transmission will only be forwarded through the primary switch.
[0074] In some other embodiments, if the switch is a standby switch and the communication link between the primary switch and the receiving member is abnormal, it can also perform the data forwarding function through the following step S309.
[0075] S309. Receive the information to be forwarded from the primary switch and send it to the receiving member.
[0076] Exemplarily, if the switch is a standby switch, it can receive the information to be forwarded from the primary switch and send the information to be forwarded to the receiving member through the member port corresponding to the receiving member on the switch.
[0077] The present invention can achieve the synchronization of the address tables of two FPGAs inside the switch through the cross-chip aggregation channel, and can achieve the synchronization of the address tables between different switches through the channel aggregation port; in addition, through operations such as clarifying the master-slave status, establishing a communication link, and configuring the cross-device aggregation port, the present invention can complete the link aggregation operation on the switch with a dual-FPGA architecture. Further, by evenly dispersing the information to be forwarded on different channel aggregation ports to achieve load balancing, it can prevent the situation where a single channel aggregation port bears too much traffic when there are failures in the links between a large number of switches and a large number of member devices, and can improve the communication efficiency.
[0078] The embodiment of the present invention also provides a link aggregation system. The system may include a plurality of switches as provided in the above embodiment 2, and these switches may execute the method provided in embodiment 3.
[0079] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.
[0080] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
Claims
1. A method for cross-device link aggregation of a switch supporting load balancing, characterized in that, The method is applied to a switch with a dual-FPGA architecture in a link aggregation system. The method includes: Determine the primary / backup status of the switch and establish a communication link between the switch and other switches; Configure member ports according to the primary / backup status of the switch, and isolate the member ports connected to the standby cross-device aggregation ports. Herein, the member devices include multiple cross-device aggregation ports, which are respectively mounted on different switches in the system, and the standby cross-device aggregation ports are mounted on the standby switch; Synchronize the address tables of the two FPGAs inside the switch through the cross-chip channel, and synchronize the address tables with other switches through the channel aggregation ports to complete the link aggregation operation.
2. The method according to claim 1, characterized in that, The determining of the primary / backup status of the switch includes: Compare the IPv4 addresses of the switch and other switches; Take the switch with the largest IPv4 address as the primary switch, and the remaining switches as standby switches.
3. The method according to claim 1, wherein When the switch is the primary switch, the method further includes: Receive the information to be forwarded from the sending member; Determine whether the communication link between the switch and the receiving member is normal. Herein, the sending member and the receiving member are both one of the member devices; If the communication link is normal, send the information to be forwarded to the receiving member through the member port corresponding to the receiving member on the switch. Herein, the member ports correspond one-to-one with the member devices, and the switch communicates with the member devices corresponding to the member ports through the member ports; If the communication link is not normal, send the information to be forwarded to another standby switch through the channel aggregation port of the switch, so that the another standby switch sends the information to be forwarded to the receiving member.
4. The method according to claim 3, wherein Before establishing the communication link between the switch and other switches, the method further includes: Select one port from each of the two FPGAs inside the switch as the channel aggregation port to complete the configuration of the channel aggregation port.
5. The method according to claim 4, wherein The sending of the information to be forwarded to another standby switch through the channel aggregation port of the switch includes: Determine whether the load of each channel aggregation port on the switch is greater than a preset load threshold; If the load of any channel aggregation port is greater than the preset load threshold, evenly disperse the different information to be forwarded of the receiving member to the channel aggregation ports.
6. The method according to claim 1, wherein The synchronizing of the address tables of the two FPGAs inside the switch through the cross-chip channel includes: Exchange the address tables of the two FPGAs inside the switch through the cross-chip channel; Scan and compare the differences between each address table, unify the same results and reconfigure the different results to complete the synchronization of the address tables of the two FPGAs inside the switch.
7. A switch with a dual FPGA architecture, characterized in that, It includes a CPU and two FPGAs; the CPU is used for: Determine the primary / backup status of the switch and establish a communication link between the switch and other switches; Configure member ports according to the master / backup status of the switch, and isolate the member ports connected to the standby cross-device aggregation port, where the member devices include multiple cross-device aggregation ports, which are respectively mounted on different switches in the link aggregation system, and the standby cross-device aggregation port is mounted on the standby switch; Synchronize the address tables of two FPGAs inside the switch through the cross-chip channel, and synchronize the address tables with other switches through the channel aggregation port to complete the link aggregation operation.
8. The switch according to claim 7, characterized in that, The FPGA includes: A CPU insertion capture module, which is used to report packets from the channel aggregation port to the CPU, and insert and forward the packets sent by the CPU; A port configuration module, which is used to configure the port status according to the configuration information; An address table management module, which is used to update and maintain the address table inside the FPGA.
9. The switch according to claim 7, characterized in that, The interfaces on the FPGA include: the channel aggregation port, the PCIE interface, and the member port; The FPGA communicates with other switches through the channel aggregation port, communicates with the CPU through the PCIE interface, and communicates with the member devices through the member port.
10. A link aggregation system, characterized in that, The system includes multiple switches as described in any one of claims 7-9, and the switches are used to execute the method as described in any one of claims 1-6.