ZYNQ-based energy router controller and control method thereof

Abstract

The invention relates to the technical field of routing communication, in particular to a ZYNQ-based energy router controller and a control method thereof. The controller comprises a PL side module and a PS side module, wherein the PL side module comprises an ADC module, a PWM module, a DAC module, a PCI Express2.0 module, an SFP + module, a Memory Interface Generator module and an AXI-DMA module; and the PS side module is used for establishing a self-defined and customized Linux kernel. The controller realizes compatibility between different platforms and different series through modular design. And meanwhile, through time sequence design optimization, CLB and BRAM resources occupied by the design are reduced, so that different series of FPGAs can carry the software architecture of the controller.

Description

Technical Field

[0001] The present invention relates to the technical field of routing communication, and particularly relates to an energy router controller based on ZYNQ and a control method thereof. Background Art

[0002] The statements in this part merely provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] With the development of the power grid structure, the distribution network has evolved from the traditional distribution network architecture to a microgrid and finally to an integrated energy system. The energy carrier has changed from traditional electric energy to the coexistence of primary and secondary energies such as electricity, heat, and gas. At the same time, the change in the distribution network architecture also poses higher requirements for the design of the controller. The energy router has a wide control range, and the algorithm is more complex and large compared to a single converter. At the same time, real-time control communication is required between controllers at different levels and functions in the energy router. This poses extremely high requirements for the operating main frequency and computing power of the controller. In traditional microgrid and energy router control, the main control chip often uses DSP (Digital Signal Processor). Compared with FPGA (Field-Programmable Gate Array), DSP has a lower development difficulty because it integrates key peripherals such as ADC (Analog-to-Digital Converter) and PWM (Pulse-width modulator) internally. Since it is still a traditional CPU, the control of peripherals mainly relies on reading and writing registers.

[0004] However, the traditional DSP architecture can only achieve software programmability and does not have hardware programmability. The number of peripherals is fixed and user-defined cannot be achieved. Moreover, due to different pre-developed hardware driver libraries among manufacturers, the software code is not compatible between different manufacturers and different series of main control chips of the same manufacturer. The highly abstract hardware driver library, although solving the compatibility problem between different series, has particularly prominent problems such as poor code execution efficiency and incompatibility between manufacturers.

[0005] With the development of the distribution network, the main controller architecture has evolved into a heterogeneous architecture of FPGA + DSP, which combines serial processing capabilities and parallel processing capabilities. The DSP runs custom software, and the FPGA runs custom hardware. Inter-chip communication relies on specific protocols to complete. However, although the software and hardware of the FPGA + DSP heterogeneous architecture are programmable, there is no mature and universal industry standard for inter-chip communication, which depends on users to develop by themselves, greatly limiting the processing capacity of the control system. At the same time, inter-chip communication occupies a large amount of data I / O, which also limits the hardware scalability of the controller. Moreover, compared with the DSP, the FPGA has greater development difficulty, a longer development cycle, and higher hardware costs, with higher requirements for developers, which also restricts the application and promotion of this controller architecture.

[0006] Based on the above architecture defects, existing methods attempt to introduce control platforms such as ZYNQ into the controller design to improve control performance. However, the controller based on ZYNQ has problems such as a long development cycle and great pre-development difficulty. Therefore, there is currently a lack of an energy router controller with high compatibility, strong applicability, and high efficiency. Summary of the Invention

[0007] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide an energy router controller based on ZYNQ and its control method. Through modular design, the controller realizes compatibility between different platforms and different series. At the same time, through the optimization of timing design, the CLB and BRAM resources occupied by the design are reduced, so that the software architecture of this controller can be carried by FPGAs of different series.

[0008] To achieve the above purpose, the present invention is realized through the following technical solutions:

[0009] The first aspect of the present invention provides an energy router controller based on ZYNQ (Zynq-7000 All Programmable SoC), which includes a PL-side module and a PS-side module. The PL-side module includes an ADC module, a PWM module, a DAC module, a PCI Express2.0-RC (Root Complex) module, an SFP+ module, a Memory Interface Generator module, and an AXI-DMA module.

[0010] Among them, the ADC module and the DAC module are used for data reading and conversion. The PCI Express2.0 module and the SFP+ module are used for communication between networked controllers. The PWM module is used for PWM modulation. The Memory Interface Generator module is used to realize the control of the system running memory. The AXI-DMA module is used to process the interaction of a large amount of data.

[0011] The ADC module designs an interface form based on the data bus, enabling the automatic control of the number of AD7616 chips during development according to the generated Linux kernel code; the PWM module can automatically complete output channel pairing and the trigger action modes (set high, set low, flip) within the channel according to the generated Linux kernel code.

[0012] The PS-side module builds a customized Linux kernel. Among them, the number and parameters of the ADC, PWM, and DAC modules are configured according to user requirements, and the corresponding Linux kernel and startup file are generated after configuration. Specifically, the user inputs the corresponding requirements, including the channel types (analog input, analog output, digital input, digital output) and the corresponding quantities. Then the program judges the corresponding module quantities and the number of IO occupations, and then completes the configuration of the number of ADC modules, the range setting of the ADC module, the channel number of the ADC module, the PWM channel pairing, and the action mode setting. Then, based on the comprehensive configuration data, the corresponding Linux kernel and startup file are generated.

[0013] Furthermore, the PL-side interfaces are all AXI-Lite and AXI-Stream interfaces based on the AMBA architecture.

[0014] Furthermore, the DAC module is used for communication between ZYNQ and an external DAC chip, adopts the SPI protocol, provides two DAC interfaces, and uses a daisy-chain loopback between multiple DAC chips.

[0015] Furthermore, the AXI_Innerconnect module is used to control the AXI-Lite bus and simultaneously complete register address mapping. It realizes the time-division multiplexing of the bus by controlling the AXI bus control right; and completes the address mapping of the PL-side registers through the internal base address register (BaseAddress Register).

[0016] Furthermore, the PS side builds a customized Linux kernel through Peta-Linux.

[0017] Furthermore, it also includes several clock modules and reset modules, which are used to generate the clock signals and reset signals required by each module respectively.

[0018] The second aspect of the present invention provides a control method for an energy router controller based on the ZYNQ-based one described in the first aspect, including the following steps:

[0019] First, the ZYNQ chip controls the external ADC chip to start conversion. After the ADC chip completes the conversion, the conversion result register in the external ADC chip (AD7616 / AD7606) is read through a 16-bit data bus and transferred to the data buffer FIFO in the PL-side ADC module in the order of channel numbers. The PS controls the AXI-Lite bus to read the specified data buffer FIFO through the read channel number, converts it into the actual value through a transfer function, and then sends it to the relevant closed-loop control algorithm; the control algorithm combines the reference value and the actual value and then outputs a control signal; the control signal is output to other co-controllers in the form of an analog quantity through the DAC module, or is directly output to the power stage in the form of a PWM modulation wave after being carrier-modulated by the PWM module to control the switching of power devices.

[0020] The execution process of the closed-loop transfer function is as follows: The conversion result is read through the ADC module. The conversion result is a signed 16-bit integer data, that is, from -32,768 to 32,767. It corresponds to the negative full scale to the positive full scale, and the corresponding relationship is linear. Dividing the 16-bit integer data by 32768 can obtain the actual input analog voltage. The range is set when generating the Linux kernel.

[0021] Furthermore, the communication between network controllers is completed through the PCI Express 2.0 module and the SFP+ module.

[0022] The third aspect of the present invention provides a medium, on which a program is stored, and when the program is executed by a processor, it implements the steps in the control method of the ZYNQ-based energy router controller as described in the second aspect of the present invention.

[0023] The fourth aspect of the present invention provides a device, including a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the control method of the ZYNQ-based energy router controller as described in the second aspect of the present invention.

[0024] The fifth aspect of the present invention provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps in the control method of the ZYNQ-based energy router controller as described in the second aspect of the present invention.

[0025] The above one or more technical solutions have the following beneficial effects:

[0026] The present invention discloses an energy router controller based on ZYNQ and its control method. Since each module is designed independently, each module can be reused, edited, and deleted, realizing user-defined at the hardware layer; the PS side realizes user-defined at the software layer. With the standardization of interfaces, the compatibility and applicability of the software architecture are greatly improved. At the same time, with the on-chip AXI protocol interconnection, it ensures high-bandwidth and low-latency interconnection between the PS and the PL. The dual ARM cores are integrated with the PL, adopting the AMP architecture, combining the high interactivity and command-line instructions of Linux, as well as the high real-time and determinacy of the bare metal, improving the processing ability and human-computer interaction performance of the controller. Due to the highly user-defined functions of software and hardware, the software architecture is suitable for the design of controller software in various scenarios. The extremely high applicability makes the software architecture applicable to most application scenarios, greatly simplifying the development difficulty of ZYNQ, enabling developers to focus on the design and operation of control algorithms.

[0027] Advantages of additional aspects of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The specification drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0029] Figure 1 It is the overall architecture diagram of the controller in Embodiment 1 of the present invention;

[0030] Figure 2 It is the architecture diagram of the PL side of the controller in Embodiment 1 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof;

[0033] Embodiment 1:

[0034] Embodiment 1 of the present invention provides an energy router controller based on ZYNQ, as Figure 1 shown, which includes a PL-side module and a PS-side module. The PS side and the PL side are connected through an AXI-Lite interface and an AXI-Stream interface.

[0035] As Figure 2 shown, the PL (Programmable Logic) side module includes an ADC module (AD7616 / AD7606), a PWM module, a DAC module (AD5754 / AD5676), a serial port module (UART16550), a PCI Express2.0-RC (Root Complex) module, an SFP+ module, a Memory Interface Generator module, a CDMA module, an AXI_Innerconnect module, and several clock modules and reset modules;

[0036] The interfaces of the PL-side module are all AXI-Lite and AXI-Stream interfaces based on the AMBA (Advanced Microcontroller Bus Architecture) architecture, adopting an interface standard with a wide application range and a high occupancy rate to expand the practicality of the software architecture. Register reading and writing are completed by the AXI-Lite interface, and a large amount of data interaction is completed by the AXI-Stream interface.

[0037] The AXI_Innerconnect module is used to control the AXI-Lite interface between the PS and the PL, and at the same time complete the register address mapping. The time-sharing multiplexing of the interface is realized by controlling the control right of the AXI interface; the address mapping of the PL-side registers is completed through the internal base address register (BaseAddress Register). The modules inside the PL side realize the time-sharing multiplexing of the AXI interface and the PS-PL interconnection through the AXI_Innerconnect module.

[0038] The ADC module realizes the control function of the ZYNQ chip for the external ADC chip. To save I / O and increase the bandwidth at the same time, a 16-bit parallel port is used as the data bus, and the time-sharing multiplexing of the data bus is realized through the nCS and nRD signals. Up to 6 ADCs can be mounted, and the setting of the ADC mounting quantity is realized by reading and writing the Module_EN bit in the IP core register.

[0039] The PWM module realizes the PWM modulation function, with a time-domain resolution of 4 ns. It can realize functions such as dead zone, output complementarity, and initial phase. The number of output channels reaches 48 or 96, and the channels can be paired, and the action mode can be set.

[0040] The DAC module realizes the control function of the ZYNQ chip for the external DAC chip. It adopts the SPI protocol, provides two DAC interfaces, and uses a daisy-chain loopback between multiple DAC chips.

[0041] The Memory Interface Generator is used to control the off-chip DDR3 SDRAM on the PL side ( Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is used as the off-chip RAM memory of the system, providing a larger operating memory for the system and serving as the data I / O buffer for PCI Express and SFP+. This module is used to generate the clock, reset signal, 32-bit address signal, 32-bit data signal, and hardware refresh signal required for the normal operation of DDR SDRAM, control the normal operation of the external DDR SDRAM, and implement the read and write functions of the ZYNQ chip for DDR SDRAM. Data input and read / write SDRAM addresses are achieved through the AXI-Stream interface. After module address mapping, the corresponding address is transferred to the 32-bit address bus and sent to the DDR SDRAM chip in parallel, and the corresponding data is exchanged through the 32-bit data bus.

[0042] The serial port module is used to realize the serial port expansion on the PL side. Serial communication on the PL side is achieved through the serial port module.

[0043] The PCI Express module is used to implement the hardware layer, link layer, and transaction layer of the PCI Express 2.0 protocol, realize packet unpacking and packing, and provide AXI-Lite and AXI-Stream interfaces for high-speed data to achieve high-speed data transceiver.

[0044] The SFP+ module realizes 10 Gigabit Ethernet based on the GTX transceiver and provides 4 SFP+ data interfaces at the same time. It consists of a UDP / IP protocol stack and a 10G Ethernet Subsystem. The UDP / IP protocol stack completes the protocol layer of 10 Gigabit Ethernet, and the 10G Ethernet Subsystem completes the physical layer and link layer of 10 Gigabit Ethernet.

[0045] In this embodiment, the above two IP cores are used to complete the protocol layer processing of the corresponding protocols, and the physical layer is implemented by the GTX transceiver. The above modules send the packed data packets to the GTX transceiver FIFO, and the GTX transceiver completes data sending and receiving. After the received data is sent to the FIFO, the PCIE module and the SFP+ module complete unpacking. At the same time, the GTX provides SFP+ and PCIE 2.0 physical layer interfaces for connecting the hardware circuit.

[0046] The CDMA module is used to process a large amount of data interaction. By specifying the source address, destination address, and data length, it realizes data transfer without the CPU, reduces the CPU burden, and completes the large-volume and high-bandwidth data interaction between DDR3 SDRAM and SFP+, PCI Express, and PS. The address configuration is realized through the AXI-Lite interface, and the data I / O is realized through the AXI-Stream interface. The CDMA provides one AXI-Lite interface to configure the source address, destination address, and data length, and provides two AXI-Stream interfaces to realize the data interaction between the source address and the destination address.

[0047] In addition to the above modules, there are several clock modules and reset modules on the PL side, which are used to generate the clock signals and reset signals required by each module respectively.

[0048] The ADC module reads the external ADC conversion value and stores it in the register to obtain the register value. The PS side reads the specified register value through the AXI-Lite interface, converts it into the actual value through the transfer function, and then sends it to the relevant closed-loop control algorithm. After combining the reference value and the actual value, the control algorithm outputs a control signal. The control signal is output to other co-controllers in the form of an analog quantity through the DAC module, or directly output to the power stage in the form of a PWM modulated wave after being carrier-modulated by the PWM module to control the switching of the power device. The relevant data is temporarily stored in the DDR SDRAM and can be read and written through MIG (Memory Interface Generator).

[0049] In a specific implementation, the communication between the networking controllers is completed through the PCI Express 2.0 module and the SFP+ module. After the SFP+ module sets the source address and destination address of the AXI-DMA module by the PS-side module, the DMA module transfers the data to the data FIFO of the SFP+ module, and the SFP module starts to transmit. The SFP module receives the data into the FIFO and transfers it to the DDR SDRAM through the DMA module. The data reading of the PCI Express 2.0 module is completed by the PCIE module and the CDMA module without the intervention of the PS side. After the PCIE unpacks the data, it performs address mapping through the BAR (Base Address Register). The mapped address is directly handed over to the CDMA module, which completes the transfer. The write request is initiated by the PS side. The address is handed over to the CDMA module and the PCIE module, and after being packetized through the BAR mapping of the PCIE, it is completed by the CDMA module for transfer. The initialization enumeration process in the PCI Express protocol runs by itself after the PCIE module is powered on to complete the enumeration, classification, and numbering of the devices mounted on the PCIE bus.

[0050] The PS-side module builds a customized Linux kernel with the General Interrupt Controller (GIC) built-in. Among them, the PS-side builds a customized Linux kernel through Peta-Linux. According to the user's needs, corresponding modules and parameters are configured, and the corresponding Linux kernel and startup files are generated after configuration. Specifically, the user inputs corresponding requirements, including channel types (AI, AO, DI, DO) and the corresponding quantities. Then the program judges the corresponding module quantities and IO occupation quantities, and then completes the configuration of the ADC module quantity, the range setting of the ADC module, the channel number of the ADC module, the PWM channel pairing, and the action mode setting. Then, based on the corresponding configuration data, the corresponding Linux kernel and startup files are generated.

[0051] The PS-side builds a customized Linux system through Peta-Linux. Core-1 runs the customized Linux system, responsible for communication and command-line processing; Core-2 runs in the Bare-Metal mode, only executing control algorithms. The two are interconnected through the shared PS-side Message DDR memory and use the Open-AMP protocol for inter-core communication. The PS and PL are interconnected through the standard AXI interface within the AMBA architecture.

[0052] In a specific implementation manner, the Linux system of this embodiment is set up in five aspects, namely, customizing for the kernel, customizing for security, customizing for drivers, customizing for the Linux system-on-chip and on-chip GIC, and customizing for the energy router control.

[0053] 1. For the kernel. The access priority of the system running memory is divided into two levels. The first level is the real-time control function within CPU2, which allocates dedicated running memory for real-time tasks and directly accesses it through the AXI-Stream interface of the Memory Interface Generator within the PL, reducing read-write latency and AXI interface occupation conflicts. At the same time, it has the access permission to the PS-side running memory; the second level is the Linux system-on-chip within CPU1, and CPU1 can only access the PS-side running memory and has no access permission to the PL-side memory.

[0054] 2. For the drivers. Real-time character device drivers for the PWM module and ADC module are designed. For module configuration, the write register latency is shortened by directly reading and writing registers by skipping Linux. For data reading, by associating the specified DMA channel within the Linux system with the device driver, the data within the module is directly transferred into the user-mode memory through DMA, reducing the system latency of reading registers one by one.

[0055] 3. Security-oriented. For the core modules of the control function, namely the PWM module, ADC module, and DAC module, CPU1 implements module security protection by monitoring system calls through the Linux system and setting driver file read and write permissions. For operations that write to the above modules, CPU1 monitors the user who initiates the operation. For users who are not the root users of the on-chip system, it is prohibited to write data to the core modules. The module driver file read and write permissions are managed by the on-chip Linux system to ensure that the read and write permissions are not tampered with.

[0056] 4. A four-level interrupt priority control strategy is proposed for Linux on-chip system and on-chip GIC. The first priority is the emergency fault interrupt on the PL side, which is generated by the limit comparison module in the ADC module. This level of interrupt is directly bound to the GIC in the PS, directly preempting all resource processing on the PS side, bypassing the interrupt scheduler of the Linux kernel, and reducing the interrupt response time as much as possible. The second priority is ordinary faults, such as the overtemperature fault of the on-chip temperature sensor. This interrupt is directly bound to the GIC, but participates in the interrupt queue. After the interrupt response in the queue is completed, it is processed by the PS. The third level is the control interrupt of the PS, which is generated by the PWM module cycle by cycle and is used to execute the converter control function. This level of interrupt is bound to the GIC, but by default enters the end of the queue and waits for all fault responses to be completed before execution. The fourth level is a Linux-based system interrupt, which is executed by the Linux system interrupt scheduler and is aimed at the data interaction interrupt of the Linux system. The implementation principle is as follows: the ADC and PWM modules are connected to the GIC in the PS through exclusive interrupt lines. When applying for an interrupt, they send a fault code to the PS side at the same time. The CPU determines the interrupt priority through a priority mapping table based on the fault code and puts it into the interrupt waiting queue in order. For control function interrupts without fault codes, GIC directly puts them at the end of the interrupt waiting queue. The CPU responds to interrupts one by one according to the interrupt waiting sequence. For non-real-time data interaction interrupts, the control is handed over to the interrupt scheduler of the Linux system, which only responds in CPU1 to avoid interference with real-time interrupts.

[0057] 5. A three - level fault protection mechanism is proposed for the control of the energy router. The first level is the PL hardware protection. By comparing the input through EMIO or the internal limit comparison module of the ADC module with the threshold value, the interrupt flag bit on the PL side is triggered, and the PWM output is directly turned off. The second level is the fault detection interrupt on the PS side. By detecting the state of the power devices, fault diagnosis is performed. The third level is the on - site protection, system recovery, and fault status upload on the PS side. Under normal operating conditions, the PS side retains the controller core state and data within 1 s. In the fault state, the PS side transfers the saved data to the external ROM through DMA and uploads it through communication methods such as Ethernet and serial port. When the PL - side ADC module detects faults such as over - current and over - voltage, the ADC module directly requests an interrupt from the PS side. The PS side preferentially activates the backup power module and clears the interrupt flag bit. If the fault still exists after the backup power module is activated, the PWM output is turned off, the system state is transferred to the external ROM, and the fault status is uploaded. If the fault disappears after the backup is activated, only the fault status is uploaded, and the PWM output is not turned off. At the same time, fault diagnosis starts to be executed. The PL - side ADC module collects the temperature of the controller chip, as well as the current stress, voltage stress, device temperature, and converter input and output waveforms of the power devices. If the temperature of a single device is abnormal, the power module conducts bidirectionally, the converter has no output (single - phase) or output phase loss (three - phase), etc., it is determined as a power device fault; if the temperature of multiple devices is over - temperature, it is determined as a thermal failure. The forced cooling is preferentially activated. If there are still multiple power modules with over - temperature after activation, the PWM output is turned off and the fault status is uploaded; if a bus fault such as over - voltage or under - voltage occurs on the DC bus is detected, the PWM output is directly turned off and the fault status is uploaded.

[0058] Since each module is independent of each other, each module can be reused, edited, and deleted to achieve user - defined at the hardware layer; the PS side realizes user - defined at the software layer. With the standardization of the interfaces, the compatibility and applicability of this software architecture are greatly improved. At the same time, with the on - chip AXI protocol interconnection, it ensures a large - bandwidth and low - latency interconnection between the PS and the PL. The dual - ARM cores are integrated with the PL and adopt the AMP architecture, combining the high interactivity and command - line instructions of Linux, as well as the high real - time performance and determinacy of the bare - metal machine, improving the processing ability and human - machine interaction performance of the controller. Due to the high degree of software and hardware user - defined functions, this software architecture is suitable for the controller software design in various scenarios. The extremely high applicability makes this software architecture suitable for most application scenarios, greatly simplifying the development difficulty of ZYNQ, enabling developers to focus on the design and operation of control algorithms.

[0059] Embodiment 2:

[0060] Embodiment 2 of the present invention provides a control method for the energy router controller based on the ZYNQ described in Embodiment 1, including the following steps:

[0061] The external ADC conversion value is read through the ADC module and stored in the register to obtain the register value. The PS side reads the specified register value through the AXI-Lite bus, converts it into the actual value through the transfer function, and then sends it to the relevant closed-loop control algorithm. After combining the reference value and the actual value, the control algorithm outputs a control signal. The control signal is output to other co-controllers in the form of an analog quantity through the DAC module, or directly output to the power stage in the form of a PWM modulated wave after being carrier-modulated by the PWM module to control the switching of the power device. The relevant data is temporarily stored in the DDR SDRAM and can be read and written through the MIG (Memory Interface Generator).

[0062] In a specific embodiment, the communication between the networking controllers is completed through the PCI Express 2.0 module and the SFP+ module. After the SFP+ module sets the source address and destination address of the AXI-DMA module by the PS side module, the DMA module transfers the data to the data FIFO of the SFP+ module, and the SFP module starts to transmit. The SFP module receives the data into the FIFO and transfers it to the DDR SDRAM through the DMA module. The data reading of the PCI Express 2.0 module is completed by the PCIE module and the CDMA module without the intervention of the PS side. After the PCIE unpacking, the address mapping is performed through the BAR (Base Address Register), and the mapped address is directly handed over to the CDMA module, which completes the transfer. The write request is initiated by the PS side, and the address is handed over to the CDMA module and the PCIE module. After being packetized through the BAR mapping of the PCIE, the CDMA module completes the transfer. The initialization enumeration process in the PCI Express protocol runs by itself after the PCIE module is powered on to complete the enumeration, classification, and numbering of the devices mounted on the PCIE bus.

[0063] Embodiment 3:

[0064] Embodiment 3 of the present invention provides a medium on which a program is stored. When the program is executed by a processor, it implements the steps in the control method of the ZYNQ-based energy router controller as described in Embodiment 2 of the present invention.

[0065] Embodiment 4:

[0066] Embodiment 4 of the present invention provides a device, including a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the control method of the ZYNQ-based energy router controller as described in Embodiment 2 of the present invention.

[0067] Embodiment 5:

[0068] Embodiment 5 of the present invention provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps in the control method of the ZYNQ-based energy router controller as described in Embodiment 2 of the present invention.

[0069] The steps involved in the devices in the above Embodiments 2, 3, 4, and 5 correspond to those in Embodiment 1, and for the specific implementation manners, reference may be made to the relevant description parts of Embodiment 1.

[0070] Those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general computer device. Optionally, they can be implemented by program codes executable by the computing device, so that they can be stored in the storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0071] Although the specific implementation manners of the present invention are described above in conjunction with the drawings, it is not a limitation on the protection scope of the present invention. Those skilled in the art should understand that based on the technical solutions of the present invention, various modifications or deformations that can be made without creative efforts by those skilled in the art are still within the protection scope of the present invention.

Claims

1. An energy router controller based on ZYNQ, characterized in that It includes a PL-side module and a PS-side module. The PL-side module includes an ADC module, a PWM module, a DAC module, a PCI Express 2.0 module, an SFP+ module, a Memory Interface Generator module, and an AXI-DMA module. Among them, the ADC module and the DAC module are used for data reading and conversion. The PCI Express 2.0 module and the SFP+ module are used for communication between network controllers. The PWM module is used for PWM modulation. The Memory Interface Generator module is used to implement system running memory control. The AXI-DMA module is used to process the interaction of a large amount of data. The PS-side module builds a customized Linux kernel. Among them, corresponding modules and parameter configurations are made according to user requirements, and the corresponding Linux kernel and startup files are generated after configuration.

2. The ZYNQ-based energy router controller according to claim 1, wherein The PL-side interfaces are all AXI-Lite and AXI-Stream interfaces based on the AMBA architecture.

3. The ZYNQ-based energy router controller according to claim 1, characterized in that The DAC module is used for communication between ZYNQ and an external DAC chip, adopts the SPI protocol, provides two DAC interfaces, and daisy-chain loopback is used between multiple DAC chips.

4. The ZYNQ-based energy router controller according to claim 1, characterized in that The PS-side builds a customized Linux kernel through Peta-Linux. Specifically, corresponding modules and parameter configurations are made according to user requirements, and the corresponding Linux kernel and startup files are generated after configuration.

5. The ZYNQ-based energy router controller according to claim 1, characterized in that It also includes several clock modules and reset modules, which are used to generate the clock signals and reset signals required by each module respectively.

6. A control method for the ZYNQ-based energy router controller according to any one of claims 1-5, characterized in that, It includes the following steps: Read the external ADC conversion value through the ADC module and transfer it to the register to obtain the register value. The PS reads the specified register value through the AXI-Lite bus, converts it into the actual value through the transfer function, and then sends it to the relevant closed-loop control algorithm. The control algorithm combines the reference value and the actual value and then outputs a control signal. The control signal is output to other co-controllers in the form of an analog quantity through the DAC module, or directly output to the power stage in the form of a PWM modulation wave after being carrier-modulated by the PWM module to control the switching of power devices.

7. The control method of the energy router controller based on ZYNQ according to claim 6, wherein The communication between network controllers is completed through the PCI Express 2.0 module and the SFP+ module.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the control method of the ZYNQ-based energy router controller described in claim 6.

9. A computer-readable storage medium, characterized in that, Among them, multiple instructions are stored, and the instructions are suitable for being loaded and executed by the processor of the terminal device to implement the control method of the ZYNQ-based energy router controller described in claim 6.

10. A terminal device, characterized in that, It includes a processor and a computer-readable storage medium. The processor is used to implement each instruction. The computer-readable storage medium is used to store multiple instructions, and the instructions are suitable for being loaded and executed by the processor to implement the control method of the ZYNQ-based energy router controller described in claim 6.

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