Energy router controller based on zynq and control method thereof

Abstract

The application discloses a kind of energy router controller and control method based on ZYNQ related to routing communication technical field, especially.The controller includes: PL side module and PS side module, PL side module includes ADC module, PWM module, DAC module, PCI Express2.0 module, SFP+ module, Memory Interface Generator module and AXI-DMA module;PS side module builds the customized Linux kernel of self-defined customization.The controller is compatible between different platforms and different series by modular design.At the same time, through timing design optimization, reduce the CLB, BRAM resources occupied by design, so that the software architecture of the controller can be carried on different series of FPGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of routing communication, in particular to an energy router controller based on ZYNQ and a control method thereof. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] With the development of power grid structure, the distribution network develops from the traditional distribution network architecture to the microgrid, and finally to the integrated energy system. The energy carrier changes from traditional electricity to electricity, heat, gas and other primary and secondary energy. At the same time, the change of the distribution network architecture also puts forward higher requirements for the design of the controller. The energy router has a wide control range, and the algorithm is more complex and large compared with a single converter. At the same time, real-time communication between controllers of different levels and functions in the energy router is needed. This puts forward very high requirements for the operation frequency and computing power of the controller. In the traditional microgrid and energy router control, the main control chip often uses DSP (Digital Signal Processor). Compared with FPGA (Field-Programmable Gate Array), DSP has low development difficulty due to the internal integration of ADC (Analog-to-Digital Converter) and PWM (Pulse-width modulator) and other key peripherals. Since it is still a traditional CPU, the control of peripherals is mainly based on reading and writing registers.

[0004] However, the traditional DSP architecture can only realize software programmability and does not have hardware programmability. The number of peripherals is fixed and cannot be customized by the user. Moreover, due to the differences in pre-developed hardware driver libraries between manufacturers, the software code does not have compatibility between different manufacturers and different series of main control chips of the same manufacturer. Although the highly abstracted hardware driver library solves the compatibility problem between different series, the code execution efficiency is poor and the incompatibility between manufacturers is particularly prominent.

[0005] With the development of power distribution network, the main controller architecture develops into a heterogeneous architecture of FPGA+DSP. The serial processing capability and parallel processing capability are both available. The DSP runs self-defined software, and the FPGA runs self-defined hardware. The inter-chip communication is completed by relying on a specific protocol. However, the FPGA+DSP heterogeneous architecture is programmable in software and hardware, but there is no mature and general industry specification for inter-chip communication, which depends on user self-development, greatly limits the processing capability of the control system, and at the same time, the inter-chip communication occupies a large amount of data IO, which also limits the hardware scalability of the controller. Compared with DSP, FPGA has greater development difficulty, longer development cycle, higher hardware cost, and higher requirements for developers, which also limits the application and promotion of the controller architecture.

[0006] Based on the above-mentioned architecture defects, the existing method attempts to introduce a control platform such as ZYNQ into the controller design to improve the control performance. However, the ZYNQ-based controller has the problems of long development cycle and great pre-development difficulty. Therefore, there is currently a lack of a high-compatibility, high-applicability and high-efficiency energy router controller. SUMMARY

[0007] In view of the deficiencies in the prior art, the purpose of the present application is to provide an energy router controller based on ZYNQ and a control method thereof. The controller is designed by modularization to realize compatibility between different platforms and different series. At the same time, through timing design optimization, the CLB and BRAM resources occupied by the design are reduced, so that the software architecture of the controller can be carried on different series of FPGAs.

[0008] In order to achieve the above-mentioned purpose, the present application is realized by the following technical solutions:

[0009] The first aspect of the present application provides an energy router controller based on ZYNQ (Zynq-7000 All Programmable SoC), which comprises a PL side module and a PS side module. The PL side module comprises an ADC module, a PWM module, a DAC module, a PCI Express2.0-RC (Root Complex) module, an SFP+ module, a Memory Interface Generator module and an AXI-DMA module.

[0010] The ADC module and the DAC module are used for data reading and conversion. The PCI Express2.0 module and the SFP+ module are used for communication between networked controllers. The PWM module is used for PWM modulation. The Memory Interface Generator module is used for realizing system running memory control. The AXI-DMA module is used for processing a large amount of data interaction.

[0011] The ADC module designs an interface form based on a data bus, so that the number of AD7616 chips can be automatically controlled according to the generated Linux kernel code during development; the PWM module can automatically complete output channel pairing, trigger action mode (high, low, flip) in the channel according to the generated Linux kernel code.

[0012] The PS side module builds a customized Linux kernel, wherein the number and parameters of the ADC, PWM and DAC modules are configured according to user requirements, and the corresponding Linux kernel and startup file are generated after the configuration.

[0013] Further, the PL side interfaces are all AXI-Lite and AXI-Stream interfaces based on the AMBA architecture.

[0014] Further, the DAC module is used for communication between the ZYNQ and an external DAC chip, adopts the SPI protocol, provides two DAC interfaces, and adopts a daisy chain loop among multiple DAC chips.

[0015] Further, the AXI_Innerconnect module is used for controlling the AXI-Lite bus and simultaneously completing register address mapping.

[0016] Further, the PS side builds a customized Linux kernel through Peta-Linux.

[0017] Further, a plurality of clock modules and reset modules are further included, and are respectively used for generating clock signals and reset signals required by the modules.

[0018] The second aspect of the present application provides a control method of the ZYNQ-based energy router controller according to the first aspect, comprising the following steps:

[0019] Firstly, the external ADC chip is controlled by the ZYNQ chip to start conversion. After the conversion of the ADC chip is completed, the conversion result register in the external ADC chip (AD7616 / AD7606) is read through a 16-bit data bus and is sequentially stored into the data buffer FIFO in the PL side ADC module, and the PS controls the AXI-Lite bus to read the specified data buffer FIFO through the read channel number, and the actual value is obtained after the conversion through the transfer function and is sent to the phase closing loop control algorithm; the control algorithm outputs the control signal after combining the reference value and the actual value; the control signal is output to other cooperative controllers in the form of analog quantity through the DAC module, or is directly output to the power stage in the form of PWM modulation wave after being modulated by the PWM module, and the power device switch is controlled.

[0020] The closed-loop transfer function execution process is as follows: the conversion result is read through the ADC module, and the conversion result is a signed 16-bit integer data, i.e. from -32,768 to 32,767. The corresponding negative full scale to the positive full scale is linear. The 16-bit integer data is divided by 32768 to obtain the actual input analog voltage. The range is set when the Linux kernel is generated.

[0021] Further, the communication between the networked controllers is completed through the PCI Express2.0 module and the SFP+ module.

[0022] The third aspect of the present application provides a medium having a program stored thereon, and the program is executed by a processor to realize the steps in the control method of the ZYNQ-based energy router controller according to the second aspect of the present application.

[0023] The fourth aspect of the present application provides a device including a memory, a processor and a program stored in the memory and executable on the processor, and the processor executes the program to realize the steps in the control method of the ZYNQ-based energy router controller according to the second aspect of the present application.

[0024] The fifth aspect of the present application provides a computer program product including a computer program, and the computer program is executed by a processor to realize the steps in the control method of the ZYNQ-based energy router controller according to the second aspect of the present application.

[0025] The above one or more technical solutions have the following beneficial effects:

[0026] The application discloses an energy router controller based on ZYNQ and a control method thereof, wherein, due to the independent design among the modules, the modules can be reused, edited and deleted, and user customization of a hardware layer is realized; user customization of a software layer is realized on a PS side; and due to the standardization of interfaces, the compatibility and applicability of the software architecture are greatly improved; meanwhile, due to the AXI protocol interconnection in a chip, the high bandwidth and low delay interconnection of the PS and the PL are ensured; the double ARM cores are integrated with the PL, the AMP architecture is adopted, the high interactivity of Linux and the command line instruction are combined with the high real-time performance and determinacy of a bare machine, and the processing capacity and man-machine interaction performance of the controller are improved; due to the high user customization function of the software and hardware, the software architecture is suitable for the controller software design in multiple scenes; the high applicability makes the software architecture suitable for most application scenes, greatly simplifies the development difficulty of the ZYNQ, and makes the developers focus on the design and operation of the control algorithm.

[0027] Advantages of the additional aspects of the application will be in part apparent to those of ordinary skill in the art, and will in part appear hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which form a part of this specification, are included to provide a further understanding of the application, and are incorporated by reference herein. The embodiments illustrated in the drawings are presented by way of example in connection with the

[0029] Figure 1 It is a controller overall architecture diagram in the embodiment one of the application;

[0030] Figure 2 It is a controller PL side architecture diagram in the embodiment one of the application. DETAILED DESCRIPTION

[0031] It should be noted that the following detailed description is merely exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0032] It should be noted that the terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise, and it should also be understood that, when the terms "comprise" and / or "include" are used in the specification, there is a presence of features, steps, operations, devices, components and / or combinations thereof;

[0033] Embodiment one:

[0034] The embodiment one of the present application provides a ZYNQ-based energy router controller, as shown in the figure, comprising a PL side module and a PS side module. Figure 1 The PS side and the PL side are connected through an AXI-Lite interface and an AXI-Stream interface.

[0035] As shown in the figure, Figure 2 The PL (Programmable Logic) side module comprises an ADC module (AD7616 / AD7606), a PWM module, a DAC module (AD5754 / AD5676), a serial port module (UART16550), a PCI Express2.0-RC (Root Complex) module, an SFP+ module, a Memory Interface Generator module, a CDMA module, an AXI_Innerconnect module and a plurality of clock modules and reset modules.

[0036] The interfaces of the PL side module are all AXI-Lite and AXI-Stream interfaces based on the AMBA (Advanced Microcontroller Bus Architecture) architecture, and the interface standards with wide application range and high occupancy are adopted to expand the practicability of the software architecture. The register reading and writing are completed by the AXI-Lite interface, and the large amount of data interaction is completed by the AXI-Stream interface.

[0037] The AXI_Innerconnect module is used for controlling the AXI-Lite interface of PS-PL and simultaneously completing the register address mapping. The time-sharing multiplexing of the interface is realized by controlling the control right of the AXI interface, and the address mapping of the PL side register is completed by the internal base address register (BaseAddress Register). The time-sharing multiplexing of the AXI interface and the interconnection of PS-PL are realized by the AXI_Innerconnect module of the PL side internal module.

[0038] The ADC module realizes the control function of the ZYNQ chip on the external ADC chip, and 16-bit parallel ports are adopted as the data bus for saving IO and increasing bandwidth, and the time-sharing multiplexing of the data bus is realized through nCS and nRD signals. The maximum number of ADCs that can be mounted is 6, and the setting of the mounting number of ADCs is realized by reading and writing the Module_EN bit of the internal register.

[0039] The PWM module realizes the modulation function of PWM, the time domain resolution is 4ns, the functions such as dead zone, output complement, initial phase can be realized, the output channel number reaches 48 or 96, the channels can be paired, and the action mode can be set.

[0040] The DAC module realizes the control function of the ZYNQ chip on the external DAC chip, adopts the SPI protocol, provides two DAC interfaces, and adopts the daisy chain loop among multiple DAC chips.

[0041] The Memory Interface Generator is used for controlling the PL side external DDR3 SDRAM ( Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is used as the system external RAM memory, provides greater running memory for the system, and is used as the data IO buffer of the PCI Express and SFP+. The module is used for generating the clock and reset signals, 32-bit address signals, 32-bit data signals, and hardware refresh signals required for the normal work of the DDR SDRAM, controls the normal work of the external DDR SDRAM, and realizes the read and write functions of the ZYNQ chip on the DDR SDRAM. The data input, read and write SDRAM address are realized through the AXI-Stream interface. After the address mapping of the module, the corresponding address is transferred to the 32-bit address bus and is sent to the DDR SDRAM chip in parallel, and the corresponding data is realized through the 32-bit data bus.

[0042] The serial port module is used for realizing the PL side serial port expansion. The serial port communication of the PL side is realized through the serial port module.

[0043] The PCI Express module is used for realizing the hardware layer, link layer and transaction layer of the PCI Express 2.0 protocol, realizing the unpacking and packing of the data packet, providing the AXI-Lite and AXI-Stream interfaces for the high-speed data, and realizing the high-speed data transmission and reception.

[0044] The SFP+ module realizes the 10-gigabit Ethernet based on the GTX transceiver, and provides four SFP+ data interfaces. The SFP+ module is composed of the UDP / IP protocol stack and the 10G Ethernet Subsystem. The UDP / IP protocol stack completes the protocol layer of the 10-gigabit Ethernet, and the 10G Ethernet Subsystem completes the physical layer and link layer of the 10-gigabit Ethernet.

[0045] In the embodiment, the two IP cores are used to complete the protocol layer processing of the corresponding protocol, and the physical layer is realized by the GTX transceiver. The module sends the packed data packet to the FIFO of the GTX transceiver, and the GTX transceiver completes the data sending and receiving. The received data is sent to the FIFO, and the unpacking is completed by the PCIE module and the SFP+ module. Meanwhile, the GTX provides the SFP+ and PCIE 2.0 physical layer interfaces, which are used for connecting the hardware circuit.

[0046] The CDMA module is used for processing interaction of a large amount of data, and realizes data transfer without CPU by specifying a source address, a target address and a data length, thereby reducing the burden of the CPU and completing large-amount and large-bandwidth data interaction between the DDR3 SDRAM and the SFP+, the PCI Express and the PS. The address configuration is realized through the AXI-Lite interface, and the data IO is realized through the AXI-Stream interface. The CDMA provides one AXI-Lite interface for realizing configuration of the source address, the target address and the data length, and provides two AXI-Stream interfaces for realizing data interaction between the source address and the target address.

[0047] In addition to the above modules, the PL side has several clock modules and reset modules, which are respectively used for generating clock signals and reset signals required by the modules.

[0048] The external ADC conversion values are read through the ADC module and stored in the register to obtain the register values, the PS side reads the specified register values through the AXI-Lite interface, and the actual values are obtained after being converted through a transfer function and then sent to the phase closing loop control algorithm. The control algorithm outputs a control signal after combining the reference value and the actual value; the control signal is output to other cooperative controllers in the form of an analog quantity through the DAC module, or is directly output to the power stage in the form of a PWM modulation wave after being modulated by the PWM module, thereby controlling the switching of the power device. The related data is temporarily stored in the DDR SDRAM, and can be read and written through the MIG (Memory Interface Generator).

[0049] In a specific embodiment, the communication between the networked controllers is completed through the PCI Express2.0 module and the SFP+ module. After the PS side module sets the source address and the target address of the AXI-DMA module, the DMA module transfers the data to the data FIFO of the SFP+ module, and the SFP module starts transmission. The SFP module receives the data into the FIFO, and the data is transferred to the DDR SDRAM through the DMA module. The data reading of the PCI Express2.0 module is completed by the PCIE module and the CDMA module without the intervention of the PS side. After being unpacked by the PCIE, the address is mapped through the BAR (Base Address Register), and the mapped address is directly handed over to the CDMA module, and the transfer is completed by the CDMA module. The write request is initiated by the PS side, the address is handed over to the CDMA module and the PCIE module, and the package is completed after being mapped by the BAR of the PCIE, and the transfer is completed by the CDMA module. The enumeration process initialized in the PCI Express protocol is run by the PCIE module after being powered on, and the enumeration, classification and numbering of the devices mounted on the PCIE bus are completed.

[0050] The PS side module builds a customized Linux kernel with a built-in GIC (General Interrupt Controller). The PS side builds a customized Linux kernel through Peta-Linux. According to user requirements, corresponding modules and parameters are configured, and the corresponding Linux kernel and startup file are generated after configuration. Specifically, the user inputs the corresponding requirements, including channel types (AI, AO, DI, DO) and corresponding quantities. Then the program judges the corresponding module quantity, IO occupation quantity, and then completes the ADC module quantity configuration, ADC module range setting, ADC module channel number, PWM channel pairing, and action mode setting. Then the corresponding configuration data is integrated to generate the corresponding Linux kernel and startup file.

[0051] The PS side builds a customized Linux system through Peta-Linux, Core-1 runs the customized Linux system and is responsible for communication and command line processing; Core-2 runs in Bare-Metal mode and only executes control algorithms. The two are interconnected through a shared PS side Message DDR memory and use Open-AMP protocol for inter-core communication. The PS and the PL are interconnected through the standard AXI interface of the AMBA architecture.

[0052] In a specific embodiment, the Linux system of the present embodiment is set up in five aspects, namely kernel customization, security customization, driver customization, Linux system on chip and on-chip GIC customization, and energy router control customization.

[0053] 1. Kernel-oriented. The access priority of the system running memory is divided into two levels. The first level is the real-time control function in CPU2, which allocates dedicated running memory for real-time tasks and directly accesses through the AXI-Stream interface of the PL Memory Interface Generator, reducing read-write delay and AXI interface occupation conflict, and at the same time having access permission to the PS side running memory; the second level is the Linux system on chip in CPU1, which can only access the PS side running memory and has no access permission to the PL side memory.

[0054] 2. Driver-oriented. Real-time character device drivers for PWM modules and ADC modules are designed. For module configuration, the write register delay is shortened by directly reading and writing registers without Linux. For reading data, the module data is directly moved into user mode memory through DMA by associating the specified DMA channel in the Linux system with the device driver, reducing the system delay of reading registers one by one.

[0055] 3. Security. For the control function core modules, i.e. PWM module, ADC module, DAC module, CPU1 realizes module security protection by Linux system monitoring system calls, setting drive file read-write permissions, etc. For the operation of writing into the above-mentioned modules, CPU1 monitors the operation initiating user. For the non-system-on-chip root user, it is prohibited to write data into the core module. The module drive file read-write permission is managed by the on-chip Linux system, which ensures that the read-write permission is not tampered.

[0056] 4. For the Linux system-on-chip and the on-chip GIC, a four-level interrupt priority control strategy is proposed. The first priority is the emergency fault interrupt on the PL side, which is generated by the ADC module inner limit comparison module. This level of interrupt is directly bound to the GIC in the PS, directly preoccupies all resources processing on the PS side, bypasses the Linux kernel interrupt scheduler, and reduces the interrupt response time as much as possible. The second priority is the ordinary fault, such as the over-temperature fault of the on-chip temperature sensor. This interrupt is directly bound to the GIC, but participates in the interrupt queuing, and the interrupt response is completed in the queue and then processed by the PS. The third level is the control interrupt of the PS, which is generated by the PWM module every cycle, and is used to execute the converter control function. This level of interrupt is bound to the GIC, but by default enters the end of the queue and waits for all fault responses to be completed. The fourth level is the Linux-based system interrupt, which is executed through the Linux system interrupt scheduler and is the data interaction interrupt for the Linux system. The implementation principle is as follows: the ADC and PWM modules are connected to the GIC in the PS through dedicated interrupt lines, and when the interrupt is applied, the fault code is sent to the PS side at the same time. CPU determines the interrupt priority based on the priority mapping table of the fault code, and puts it into the interrupt waiting queue in order. For the control function interrupt without fault code, the GIC is directly put into the end of the interrupt waiting queue. CPU responds to the interrupt one by one according to the interrupt waiting sequence. For the non-real-time data interaction interrupt, the control right is handed over to the interrupt scheduler of the Linux system, which is only responded in CPU1, avoiding the interference to the real-time interrupt.

[0057] 5. Energy-oriented router control, a three-level fault protection mechanism is proposed. The first level is the PL hardware protection. By comparing the threshold value through the EMIO input or the internal limit comparison module of the ADC module, the PL side interrupt flag is triggered, and the PWM output is directly turned off. The second level is the PS side fault detection interrupt. By detecting the state of the power device, fault diagnosis is performed. The third level is the on-site protection of the PS side, system recovery and fault state uploading. In the normal operation state, the PS side retains the controller kernel state and data within 1s. In the fault state, the PS saves the data to the external ROM through DMA transfer, and uploads it through Ethernet, serial port and other communication methods. The PL side ADC module detects the occurrence of overcurrent, overvoltage and other faults, and directly applies an interrupt to the PS side from the ADC module. The PS side preferentially inputs the backup power module, and clears the interrupt flag. If the fault still exists after the backup power module is input, the PWM output is turned off, the system state is transferred to the external ROM, and the fault state is uploaded. If the fault disappears after the backup is input, only the fault state is uploaded, and the PWM output is not turned off. At the same time, fault diagnosis is started. The PL side ADC module collects the controller chip temperature and the power device current stress, voltage stress, device temperature and inverter input and output waveform. Single device temperature anomaly, power module bidirectional conduction, inverter no output (single phase) or output phase loss (three phase) are judged as power device fault; multiple devices overheat, then determine as thermal failure, preferentially start forced cooling, if multiple power modules still overheat after starting, turn off PWM output and upload fault state; if overvoltage, undervoltage and other bus faults occur on the DC bus, directly turn off the PWM output and upload the fault state.

[0058] Since each module is independent of each other, each module can be reused, edited and deleted to realize user-defined hardware layer; the PS side realizes user-defined software layer. With the standardization of the interface, the compatibility and applicability of the software architecture are greatly improved. At the same time, with the AXI protocol interconnection in the chip, the high bandwidth and low delay interconnection of PS and PL are guaranteed. The dual-ARM core and PL are integrated, and the AMP architecture is adopted, which combines the high interactivity of Linux and command line instructions, and the high real-time performance and determinacy of bare machine, improves the processing capacity and man-machine interaction performance of the controller. Due to the high degree of user-defined function of software and hardware, the software architecture is suitable for controller software design in multiple scenarios. The high applicability makes the software architecture suitable for most application scenarios, greatly simplifies the development difficulty of ZYNQ, and enables the developer to focus on the design and operation of the control algorithm.

[0059] Embodiment two

[0060] The embodiment two of the present application provides a control method based on the ZYNQ-based energy router controller in the embodiment one, which comprises the following steps:

[0061] The external ADC conversion value is read by the ADC module, and the register value is stored in the register, the PS side reads the specified register value through the AXI-Lite bus, and the actual value is converted through a transfer function and then sent to the phase closing loop control algorithm. The control algorithm outputs a control signal after combining the reference value and the actual value; the control signal is output to other cooperative controllers in the form of an analog quantity through the DAC module, or is directly output to the power stage in the form of a PWM modulation wave after being modulated by the PWM module, to control the switching of the power device. The related data is temporarily stored in the DDR SDRAM, and can be read and written through the MIG (Memory Interface Generator).

[0062] In a specific embodiment, the communication between the networked controllers is completed through a PCI Express 2.0 module and an SFP+ module. After the PS side module sets the source address and the target address of the AXI-DMA module, the DMA module transfers the data to the data FIFO of the SFP+ module, and the SFP module starts transmission. The SFP module receives the data into the FIFO, and the data is transferred to the DDR SDRAM through the DMA module. The data reading of the PCI Express 2.0 module is completed by the PCIE module and the CDMA module without the intervention of the PS side. After being unpacked by the PCIE, the address is mapped through the BAR (Base Address Register), and the mapped address is directly handed over to the CDMA module for transfer. The write request is initiated by the PS side, and the address is handed over to the CDMA module and the PCIE module. After being mapped by the BAR of the PCIE, the package is completed by the CDMA module for transfer. The enumeration process initialized in the PCI Express protocol is run by the PCIE module after power-on, to complete the enumeration, classification and numbering of the devices mounted on the PCIE bus.

[0063] Embodiment three

[0064] Embodiment three of the present application provides a medium having a program stored thereon, and the program is executed by a processor to realize the steps in the control method of the ZYNQ-based energy router controller according to embodiment two of the present application.

[0065] Embodiment four

[0066] Embodiment four of the present application provides a device comprising a memory, a processor and a program stored in the memory and executable on the processor, and the processor realizes the steps in the control method of the ZYNQ-based energy router controller according to embodiment two of the present application when executing the program.

[0067] Embodiment five

[0068] The embodiment five of the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the steps in the control method of the ZYNQ-based energy router controller according to the embodiment two of the present application.

[0069] The steps involved in the devices of the above embodiments two, three, four and five correspond to the embodiment one, and the specific embodiments can refer to the relevant description part of the embodiment one.

[0070] Those skilled in the art should understand that each module or each step of the present application described above can be realized by a general computer device, alternatively, they can be realized by program codes executable by a computing device, so that they can be stored in a storage device and executed by a computing device, or they can be respectively manufactured into each integrated circuit module, or a plurality of modules or steps among them can be manufactured into a single integrated circuit module to realize. The present application is not limited to any specific combination of hardware and software.

[0071] Although the specific embodiments of the present application are described above in combination with the drawings, the present application is not limited to the scope of the drawings, and those skilled in the art should understand that various modifications or changes made on the basis of the technical solutions of the present application without creative labor are still within the protection scope of the present application.

Claims

1. A control method of a ZYNQ-based energy router controller, characterized in that, The ZYNQ-based energy router controller comprises a PL side module and a PS side module, the PL side module comprises an ADC module, a PWM module, a DAC module, a PCI Express 2.0 module, an SFP+ module, a Memory Interface Generator module and an AXI-DMA module, wherein the ADC module and the DAC module are used for reading and converting data, the PCI Express 2.0 module and the SFP+ module are used for communication between network controllers, the PWM module is used for PWM modulation, the Memory Interface Generator module is used for realizing system running memory control, and the AXI-DMA module is used for processing interaction of a large amount of data. The PS side module builds a customized Linux kernel, wherein the number and parameters of the ADC, PWM and DAC modules are configured according to user requirements, and the corresponding Linux kernel and a startup file are generated after the configuration, Core-1 runs the customized Linux system and is responsible for communication and command line processing, and Core-2 runs in a Bare-Metal bare machine mode and only executes a control algorithm. An external ADC conversion value is read by the ADC module and stored in a register to obtain a register value, the PS reads the specified register value through an AXI-Lite bus, and the actual value is obtained after being converted through a transfer function and then sent to a phase closing loop control algorithm; the control algorithm outputs a control signal after combining a reference value and the actual value; the control signal is output to other cooperative controllers in the form of an analog quantity through the DAC module, or is directly output to a power stage in the form of a PWM modulation wave after being modulated by the PWM module, so as to control a power device switch.

2. The control method of the ZYNQ-based energy router controller according to claim 1, wherein, The PL side interfaces are all AXI-Lite and AXI-Stream interfaces based on the AMBA architecture.

3. The control method of the ZYNQ-based energy router controller according to claim 1, wherein, The DAC module is used for communication between the ZYNQ and an external DAC chip, adopts an SPI protocol, provides two DAC interfaces, and adopts a daisy chain loop among multiple DAC chips.

4. The control method of the ZYNQ-based energy router controller according to claim 1, wherein, A plurality of clock modules and reset modules are further included and are respectively used for generating clock signals and reset signals required by the modules.

5. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to realize the control method of the ZYNQ-based energy router controller.

6. A computer-readable storage medium, characterized in that, The computer program is executed by the processor to realize the control method of the ZYNQ-based energy router controller.

7. A terminal device, characterized by comprising: The computer program is executed by the processor to realize the control method of the ZYNQ-based energy router controller.

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