Protocol layer data processing method and device for FPGA (Field Programmable Gate Array) transmission

Abstract

The embodiment of the invention provides a protocol layer data processing method and device for FPGA transmission, and the method comprises the steps: obtaining protocol analysis data, and determining load type information based on the protocol analysis data; determining a processing module corresponding to the load type information based on the load type information; wherein the number of the processing modules is at least two, and the at least two processing modules are used for processing at least two pieces of protocol analysis data in parallel; and sending the protocol analysis to a processing module corresponding to the load type information for processing to obtain target data. By setting the processing module with the fixed processing flow, the received data is distributed to different processing modules according to types, so that the processing efficiency of the FPGA is improved, and the complex tree branch jump of the state machine is avoided.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of FPGA programming, and particularly to a method for processing protocol layer data for FPGA transmission. Background Art

[0002] With the development of communication technologies, the speed of data communication is getting higher and higher. High-speed data communication is applied in more and more fields. Data exchange can be achieved through high-speed communication between different data devices, between different boards of the same device, and even between different components of the same board. The protocols for data exchange have become more and more perfect and complex. The protocol layer is an independent layer in the international standard data communication model and is a very important part of data communication. The technical level achieved by the protocol layer has a significant impact on the performance of the entire data communication product.

[0003] For customized projects to achieve certain unique performances or special technical requirements, some non-generalized design solutions and non-standard interface modes are usually adopted. It is very difficult to use general data communication components or chips for such design mode solutions. Such solutions can only use general function chips (FPGA or CPU) as the hardware carrier, and then implement the functions of the solutions through firmware / software programming of these chips. Due to the extremely high data throughput rate of high-speed data communication (up to dozens of Gb / s or even hundreds of Gb / s), FPGA is almost the only optional chip for such solutions. The GTX interface configured by the FPGA is the physical layer interface for data communication. The protocol layer for high-speed communication is implemented by programming the general logic array of the FPGA.

[0004] The programming language of FPGA (Verilog or VHDL) is a hardware description language and parallel processing program statements, which are suitable for the implementation of high-speed signal processing flows. The FPGA uses a state machine to describe the states of various stages in the process, and realizes state transitions based on various signal quantities to implement a specific function of the signal processing flow. Traditional protocol layer programming uses a state machine to describe complex communication protocols, resulting in a large number of states in the state machine, complex and variable state jump branches, and chaotic and complicated execution flows of the state machine. Such programming leads to low program development efficiency, long development cycles, chaotic program code structures, easy errors, and poor maintainability and scalability.

[0005] Therefore, there is an urgent need for a better solution. Summary of the Invention

[0006] In view of this, the embodiments of this specification provide a method for processing protocol layer data for FPGA transmission. One or more embodiments of this specification also relate to a device for processing protocol layer data for FPGA transmission, a computing device, a computer-readable storage medium, and a computer program to solve the technical defects existing in the prior art.

[0007] According to the first aspect of the embodiments of this specification, a method for processing protocol layer data for FPGA transmission is provided, including: Obtain protocol parsing data, and determine payload type information based on the protocol parsing data; Determine a processing module corresponding to the payload type information based on the payload type information; wherein, the number of processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; Send the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data.

[0008] In a possible implementation manner, obtaining protocol parsing data and determining payload type information based on the protocol parsing data includes: Obtain protocol parsing data, decompose the protocol parsing data, and determine the packet header and payload data; Determine the payload type information based on the packet header; wherein, the payload type information is used to determine the use of the payload data.

[0009] In a possible implementation manner, before determining the processing module corresponding to the payload type information based on the payload type information, it further includes: Determine the number of function items and the function process of the protocol layer; Determine the number of processing modules based on the number of function items; Determine the processing process of the processing module based on the function process.

[0010] In a possible implementation manner, determining the processing module corresponding to the payload type information based on the payload type information includes: Judge whether there is a specified function based on the payload type information; When there is a specified function, judge whether other processes need to be synchronized to determine the judgment result; Determine the processing module corresponding to the payload type information based on the judgment result.

[0011] In a possible implementation manner, determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that other processes need to be synchronized, set the parallel protocol data output state and enter the data exchange process processing module.

[0012] In a possible implementation manner, determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that other processes do not need to be synchronized, judge whether a reply is needed; When a reply is needed, set the parallel reply data state and enter the protocol reply process processing module.

[0013] In a possible implementation, Data caching is adopted between different protocol layers as the inter-layer data interface; The data stream control of the inter-layer protocol stack adopts a Valid / Ready handshake architecture.

[0014] According to the second aspect of the embodiments of this specification, a protocol layer data processing device for FPGA transmission is provided, including: A data parsing module, configured to obtain protocol parsing data and determine payload type information based on the protocol parsing data; An allocation processing module, configured to determine a processing module corresponding to the payload type information based on the payload type information; wherein, the number of processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; A data processing module, configured to send the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data.

[0015] According to the third aspect of the embodiments of this specification, a computing device is provided, including: A memory and a processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data processing method for FPGA transmission are implemented.

[0016] According to the fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided, which stores computer-executable instructions. When the instructions are executed by the processor, the steps of the above-mentioned protocol layer data processing method for FPGA transmission are implemented.

[0017] According to the fifth aspect of the embodiments of this specification, a computer program is provided. When the computer program is executed on a computer, the computer is made to execute the steps of the above-mentioned protocol layer data processing method for FPGA transmission.

[0018] The embodiments of this specification provide a protocol layer data processing method and apparatus for FPGA transmission. The protocol layer data processing method for FPGA transmission includes: obtaining protocol parsing data, and determining payload type information based on the protocol parsing data; determining a processing module corresponding to the payload type information based on the payload type information; where the number of processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; sending the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data. By setting up processing modules with a fixed processing flow, the received data is distributed to different processing modules according to the type, improving the processing efficiency of the FPGA and avoiding complex tree-like branch jumps of the state machine. Description of the Drawings

[0019] Figure 1 is a flowchart of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 2 is a schematic diagram of data transmission link establishment of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 3 is a schematic diagram of data transmission link disconnection of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 4 is a schematic diagram of the payload data transmission control principle of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 5 is a schematic diagram of the hierarchical protocol stack of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 6 is a schematic diagram of the flow control function principle of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 7 is a schematic diagram of data exchange of the flow control function of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 8 is a schematic diagram of data reply of the flow control function of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 9 is a schematic diagram of the intermediate layer process of the payload data frame of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 10 is a schematic diagram of the final layer processing principle of the payload data of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 11 It is a schematic diagram of the data interface of the payload data of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 12 It is a schematic diagram of the data reply of the payload data of a protocol layer data processing method for FPGA transmission provided by an embodiment of this specification; Figure 13 It is a schematic structural diagram of a protocol layer data processing device for FPGA transmission provided by an embodiment of this specification; Figure 14 It is a structural block diagram of a computing device provided by an embodiment of this specification. Detailed implementation manners

[0020] Many specific details are set forth in the following description in order to provide a thorough understanding of this specification. However, this specification can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of this specification. Therefore, this specification is not limited by the specific implementations disclosed below.

[0021] The terms used in one or more embodiments of this specification are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of this specification. The singular forms "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0023] In order to improve the development efficiency of the data transmission protocol layer, reduce the development cycle, and enhance the readability and maintainability of the code. The present invention proposes a novel architecture to implement the protocol layer for high-speed data communication. The present invention adopts multiple parallel data stream processing lines at the receiving end, and realizes data exchange between different pipelines and coordinates / synchronizes the execution processes between different pipelines through asynchronous handshaking. Such an architecture reduces the jump branches of the state machine, makes the data stream processing flow clear, and the module functions are clearly divided. At the sending end, the sending requests of all sending modules first apply to the arbiter, and the arbiter sorts the application signals according to the priorities and allows a certain sending unit to execute the sending operation, so that the entire sending process proceeds orderly as required. The coupling between the state machine and the functions of the programming architecture of the present invention is less. Even if an error occurs during the development process, the developer can quickly and clearly locate and correct the error without introducing new errors during the process of correcting the error, thereby improving the reliability of program development. For specific details, please refer to the following description.

[0024] In this specification, a method for processing protocol layer data for FPGA transmission is provided. This specification also relates to a device for processing protocol layer data for FPGA transmission, a computing device, and a computer-readable storage medium, which will be described in detail one by one in the following embodiments.

[0025] See Figure 1 , Figure 1 FIG. shows a flowchart of a method for processing protocol layer data for FPGA transmission according to an embodiment of this specification, which specifically includes the following steps.

[0026] Step 101: Obtain protocol parsing data, and determine payload type information based on the protocol parsing data.

[0027] In a possible implementation manner, obtaining protocol parsing data and determining payload type information based on the protocol parsing data includes: obtaining protocol parsing data, decomposing the protocol parsing data to determine the packet header and payload data; determining payload type information based on the packet header; wherein, the payload type information is used to determine the use of the payload data.

[0028] In practical applications, in data communication, the protocol layer completes two major functions of data transmission and transmission control. These functions are all completed by sending / receiving different types of frames on the same data channel and parsing, executing, and responding to these frames. The receiving process of protocol layer programming for FPGA is to receive data - decompose data packets - analyze data packets - process data packets, and the sending process is to analyze requirements - assemble data packets - send data packets. The data for data transmission includes payload data, which is relatively long and the processing process is relatively complex. The transmission control data packets are relatively short and the processing process is relatively straightforward.

[0029] Data transmission refers to the steps and methods required to complete data transmission. It is divided into two categories: payload data transmission and flow control protocol transmission. The generalized data control process includes processes such as data addressing, link establishment, link disconnection, backpressure, and data reverse confirmation. The link establishment process of data transmission is that the sending end and the receiving end exchange control information frames until the information required for data is established between the transmitting end and the sending end.

[0030] The link establishment process is generally initiated by the data sending end, requesting some data needed during transmission. The data receiving party responds to the request and sends the data required by the sending party back to the sending party. Then, the synchronization information between each other is sent multiple times to complete information synchronization. After the link establishment is completed, the data sending process is entered.

[0031] See Figure 2 , Figure 2 which is the schematic diagram of data communication link establishment. Some data transmissions are connection-based. Before the data transmission process starts, a connection relationship must be established between the transmission and the sending end to achieve the information synchronization required for transmission, including transmission sequence number synchronization and acknowledgment sequence number synchronization, as well as the reliability of these synchronizations. Connection-based data transmission can achieve error-free transmission between point-to-point. If this mode is not adopted, the link establishment process is not required.

[0032] See Figure 3 , Figure 3 which is the schematic diagram of data transmission link disconnection. For connection-based data transmission, after the data transmission is completed, the connection needs to be disconnected and resources released.

[0033] See Figure 4 , Figure 4 which is the schematic diagram of payload data transmission control, consisting of a data acknowledgment module and a data backpressure module. The data acknowledgment module sends from the data receiver to the data sender, indicating that the frame numbers of consecutive sequence number data frames have been acknowledged. The data backpressure signal is sent from the receiving module to the sending module, indicating that the receiving processing capacity or buffer area of the local party is insufficient. Please ask the sending party to temporarily reduce the sending speed or stop the sending process to ensure that the sent data is not lost.

[0034] From Figure 2 、 Figure 3 and Figure 4 it can be seen that flow control is some information exchanged between the data sending end and the data receiving end. These information are either sent actively or in response to the information of the other party. The sending and receiving parties communicate some information in their own transmission processes through flow control information, and adjust their own data transmission processes through the information of the other party to ensure the synchronization and coordination of their own transmission processes with the transmission processes of the other party. The flow control information is completed through flow control information frames. The characteristics of flow control frames are simple frame structure, small frame length, high frequency, and high transmission priority.

[0035] Due to the need for complex data exchange functions, data transfer protocols often adopt multi-layer protocol encapsulation from high to low. The high-level protocol packet serves as the payload data of the low-level protocol, and the low-level protocol data packet is encapsulated with a packet header / packet tail; the encapsulated protocol data packet is encapsulated again with a packet header / packet tail to become a lower-level protocol data packet; and so on until the lowest-level protocol data packet is encapsulated.

[0036] Receiving and processing this flow control information is to receive and process these protocol control frames. The data is unpacked layer by layer from low to high to extract functional characteristics, and different functional modules are executed according to different received requirements. Different from the execution mode of the CPU based on the von Neumann architecture, the execution of the FPGA is parallel, and different functional branches are completed through the jump of the state machine. If programmed in the traditional method, the states of the state machine are numerous, the state transition relationships are complex, and the reliability of development is reduced.

[0037] In a possible implementation, before determining the processing module corresponding to the payload type information based on the payload type information, it further includes: determining the number of function items and the function process of the protocol layer; determining the number of processing modules based on the number of function items; and determining the processing process of the processing module based on the function process.

[0038] The present invention adopts a parallel processing architecture for the protocol parsing of the input data of a specific layer according to the programming characteristics of the FPGA. The protocol processing program sets the same number of processing processes according to the number of function items of the layer, and each process processes in parallel. A new data receiving process is designed to process data frames hierarchically and in parallel. Each processing process only needs to use a small state machine to complete the information process of a function. The number of states of the state machine is very small, and the state transition is clear and simple.

[0039] Specifically, hierarchical processing means that according to the protocol encapsulation level, the processing of the protocol is also hierarchical according to the protocol level. The protocol processing program for a specific layer is called a protocol stack. The protocol stack receives the input of the lower-level protocol data and decomposes the data packet into two parts: the packet header and the payload data. The packet header contains information such as the packet type to determine the use of the payload data.

[0040] In a possible implementation, data caching is used as the inter-layer data interface between different protocol layers; the data flow control of the inter-layer protocol stack adopts a Valid / Ready handshake architecture.

[0041] The hierarchical processing of the protocol makes the function of each protocol stack clear and the programming simple. Data caching is used as the inter-layer data interface between different protocol layers, and the data flow control of the inter-layer protocol stack adopts a Valid / Ready handshake architecture, which can effectively process a large number of data payloads that appear in a short time. Such a protocol processing architecture is more suitable for high-speed data transmission.

[0042] Step 102: Determine the processing module corresponding to the load type information based on the load type information; wherein, the number of processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel.

[0043] In practical applications, control frames are generally relatively small, with simple and clear functional requirements, and do not contain load data or contain very little auxiliary load data. The control frame processing program completes the required processing directly in the program flow according to the functional type requirements and their attached data in the packet header. The data frame contains load data with a complex structure. The load data is the data packet of the upper-level protocol, and the protocol stack at this layer does not directly process the protocol of the higher layer to avoid a long and complex protocol processing flow. The protocol stack at this layer simply caches the load data and uses it as the input of the higher-level protocol stack.

[0044] In the data reception process of the FPGA, based on the programming characteristics of the FPGA, parallel processing as shown in Figure 5 can be achieved. Among them, the protocol input data can be sent to the processing modules of Function 1 module, Function 2 module... Function n module, as well as Data Processing Module 1, Data Processing Module 2... Data Processing Module m. Correspondingly, the processing modules of Function 1 module, Function 2 module... Function n module respectively generate reply data frames 1, reply data frames 2... reply data frames n or jump to other processes, and the processed data generated by Data Processing Module 1, Data Processing Module 2... Data Processing Module m are respectively stored in data buffer 1, data buffer 2... data buffer m. The essence of FPGA programming is to combine some discrete logic gates into user-specified functional units. Parallel processing is to form multiple functional units at one time. These functional units are physically independent and independently execute their own program flows under the drive of the clock. In FPGA programming, the program flow is the design and implementation of the state machine. The state machine realizes each step of the functional flow through state jumps.

[0045] In a possible implementation manner, determining the processing module corresponding to the load type information based on the load type information includes: judging whether there is a specified function based on the load type information; in the case where there is a specified function, judging whether it is necessary to synchronize other processes to determine the judgment result; determining the processing module corresponding to the load type information based on the judgment result.

[0046] Further, determining the processing module corresponding to the load type information based on the judgment result includes: in the case where the judgment result is that it is necessary to synchronize other processes, setting the parallel protocol data output state and entering the data exchange process processing module.

[0047] Further, determining a processing module corresponding to the load type information based on the judgment result includes: when the judgment result is that other processes do not need to be synchronized, determining whether a reply is required; when a reply is required, setting the parallel reply data status and entering the protocol reply process processing module.

[0048] Specifically, refer to Figure 6 、 Figure 7 and Figure 8 which are the schematic diagrams of the specific flow control functions and are composed of three relatively independent processes. Figure 6 The main process of is responsible for data reception, data packet separation, extraction of protocol data, determination and screening of protocol functions, and interaction with the data exchange process and the data reply process. Figure 7 The data exchange process of is responsible for notifying associated processes of the received data. Figure 8 The data reply process of is responsible for replying relevant protocols. The data exchange process and the data reply process are optional items and are configured according to protocol functions.

[0049] From Figure 6 、 Figure 7 and Figure 8 it can be seen that all processes are only related to one function item, the process jumps are very simple, and there are no very complex branch jumps. Different functions are completed by instantiating multiple processes.

[0050] Figure 9 is the schematic diagram of the process of receiving, caching, and forwarding the middle layer of the load data frame. From Figure 9 it can be seen that the protocol stack of the middle layer of the load data is just a bridge. It receives data from the upstream, decomposes and strips the load data of the next layer, and sends it to the next layer protocol stack through caching. This hierarchical processing mode makes the processing of each layer very simple.

[0051] The processing mode of the final layer of the load data frame is different from the bridging mode of the middle layer. The final layer protocol stack directly receives data and assembles scattered data segments into a complete data block for the App layer to call.

[0052] Step 103: Send the protocol parsing to the processing module corresponding to the load type information for processing to obtain the target data.

[0053] In practical applications, Figure 10 、 Figure 11 、 Figure 12 are the schematic diagrams of the processing of the protocol stack of the final layer of the load data, which are respectively composed of three processes. Figure 10 is the main function process, and its function is data caching and data recombination. Figure 11 is the app data interface. Figure 12This is the data reply process. The most important function among them is the processing of the received frame sequence number. The frame sequence number is the only criterion for receiving integrity. However, when there is no omission between the received sequence number and the initial sequence number and all are received, it is considered that all received data is correct and valid. The receiving process returns this sequence number to the sending process. The sending process releases the buffer area according to the received reply sequence number and sends new data until all app data is sent.

[0054] The receiving program process is the core of the entire data receiving program. The present invention splits the complex receiving process into a series of parallel processes, making each process simple and smooth. Different processes of the present invention transfer data and coordinate the execution process through asynchronous handshake signals. The entire programming is modular and standardized.

[0055] The embodiments of the present specification provide a method and device for protocol layer data processing for FPGA transmission. The method for protocol layer data processing for FPGA transmission includes: obtaining protocol parsing data, determining payload type information based on the protocol parsing data; determining a processing module corresponding to the payload type information based on the payload type information; wherein the number of processing modules is at least two, and the at least two processing modules are used for parallel processing of at least two protocol parsing data; sending the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data. By setting processing modules with fixed processing processes, the received data is allocated to different processing modules according to the type, improving the processing efficiency of the FPGA and avoiding complex tree-like branch jumps of the state machine.

[0056] Corresponding to the above method embodiments, the present specification also provides embodiments of a device for protocol layer data processing for FPGA transmission. Figure 13 The structural schematic diagram of a device for protocol layer data processing for FPGA transmission provided by an embodiment of the present specification is shown. As Figure 13 shown, the device includes: A data parsing module 1301, configured to obtain protocol parsing data and determine payload type information based on the protocol parsing data; An allocation processing module 1302, configured to determine a processing module corresponding to the payload type information based on the payload type information; wherein the number of processing modules is at least two, and the at least two processing modules are used for parallel processing of at least two protocol parsing data; A data processing module 1303, configured to send the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data.

[0057] In a possible implementation manner, obtaining protocol parsing data and determining payload type information based on the protocol parsing data includes: Obtaining protocol parsing data, decomposing the protocol parsing data, and determining the packet header and payload data; Determine the payload type information based on the packet header; wherein, the payload type information is used to determine the usage of the payload data.

[0058] In a possible implementation, before determining the processing module corresponding to the payload type information based on the payload type information, it further includes: Determine the number of functional items and the functional process of the protocol layer; Determine the number of processing modules based on the number of functional items; Determine the processing process of the processing module based on the functional process.

[0059] In a possible implementation, determining the processing module corresponding to the payload type information based on the payload type information includes: Judge whether there is a specified function based on the payload type information; When there is a specified function, judge whether it is necessary to synchronize other processes and determine the judgment result; Determine the processing module corresponding to the payload type information based on the judgment result.

[0060] In a possible implementation, determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that it is necessary to synchronize other processes, set the parallel protocol data output status and enter the data exchange process processing module.

[0061] In a possible implementation, determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that it is not necessary to synchronize other processes, judge whether a reply is needed; When a reply is needed, set the parallel reply data status and enter the protocol reply process processing module.

[0062] In a possible implementation, Data caching is adopted between different protocol layers as the inter-layer data interface; The data flow control of the inter-layer protocol stack adopts a Valid / Ready handshake architecture.

[0063] The embodiments of this specification provide a protocol layer data processing method and apparatus for FPGA transmission. The protocol layer data processing apparatus for FPGA transmission includes: obtaining protocol parsing data and determining payload type information based on the protocol parsing data; determining a processing module corresponding to the payload type information based on the payload type information; where the number of processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; sending the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data. By setting up processing modules with a fixed processing flow, the received data is allocated to different processing modules according to the type, improving the processing efficiency of the FPGA and avoiding complex tree-like branch jumps of the state machine.

[0064] The above is a schematic solution of a protocol layer data processing apparatus for FPGA transmission in this embodiment. It should be noted that the technical solution of the protocol layer data processing apparatus for FPGA transmission and the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission belong to the same concept. For the details not described in detail in the technical solution of the protocol layer data processing apparatus for FPGA transmission, reference can be made to the description of the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission.

[0065] Figure 14 The structural block diagram of a computing device 1400 provided according to an embodiment of this specification is shown. The components of the computing device 1400 include, but are not limited to, a memory 1410 and a processor 1420. The processor 1420 is connected to the memory 1410 through a bus 1430, and a database 1450 is used to store data.

[0066] The computing device 1400 also includes an access device 1440, which enables the computing device 1400 to communicate via one or more networks 1460. Examples of such networks include the Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or a combination of communication networks such as the Internet. The access device 1440 may include one or more of any type of wired or wireless network interface (e.g., network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, Worldwide Interoperability for Microwave Access (Wi-MAX) interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth interface, Near Field Communication (NFC).

[0067] In one embodiment of the present specification, the above components of the computing device 1400 and Figure 14 other components not shown therein may also be connected to each other, for example, via a bus. It should be understood that Figure 14 the block diagram of the computing device shown is for illustrative purposes only and is not a limitation on the scope of the present specification. Those skilled in the art may add or replace other components as needed.

[0068] The computing device 1400 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 1400 can also be a mobile or stationary server.

[0069] Among them, the processor 1420 is used to execute the following computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data processing method for FPGA transmission are implemented. The above is a schematic solution of a computing device in this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission belong to the same concept. For the details not described in detail in the technical solution of the computing device, reference can be made to the description of the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission.

[0070] An embodiment of this specification also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data processing method for FPGA transmission are implemented.

[0071] The above is a schematic solution of a computer-readable storage medium in this embodiment. It should be noted that the technical solution of this storage medium and the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission belong to the same concept. For the details not described in detail in the technical solution of the storage medium, reference can be made to the description of the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission.

[0072] An embodiment of this specification also provides a computer program. When the computer program is executed on a computer, the computer is made to execute the steps of the above-mentioned protocol layer data processing method for FPGA transmission.

[0073] The above is a schematic solution of a computer program in this embodiment. It should be noted that the technical solution of this computer program and the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission belong to the same concept. For the details not described in detail in the technical solution of the computer program, reference can be made to the description of the technical solution of the above-mentioned protocol layer data processing method for FPGA transmission.

[0074] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0075] The computer instructions include computer program code, which may be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, removable hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0076] It should be noted that for the foregoing method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of this specification are not limited by the described action sequence, because according to the embodiments of this specification, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential for the embodiments of this specification.

[0077] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The alternative embodiments do not elaborate on all the details and do not limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this specification, so that those skilled in the art can understand and utilize this specification well. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A protocol layer data processing method for FPGA transmission, characterized in that Including: Obtain protocol parsing data, and determine payload type information based on the protocol parsing data; Determine the processing module corresponding to the payload type information based on the payload type information; wherein, the number of the processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; Send the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data.

2. The method according to claim 1, wherein The obtaining protocol parsing data and determining payload type information based on the protocol parsing data includes: Obtain protocol parsing data, decompose the protocol parsing data, and determine a packet header and payload data; Determine payload type information based on the packet header; wherein, the payload type information is used to determine the use of the payload data.

3. The method according to claim 1, characterized in that, Before determining the processing module corresponding to the payload type information based on the payload type information, it further includes: Determine the number of function items and the function process of the protocol layer; Determine the number of the processing modules based on the number of function items; Determine the processing process of the processing module based on the function process.

4. The method according to claim 1, wherein The determining the processing module corresponding to the payload type information based on the payload type information includes: Judge whether there is a specified function based on the payload type information; When there is the specified function, judge whether other processes need to be synchronized to determine a judgment result; Determine the processing module corresponding to the payload type information based on the judgment result.

5. The method according to claim 4, characterized in that, The determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that other processes need to be synchronized, perform parallel protocol data output status setting and enter the data exchange process processing module.

6. The method according to claim 4, characterized in that The determining the processing module corresponding to the payload type information based on the judgment result includes: When the judgment result is that other processes do not need to be synchronized, judge whether a reply is needed; When a reply is needed, perform parallel reply data status setting and enter the protocol reply process processing module.

7. The method according to claim 3, wherein Data caching is adopted between different protocol layers as an inter-layer data interface; The inter-layer protocol stack data flow control adopts a Valid / Ready handshaking architecture.

8. A protocol layer data processing device for FPGA transmission, characterized in that Including: A data parsing module, configured to obtain protocol parsing data and determine payload type information based on the protocol parsing data; An allocation processing module, configured to determine the processing module corresponding to the payload type information based on the payload type information; wherein, the number of the processing modules is at least two, and the at least two processing modules are used to process at least two protocol parsing data in parallel; A data processing module, configured to send the protocol parsing to the processing module corresponding to the payload type information for processing to obtain target data.

9. A computing device, characterized in that, Including: A memory and a processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the protocol layer data processing method for FPGA transmission according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the steps of the protocol layer data processing method for FPGA transmission described in any one of claims 1 to 7 are implemented.

Images