Message receiving method and message sending method

Abstract

The embodiment of the invention provides a message receiving method and a message sending method, and relates to the field of message transmission technologies and the like. The method comprises the following steps: after a first message is stored through an FPGA (Field Programmable Gate Array), updating a current value of a first pointer of a first queue; and when the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, processing the first message according to the length and the RSS value obtained by the CPU, and updating the current value of the tail pointer. According to the method provided by the invention, the current value of the tail pointer is different from the current value of the head pointer, so that the FPGA is indicated to store the first message, the FPGA does not need to store a write completion flag bit, the occupied PCIE bandwidth can be reduced, and the time delay of receiving the message is reduced.

Description

Technical Field

[0001] This application relates to the field of message transmission technologies, and in particular, to a message receiving method and a message sending method. Background Art

[0002] Currently, a message receiving device can perform message receiving and processing based on heterogeneous computing of a Central Processing Unit (CPU) and a Field-Programmable Gate Array (FPGA).

[0003] In the related art, a Field-Programmable Gate Array (FPGA) receives a message and stores the message in a storage area corresponding to the physical address of the message. Furthermore, a write completion flag bit is stored in a descriptor corresponding to the physical address of the descriptor. When the Central Processing Unit (CPU) detects the write completion flag bit, the message is processed.

[0004] In the above technology, storing the write completion flag bit in the descriptor corresponding to the physical address of the descriptor by the FPGA will occupy the bandwidth of the Peripheral Component Interconnect Express (PCIE), resulting in a relatively high delay in receiving messages. Summary of the Invention

[0005] Embodiments of this application provide a message receiving method and a message sending method for reducing the occupied PCIE bandwidth and reducing the delay in receiving messages.

[0006] In a first aspect, an embodiment of this application provides a message receiving method, which is applied to a first device. The first device includes a Central Processing Unit (CPU) and a Field-Programmable Gate Array (FPGA). The method includes:

[0007] Receiving, by the FPGA, a first message from a second device according to a physical address of a descriptor; the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of a first queue;

[0008] Storing, by the FPGA, parsing information of the first message and the first message according to the physical address of the descriptor, and updating the current value of the head pointer of the first queue;

[0009] When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the first packet and the parsing information according to the descriptor physical address indicated by the current value of the tail pointer;

[0010] The CPU processes the first packet according to the parsing information and updates the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0011] In this solution, after the FPGA stores the first packet, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the first packet, realizing that the storage of the first packet by the FPGA is indicated by the difference between the current value of the tail pointer and the current value of the head pointer. The FPGA does not need to store a write completion flag bit in the descriptor corresponding to the descriptor physical address, which can reduce the PCIE bandwidth occupation and reduce the delay of receiving packets. In the related art, the FPGA needs to store a write completion flag bit in the descriptor corresponding to the descriptor physical address, which will cause a large occupation of the PCIE bandwidth and a high delay of receiving packets.

[0012] In some embodiments, the storing, by the FPGA, the parsing information of the first packet and the first packet according to the descriptor physical address includes:

[0013] The FPGA determines the descriptor corresponding to the descriptor physical address;

[0014] The FPGA stores the parsing information into the descriptor corresponding to the descriptor physical address.

[0015] The FPGA obtains the packet physical address from the descriptor corresponding to the descriptor physical address;

[0016] The FPGA determines the storage area corresponding to the packet physical address;

[0017] The FPGA stores the first packet into the storage area corresponding to the packet physical address.

[0018] In some embodiments, the method further includes:

[0019] The CPU allocates at least one consecutive descriptor physical address and at least one packet physical address, where the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0020] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address;

[0021] The CPU writes the at least one descriptor physical address into the FPGA.

[0022] In some embodiments, after the CPU allocates the consecutive at least one descriptor physical address and at least one packet physical address, the method further includes:

[0023] Initializing a first queue and a second queue;

[0024] Wherein, after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device has received a first packet, and the current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to batch release descriptors.

[0025] In some embodiments, the method further includes:

[0026] When the CPU determines that the current value of the head pointer is equal to a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, the packet physical addresses in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor are batch released; wherein, the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer;

[0027] The CPU rewrites new packet physical addresses into each of the first quantity of descriptors, and updates the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the packet physical addresses in the first quantity of descriptors.

[0028] In this solution, if the CPU determines that the current value of the head pointer is a multiple of the first quantity, and the current value of the pointer of the second queue is different from the current value of the head pointer, the packet physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor are released in batches. This helps to rewrite the new packet physical addresses in each of the first quantity of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors, which can improve the efficiency of release and rewrite, thereby reducing the PCIE bandwidth occupancy and the latency of receiving packets. In the related art, before the FPGA stores the write completion flag bit in the descriptor corresponding to the descriptor physical address, the descriptor physical address and the packet physical address have already been stored in the descriptor. Since the amount of data that the descriptor can carry is limited, the write completion flag bit will occupy the descriptor physical address, resulting in an incorrect descriptor physical address. Therefore, when releasing in batches, it is necessary to release all of the descriptor physical address, the packet physical address, etc., in order to re-store the physical address of the descriptor, the new packet physical address, etc., resulting in a low efficiency of release and rewrite, and thus a large occupancy of the PCIE bandwidth and a high latency of receiving packets.

[0029] In a second aspect, an embodiment of the present application provides a packet sending method, which is applied to a first device. The first device includes a CPU and an FPGA. The method includes:

[0030] The FPGA obtains the packet physical address associated with the descriptor physical address and the length of the first packet according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0031] The FPGA obtains the first packet according to the packet physical address and the length, and updates the current value of the head pointer of the first queue;

[0032] When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first packet to the second device according to the descriptor physical address, and updates the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0033] In this solution, after the FPGA obtains the first packet, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first packet to the second device. By using the difference between the current value of the tail pointer and the current value of the head pointer to indicate that the FPGA has obtained and stored the first packet, the FPGA does not need to store the read completion flag bit in the descriptor corresponding to the physical address of the descriptor, which can reduce the PCIE bandwidth occupancy and reduce the latency of sending packets. In the related art, the FPGA needs to store the read completion flag bit in the descriptor corresponding to the physical address of the descriptor, which results in a large occupancy of the PCIE bandwidth and a high latency of sending packets.

[0034] In some embodiments, the step of the FPGA obtaining the physical address of the packet associated with the physical address of the descriptor and the length of the first packet according to the physical address of the descriptor includes:

[0035] The FPGA determines the descriptor corresponding to the physical address of the descriptor;

[0036] The FPGA obtains the physical address of the packet associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor.

[0037] In some embodiments, the step of the FPGA obtaining the first packet according to the physical address of the packet and the length includes:

[0038] The FPGA determines the storage area corresponding to the physical address of the packet;

[0039] The FPGA obtains the first packet from the storage area corresponding to the physical address of the packet according to the length.

[0040] In some embodiments, the method further includes:

[0041] The CPU allocates at least one consecutive physical address of the descriptor and at least one physical address of the packet, where the at least one physical address of the descriptor is associated with the at least one physical address of the packet, the at least one physical address of the descriptor includes the physical address of the descriptor, and the at least one physical address of the packet includes the physical address of the packet;

[0042] For one physical address of the descriptor in the at least one physical address of the descriptor and the physical address of the packet associated with the physical address of the descriptor, the CPU stores the physical address of the descriptor, the physical address of the packet associated with the physical address of the descriptor, and the length of the first packet into the descriptor corresponding to the physical address of the descriptor;

[0043] The CPU writes the at least one descriptor physical address to the FPGA.

[0044] In some embodiments, after the CPU allocates the consecutive at least one descriptor physical address and at least one packet physical address, the method further includes:

[0045] Initializing a first queue and a second queue;

[0046] Wherein, after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device sends the first packet, and the current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

[0047] In some embodiments, the method further includes: when the CPU determines that the current value of the head pointer is a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, batch releasing the packet physical addresses in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor, and the length of the first packet; wherein, the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer;

[0048] The CPU rewrites a new packet physical address and the length of a new packet in each of the first quantity of descriptors, and updates the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the packet physical addresses in the first quantity of descriptors and the length of the first packet.

[0049] In this solution, if the CPU determines that the current value of the head pointer is a multiple of the first quantity, and the current value of the pointer of the second queue is different from the current value of the head pointer, the packet physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor and the length of the first packet are released in batches. This helps to rewrite the new packet physical addresses and the lengths of the new packets in each of the first quantity of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors, which can improve the efficiency of release and rewrite, thereby reducing the PCIE bandwidth occupation and the latency of receiving packets. In the related art, before the write completion flag bit is stored in the descriptor corresponding to the descriptor physical address in the FPGA, the descriptor physical address, the packet physical address, and the length of the first packet have already been stored in the descriptor. Since the amount of data that a descriptor can carry is limited, the write completion flag bit will occupy the descriptor physical address, resulting in an incorrect descriptor physical address. Therefore, when releasing in batches, it is necessary to release all of the descriptor physical address, the packet physical address, etc., in order to re-store the physical address of the descriptor, the new packet physical address, etc., resulting in a low efficiency of release and rewrite, and thus a large occupation of the PCIE bandwidth and a high latency of sending packets.

[0050] In a third aspect, an embodiment of the present application provides a packet transmission device, which is applied to a first device. The device includes:

[0051] A first processing module, configured to receive a first packet from a second device according to a descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0052] The first processing module is further configured to store the parsing information of the first packet and the first packet according to the descriptor physical address, and update the current value of the head pointer of the first queue;

[0053] A second processing module, configured to, when determining that the current value of the tail pointer of the first queue is different from the current value of the head pointer, obtain the packet physical address and the parsing information according to the descriptor physical address indicated by the current value of the tail pointer;

[0054] The second processing module is further configured to obtain the first packet according to the packet physical address, process the first packet according to the parsing information, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0055] The packet receiving device provided by the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0056] In some embodiments, the first processing module is specifically configured to:

[0057] Determine the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0058] Store the parsing information to the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0059] Obtain the physical address of the message from the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0060] Determine the storage area corresponding to the physical address of the message through the FPGA;

[0061] Store the first message to the storage area corresponding to the physical address of the message through the FPGA.

[0062] In some embodiments, the second processing module is further configured to:

[0063] Allocate at least one consecutive physical address of the descriptor and at least one physical address of the message through the CPU, wherein the at least one physical address of the descriptor is associated with the at least one physical address of the message, the at least one physical address of the descriptor includes the physical address of the descriptor, and the at least one physical address of the message includes the physical address of the message;

[0064] For one physical address of the descriptor in the at least one physical address of the descriptor and the physical address of the message associated with the physical address of the descriptor, store the physical address of the descriptor and the physical address of the message associated with the physical address of the descriptor to the descriptor corresponding to the physical address of the descriptor through the CPU;

[0065] Write the at least one physical address of the descriptor into the FPGA through the CPU.

[0066] In some embodiments, the second processing module is further configured to: initialize a first queue and a second queue;

[0067] Wherein, after initialization, the first queue and the second queue store the at least one physical address of the descriptor, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used by the CPU to determine whether the first device has received a first message, and the current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to batch release descriptors.

[0068] In some embodiments, the second processing module is further configured to:

[0069] When the CPU determines that the current value of the head pointer is a multiple of the first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, the message physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor are released in batches; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the head pointer;

[0070] The CPU rewrites a new message physical address in each of the first quantity of descriptors, and updates the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to release the message physical addresses in the first quantity of descriptors in batches.

[0071] The message receiving device provided by the embodiments of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0072] In a fourth aspect, an embodiment of the present application provides a message sending device, which is applied to a first device, and the device includes:

[0073] A first processing module, configured to obtain the message physical address associated with the descriptor physical address and the length of the first message according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0074] The first processing module is configured to obtain the first message according to the message physical address and the length, and update the current value of the head pointer of the first queue;

[0075] A second processing module, configured to, when determining that the current value of the tail pointer of the first queue is different from the current value of the head pointer, control the first processing module to send the obtained first message to the second device according to the descriptor physical address, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0076] The message sending device provided by the embodiments of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0077] In some embodiments, the first processing module is specifically configured to: determine the descriptor corresponding to the descriptor physical address; obtain the message physical address associated with the descriptor physical address and the length of the first message from the descriptor corresponding to the descriptor physical address.

[0078] In some embodiments, the first processing module is specifically configured to: determine a storage area corresponding to the physical address of the message; and obtain the first message from the storage area corresponding to the physical address of the message according to the length.

[0079] In some embodiments, the second processing module is further configured to:

[0080] allocate at least one consecutive descriptor physical address and at least one message physical address, where the at least one descriptor physical address is associated with the at least one message physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one message physical address includes the message physical address;

[0081] for one descriptor physical address in the at least one descriptor physical address and the message physical address associated with the descriptor physical address, store the descriptor physical address, the message physical address associated with the descriptor physical address, and the length of the first message into the descriptor corresponding to the descriptor physical address;

[0082] write the at least one descriptor physical address into the first processing module.

[0083] In some embodiments, after allocating the at least one consecutive descriptor physical address and at least one message physical address, the second processing module is further configured to: initialize a first queue and a second queue;

[0084] wherein after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used by the second processing module to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

[0085] In some embodiments, the second processing module is further configured to:

[0086] when it is determined that the current value of the head pointer is a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, batch release the message physical addresses in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor, and the length of the first message; wherein the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer;

[0087] Rewrite the new packet physical address and the length of the new packet in each of the first quantity of descriptors, and update the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the packet physical addresses in the first quantity of descriptors and the length of the first packet.

[0088] The packet sending device provided by the embodiments of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0089] In a fifth aspect, the present application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0090] The memory stores computer-executable instructions;

[0091] The processor executes the computer-executable instructions stored in the memory to implement the methods as in the first aspect and / or the second aspect.

[0092] The electronic device provided by the embodiments of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0093] In a sixth aspect, the embodiments of the present application provide a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the methods as in the first aspect and the second aspect.

[0094] When the computer-executable instructions in the computer-readable storage medium provided by the embodiments of the present application are executed by a processor, the technical solutions shown in the above method embodiments can be implemented, and their implementation principle and beneficial effects are similar, and will not be elaborated here.

[0095] In a seventh aspect, the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the methods as in the first aspect and the second aspect.

[0096] When the computer program in the computer program product provided by the embodiments of the present application is executed by a processor, the technical solutions shown in the above method embodiments can be implemented, and their implementation principle and beneficial effects are similar, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0098] Figure 1The corresponding relationship between the descriptor physical address and the descriptor provided by the embodiment of the present application;

[0099] Figure 2 The processing flow of the CPU when receiving a message in the related art;

[0100] Figure 3 The processing flow of the CPU when sending a message in the related art;

[0101] Figure 4 The flowchart of a message receiving method provided by the embodiment of the present application Figure 1 ;

[0102] Figure 5 The flowchart of a message receiving method provided by the embodiment of the present application Figure 2 ;

[0103] Figure 6 The flowchart of a message receiving method provided by the embodiment of the present application Figure 3 ;

[0104] Figure 7 The flowchart of a message receiving method provided by the embodiment of the present application Figure 4 ;

[0105] Figure 8 The flowchart of a message sending method provided by the embodiment of the present application Figure 1 ;

[0106] Figure 9 The flowchart of a message sending method provided by the embodiment of the present application Figure 2 ;

[0107] Figure 10 The flowchart of a message sending method provided by the embodiment of the present application Figure 3 ;

[0108] Figure 11 The flowchart of a message sending method provided by the embodiment of the present application Figure 4 ;

[0109] Figure 12 The structural schematic diagram of a message transmission device provided by the embodiment of the present application;

[0110] Figure 13 The structural diagram of an electronic device provided by the embodiment of the present application.

[0111] Through the above-mentioned drawings, the clear embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Implementation Manner

[0112] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0113] Glossary of Terms:

[0114] Bandwidth of the Peripheral Component Interconnect Express (PCIE) High-Speed Serial Computer Expansion Bus Standard: PCIE is a high-speed serial computer expansion bus standard used to connect various components inside a device. When the CPU and FPGA store or retrieve data in the device, they both occupy the PCIE bandwidth.

[0115] Transaction Layer Packet (TLP): TLP is a data encapsulation format packet used in the transaction layer of PCIE. In PCIE, messages are not transmitted in the form of a continuous data stream, but are split into individual TLPs for transmission.

[0116] Packet transmission method based on TLP: In this method, the maximum payload length of the TLP is relatively small, and each TLP carries a relatively small amount of data. If the amount of data in the message to be transmitted is large, the message will be split into multiple messages with smaller amounts of data, and then multiple messages with smaller amounts of data will be transmitted through multiple TLPs.

[0117] Large-packet transmission method based on TLP: In this method, by increasing the maximum payload length of the TLP, each TLP can carry a larger amount of data. For a message with a large amount of data, there is no need to split it, and it is transmitted through one TLP.

[0118] Direct Memory Access (DMA): Allows the FPGA to directly store data or retrieve data in the memory of the first device without the interference of the CPU.

[0119] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. For example, the first value and the second value are only used to distinguish different values, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily limit being different from each other.

[0120] It should be noted that in the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner.

[0121] In the embodiments of the present application, "at least one" means one or more, and "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item (s) or plural items (s). For example, at least one (item) of a, b, or c may represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c may be single or multiple.

[0122] With the development of the mobile Internet, innovative breakthroughs have continuously emerged in applications such as autonomous driving and artificial intelligence. The scale of data to be processed has grown exponentially, and the processors in devices need to have more powerful data processing capabilities to ensure that a large amount of data can be efficiently processed and transmitted in a short time.

[0123] Currently, a dual - processor of a central processing unit (CPU) and a field - programmable gate array (FPGA) can be integrated in a device, and the CPU and the FPGA are used to collaboratively process packets to achieve efficient packet processing.

[0124] In the related art, through the Direct Memory Access (DMA) technology, the CPU and the FPGA can directly access the memory of the first device, thereby enabling the CPU and the FPGA to collaboratively process the received packets. Specifically, the CPU and the FPGA directly interact with the descriptors corresponding to the physical addresses of the descriptors in the memory and the storage area corresponding to the physical addresses of the packets.

[0125] First, the process of the CPU and the FPGA collaboratively processing packets in the related art will be described below.

[0126] Figure 1 This is the correspondence relationship between the physical address of the descriptor and the descriptor provided by the embodiment of the present application. As Figure 1 shown, it includes: multiple physical addresses of descriptors and multiple descriptors, where one physical address of a descriptor corresponds to one descriptor.

[0127] The multiple descriptors are stored in a circular descriptor queue.

[0128] The multiple physical addresses of descriptors include, for example, the physical address of descriptor 1, the physical address of descriptor 2, and the physical address of descriptor 3. The multiple descriptors include, for example, descriptor 1, descriptor 2, and descriptor 3.

[0129] Among them, the multiple physical addresses of descriptors are allocated by the CPU as consecutive multiple physical addresses of descriptors. After the CPU allocates consecutive multiple physical addresses of descriptors, the multiple physical addresses of descriptors can be written into the FPGA.

[0130] The CPU can also allocate consecutive multiple physical addresses of packets. The multiple physical addresses of packets include, for example, the physical address of packet 1, the physical address of packet 2, and the physical address of packet 3.

[0131] During the process of receiving packets, the CPU initializes the circular descriptor queue, and writes the multiple physical addresses of descriptors and the multiple physical addresses of packets into the multiple descriptors. Among them, one physical address of a descriptor and one physical address of a packet are written (or stored) into the corresponding one descriptor. Exemplarily, the physical address of descriptor 1 and the physical address of packet 1 are written (or stored) into descriptor 1. It should be noted that the physical address of the descriptor and the physical address of the packet written in the same descriptor can be considered associated.

[0132] During the process of receiving a message, the FPGA obtains the message physical address from the descriptor according to the descriptor physical address, writes the received message into the storage area corresponding to the message physical address, and writes back the length of the message, the receive side scaling - receive packet steering (RSS) value of the message, and the write completion flag bit to the descriptor.

[0133] During the process of sending a message, the CPU initializes the circular descriptor queue, writes multiple descriptor physical addresses, multiple message physical addresses, and the lengths of multiple messages into multiple descriptors. Among them, one descriptor physical address, one message physical address, and the length of one message are written (or stored) into the corresponding one descriptor, where one message corresponds to one message physical address. Exemplarily, the descriptor physical address 1, the message physical address 1, and the length of message 1 are written (or stored) into descriptor 1, where the physical address of message 1 is the message physical address 1.

[0134] During the process of sending a message, the FPGA obtains the message physical address and the length of the message from the descriptor according to the descriptor physical address, obtains the message from the storage area corresponding to the message physical address according to the length of the message, writes back the read completion flag bit to the descriptor, and sends the obtained message under the control of the CPU.

[0135] The following combines Figure 2 , to illustrate the operations performed by the CPU during the process of receiving a message.

[0136] Figure 2 It is the processing flow of the CPU when receiving a message in the related technology. As Figure 2 shown, it includes:

[0137] S201. After the FPGA writes back the length of the message, the RSS value of the message, and the write completion flag bit to the descriptor in the circular descriptor queue, obtain the descriptor indicated by the current value of the pointer of the circular descriptor queue from the circular descriptor queue.

[0138] S202. Determine whether the write completion flag bit in the descriptor exists.

[0139] If it exists, execute S203; otherwise, execute S202.

[0140] S203. Obtain the message according to the message physical address in the descriptor, and process the message according to the length of the message and the RSS value of the message in the descriptor.

[0141] S204. Determine whether the current value of the pointer of the circular descriptor queue is equal to a multiple of the first quantity.

[0142] If yes, execute S205; otherwise, execute S206.

[0143] S205: Release descriptors in batches, and rewrite the descriptor physical address, packet physical address, etc. into the released descriptors.

[0144] S206: Update the current value of the pointer of the circular descriptor queue.

[0145] Based on Figure 2 the related technology shown above, the FPGA needs to write a write completion flag bit in the descriptor to indicate that the CPU obtains the packet. After releasing the descriptor, the CPU needs to rewrite the descriptor physical address. Both the FPGA's writing of the write completion flag bit and the CPU's writing of the descriptor physical address will occupy the PCIE bandwidth, increasing the latency of receiving packets.

[0146] Based on the above technical problems, the technical concept of the embodiments of the present application is as follows: The FPGA receives the first packet from the second device according to the descriptor physical address, where the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue; the FPGA stores the parsing information of the first packet according to the descriptor physical address; the FPGA stores the first packet according to the packet physical address associated with the descriptor physical address and updates the current value of the head pointer of the first queue; when the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the packet physical address and the parsing information of the first packet according to the descriptor physical address indicated by the current value of the tail pointer; the CPU obtains the first packet according to the packet physical address, processes the first packet according to the length and RSS value of the first packet, and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0147] Through the above method, it is realized that the FPGA does not need to write a write completion flag bit in the descriptor corresponding to the descriptor physical address. By the difference between the current value of the tail pointer and the current value of the head pointer, it can be indicated that the FPGA has stored the first packet, which can reduce the occupied PCIE bandwidth and reduce the latency of receiving packets.

[0148] The following combines Figure 3 to illustrate the operations performed by the CPU during the process of sending packets.

[0149] Figure 3 The following is the processing flow of the CPU when sending packets in the related technology. As Figure 3 shown, it includes:

[0150] S301. After the FPGA writes the read completion flag bit back to the descriptor in the circular descriptor queue, obtain the descriptor currently pointed to by the pointer of the circular descriptor queue from the circular descriptor queue.

[0151] S302. Determine whether the read completion flag bit in the descriptor exists.

[0152] If it exists, execute S303; otherwise, execute S302.

[0153] S303. Control the FPGA to send the packet corresponding to the descriptor.

[0154] S304. Determine whether the current value of the pointer of the circular descriptor queue is equal to a multiple of the first quantity.

[0155] If it is, execute S305; otherwise, execute S306.

[0156] S305. Batch release the descriptors, and rewrite the descriptor physical address, packet physical address, and packet length, etc. in the released descriptors.

[0157] S306. Update the current value of the pointer of the circular descriptor queue.

[0158] Based on Figure 3 In the related technology shown, the FPGA needs to write the read completion flag bit in the descriptor to indicate that the CPU controls the FPGA to send the packet. When releasing the descriptor, the CPU needs to rewrite the descriptor physical address. Both the FPGA's writing of the read completion flag bit and the CPU's writing of the descriptor physical address will occupy the PCIE bandwidth, increasing the latency of sending the packet.

[0159] Based on the above technical problems, the technical concept of the embodiment of this application is as follows: The FPGA obtains the packet physical address associated with the descriptor physical address and the length of the first packet according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue; the FPGA obtains the first packet according to the packet physical address and length, and updates the current value of the head pointer of the first queue; when the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first packet to the second device according to the descriptor physical address, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0160] Through the above method, it is realized that the FPGA does not need to write the read completion flag bit in the descriptor corresponding to the descriptor physical address. By the difference between the current value of the tail pointer and the current value of the head pointer, it can be indicated that the FPGA has obtained and stored the first packet, which can reduce the occupation of the PCIE bandwidth and reduce the latency of sending the packet.

[0161] The following uses specific embodiments to elaborate in detail on the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0162] Figure 4 Flow schematic of a message receiving method provided for an embodiment of this application Figure 1 , such as Figure 4 shown, this method includes:

[0163] S401. Receive a first message from a second device by an FPGA according to a descriptor physical address, where the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of a first queue.

[0164] The FPGA is the FPGA of the first device. For simplicity of description, in all embodiments mentioned in this article, if there is no additional description, the FPGA is defaulted to the FPGA in the first device.

[0165] The descriptor physical address is one of at least one descriptor physical address, and the at least one descriptor physical address is pre-stored in the first queue.

[0166] The current value of the head pointer of the first queue is used to indicate one descriptor physical address among the at least one descriptor physical address stored in the first queue.

[0167] The first queue can be a circular queue, and this circular queue can be called a used circular descriptor queue.

[0168] The first queue includes N ordered data structure units, and each data structure unit pre-stores a descriptor physical address. N is an integer greater than or equal to 1.

[0169] Among them, N can be flexibly adjusted according to the message receiving requirements of the first device and / or the performance requirements of the first device. The value range of N can be between 1024 and 8112, and a common value of N is 4096.

[0170] Exemplarily, in a scenario where the first device is applied to a scenario with extremely high real-time requirements and large message receiving requirements, N can be 8112 to ensure that enough descriptor physical addresses can be stored.

[0171] Exemplarily, in a scenario where the first device is applied to a scenario with small message receiving requirements, N can be 1024 to save memory resources in the first device.

[0172] Next, the process of receiving the first packet from the second device by the FPGA according to the physical address of the descriptor will be described.

[0173] In one implementation, the FPGA obtains the physical address of the descriptor pointed to by the current head pointer according to the current value of the head pointer of the first queue; the FPGA obtains the packet queue number according to the physical address of the descriptor; when the FPGA obtains the packet queue number, it can receive the first packet from the second device according to the packet queue number; when the FPGA does not obtain the packet queue number, it can also directly receive the first packet from the second device.

[0174] Optionally, the first device can be a packet receiving device, and the second device can be a packet sending device, or the first device can be a packet sending device, and the second device can be a packet receiving device.

[0175] During the process of receiving packets, the first device can be a packet receiving device, and the second device can be a packet sending device.

[0176] During the process of sending packets, the first device can be a packet sending device, and the second device can be a packet receiving device.

[0177] In one implementation, the first packet can be a packet sent by the second device to the first device using the large packet transmission method based on TLP.

[0178] In the related art, the second device uses the small packet transmission method based on TLP to send the first packet to the first device. In this transmission method, if the data volume of the first packet is large, the second device will split the first packet into multiple second packets with smaller data volumes and send them to the first device. The first device receives multiple second packets through the FPGA and reassembles the multiple second packets to obtain the first packet. In the embodiments of the present application, the second device uses the large packet transmission method based on TLP to send the first packet to the first device, and the first device does not need to reassemble the first packet, which can reduce the delay of the first device receiving the packet.

[0179] S402. The FPGA stores the parsing information of the first packet and stores the first packet according to the physical address of the descriptor, and updates the current value of the head pointer of the first queue.

[0180] In one implementation, when the FPGA receives the first packet, it can obtain the parsing information of the first packet.

[0181] The parsing information of the first packet at least includes: the length of the first packet and the Receive Side Scaling - Receive Packet Steering (RSS) value when receiving the first packet.

[0182] It should be noted that when the FPGA receives the first packet, the parsing information of the first packet can be obtained, which can refer to the related technology and will not be elaborated here.

[0183] In one implementation, the parsing information of the first packet can be stored in the descriptor corresponding to the physical address of the descriptor.

[0184] In one implementation, the FPGA stores the first packet according to the physical address of the packet associated with the physical address of the descriptor.

[0185] Next, the process of the FPGA storing the first packet according to the physical address of the packet associated with the physical address of the descriptor will be described.

[0186] In one implementation, the FPGA obtains the physical address of the packet according to the physical address of the descriptor; the FPGA stores the first packet according to the physical address of the packet.

[0187] In one implementation, the first packet is stored in the storage area corresponding to the physical address of the packet.

[0188] In one implementation, updating the current value of the head pointer of the first queue can be understood as adding 1 to the current value of the head pointer.

[0189] Exemplarily, when the head pointer is 0 and points to the physical address of the descriptor in the first data structure unit, the head pointer is updated to 1, and when the head pointer is 1, it points to the physical address of the descriptor in the second data structure unit.

[0190] S403. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0191] If so, execute S403; otherwise, execute S404.

[0192] The CPU is the CPU of the first device. For simplicity of description, in all embodiments mentioned in this article, unless otherwise stated, the CPU mentioned is defaulted to the CPU in the first device.

[0193] The current value of the tail pointer and the current value of the head pointer of the first queue are used by the CPU to determine whether the FPGA has stored the first packet.

[0194] When the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU determines that the FPGA has stored the first packet.

[0195] When the current value of the tail pointer of the first queue is the same as the current value of the head pointer, the CPU determines that the FPGA has not stored the first packet.

[0196] S404. The CPU obtains the first packet and the first packet parsing information according to the descriptor physical address indicated by the current value of the tail pointer.

[0197] In one implementation, the CPU obtains the packet physical address according to the descriptor physical address, and obtains the first packet according to the packet physical address.

[0198] In one implementation, the CPU obtains the first packet from the storage area corresponding to the packet physical address.

[0199] In one implementation, the CPU obtains the first packet parsing information from the descriptor corresponding to the descriptor physical address.

[0200] S405. The CPU processes the first packet according to the parsing information of the first packet and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0201] In one implementation, the CPU processes the first packet according to the length and RSS value of the first packet included in the parsing information. The specific processing process can refer to the related technology and will not be elaborated here.

[0202] In one implementation, updating the current value of the tail pointer of the first queue can be understood as adding 1 to the current value of the tail pointer.

[0203] Beneficial effects of this embodiment: In this embodiment, after the FPGA stores the first packet, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the first packet, realizing that the difference between the current value of the tail pointer and the current value of the head pointer indicates that the FPGA has stored the first packet. The FPGA does not need to store the write completion flag bit in the descriptor corresponding to the descriptor physical address, which can reduce the PCIE bandwidth occupancy and reduce the latency of receiving packets. In the related technology, the FPGA needs to store the write completion flag bit in the descriptor corresponding to the descriptor physical address, which will cause a large occupancy of the PCIE bandwidth and a high latency of receiving packets.

[0204] Figure 5 Flow schematic of a packet receiving method provided by an embodiment of the present application Figure 2 , as Figure 5 shown, the method includes:

[0205] S501. The FPGA receives the first packet from the second device according to the descriptor physical address, and the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue.

[0206] Next, the process of receiving the first message from the second device by the FPGA according to the physical address of the descriptor will be described.

[0207] In one implementation, the FPGA obtains the physical address of the descriptor pointed to by the current head pointer according to the current value of the head pointer of the first queue; the FPGA determines the descriptor corresponding to the physical address of the descriptor according to the physical address of the descriptor; the FPGA obtains the message queue number in the descriptor; when the FPGA obtains the message queue number, it can receive the first message from the second device according to the message queue number; when the FPGA does not obtain the message queue number, it can also receive the first message from the second device.

[0208] S502. The FPGA determines the descriptor corresponding to the physical address of the descriptor.

[0209] The physical address of the descriptor is one of at least one physical address of the descriptor, and at least one physical address of the descriptor is pre-stored in the first queue. At least one physical address of the descriptor corresponds to at least one descriptor one by one, where one physical address of the descriptor corresponds to the descriptor corresponding to one physical address of the descriptor. The descriptor corresponding to the physical address of the descriptor can be stored in the storage area corresponding to the physical address of the descriptor. The descriptor may include the physical address of the descriptor and the physical address of the message. In one descriptor, the physical address of the descriptor and the physical address of the message included therein can be considered associated, that is, the physical address of the descriptor is associated with the physical address of the message, or one physical address of the descriptor corresponds to one physical address of the message.

[0210] In one implementation, the FPGA determines the descriptor corresponding to the physical address of the descriptor according to the correspondence between at least one physical address of the descriptor and at least one descriptor.

[0211] S503. The FPGA stores the parsing information of the first message into the descriptor corresponding to the physical address of the descriptor.

[0212] S504. The FPGA obtains the physical address of the message from the descriptor corresponding to the physical address of the descriptor.

[0213] S505. The FPGA determines the storage area corresponding to the physical address of the message.

[0214] In one implementation, the storage area in the memory having the physical address of the message is determined as the storage area corresponding to the physical address of the message.

[0215] S506. The FPGA stores the first message into the storage area corresponding to the physical address of the message and updates the current value of the head pointer of the first queue.

[0216] The storage area corresponding to the descriptor physical address and the storage area corresponding to the packet physical address are both located in the memory of the first device.

[0217] The FPGA can access the memory through the DMA technology. The FPGA's access to the memory includes but is not limited to: the FPGA stores the parsing information of the first packet into the descriptor corresponding to the descriptor physical address, the FPGA obtains the packet physical address from the descriptor corresponding to the descriptor physical address, and the FPGA stores the first packet into the storage area corresponding to the packet physical address, etc.

[0218] S507: The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0219] If so, execute S507; otherwise, execute S508.

[0220] S508: The CPU obtains the packet physical address and the parsing information of the first packet according to the descriptor physical address indicated by the current value of the tail pointer.

[0221] Next, the process of the CPU obtaining the packet physical address and the parsing information of the first packet according to the descriptor physical address indicated by the current value of the tail pointer will be described.

[0222] In one implementation, the CPU determines the descriptor corresponding to the descriptor physical address according to the current value of the tail pointer; the CPU obtains the packet physical address and the parsing information of the first packet from the descriptor.

[0223] The CPU can access the memory through the DMA technology. The CPU's access to the memory includes but is not limited to: the CPU obtains the packet physical address and the parsing information of the first packet from the descriptor corresponding to the descriptor physical address.

[0224] S509: The CPU obtains the first packet according to the packet physical address, processes the first packet according to the parsing information of the first packet, and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0225] Next, the process of the CPU obtaining the first packet according to the packet physical address will be described.

[0226] In one implementation, the CPU determines the storage area corresponding to the packet physical address according to the packet physical address; the CPU obtains the first packet in the storage area corresponding to the packet physical address.

[0227] Before receiving the packet, the first device can also perform initialization processing. The following is combined with Figure 6Describe a message receiving method involving initialization processing.

[0228] Figure 6 The flowchart of a message receiving method provided by an embodiment of this application Figure 3 , as Figure 6 shown, this method includes:

[0229] S601. Allocate at least one consecutive descriptor physical address and at least one message physical address through the CPU, where at least one descriptor physical address is associated with at least one message physical address.

[0230] Specifically, the first device allocates at least one consecutive descriptor physical address and at least one message physical address in the memory of the first device through the CPU. Among them, one descriptor physical address corresponds to the descriptor corresponding to this descriptor physical address in the memory of the first device. One message physical address corresponds to the storage area corresponding to this message physical address in the memory of the first device.

[0231] S602. Initialize the first queue and the second queue.

[0232] After initialization, the first queue and the second queue store at least one descriptor physical address. The current values of the head pointer and the tail pointer of the first queue are the first preset value, and the current value of the pointer of the second queue is the first preset value.

[0233] The first preset value is, for example, 0.

[0234] The current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device has received the first message. It can also be understood that the current values of the tail pointer and the head pointer of the first queue are used for the CPU to determine whether the FPGA has stored the first message.

[0235] The second queue can be a circular queue, and this circular queue can be called an available descriptor circular queue.

[0236] The current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

[0237] S603. For one descriptor physical address among at least one descriptor physical address and the message physical address associated with the descriptor physical address, store the descriptor physical address and the message physical address associated with the descriptor physical address to the descriptor corresponding to the descriptor physical address through the CPU.

[0238] In one implementation, when the first device supports sending messages in multiple queues, the CPU can also store the message queue number to the descriptor corresponding to the descriptor physical address.

[0239] S604. Write the physical addresses of at least one descriptor into the FPGA through the CPU.

[0240] S605. Execute S401 to S406, or S501 to S509.

[0241] In some embodiments, when the number of first messages received by the first device reaches the first quantity, release the first quantity of descriptors in batch. The following describes the message receiving method involving batch release in conjunction with Figure 7 the description of the message receiving method involving batch release will be given.

[0242] Figure 7 The flowchart of a message receiving method provided by an embodiment of the present application Figure 4 , as Figure 7 shown, the method includes:

[0243] S701. Execute S401 to S406, S501 to S509, or S601 to S605.

[0244] S702. Determine, through the CPU, whether the current value of the head pointer of the first queue is equal to a multiple of the first quantity.

[0245] The first quantity is, for example, 32.

[0246] Optionally, the first quantity can be set according to the expected number of first messages to be received.

[0247] If so, execute S703; otherwise, execute S701.

[0248] S703. Determine, through the CPU, whether the current value of the pointer of the second queue is the same as the current value of the head pointer.

[0249] If so, execute S701; otherwise, execute S704.

[0250] S704. Release, through the CPU, the message physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor in batch, where the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the head pointer.

[0251] Exemplarily, the first preset value of the head pointer is 0, the first quantity is 32. When the current value of the pointer of the second queue is 0 and the current value of the head pointer is 32, the target descriptor is: the descriptor corresponding to the physical address of the descriptor pointed to when the head pointer is 32, and the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor are: the descriptors corresponding to the physical addresses of the descriptors pointed to when the head pointer is 0 to the descriptors corresponding to the physical addresses of the descriptors pointed to when the head pointer is 31.

[0252] In one implementation, when including the message queue number in the descriptor, the message queue numbers in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor can also be released in batches.

[0253] S705. Update the current value of the pointer of the second queue to the current value of the head pointer by rewriting the new message physical address in each of the first quantity of these descriptors through the CPU.

[0254] The current value of the pointer of the second queue is used to indicate whether to release the message physical addresses in the first quantity of descriptors in batches.

[0255] In one implementation, when the first device supports multi-queue message sending, the message queue numbers can also be rewritten in each of the first quantity of these descriptors through the CPU.

[0256] Beneficial effects of this embodiment: In this embodiment, if the CPU determines that the current value of the head pointer is a multiple of the first quantity and the current value of the pointer of the second queue is different from the current value of the head pointer, the message physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor are released in batches. This helps to rewrite the new message physical address in each of the first quantity of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors, which can improve the efficiency of release and rewrite, thereby reducing the occupation of the PCIE bandwidth and reducing the delay of receiving messages. In the related art, before storing the write completion flag bit in the descriptor corresponding to the descriptor physical address in the FPGA, the descriptor physical address and the message physical address have already been stored in the descriptor. Since the amount of data that the descriptor can carry is limited, the write completion flag bit will occupy the descriptor physical address, resulting in an incorrect descriptor physical address. Therefore, when releasing in batches, it is necessary to release all of the descriptor physical address, message physical address, etc., in order to re-store the physical address of the descriptor, the new message physical address, etc., resulting in a low efficiency of release and rewrite, and thus a large occupation of the PCIE bandwidth and a high delay of receiving messages.

[0257] Figure 8 Schematic flow of a message sending method provided by an embodiment of the present application Figure 1 , as Figure 8 shown, the method includes:

[0258] S801. Obtain the message physical address associated with the descriptor physical address and the length of the first message according to the descriptor physical address through the FPGA, where the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue.

[0259] Next, the process of obtaining the physical address of the message associated with the descriptor physical address and the length of the first message by the FPGA according to the descriptor physical address will be described.

[0260] In one implementation,

[0261] The FPGA obtains the descriptor physical address pointed to by the current head pointer according to the current value of the head pointer of the first queue;

[0262] The FPGA obtains the physical address of the message associated with the descriptor physical address and the length of the first message according to the descriptor physical address.

[0263] S802. Obtain the first message by the FPGA according to the physical address of the message associated with the descriptor physical address and the length of the first message, and update the current value of the head pointer of the first queue.

[0264] In one implementation, the FPGA stores the obtained first message in the cache of the FPGA.

[0265] Among them, the cache of the FPGA can be a First In First Out Buffer (FIFO).

[0266] S803. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0267] If so, execute S803; otherwise, execute S804.

[0268] S804. The CPU controls the FPGA to send the obtained first message to the second device according to the descriptor physical address, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0269] Next, the process of the CPU controlling the FPGA to send the obtained first message to the second device according to the descriptor physical address will be described.

[0270] In one implementation, the CPU sends a control signal to the FPGA, and the control signal instructs the FPGA to send the first message to the second device; after receiving the control signal, the FPGA sends the obtained first message to the second device according to the descriptor physical address.

[0271] Next, the process of the FPGA sending the obtained first message to the second device according to the descriptor physical address will be described.

[0272] In one implementation, the FPGA obtains the message queue number according to the descriptor physical address; when the FPGA obtains the message queue number, it can send the obtained first message to the second device according to the message queue number; when the FPGA fails to obtain the message queue number, it can also send the obtained first message to the second device.

[0273] The first message can be a message sent by the first device to the second device using the large packet transmission method based on TLP.

[0274] In the related art, the first device uses the small packet transmission method based on TLP to send the first message to the second device. In this transmission method, if the data volume of the first message is large, the first device will split the first message into multiple second messages with smaller data volumes and send them to the second device. In the embodiments of the present application, the first device uses the large packet transmission method based on TLP to send the first message to the second device, without splitting the first message, which can reduce the delay of the first device sending the message.

[0275] The beneficial effect of this embodiment: After the FPGA obtains the first message, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first message to the second device, realizing that when the current value of the tail pointer is different from the current value of the head pointer, it indicates that the FPGA has obtained and stored the first message. The FPGA does not need to store the read completion flag bit in the descriptor corresponding to the descriptor physical address, which can reduce the PCIE bandwidth occupation and reduce the delay of sending the message. In the related art, the FPGA needs to store the read completion flag bit in the descriptor corresponding to the descriptor physical address, which will cause a large occupation of the PCIE bandwidth and result in a high delay of sending the message.

[0276] Figure 9 Flow schematic of a message sending method provided by an embodiment of the present application Figure 2 as Figure 9 shown, the method includes:

[0277] S901. The FPGA determines the descriptor corresponding to the descriptor physical address.

[0278] It should be noted that the execution method of S901 is similar to that of S502, and will not be elaborated here.

[0279] S902. The FPGA obtains the message physical address associated with the descriptor physical address and the length of the first message from the descriptor corresponding to the descriptor physical address.

[0280] S903. The FPGA determines the storage area corresponding to the message physical address.

[0281] S904. The FPGA obtains the first message from the storage area corresponding to the physical address of the message according to the length of the first message, and updates the current value of the head pointer of the first queue.

[0282] Next, the process of the FPGA obtaining the first message from the storage area corresponding to the physical address of the message according to the length of the first message will be described.

[0283] In one implementation, the FPGA obtains the physical address of the message from the descriptor corresponding to the physical address of the descriptor; the FPGA obtains the first message from the storage area corresponding to the physical address of the message according to the length of the first message.

[0284] S905. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0285] If so, execute S905; otherwise, execute S906.

[0286] S906. The CPU controls the FPGA to send the obtained first message to the second device according to the physical address of the descriptor, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0287] Next, the process of the FPGA sending the obtained first message to the second device according to the physical address of the descriptor will be described.

[0288] In one implementation, the FPGA determines the descriptor corresponding to the physical address of the descriptor according to the physical address of the descriptor; the FPGA obtains the message queue number in the descriptor; when the FPGA obtains the message queue number, it can send the first message to the second device according to the message queue number; when the FPGA does not obtain the message queue number, it can also send the first message to the second device.

[0289] Before message sending, the first device can also perform initialization processing. The following combines Figure 10 The message sending method involving initialization processing will be described.

[0290] Figure 10 A flowchart of a message sending method provided by an embodiment of the present application Figure 3 is shown in Figure 10 and includes:

[0291] S1001. The CPU allocates at least one consecutive physical address of the descriptor and at least one physical address of the message, where at least one physical address of the descriptor is associated with at least one physical address of the message.

[0292] S1002. Initialize the first queue and the second queue.

[0293] After initialization, the first queue and the second queue store at least one descriptor physical address. The current values of the head pointer and the tail pointer of the first queue are the first preset values, and the current value of the pointer of the second queue is the first preset value.

[0294] The current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device sends the first message. It can also be understood that the current value of the tail pointer and the current value of the head pointer of the first queue are used for the CPU to determine whether the FPGA has acquired and stored the first message.

[0295] The current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

[0296] S1003. For one descriptor physical address among at least one descriptor physical address and the message physical address associated with the descriptor physical address, the CPU stores the descriptor physical address, the message physical address associated with the descriptor physical address, and the length of the first message into the descriptor corresponding to the descriptor physical address.

[0297] In one implementation, when the first device supports receiving messages in multiple queues, the CPU can also store the message queue number into the descriptor corresponding to the descriptor physical address.

[0298] S1004. The CPU writes at least one descriptor physical address into the FPGA.

[0299] S1005. Execute S801 to S804, or S901 to S906.

[0300] In some embodiments, when the number of first messages sent by the first device reaches the first quantity, batch release the first quantity of descriptors. The following combines Figure 11 to illustrate the message sending method involving batch release.

[0301] Figure 11 The flowchart of a message sending method provided by an embodiment of the present application Figure 4 is as Figure 11 shown. The method includes:

[0302] S1101. Execute S801 to S804, S901 to S906, or S1001 to S1005.

[0303] S1102. The CPU determines whether the current value of the head pointer is equal to a multiple of the first quantity.

[0304] If so, execute S1103; otherwise, execute S1101.

[0305] S1103. Determine whether the current value of the pointer of the second queue is the same as the current value of the head pointer through the CPU.

[0306] If so, execute S1101; otherwise, execute S1104.

[0307] S1104. Release in batch through the CPU the packet physical address and the length of the first packet in the descriptors corresponding to the physical addresses of the first number of descriptors before the target descriptor, where the target descriptor is the descriptor corresponding to the physical address pointed to by the head pointer currently.

[0308] In an implementation, when the packet queue number is included in the descriptor, the packet queue numbers in the descriptors corresponding to the physical addresses of the first number of descriptors before the target descriptor can also be released in batch.

[0309] S1105. Rewrite the new packet physical address and the length of the new packet in each of the first number of such storage areas through the CPU, and update the current value of the pointer of the second queue to the current value of the head pointer.

[0310] The current value of the pointer of the second queue is used to indicate whether to release in batch the packet physical address and the length of the packet in the first number of descriptors before the target descriptor.

[0311] In an implementation, when the first device supports receiving packets in multiple queues, the packet queue numbers can also be rewritten in each of the first number of such descriptors through the CPU.

[0312] Advantages of this embodiment: If the CPU determines that the current value of the head pointer is a multiple of the first quantity, and the current value of the pointer of the second queue is different from the current value of the head pointer, then the packet physical addresses and the length of the first packet in the descriptors corresponding to the physical addresses of the first quantity of descriptors before the target descriptor are released in batches. This helps to rewrite the new packet physical addresses and the length of the new packet in each of the first quantity of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the physical addresses of the first quantity of descriptors, which can improve the efficiency of release and rewrite, thereby reducing the occupation of the PCIE bandwidth and reducing the latency of receiving packets. In the related art, before the write completion flag bit is stored in the descriptor corresponding to the descriptor physical address in the FPGA, the descriptor physical address, the packet physical address, and the length of the first packet have already been stored in the descriptor. Since the amount of data that the descriptor can carry is limited, the write completion flag bit will occupy the descriptor physical address, resulting in an incorrect descriptor physical address. Therefore, when releasing in batches, it is necessary to release all of the descriptor physical address, the packet physical address, etc., in order to re-store the physical address of the descriptor, the new packet physical address, etc., resulting in a low efficiency of release and rewrite, and further resulting in a large occupation of the PCIE bandwidth and a high latency of sending packets.

[0313] Figure 12 The structural schematic diagram of a packet transmission device provided by an embodiment of the present application. The packet transmission device is applied to a first device, such as Figure 12 shown, the packet transmission device 120 includes: a first processing module 1201 and a second processing module 1202.

[0314] In some embodiments, the first processing module 1201 is, for example, an FPGA, and the second processing module 1202 is, for example, a CPU.

[0315] In some embodiments, when the packet transmission device 120 is used to receive a first packet from a second device, the packet transmission device 120 can also be referred to as a packet receiving device.

[0316] In some embodiments, when the packet transmission device 120 is used to send a first packet to a second device, the packet transmission device 120 can also be referred to as a packet sending device.

[0317] When the packet transmission device 120 is used to receive a first packet from a second device, the first processing module 1201 and the second processing module 1202 are used to perform the following operations:

[0318] The first processing module 1201 is used to receive a first packet from the second device according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0319] The first processing module 1201 is further configured to store the parsing information of the first packet and the first packet according to the physical address of the descriptor, and update the current value of the head pointer of the first queue;

[0320] The second processing module 1202 is configured to, when determining that the current value of the tail pointer of the first queue is different from the current value of the head pointer, obtain the physical address of the packet and the parsing information according to the physical address of the descriptor indicated by the current value of the tail pointer;

[0321] The second processing module 1202 is further configured to obtain the first packet according to the physical address of the packet, process the first packet according to the parsing information, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0322] It should be noted here that the above packet transmission device 120 provided in the embodiment of the present application can implement the method steps in the method embodiment when the first device receives the first packet from the second device, and can achieve the same technical effect. The same parts and beneficial effects as those in the method embodiment will not be specifically described in this embodiment.

[0323] In some embodiments, the first processing module 1201 is specifically configured to:

[0324] Determine the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0325] Store the parsing information to the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0326] In some embodiments, the first processing module 1201 is specifically configured to:

[0327] Obtain the physical address of the packet from the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0328] Determine the storage area corresponding to the physical address of the packet through the FPGA;

[0329] Store the first packet to the storage area corresponding to the physical address of the packet through the FPGA.

[0330] In some embodiments, the second processing module 1202 is further configured to:

[0331] The CPU allocates at least one consecutive descriptor physical address and at least one packet physical address, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0332] For one descriptor physical address among the at least one descriptor physical address and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address;

[0333] The CPU writes the at least one descriptor physical address into the FPGA.

[0334] In some embodiments, the second processing module 1202 is further configured to:

[0335] Initialize a first queue and a second queue;

[0336] Wherein, after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used by the CPU to determine whether the first device has received a first packet, and the current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to batch release descriptors.

[0337] In some embodiments, the second processing module 1202 is further configured to:

[0338] When the CPU determines that the current value of the head pointer is a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, then batch release the packet physical addresses in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor; wherein, the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer;

[0339] The CPU rewrites a new packet physical address into each of the first quantity of descriptors, and updates the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the packet physical addresses in the first quantity of descriptors.

[0340] It should be noted here that the above message transmission device 120 provided in the embodiments of the present application can implement the method steps in the method embodiments when the first device receives the first message from the second device, and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described herein.

[0341] During the process of the message transmission device 120 sending the first message to the second device, the first processing module 1201 and the second processing module 1202 are used to perform the following operations:

[0342] The first processing module 1201 is used to obtain the message physical address associated with the descriptor physical address and the length of the first message according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue.

[0343] The first processing module 1201 is used to obtain the first message according to the message physical address and the length, and update the current value of the head pointer of the first queue.

[0344] When the second processing module 1202 determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, it controls the first processing module 1201 to send the obtained first message to the second device according to the descriptor physical address, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0345] It should be noted here that the above message transmission device 120 provided in the embodiments of the present application can implement the method steps in the method embodiments when the first device sends the first message to the second device, and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described herein.

[0346] In some embodiments, the first processing module 1201 is specifically used for:

[0347] Determine the descriptor corresponding to the descriptor physical address;

[0348] Obtain the message physical address associated with the descriptor physical address and the length of the first message from the descriptor corresponding to the descriptor physical address.

[0349] In some embodiments, the first processing module 1201 is specifically used for:

[0350] Determine the storage area corresponding to the message physical address;

[0351] Obtain the first message from the storage area corresponding to the message physical address according to the length.

[0352] In some embodiments, the second processing module 1202 is further configured to:

[0353] Allocate at least one consecutive descriptor physical address and at least one packet physical address, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0354] For one descriptor physical address in the at least one descriptor physical address and the packet physical address associated with the descriptor physical address, store the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet into the descriptor corresponding to the descriptor physical address;

[0355] Write the at least one descriptor physical address to the first processing module 1201.

[0356] In some embodiments, after allocating the at least one consecutive descriptor physical address and at least one packet physical address, the second processing module 1202 is further configured to:

[0357] Initialize a first queue and a second queue;

[0358] Wherein, after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used by the second processing module 1202 to determine whether the first device sends the first packet, and the current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

[0359] In some embodiments, the second processing module 1202 is further configured to:

[0360] When it is determined that the current value of the head pointer is a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, batch release the packet physical addresses and the length of the first packet in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor; wherein the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer;

[0361] Rewrite a new packet physical address and the length of the new packet in each of the first quantity of descriptors, and update the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the packet physical addresses in the first quantity of descriptors and the length of the first packet.

[0362] It should be noted here that the above-mentioned packet transmission device 120 provided in the embodiments of the present application can implement the method steps in the method embodiments when the first device sends the first packet to the second device, and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described in this embodiment.

[0363] It should be understood that the above-mentioned packet transmission device 120 is embodied in the form of functional modules. The term "module" here may refer to an application-specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group of processors, etc.) for executing one or more software or firmware programs, and a memory, a combined logic circuit and / or other suitable components that support the described functions.

[0364] Figure 13 This is a structural diagram of an electronic device provided in the embodiments of the present application. As Figure 13 shown, the electronic device 130 includes a processor 1301 and a memory 1302. Among them, the processor 1301 is communicatively connected to the memory 1302, and the memory 1302 is used to store computer execution instructions; the processor 1301 is configured to execute the technical solutions in any of the foregoing method embodiments by executing the computer execution instructions stored in the memory 1302.

[0365] Optionally, the memory 1302 can be either independent or integrated with the processor 1301. Optionally, when the memory 1302 is a device independent of the processor 1301, the electronic device 1300 may further include: a bus 1303 for connecting the above-mentioned devices.

[0366] This electronic device is used to execute the technical solutions in any of the foregoing method embodiments, and its implementation principles and technical effects are similar, which will not be elaborated here.

[0367] The embodiments of the present application further provide a computer-readable storage medium, in which computer execution instructions are stored, and when the computer execution instructions are executed by a processor, they are used to implement the technical solutions provided in any of the foregoing method embodiments.

[0368] An embodiment of this application also provides a computer program product, including a computer program which, when executed by a processor, is used to implement the technical solutions provided in the foregoing method embodiments.

[0369] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0370] Furthermore, it should be noted that although the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0371] It should be understood that the above device embodiments are illustrative, and the devices of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0372] In addition, without special description, in each embodiment of this application, each functional unit / module can be integrated in one unit / module, or each unit / module can exist physically alone, or two or more units / modules can be integrated together. The above integrated unit / module can be implemented in the form of hardware or in the form of a software program module.

[0373] When the integrated unit / module is implemented in the form of hardware, the hardware can be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0374] When the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. And the aforementioned memory includes: USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs, etc., all kinds of media that can store program codes.

[0375] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as the scope described in this specification.

[0376] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only illustrative, and the true scope and spirit of the present application are pointed out by the following claims.

[0377] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A message receiving method, characterized in that, Applied to a first device, the first device includes a central processing unit (CPU) and a field programmable gate array (FPGA), and the method includes: Receiving, by the FPGA, a first message from a second device according to a descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of a first queue; Storing, by the FPGA, the parsing information of the first message and the first message according to the descriptor physical address, and updating the current value of the head pointer of the first queue; When it is determined by the CPU that the current value of the tail pointer of the first queue is different from the current value of the head pointer, obtaining, by the CPU, the first message and the parsing information according to the descriptor physical address indicated by the current value of the tail pointer; Processing, by the CPU, the first message according to the parsing information and updating the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

2. The method according to claim 1, wherein The storing, by the FPGA, the parsing information of the first message and the first message according to the descriptor physical address includes: Determining, by the FPGA, a descriptor corresponding to the descriptor physical address; Storing, by the FPGA, the parsing information into the descriptor corresponding to the descriptor physical address; Obtaining, by the FPGA, a message physical address from the descriptor corresponding to the descriptor physical address; Determining, by the FPGA, a storage area corresponding to the message physical address; Storing, by the FPGA, the first message into the storage area corresponding to the message physical address.

3. The method according to claim 1 or 2, characterized in that The method further includes: Allocating, by the CPU, at least one consecutive descriptor physical address and at least one message physical address, wherein the at least one descriptor physical address is associated with the at least one message physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one message physical address includes the message physical address; For one descriptor physical address among the at least one descriptor physical address and the message physical address associated with the descriptor physical address, storing, by the CPU, the descriptor physical address and the message physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address; Writing, by the CPU, the at least one descriptor physical address into the FPGA.

4. The method according to claim 3, characterized in that, After allocating, by the CPU, the at least one consecutive descriptor physical address and at least one message physical address, the method further includes: Initializing a first queue and a second queue; After initialization, the first queue and the second queue store the at least one descriptor physical address. The current values of the head pointer and the tail pointer of the first queue are a first preset value, and the current value of the pointer of the second queue is the first preset value. The current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device has received a first message. The current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to batch release descriptors.

5. The method according to claim 4, wherein The method further includes: When the CPU determines that the current value of the head pointer is a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, release the message physical addresses in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor in batch; wherein, the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer; Rewrite new message physical addresses in each of the first quantity of descriptors by the CPU, and update the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the message physical addresses in the first quantity of descriptors.

6. A message sending method, characterized in that, Applied to a first device, the first device includes a CPU and an FPGA, and the method includes: The FPGA obtains the message physical address associated with the descriptor physical address and the length of the first message according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue; The FPGA obtains the first message according to the message physical address and the length, and updates the current value of the head pointer of the first queue; When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first message to a second device according to the descriptor physical address, and updates the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

7. The method according to claim 6, wherein The obtaining, by the FPGA, of the message physical address associated with the descriptor physical address and the length of the first message according to the descriptor physical address includes: The FPGA determines the descriptor corresponding to the descriptor physical address; The FPGA obtains the message physical address associated with the descriptor physical address and the length of the first message from the descriptor corresponding to the descriptor physical address; The obtaining, by the FPGA, of the first message according to the message physical address and the length includes: The FPGA determines the storage area corresponding to the message physical address; The FPGA obtains the first message from the storage area corresponding to the message physical address according to the length.

8. The method according to claim 6 or 7, characterized in that, The method further includes: The CPU allocates at least one consecutive descriptor physical address and at least one message physical address, wherein the at least one descriptor physical address is associated with the at least one message physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one message physical address includes the message physical address; For one descriptor physical address among the at least one descriptor physical address and the message physical address associated with the descriptor physical address, the CPU stores the descriptor physical address, the message physical address associated with the descriptor physical address, and the length of the first message into the descriptor corresponding to the descriptor physical address; The CPU writes the at least one descriptor physical address into the FPGA.

9. The method according to claim 8, wherein After the CPU allocates the at least one consecutive descriptor physical address and at least one message physical address, the method further includes: Initializing a first queue and a second queue; Wherein, after initialization, the first queue and the second queue store the at least one descriptor physical address, the current values of the head pointer and the tail pointer of the first queue are a first preset value, the current value of the pointer of the second queue is the first preset value, the current values of the head pointer and the tail pointer of the first queue are used for the CPU to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to batch release the descriptors corresponding to the descriptor physical addresses.

10. The method according to claim 9, characterized in that, The method further includes: When the CPU determines that the current value of the head pointer is equal to a multiple of a first quantity, if the current value of the pointer of the second queue is different from the current value of the head pointer, batch release the message physical addresses and the length of the first message in the descriptors corresponding to the first quantity of descriptor physical addresses before the target descriptor; wherein, the target descriptor is the descriptor corresponding to the descriptor physical address currently pointed to by the head pointer; The CPU rewrites a new message physical address and the length of a new message into each of the first quantity of descriptors, and updates the current value of the pointer of the second queue to the current value of the head pointer; the current value of the pointer of the second queue is used to indicate whether to batch release the message physical addresses and the length of the first message in the first quantity of descriptors.

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