Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device includes a plurality of layers of memory cells stacked on a substrate at intervals in a direction perpendicular to the substrate; the memory unit comprises a transistor, and the transistor comprises a grid electrode extending towards the direction of the substrate, a semiconductor layer at least partially surrounding the side wall of the grid electrode, and a grid electrode insulating layer located between the grid electrode and the semiconductor layer; the transistor further comprises a first source / drain electrode, a second source / drain electrode and a protection layer, wherein the protection layer is at least located between the semiconductor layer and the first source / drain electrode and the second source / drain electrode. The semiconductor device comprises the protection layer, and the protection layer can be used for protecting the semiconductor layer so as to avoid the adverse effect of the manufacturing process on the semiconductor layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technologies, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technologies, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the needs of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, an exemplary embodiment of the present application provides a semiconductor device, including:

[0006] Multiple layers of memory cells stacked at intervals along a direction perpendicular to the substrate on the substrate;

[0007] The memory cell includes a transistor, the transistor includes a gate extending in a direction toward the substrate, a semiconductor layer at least partially surrounding the sidewalls of the gate, and a gate insulating layer located between the gate and the semiconductor layer;

[0008] The transistor further includes a first source / drain and a second source / drain, and a protective layer, and the protective layer is at least located between the semiconductor layer and the first source / drain and the second source / drain.

[0009] In some embodiments, the protective layer is in contact with the semiconductor layer and in contact with the first source / drain and the second source / drain.

[0010] In some embodiments, the material of the protective layer includes TiN or ITO.

[0011] In some embodiments, the protective layer surrounds the semiconductor layer, and in the circumferential direction of surrounding the semiconductor layer, the protective layer is separated into two parts, a first part is in contact with the first source / drain, and a second part is in contact with the second source / drain.

[0012] In some embodiments, the semiconductor layers of the memory cells in different layers are separated from each other; the protective layers of the memory cells in different layers are disconnected.

[0013] In some embodiments, it further includes a word line via and lateral grooves located in the word line via and distributed in different layers. The inner walls of the lateral grooves are sequentially provided with the protection layer and the semiconductor layer in the direction towards the word line. The first part and the second part of the protection layer surround the side walls of the semiconductor layer;

[0014] Both the protection layer and the semiconductor layer are distributed on the vertical side walls and the horizontal side walls of the lateral grooves.

[0015] In some embodiments, each of the transistors of the stacked memory cells in different layers shares a word line, and the gate of each transistor is a part of the corresponding word line; the word line includes a vertical portion extending in the direction towards the substrate and an extending portion extending from the vertical portion in a direction parallel to the substrate; the semiconductor layer and the protection layer are sequentially located on the surface of the extending portion according to the shape of the extending portion.

[0016] This application also provides a manufacturing method of a semiconductor device, including the following steps:

[0017] Form an insulating layer and a sacrificial layer alternately on a substrate to form a stacked structure;

[0018] Form a word line via penetrating the stacked structure;

[0019] Etch the sacrificial layer in the word line via in a direction parallel to the substrate to form lateral grooves;

[0020] Form a semiconductor layer in the lateral grooves;

[0021] Form a gate insulating layer and a word line in the word line via and the lateral grooves in sequence;

[0022] Wherein, before forming the semiconductor layer, a protection layer is formed in the lateral grooves;

[0023] After forming the protection layer and the semiconductor layer, replace the sacrificial layer with a conductive layer to form a first source / drain electrode and a second source / drain electrode in contact with the protection layer.

[0024] In some embodiments, the sacrificial layer and the protection layer have different etching selectivity ratios under the same etching conditions.

[0025] In some embodiments, the insulating layer is silicon oxide and the sacrificial layer is silicon nitride; the protection layer includes TiN and may further include metal oxides such as ITO or IGZO. The TiN or ITO is a conductive layer, and the IGZO can be a semiconductor layer.

[0026] In some embodiments, it further includes:

[0027] In the circumferential direction where the protective layer surrounds the semiconductor layer, a part of the protective layer is removed by etching, so that the protective layer is separated into two parts, a first part is in contact with the first source / drain, and a second part is in contact with the second source / drain.

[0028] In some embodiments, before forming the gate insulating layer and the word line,

[0029] Deposit a dummy material film in the word line hole and fill the lateral groove to form a dummy layer;

[0030] Etch and remove the semiconductor layer and the protective layer covering the insulating layer in the word line hole, and disconnect the semiconductor layer and the protective layer between different memory cells.

[0031] In some embodiments, the dummy layer is made of a material different from the protective layer and the semiconductor layer, and the dummy layer contains alumina.

[0032] In some embodiments, etching and removing the semiconductor layer and the protective layer covering the insulating layer in the word line hole includes:

[0033] Remove the dummy layer and the semiconductor layer covering the insulating layer through a first wet etching process;

[0034] Remove the protective layer covering the insulating layer through a second wet etching process, and retain the dummy layer in the lateral groove;

[0035] Remove the dummy layer in the lateral groove through a third wet etching process, and retain the protective layer and the semiconductor layer in the lateral groove.

[0036] In some embodiments, after forming the protective layer and the semiconductor layer in the lateral groove, further includes:

[0037] Thermally anneal the stacked structure within a temperature range of 300°C - 400°C.

[0038] In some embodiments, after forming the word line, includes:

[0039] Use phosphoric acid to remove the sacrificial layer in the regions corresponding to the first source / drain and the second source / drain to be formed, exposing the protective layer; replace the sacrificial layer with a conductive material to form a conductive layer in contact with the protective layer; the conductive layer includes a first source / drain and a second source / drain that are insulated from each other.

[0040] An embodiment of the present application provides an electronic device, including the semiconductor device described in any of the above embodiments, or the electronic device is manufactured by the manufacturing method provided in any of the above embodiments.

[0041] Other features and advantages of the present application will be set forth in the following description, and in part will be obvious from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the accompanying drawings. Description of the Drawings

[0042] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the description. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0043] Figure 1A Schematic cross-sectional view parallel to the substrate of the conductive layer of a semiconductor device provided for an exemplary embodiment of the present application;

[0044] Figure 1B Along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0045] Figure 1C Along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown;

[0046] Figure 1D Along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in the structure shown;

[0047] Figure 2 Schematic cross-sectional view perpendicular to the substrate taken along a plane perpendicular to the substrate after forming a stacked structure including an insulating layer and a sacrificial layer in a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application;

[0048] Figure 3 Schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the sacrificial layer) of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application;

[0049] Figure 4A Along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application;

[0050] Figure 4B Along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in the structure shown of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application;

[0051] Figure 5 An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0052] Figure 6 An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0053] Figure 7 An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0054] Figure 8 An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0055] Figure 9A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0056] Figure 9B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown; and

[0057] Figure 9C An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A a cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in the structure shown. Detailed Embodiments

[0058] To make the objectives, technical solutions, and advantages of the present application more clear and understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0059] The embodiments in this application can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation manners and contents can be transformed into various forms without departing from the spirit and scope of this application. Therefore, this application should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments in this application can be combined arbitrarily with each other.

[0060] The drawing ratios in this application can be used as a reference in the actual process, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shape, values, etc. shown in the drawings.

[0061] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to this application. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0062] In this specification, unless otherwise clearly specified and limited, the terms "arrange" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0063] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of the components, rather than to limit the quantity.

[0064] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "metal layer" can be changed to "metal film".

[0065] In the description of the present application, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In the present application, the channel layer refers to the region through which current mainly flows. In the present application, the terms "metal oxide semiconductor channel", "channel", and "semiconductor layer" are sometimes interchangeable.

[0066] As used in the embodiments of the present disclosure, the term "first direction" X is defined as the arrangement direction of capacitors and transistors; the term "second direction" Y is defined as a direction that intersects the "first direction" X and is parallel to the extension direction of the bit line; the term "third direction" Z is defined as a direction perpendicular to the substrate, that is, a direction parallel to the extension direction of the word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as Figures 1A - 1D , Figure 3 and Figures 4A - 4B etc.

[0067] As used in the present application, the term "section line aa'" is a line parallel to the first direction X and passing through the transistor region, the bit line region, and the capacitor region; the term "section line bb'" is a line parallel to the first direction X and not passing through the transistor region, the bit line region, and the capacitor region; and the term "section line cc'" is a line parallel to the second direction Y and only passing through the capacitor region. The specific positions of these section lines can be as Figure 1A shown.

[0068] Thus, an exemplary embodiment of the present application provides a semiconductor device, including: a plurality of memory cells stacked at intervals along a direction perpendicular to the substrate on the substrate; the memory cells include transistors, the transistors include a gate extending in a direction toward the substrate, a semiconductor layer at least partially surrounding the sidewalls of the gate, and a gate insulating layer located between the gate and the semiconductor layer; the transistors further include a first source / drain and a second source / drain, and a protective layer, and the protective layer is at least located between the semiconductor layer and the first source / drain and the second source / drain.

[0069] In an exemplary embodiment, the protective layer is in contact with the semiconductor layer and in contact with the first source / drain and the second source / drain.

[0070] In an exemplary embodiment, the material of the protective layer includes materials such as TiN, ITO, and IGZO.

[0071] Such as Figures 1A - 1DAs shown, the semiconductor device of the present application may include multiple layers of memory cells stacked at intervals along a direction perpendicular to the substrate 10 (i.e., the third direction Z); the memory cells may include at least one transistor, and the transistor includes a gate 70 extending in a direction toward the substrate 10, a semiconductor layer 60 at least partially surrounding the sidewalls of the gate 70, and a gate insulating layer 61 located between the gate 70 and the semiconductor layer 60.

[0072] In the present application, surrounding can be understood as partially or entirely surrounding the gate 70. In some embodiments, the surrounding may be entirely surrounding as a whole. The cross-section of the surrounded channel may be a closed ring, and the shape of the ring is adapted to the outer contour shape of the cross-section of the gate 70. Exemplarily, the cross-section of the gate 70 is, for example, a circular, rectangular, elliptical, or other structure. The cross-section is intercepted along a direction parallel to the substrate 10. In an exemplary embodiment, the surrounding may be partial surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0073] Continuing to refer to Figure 1A and Figure 1B , each of the transistors of the semiconductor device provided by the exemplary embodiment of the present application further includes a first source / drain and a second source / drain, and a protective layer 40, and the protective layer 40 is at least located between the semiconductor layer 60 and the first source / drain 81 and the second source / drain 82. The protective layer 40 is in contact with the semiconductor layer 60 and is in contact with the first source / drain 81 and the second source / drain 82.

[0074] Although the first source / drain and the second source / drain are used herein to label two separate and different source / drains, it is not intended that the source / drains referred to as the "first" source / drain and the "second" source / drain have a unique meaning. In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain 81 and the second source / drain 82 is the source of the transistor, and the other is the drain of the transistor.

[0075] In some embodiment manners, the protective layer 40 may be a semiconductor film layer, and the protective layer 40 may not be disconnected between the first source / drain 81 and the second source / drain 82. In some embodiments, the protective layer 40 may be a conductive film layer, and physical disconnection is required between the first source / drain 81 and the second source / drain 82 to maintain insulation.

[0076] Refer to Figure 1AIt can be seen that the protective layer 40 surrounds the semiconductor layer 60. In the circumferential direction around the semiconductor layer 60, the protective layer 40 is divided into two parts between the first source / drain 81 and the second source / drain 82. For example, the protective layer 40 can be divided into two parts by a notch 41, namely a first part 410 and a second part 420. One semiconductor layer 60 of each transistor corresponds to one protective layer 40, and the protective layer 40 can include a first part 410 and a second part 420 that are insulated from each other, and these two parts are insulated from each other by two notches 41.

[0077] In an exemplary embodiment, the protective layer 40 can be made of a material with a high etching selectivity to a sacrificial layer (such as silicon nitride), such as TiN. The above arrangement can protect the semiconductor layer during the manufacturing process.

[0078] In the present application, by providing a protective layer between the source / drain of the transistor and the semiconductor layer, it is possible to form the semiconductor layer first and then form the source / drain. The protective layer protects the material of the semiconductor layer sensitive to the etching solution during the formation of the source / drain, such as a metal oxide semiconductor material (such as IGZO).

[0079] As Figure 1B shown, along the third direction, the semiconductor layers 60 of different memory cells are separated from each other. Therefore, the parasitic MOS problem caused by the connection of adjacent semiconductor layers in the semiconductor device of the present application is eliminated.

[0080] As Figure 1B shown, along the third direction Z, the protective layers 40 of the memory cells of different layers are disconnected.

[0081] Further referring to Figure 1B , for the transistors of multiple memory cells stacked at intervals in the third direction Z, a common word line 100 is shared, and the gate 70 of each transistor is a part of the corresponding word line 100. The word line 100 can include a vertical portion 71 extending along the third direction Z and an extending portion 72 extending from the vertical portion 71 in a direction parallel to the substrate 10. In the present disclosure, by providing a transverse groove in the word line hole and forming a semiconductor layer in the transverse groove, it is easy to remove the semiconductor layer and the protective layer between adjacent transverse grooves, and eliminate the parasitic MOS.

[0082] Continuing to refer to Figure 1A and Figure 1C , two adjacent columns of memory cells extending along the second direction can share a common bit line 90.

[0083] Furthermore, as Figure 1AAs shown, the semiconductor device may further include a capacitor 200. The capacitor 200 may include a first electrode 91, a second electrode (not shown), a dielectric layer (not shown), etc., as Figure 1D shown.

[0084] The technical solution of the present application will be further described below through the manufacturing process of the semiconductor device of the exemplary embodiment of the present application. The "lithography process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".

[0085] In an exemplary embodiment, the manufacturing process of the semiconductor device of the present disclosure may include:

[0086] S100: Form a stacked structure.

[0087] Exemplary steps may include: providing a substrate 10, and alternately depositing an insulating layer thin film and a sacrificial layer thin film on the substrate 10 along the third direction Z to form a stacked structure 1 including an insulating layer 20 and a sacrificial layer 30, as Figure 2 shown.

[0088] In an exemplary embodiment, chemical vapor deposition or the like may be used to deposit the insulating layer thin film and the sacrificial layer thin film.

[0089] In an exemplary embodiment, the substrate 10 may be a semiconductor substrate, such as a silicon substrate.

[0090] In an exemplary embodiment, the insulating layer 20 as a device isolation layer may use an oxide, such as silicon dioxide.

[0091] In an exemplary embodiment, the sacrificial layer 30 may use a nitride having an etching selectivity ratio with respect to a subsequently formed protective layer, such as silicon nitride.

[0092] Figure 2The stacked structure 1 shown in [figure] can include four insulating layers 20 and three sacrificial layers 30. In other exemplary embodiments, the stacked structure may further include more or fewer alternately arranged insulating layers 20 and sacrificial layers 30.

[0093] In addition, a hard mask layer (not shown) can be provided on the top of the stacked structure 1 for subsequent patterning processes and will be removed after patterning.

[0094] In an exemplary embodiment, the hard mask layer can be made of an oxide, such as silicon dioxide.

[0095] S200: Pattern the stacked structure to form a preset pattern.

[0096] Exemplary steps can include: patterning the stacked structure to form a preset pattern in the stacked structure, such as Figure 3 shown.

[0097] In an exemplary embodiment, as Figure 3 shown, the preset pattern can include 1 vertical sub-stacked structure 31 and 4 horizontal stacked structures. The 1 vertical sub-stacked structure 31 divides the 4 horizontal stacked structures into 8 horizontal sub-stacked structures 310. Grooves T are formed between two adjacent horizontal sub-stacked structures 310 in the second direction Y, for a total of 6 grooves T.

[0098] Figure 3 In [figure], the 1 vertical sub-stacked structure 31 and the 8 horizontal sub-stacked structures 310 in the insulating layer are an integral structure. The 1 vertical sub-stacked structure 31 and the 8 horizontal sub-stacked structures 310 in the sacrificial layer are an integral structure.

[0099] S300: Form an insulating layer.

[0100] Exemplary steps can include: filling each groove T with the same insulating material as the insulating layer 20, and planarizing the upper surface of the stacked structure through a Chemical Mechanical Polishing (CMP) process to form a new insulating layer 20, such as Figure 4A and Figure 4B shown.

[0101] In an exemplary embodiment, the insulating material can be filled by Atomic Layer Deposition (ALD), Spin-on Doping (SOD), etc.

[0102] S400: Form a protective layer.

[0103] Exemplary steps may include: forming, in each of the lateral sub-stack structures, i.e., at a preset position of the word line, a word line hole K extending along the third direction Z by etching (such as dry etching, and gases such as CF4 / CH2F2 can be used), and exposing the sidewalls of the insulating layers 20 and the sacrificial layer 30 along the third direction Z; by means of the formed word line hole K, laterally etching (such as wet etching, HPO3, 165 °C) at the exposed sacrificial layer 30 along a direction parallel to the substrate 10 to remove part of the material of the sacrificial layer 30, so as to form a lateral groove S extending along a direction parallel to the substrate 10, thereby exposing part of the upper surface and the lower surface (horizontal sidewalls) of the insulating layers 20 and the ends (vertical sidewalls) of the sacrificial layer 30, and forming 6 lateral grooves S in each word line hole K; depositing a protective layer material film along the sidewalls of the word line hole K and the exposed surfaces of the lateral grooves S (including horizontal sidewalls and vertical sidewalls), such as Figure 5 as shown.

[0104] such as Figure 5 as shown, the protective layer 40 surrounds the word line hole K and extends along the inner walls of the lateral grooves S (including the above-mentioned horizontal sidewalls and vertical sidewalls).

[0105] In an exemplary embodiment, the orthographic projection of the word line hole K on a plane parallel to the substrate 10 may be a rectangle, a square, a circle, an ellipse, etc.

[0106] In an exemplary embodiment, the orthographic projection of the word line hole K on a plane parallel to the substrate 10 may be surrounded by the orthographic projection of the sacrificial layer 30.

[0107] In an exemplary embodiment, the protective layer 40 may be made of a material having a high etching selectivity to the sacrificial layer (such as silicon nitride), such as TiN. The protective layer 40 can at least be used to protect the subsequently deposited semiconductor layer from the influence when the sacrificial layer needs to be etched and the semiconductor layer needs to be exposed. The protective layer of the present application can completely wrap the outer surface of the semiconductor layer connected to the first source / drain and the second source / drain, thereby eliminating the adverse effects of subsequent source / drain manufacturing processes (such as the process of removing the silicon nitride of the sacrificial layer using phosphoric acid) on the material of the semiconductor layer, such as IGZO.

[0108] S500: Form a dummy layer.

[0109] Exemplary steps may include: depositing a semiconductor material film on the surface of the protective layer 40 to form a preset semiconductor layer 60' covering the protective layer; depositing a dummy material film on the surface of the preset semiconductor layer 60' and filling the lateral grooves S to form a dummy layer 50 covering the preset semiconductor layer 60', such as Figure 6 as shown.

[0110] In an exemplary embodiment, the preset semiconductor layer 60' may be made of a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of this metal oxide semiconductor material in a weakly acidic or weakly alkaline solution is relatively slow. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as Indium Gallium Zinc Oxide (IGZO) can be used as channel materials.

[0111] In an exemplary embodiment, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x In y Zn z O a , Al x Sn y In z Zn a O d , Si x In y Zn z O a , Zn x Sn y O z , Alx Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a 、InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZO x and other materials, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0112] In an exemplary embodiment, the dummy layer 50 may be made of a material different from that of the protective layer 40 and the preset semiconductor layer 60', such as Al2O3 and the like.

[0113] S600: Remove the parasitic channel and form a semiconductor layer corresponding to each memory cell.

[0114] Exemplary steps may include: removing the dummy layer and the preset semiconductor layer covering the insulating layer through a first wet etching process;

[0115] removing the protective layer covering the insulating layer through a second wet etching process, and retaining the dummy layer in the lateral groove;

[0116] removing the dummy layer in the lateral groove through a third wet etching process, retaining the protective layer and the preset semiconductor layer in the lateral groove, and forming a semiconductor layer 60 in the lateral groove, as Figure 7 shown.

[0117] In an exemplary embodiment, when removing the materials of the dummy layer and the preset semiconductor layer on the insulating layer in the word line hole K, such as removing Al2O3 / IGZO, a low selectivity solution such as HF or HCL can be used, and the dummy layer and the preset semiconductor layer can be removed by a single etching process to expose the protective layer on the sidewall of the insulating layer.

[0118] In an exemplary embodiment, when removing the thin film of the protective layer material in the word line hole K, such as removing TiN, a solution with a high selectivity of TiN / Al2O3 can be used to remove the protective layer covering the insulating layer and retain the dummy layer in the lateral groove.

[0119] In an exemplary embodiment, the material of the dummy layer in the word line hole K is removed. When removing Al2O3 of the dummy layer, a solution with a high selectivity ratio of Al2O3 / IGZO, such as low-concentration NH3H2O, can be used to remove the dummy layer in the lateral groove, and the protective layer and the preset semiconductor layer in the lateral groove are retained.

[0120] In an exemplary embodiment, since the material of the dummy layer 50 in the lateral groove S is removed, the material of the semiconductor layer will be exposed, such as indium gallium zinc oxide IGZO being exposed, which will damage the electrical characteristics of the IGZO semiconductor layer. Therefore, a rapid thermal annealing operation can be performed on the entire stacked structure, and the temperature is controlled within the range of 300°C - 400°C to repair the IGZO semiconductor layer.

[0121] S700: Form a word line.

[0122] Exemplary steps may include: depositing an insulating material thin film along the sidewall of the word line hole K and the surface of the semiconductor layer 60 in the lateral groove S to form a gate insulating layer 61 covering the semiconductor layer 60; depositing a conductive material thin film along the surface of the gate insulating layer 61 and filling the word line hole K and the lateral groove S to form a word line 100, as Figure 8 shown. On the basis of Figure 8 , further patterning is performed to disconnect different word lines.

[0123] In an exemplary embodiment, the gate insulating layer 61 may be a high-k dielectric layer, that is, a dielectric layer with K≥3.9. The high-k dielectric layer can be used as a gate oxide. The gate insulating layer 61 can be any one or more of silicon oxide, aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0124] In an exemplary embodiment, the word line 100 can be made of a metal oxide conductive material such as ITO.

[0125] S800: Form a conductive layer.

[0126] Exemplary steps may include: replacing the sacrificial layer in the regions corresponding to the first source / drain and the second source / drain to be formed with a conductive material to form a conductive layer 80, as Figure 9A , Figure 9B and Figure 9C shown.

[0127] Subsequent steps may further include forming, on both sides of the protective layer 40 along the first direction X in the conductive layer 80, a first source / drain 81 and a second source / drain 82 that are insulated from each other; when the protective layer is a conductive film layer, removing a part of the protective layer 40 by etching in the circumferential direction of the protective layer 40 surrounding the semiconductor layer 60, so that the protective layer is separated into two parts, such as forming two notches 41 to make the protective layer disconnected in the first direction X, thereby avoiding short circuits.

[0128] Subsequent steps may further include forming a common bit line 90 extending along the second direction Y.

[0129] Subsequent steps may further include fabricating a first electrode 91, a second electrode, and a dielectric layer of the capacitor 200 to complete the fabrication of the capacitor.

[0130] An exemplary embodiment of the present application further provides a method for manufacturing a semiconductor device, including the following steps:

[0131] Alternately forming an insulating layer and a sacrificial layer on a substrate to form a stacked structure;

[0132] Forming a word line hole penetrating the stacked structure;

[0133] Etching the sacrificial layer in the word line hole along a direction parallel to the substrate to form a lateral groove extending along a direction parallel to the substrate at the sacrificial layer;

[0134] Forming a semiconductor layer in the lateral groove;

[0135] Sequentially forming a gate insulating layer and a word line in the word line hole and the lateral groove;

[0136] Wherein, before forming the semiconductor layer, a protective layer is formed in the word line hole and the lateral groove;

[0137] After forming the protective layer and the semiconductor layer, replacing the sacrificial layer with a conductive layer to form a first source / drain and a second source / drain in contact with the protective layer.

[0138] An exemplary embodiment of the present application further provides an electronic device, including the semiconductor device provided by the exemplary embodiment of the present application as above.

[0139] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc.

[0140] Although the embodiments disclosed in this application are as above, the content described is only an embodiment adopted for the convenience of understanding this application and is not used to limit this application. Any person skilled in the art within the scope of this application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the protection scope of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: Multiple layers of memory cells stacked at intervals along a direction perpendicular to the substrate on the substrate; The memory cells include transistors, and the transistors include a gate extending in a direction towards the substrate, a semiconductor layer at least partially surrounding the sidewalls of the gate, and a gate insulating layer located between the gate and the semiconductor layer; The transistors further include a first source / drain and a second source / drain, and a protective layer, and the protective layer is at least located between the semiconductor layer and the first source / drain and the second source / drain.

2. The semiconductor device according to claim 1, wherein The protective layer is in contact with the semiconductor layer and is in contact with the first source / drain and the second source / drain.

3. The semiconductor device according to claim 2, wherein, The material of the protective layer includes TiN or ITO.

4. The semiconductor device according to claim 2, wherein The protective layer surrounds the semiconductor layer, and in the circumferential direction of surrounding the semiconductor layer, the protective layer is separated into two parts, a first part is in contact with the first source / drain, and a second part is in contact with the second source / drain.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor layers of the memory cells in different layers are separated from each other; the protective layers between the memory cells in different layers are disconnected.

6. The semiconductor device according to claim 4, wherein, It further includes a word line hole and lateral grooves distributed in different layers within the word line hole. The inner walls of the lateral grooves are sequentially provided with the protective layer and the semiconductor layer in a direction towards the word line, and the first part and the second part of the protective layer surround the sidewalls of the semiconductor layer; Both the protective layer and the semiconductor layer are distributed on the vertical sidewalls and the horizontal sidewalls of the lateral grooves.

7. The semiconductor device according to claim 1, wherein The transistors of the memory cells stacked in different layers share one word line, and the gates of the transistors are part of the corresponding word line; the word line includes a vertical portion extending in a direction towards the substrate and an extending portion extending from the vertical portion in a direction parallel to the substrate; The semiconductor layer and the protective layer are sequentially located on the surface of the extending portion according to the shape of the extending portion.

8. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Alternately form an insulating layer and a sacrificial layer on the substrate to form a stacked structure; Form a word line hole penetrating the stacked structure; Etch the sacrificial layer within the word line hole in a direction parallel to the substrate to form lateral grooves; Form a semiconductor layer within the lateral grooves; Sequentially form a gate insulating layer and a word line within the word line hole and the lateral grooves; Wherein, before forming the semiconductor layer, a protective layer is formed within the lateral grooves; After forming the protective layer and the semiconductor layer, replace the sacrificial layer with a conductive layer to form a first source / drain and a second source / drain in contact with the protective layer.

9. The manufacturing method according to claim 8, characterized in that, The sacrificial layer and the protective layer have different etching selectivity ratios under the same etching conditions.

10. The manufacturing method according to claim 9, characterized in that, The insulating layer is silicon oxide, and the sacrificial layer is silicon nitride; the protective layer includes TiN or ITO.

11. The manufacturing method according to claim 10, characterized in that, It further includes: In the circumferential direction of the protective layer surrounding the semiconductor layer, remove part of the protective layer by etching, so that the protective layer is separated into two parts, a first part is in contact with the first source / drain, and a second part is in contact with the second source / drain.

12. The manufacturing method according to claim 11, characterized in that, Before forming the gate insulating layer and the word line, Deposit a dummy material film within the word line hole and fill the lateral grooves to form a dummy layer; Etch away the semiconductor layer and the protective layer covering the insulating layer in the word line hole, and disconnect the semiconductor layer and the protective layer between different memory cells.

13. The manufacturing method according to claim 12, characterized in that, The dummy layer is made of a material different from that of the protective layer and the semiconductor layer, and the dummy layer contains aluminum oxide.

14. The manufacturing method according to claim 13, characterized in that, Etching away the semiconductor layer and the protective layer covering the insulating layer in the word line hole includes: Removing the dummy layer and the semiconductor layer covering the insulating layer through a first wet etching process; Removing the protective layer covering the insulating layer through a second wet etching process, and retaining the dummy layer in the lateral groove; Removing the dummy layer in the lateral groove through a third wet etching process, and retaining the protective layer and the semiconductor layer in the lateral groove.

15. The manufacturing method according to claim 14, characterized in that, After forming the protective layer and the semiconductor layer in the lateral groove, it further includes: Thermally annealing the stacked structure within a temperature range of 300°C - 400°C.

16. The manufacturing method according to claim 15, characterized in that, After forming the word line, it includes: Using phosphoric acid to remove the sacrificial layer in the regions corresponding to the first source / drain and the second source / drain to be formed, exposing the protective layer; replacing the sacrificial layer with a conductive material to form a conductive layer in contact with the protective layer; the conductive layer includes the mutually insulated first source / drain and the second source / drain.

17. An electronic device, characterized in that, Including the semiconductor device according to any one of claims 1 - 7, or the electronic device is manufactured by the manufacturing method according to any one of claims 8 - 16.

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