Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure comprises a substrate and at least one layer of storage unit arranged on the substrate, wherein each layer of storage unit comprises a plurality of storage units arranged along a second direction; the storage unit comprises a transistor and a capacitor which are arranged along a first direction, and the first direction and the second direction intersect and are both parallel to the substrate; wherein the capacitor includes a first electrode having at least two branches. The semiconductor structure can reduce the manufacturing process difficulty of the capacitor and improve the performance of the capacitor.

Description

Technical Field

[0001] This application relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of this application.

[0005] An exemplary embodiment of this application provides a semiconductor structure, including: a substrate and at least one layer of memory cells disposed on the substrate, and each layer of memory cells includes a plurality of memory cells arranged along a second direction;

[0006] The memory cell includes a transistor and a capacitor arranged along a first direction, and the first direction intersects with the second direction and is parallel to the substrate;

[0007] Wherein the capacitor includes a first electrode having at least two branches.

[0008] In some embodiments, the at least two branches are arranged at intervals in the second direction.

[0009] Some embodiments include:

[0010] A stacked structure of insulating layers and conductive layers alternately stacked on the substrate, and the stacked structure includes a plurality of lateral conductive portions extending along the first direction and spaced apart in the second direction;

[0011] A first trench penetrating the stacked structure and located between adjacent lateral conductive portions in the second direction;

[0012] At least one second trench penetrating each of the lateral conductive portions and extending along the first direction; wherein, the second trench divides the first electrode in the conductive layer into two branches.

[0013] In some embodiments, the capacitor further includes a dielectric layer covering the inner sidewalls of the branches; different memory cells stacked on each other share the dielectric layer.

[0014] In some embodiments, the capacitor further includes a second electrode covering the dielectric layer, and the second electrode is shared by different storage units stacked on top of each other.

[0015] In some embodiments, there is a common connection layer between multiple branch portions arranged along the second direction; the second electrode is connected to the common connection layer, and the materials of the second electrode and the common connection layer are different.

[0016] In some embodiments, the transistor includes a gate, a gate insulating layer surrounding the gate, and a semiconductor layer surrounding the gate insulating layer, and the gate is a part of the corresponding word line.

[0017] In some embodiments, the word line includes a vertical portion extending along the third direction and a protruding portion protruding from the vertical portion; the transistor further includes a gate isolation layer, and the gate isolation layer is located between the vertical portion and the semiconductor layer in the first direction.

[0018] In some embodiments, the gate isolation layer includes a material different from that of the gate insulating layer.

[0019] In some embodiments, the first source / drain and the second source / drain of the transistor are located on both sides of the semiconductor layer along the first direction and are connected to the semiconductor layer;

[0020] One of the first source / drain and the second source / drain of the transistor and each branch portion of the first electrode are of an integral structure.

[0021] In some embodiments, the stacked multiple-layer storage units include alternately stacked insulating layers and conductive layers. The region of the first electrode of the conductive layer includes a second trench located between two adjacent branch portions, and the thickness of the branch portion is equal to the thickness of the conductive layer.

[0022] In some embodiments, there is a first trench filled with an isolation layer between two adjacent storage units in the second direction, and there is a third trench in the isolation layer extending towards the substrate direction, and the third trench communicates with the second trench;

[0023] The side walls of the branch portions of the first electrode are exposed in the second trench and the third trench, and an integrated dielectric layer and an integrated second electrode are sequentially distributed in the second trench and the third trench;

[0024] The second trench and the third trench are filled with a common connection layer connected to the second electrode.

[0025] In some embodiments, it further includes a support frame, and the support frame includes the stacked first electrodes and the insulating layers between the first electrodes.

[0026] An embodiment of the present application provides a method for manufacturing a semiconductor structure, including: stacked memory cells, the memory cells including transistors and capacitors, the capacitors including a first electrode electrically connected to the transistors;

[0027] Forming an insulating layer and a conductive layer that are alternately distributed along a third direction perpendicular to the substrate on the substrate to form a stacked structure;

[0028] Patterning the stacked structure to form a plurality of lateral conductive portions extending along a first direction and spaced along a second direction, the first direction intersecting the second direction and both being perpendicular to the third direction;

[0029] Forming a first trench extending along the first direction between two adjacent lateral conductive portions in the second direction;

[0030] Etching each of the lateral conductive portions and the insulating layer stacked along the third direction to form at least one second trench that penetrates each of the lateral conductive portions and the insulating layer and extends along the first direction, the second trench dividing the lateral conductive portion into at least two branch portions, and the length of the second trench along the first direction being less than the length of the first trench along the first direction;

[0031] The at least two branch portions are the first electrodes.

[0032] In some embodiments, after dividing the lateral conductive portion into at least two branch portions, it includes:

[0033] Filling the first trench with an insulating material to form a first isolation layer;

[0034] Etching and removing part of the material of the first isolation layer to form a third trench, the length of the third trench along the first direction being equal to the length of the second trench along the first direction;

[0035] The second trench and the third trench expose the sidewalls of the branch portions of the first electrode.

[0036] In some embodiments, it further includes:

[0037] Depositing a dielectric material film and then a conductive material film in the second trench and the third trench to form a dielectric layer of the capacitor and a second electrode of the capacitor.

[0038] In some embodiments, it further includes:

[0039] After forming the second electrode, a conductive material film is continuously deposited in the second trench and the third trench to cover the second electrode and fill the second trench and the third trench, forming a common connection layer, and the material of the common connection layer is different from that of the second electrode.

[0040] In some embodiments, it further includes:

[0041] A word line hole penetrating the stacked structure and extending in a third direction is formed in a region of the lateral conductive portion away from the first electrode, and a conductive layer connecting each branch portion of the first electrode is included between the outer contour of the word line hole of the conductive layer and the branch portion, and the conductive layer connecting the branch portion is one of the first source / drain and the second source / drain of the transistor.

[0042] An exemplary embodiment of the present application provides an electronic device, including the semiconductor structure of any one of the above, or fabricated by the above method.

[0043] The structure of the capacitor with the first electrode having multiple branch portions adopted in the present application simplifies the device manufacturing process, reduces the cost, and enhances the conductive performance.

[0044] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become obvious from the specification, or be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0045] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0046] Figure 1A A schematic cross-sectional view parallel to the substrate of a semiconductor structure provided for an exemplary embodiment of the present application;

[0047] Figure 1B For Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of the structure shown;

[0048] Figure 1C For Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' of the structure shown;

[0049] Figure 1D For Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line dd' of the structure shown;

[0050] Figure 2AA schematic cross-sectional view perpendicular to a substrate taken along a plane parallel to a first direction after forming a stacked structure including an insulating layer and a conductive layer, provided for an exemplary embodiment of the present application;

[0051] Figure 2B A schematic cross-sectional view perpendicular to a substrate taken along a plane parallel to a second direction after forming a stacked structure including an insulating layer and a conductive layer, provided for an exemplary embodiment of the present application;

[0052] Figure 3A A three-dimensional schematic view of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application;

[0053] Figure 3B For Figure 3A A schematic cross-sectional view taken along a plane parallel to the substrate of the structure shown;

[0054] Figure 3C For Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' in the structure shown;

[0055] Figure 3D For Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along bb' in the structure shown;

[0056] Figure 3E For Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along cc' in the structure shown;

[0057] Figure 3F For Figure 3A A schematic cross-sectional view perpendicular to the substrate taken along dd' in the structure shown;

[0058] Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application; Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' in the structure shown;

[0059] Figure 4B A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application; Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' in the structure shown;

[0060] Figure 4C A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application; Figure 1ASchematic cross-sectional view perpendicular to the substrate taken along the cross-section line cc' in the shown structure;

[0061] Figure 4D Intermediate product formed in an intermediate step of the manufacturing method of the semiconductor structure provided by the exemplary embodiment of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line dd' in the shown structure;

[0062] Figure 5A Schematic three-dimensional view of the intermediate product formed in an intermediate step of the manufacturing method of a semiconductor structure provided by the exemplary embodiment of the present application;

[0063] Figure 5B For Figure 5A Schematic cross-sectional view taken along a plane parallel to the substrate of the shown structure;

[0064] Figure 5C For the cross-section taken along Figure 5A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line aa' in the shown structure;

[0065] Figure 5D For the cross-section taken along Figure 5A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line bb' in the shown structure;

[0066] Figure 5E For the cross-section taken along Figure 5A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line cc' in the shown structure;

[0067] Figure 5F For the cross-section taken along Figure 5A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line dd' in the shown structure;

[0068] Figure 6A The intermediate product formed in an intermediate step of the manufacturing method of the semiconductor structure provided by the exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line aa' of the shown structure; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line aa' in the shown structure;

[0069] Figure 6B The intermediate product formed in an intermediate step of the manufacturing method of the semiconductor structure provided by the exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line bb' of the shown structure; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line bb' in the shown structure;

[0070] Figure 6C The intermediate product formed in an intermediate step of the manufacturing method of the semiconductor structure provided by the exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-section line dd' of the shown structure; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line dd' in the shown structure;

[0071] Figure 7A An intermediate product formed in an intermediate step of the method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown in Figure 1A ;

[0072] Figure 7B An intermediate product formed in an intermediate step of the method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown in Figure 1A ;

[0073] Figure 7C An intermediate product formed in an intermediate step of the method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in the structure shown in Figure 1A ; and

[0074] Figure 8A - Figure 8C A schematic diagram of forming a word line structure by another method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application. Detailed Embodiments

[0075] To make the objectives, technical solutions, and advantages of the present application more clear and understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0076] The embodiments herein can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation manners and contents can be transformed into various forms without departing from the gist and scope of the present application. Therefore, the present application should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0077] The drawing ratios in the present application can be used as a reference in actual processes, but are not limited thereto. For example, the aspect ratio of the channel layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic diagrams of the structure, and one aspect of the present application is not limited to the shapes or values shown in the drawings.

[0078] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationships of the components are appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0079] In this specification, unless otherwise clearly defined and limited, the terms "arrange" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0080] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of the components, rather than to limit the quantity.

[0081] In this specification, "film" and "layer" can be interchanged. For example, sometimes "metal layer" can be changed to "metal film".

[0082] An exemplary embodiment of this application provides a semiconductor structure, including a substrate and at least one layer of memory cells arranged on the substrate. One layer of memory cells includes a plurality of memory cells arranged along a second direction; bit lines connected to the memory cells; the memory cells include a transistor and a capacitor arranged along a first direction, the first direction intersects with the second direction and is parallel to the substrate; word lines connected to the memory cells; wherein the capacitor includes a first electrode having at least two branches.

[0083] The different branches of the first electrode are arranged at intervals in the second direction, and each branch is connected to the source / drain electrode of the transistor.

[0084] When manufacturing the device architecture of the present application, only trenches in the direction perpendicular to the substrate need to be formed on the stacked structure of the insulating layer and the conductive layer. These trenches divide the conductive layer and the insulating layer into branches, and a second electrode is formed on the sidewalls of the branches perpendicular to the substrate. There is no need to etch back the conductive layer or the insulating layer horizontally to form the second electrode, which can reduce the risk of the first electrode collapsing during the formation of the second electrode of the capacitor, reduce the manufacturing process difficulty, and improve the performance of the capacitor. In addition, the first electrode and the insulating layer are stacked, and when forming the second electrode, there is no need to fabricate a frame to support the first electrode, and the first electrode and the insulating layer serve as the frame of the semiconductor structure.

[0085] In an exemplary embodiment, the capacitor further includes a dielectric layer covering the branches, and the dielectric layer overlaps with each branch in the third direction.

[0086] In an exemplary embodiment, the capacitor further includes a second electrode covering the dielectric layer.

[0087] As used in the present application, the term "first direction" X is defined as the arrangement direction of the transistors and capacitors; the term "second direction" Y is defined as intersecting with the "first direction" X. Optionally, the "second direction" Y is perpendicular to the "first direction" X, that is, the extension direction of the bit line; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the extension direction of the word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as Figure 1A - Figure 1D etc. shown.

[0088] As used in the present application, the term "being an integral structure" may mean that there is no obvious fault or gap or other obvious demarcation interface between A and B at the microscopic structure. Generally, a connected film layer patterned on a film layer is an integral body. For example, A and B are made of the same material to form a film layer and have a connected structure formed simultaneously through the same patterning process.

[0089] Such as Figure 1A - Figure 1D shown, the semiconductor structure of the present application may include a substrate 10 and at least one layer of memory cells disposed on the substrate 10. Each layer of memory cells includes a plurality of memory cells arranged along the second direction Y; a bit line 90 connected to the memory cells; and a word line 80 connected to the memory cells. The memory cells may include a transistor and a capacitor arranged along the first direction X, and the capacitor may include a first electrode 61 having at least two branches, and the at least two branches are arranged at intervals in the second direction.

[0090] Such as Figure 1AAs shown, the capacitor may include a first electrode having two branches, i.e., a first electrode 61 with a first branch 321 and a second branch 322, and the first branch 321 and the second branch 322 are arranged at intervals in the second direction Y.

[0091] The semiconductor structure includes: a stacked structure of insulating layers and conductive layers alternately stacked on a substrate, the stacked structure including a plurality of lateral conductive portions extending along a first direction and spaced in a second direction;

[0092] a first trench penetrating the stacked structure and located between adjacent lateral conductive portions in the second direction;

[0093] at least one second trench penetrating each of the lateral conductive portions and extending along the first direction; wherein the second trench divides the first electrode in the conductive layer into two branches.

[0094] Reference Figure 1A 、 Figure 1C and Figure 1D and, the capacitor further includes a dielectric layer 63 covering the inner sidewalls (two sidewalls extending in the direction towards the substrate) of the first branch 321 and the second branch 322. The dielectric layer is shared by different columns of mutually stacked memory cells. Figure 1D It is also shown that the dielectric layers 63 of the capacitors of a plurality of memory cells located in the same or different layers are interconnected into an integral structure.

[0095] Continuing to refer to Figure 1A 、 Figure 1C and Figure 1D and, the capacitor further includes a second electrode 62 covering the dielectric layer 63. Figure 1D It is also shown that the second electrodes 62 of the capacitors of a plurality of memory cells located in the same or different layers are interconnected into an integral structure.

[0096] Figure 1D It is also shown that there is a common connection layer 64 between a plurality of branches arranged along the second direction Y. The second electrode 62 is connected to the common connection layer 64, and the materials of the second electrode 62 and the common connection layer 64 are different.

[0097] Reference Figure 1A - Figure 1D It can be known from reference that the stacked multi-layer memory cells include insulating layers 20 and conductive layers 30 alternately stacked, and the first electrode region of the conductive layer 30 includes a second trench T2 located between a first branch 321 and a second branch 322 adjacent in the second direction Y, and the thicknesses of the two branches are equal to the thickness of the conductive layer.

[0098] There is a first trench (not shown) filled with an isolation layer 51 between two adjacent memory cells in the second direction. In the isolation layer 51, there is a third trench T3 extending towards the substrate. The third trench T3 communicates with the second trench T2. The inner sidewalls of the first branch 321 and the second branch 322 of the first electrode are exposed in the second trench T2.

[0099] The third trench is obtained by etching back the isolation layer at the end after filling the first trench with the isolation layer, or by dry etching to remove the isolation layer corresponding to the outer sidewalls of the first branch (the two sidewalls extending towards the substrate that face away from each other) and retaining the isolation layer in other regions. The second isolation layer defines the lengths of the first electrode and the second electrode.

[0100] On the sidewalls of the second trench T2 and the third trench T3 along the third direction Z, there is a dielectric layer 63 with an integrated structure. The dielectric layer 63 only covers the sidewalls of the first branch 321 and the second branch 322 along the third direction Z, that is, the dielectric layer 63 overlaps with the first branch 321 and the second branch 322 in the third direction. The dielectric layer 63 also covers the upper surface of the protective layer 50 parallel to the substrate 10 above the topmost insulating layer 20.

[0101] On the sidewalls of the second trench T2 and the third trench T3 along the third direction Z, there is also a second electrode 62 with an integrated structure. The second electrode 62 covers the sidewalls of the dielectric layer 63 along the third direction Z and covers the upper surface of the dielectric layer 63 parallel to the substrate 10.

[0102] The second trench T2 and the third trench T3 are also filled with a common connection layer 64 connected to the second electrode. The common connection layer 64 covers the sidewalls of the second electrode along the third direction Z and covers the upper surface of the second electrode 62 parallel to the substrate 10.

[0103] Continue to refer to Figure 1B , the transistor includes a gate 70, a gate insulating layer 81 surrounding the gate 70, and a semiconductor layer 82 surrounding the gate insulating layer 81. The gate 70 is a part of the corresponding word line 80.

[0104] Herein, "surrounding" can be understood as partially or completely surrounding the gate 70 or the word line 80. In some embodiments, the surrounding can be a complete surrounding overall. The cross-section of the semiconductor layer 82 after surrounding can be a closed ring shape, and the ring shape is adapted to the outer contour shape of the cross-section of the gate. Exemplarily, the cross-section of the gate is, for example, a square structure. The cross-section is intercepted along a direction parallel to the substrate 10. In some embodiments, the surrounding can be a partial surrounding, and the cross-section after surrounding is not closed, but presents a ring shape. For example, the cross-section of the semiconductor layer 82 is a ring shape with an opening.

[0105] Figure 1B It is also shown that the word line 80 may include a vertical portion 710 extending along the third direction Z and an extending portion 720 extending from the vertical portion 710.

[0106] Figure 1B It is also shown that the transistor further includes a gate isolation layer 810, the gate isolation layer 810 is located between the vertical portion 710 and the semiconductor layer 82 in the first direction X, and the gate isolation layer 810 includes a material different from that of the gate insulating layer 81. Such a structural design of the transistor can cause the semiconductor layers 82 of at least some adjacent-layer transistors to be disconnected in the third direction.

[0107] Therefore, the gate configuration of the transistor of the present application can more easily eliminate parasitic MOS and enhance the stability of the device by designing an extending portion with lateral extension.

[0108] In an exemplary embodiment, the first source / drain and the second source / drain of each transistor are located on both sides of the annular semiconductor layer in the first direction and are connected to the semiconductor layer.

[0109] Although the first and second source / drain references are used herein to label two separate and different source / drains, it is not intended that the source / drains referred to as "first" and / or "second" source / drains have a unique meaning. It is only desired that one of the source / drains is connected to the bit line and the other may be connected to the capacitor.

[0110] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is the source of the transistor and the other is the drain of the transistor.

[0111] In an exemplary embodiment, it may further include a support frame, and the support frame may include the stacked first electrodes and the insulating layer between the first electrodes. That is, in the stacked structure, the first electrodes (conductive layers) and the insulating layer between the first electrodes jointly play a supporting role.

[0112] As Figure 1A shown, in an exemplary embodiment, each layer of memory cells includes a first column of memory cells and a second column of memory cells arranged along the first direction X, and the first column of memory cells and the second column of memory cells share a bit line 90.

[0113] The technical solution of the present application will be further described below through the manufacturing process of the semiconductor structure of the exemplary embodiment of the present application. The "lithography process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".

[0114] In an exemplary embodiment, the manufacturing process of the semiconductor structure may include:

[0115] S100: Form a stacked structure.

[0116] Exemplary steps may include: providing a substrate 10, and alternately depositing an insulating layer thin film and a conductive thin film on the substrate 10 along the third direction Z to form a stacked structure 1 including an insulating layer 20 and a conductive layer 30, as Figure 2A and Figure 2B shown.

[0117] In an exemplary embodiment, the insulating layer thin film and the conductive thin film may be deposited by a chemical vapor deposition method or a plasma enhanced chemical vapor deposition (PECVD) method.

[0118] In an exemplary embodiment, the substrate 10 may be made of glass, silicon, a flexible material, etc. The flexible material may be a material such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. In an exemplary embodiment, the substrate may be a single-layer structure or a multi-layer stacked structure. The stacked structure substrate may include: flexible material / inorganic material / flexible material. The inorganic material may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), etc. In an exemplary embodiment, the substrate 10 may be a semiconductor substrate, such as a silicon substrate.

[0119] In an exemplary embodiment, the insulating layer 20 may be made of silicon oxide (SiOx) and silicon oxynitride (SiON) or a low dielectric constant material, such as silicon dioxide (SiO2).

[0120] In an exemplary embodiment, the conductive layer 30 may be a metal layer, which may be subsequently used to form the source / drain electrodes and the electrodes of the capacitor. In an exemplary embodiment, the conductive layer 30 may be made of a material that can be etched, including but not limited to tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta). The conductive layer 30 may also have a composite structure, such as a multi-layer structure of titanium nitride (TiN) / tungsten (W). In an exemplary embodiment, the thickness of the conductive layer 30 may be the same as the thickness of the source / drain to be formed.

[0121] In an exemplary embodiment, forming the conductive layer 30 may include first depositing a Ti film layer, then depositing a TiN film layer, then depositing a tungsten film layer, and finally planarizing the tungsten film layer using a CMP process, that is, the conductive layer may have a composite structure of three film layers.

[0122] Figure 2A and Figure 2B The stacked structure 1 shown in [reference] may include 4 insulating layers 20 and 3 conductive layers 30. In other exemplary embodiments, the stacked structure may also include more or fewer alternating insulating and conductive layers.

[0123] S200: Pattern the stacked structure.

[0124] Exemplary steps may include: setting a first region 100 at an intermediate position of the stacked structure, second regions 200 on both sides of the first region, and a third region 300 on a side of the second regions 200 away from the first region 100; etching the stacked structure toward the substrate to form two first trenches T1 extending along the first direction X and penetrating the stacked structure on each side of the first region 100 in the first direction, so as to divide the stacked structure into one vertical conductive part 31 extending along the second direction Y and six horizontal conductive parts 32 extending along the first direction X separated by the vertical conductive part 31. Each horizontal conductive part 32 has a dimension M1 in the first direction X and a dimension N1 in the second direction Y. Thus, the width of each first electrode of the capacitor also has a dimension N1 in the second direction Y; continuing to etch each horizontal conductive part 32 to form a second trench T2 extending along the first direction X and penetrating the stacked structure on each horizontal conductive part 32. The dimension of the second trench T2 in the first direction X is smaller than the dimension of the first trench T1 in the first direction X, and the dimension of the second trench T2 in the second direction Y is one-third of the width of the first electrode of the capacitor, that is, one-third of the dimension N1; the second trench T2 divides each horizontal conductive part 32 into a first branch part 321 and a second branch part 322 with the same width, that is, the first branch part 321, the second branch part 322, and the dimension of the second trench T2 in the second direction Y are all the same, as Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F shown.

[0125] In an exemplary embodiment, the first trench T1 extends throughout the second region 200 and the third region 300, the second trench T2 extends throughout the third region 300, and the dimension of the third region in the first direction is the length dimension of the first electrode of the capacitor in the first direction X, that is, the dimension M2.

[0126] Figure 3A and Figure 3B show a U-shaped horizontal conductive part 32, or a horizontal conductive part 32 having two branch parts. However, in other exemplary embodiments, the preset pattern may be in other shapes. For example, two second trenches may be formed in each horizontal conductive part, and the width of each second trench is one-fifth of the width of the capacitor region. Thus, the horizontal conductive part 32 may be a horizontal conductive part having three branch parts.

[0127] In addition, before patterning the stacked structure, a barrier layer material film may also be deposited on the topmost surface of the stacked structure to form a barrier layer 40. The barrier layer 40 may adopt an insulating material different from that of the insulating layer 20, such as silicon nitride.

[0128] S300: Form a protective layer.

[0129] Exemplary steps may include: depositing a thin film of protective layer material along the bottom wall and side walls of the first trench T1 and the second trench T2 to form a protective layer 50; depositing a thin film of insulating material into the first trench T1 to cover the protective layer 50 and fill the first trench T1, forming a first isolation layer 51; depositing a thin film of insulating material into the second trench T2 to cover the protective layer 50 and fill the second trench T2, forming a second isolation layer 52; planarizing the upper surface of the stacked structure by a Chemical Mechanical Polishing (CMP) process, as Figure 4A , Figure 4B , Figure 4C and Figure 4D shown.

[0130] In an exemplary embodiment, the protective layer 50 may be made of a material different from that of the insulating layer 20, such as silicon nitride. The protective layer 50 may be used to protect the conductive layer 30 from the influence of subsequent processes.

[0131] In an exemplary embodiment, the first isolation layer 51 and the second isolation layer 52 may be made of the same material as the insulating layer 20, such as silicon oxide for both.

[0132] In an exemplary embodiment, the insulating material filled in the first trench T1 and the second trench T2 is formed in a single process.

[0133] In an exemplary embodiment, the thin film of protective layer material and the thin film of insulating material may be deposited by methods such as Atomic Layer Deposition (ALD), Spin on Dielectric (SOD), etc. For example, silicon nitride may be deposited as the protective layer by atomic layer deposition, and then silicon oxide may be deposited on the surface of the protective layer as the first isolation layer and the second isolation layer by spin coating, and the surface may be polished flat by Chemical Mechanical Polishing (CMP), and finally terminated at the uppermost barrier layer (such as silicon nitride) and made flush with the barrier layer.

[0134] S400: Form the first electrode of the capacitor.

[0135] Exemplary steps may include: patterning the stacked structure again to remove the material of the second isolation layer 52, reforming the second trench T2, dividing each lateral conductive portion 32 into a first branch portion 321 and a second branch portion 322 with the same width, exposing the inner sidewalls of the two branch portions (i.e., the sidewalls of the first branch portion 321 and the second branch portion 322 facing each other); removing a part of the material of the first isolation layer 51 to form a third trench T3, and the dimension of the third trench T3 in the first direction is equal to the dimension of the second trench T2 in the first direction, i.e., M2, thereby forming a first electrode 61 of the capacitor having at least two branch portions, as Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F shown.

[0136] In addition, before patterning the stacked structure, a thin film of barrier layer material may be deposited on the topmost layer of the stacked structure to form a barrier layer 40; a thin film of mask material may be deposited on the barrier layer 40 to form a mask layer 41. The barrier layer 40 may be made of an insulating material different from that of the insulating layer 20, such as silicon nitride. The mask layer 41 may be made of a material different from that of the barrier layer 40, such as polysilicon.

[0137] The method for forming the first electrode of the capacitor in this application does not require lateral etching to remove the insulating layer between adjacent conductive layers in the third direction, so the transistor region of the conductive layer will not be suspended, thus eliminating the step of setting a frame for supporting the conductive layer, reducing the process difficulty, and improving the process efficiency.

[0138] S500: Form the second electrode and the common connection layer of the capacitor.

[0139] Exemplary steps may include: depositing a dielectric material thin film on the surfaces of the two branch portions in the second trench T2 and the third trench T3 to form a dielectric layer 63 of the capacitor; depositing a conductive material thin film along the surface of the dielectric layer 63 to form a second electrode 62 of the capacitor; connecting the second electrode 62 with a furnace tube deposited germanium-silicon material to form a common connection layer 64; using CMP technology to grind the surface flat and then depositing a layer of silicon nitride on the surface of the common connection layer 64 as a passivation layer 65 to prevent germanium-silicon oxidation, as Figure 6A , Figure 6B and Figure 6C shown.

[0140] In an exemplary embodiment, the dielectric thin film and the conductive thin film may be deposited by Atomic Layer Deposition (ALD).

[0141] In an exemplary embodiment, the dielectric layer 63 may be a high-k dielectric layer, i.e., a dielectric layer with K≥3.9. The dielectric layer 63 may be made of at least one of the following materials: silicon oxide, aluminum oxide (Al2O3), hafnium oxide, titanium oxide, and zirconium oxide.

[0142] In an exemplary embodiment, the material that the second electrode 62 may adopt includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.

[0143] This application does not require lateral etching of the conductive layer. Therefore, the second electrode layer is only formed on the sidewalls of the conductive layer (the first electrode). Thus, the connection layer (i.e., the silicon-germanium layer) for connecting the second electrode only needs to be deposited from top to bottom along the third direction. Therefore, the probability of generating holes is reduced, thereby significantly improving the conductivity of the capacitor.

[0144] S600: Form the word line.

[0145] Exemplary steps may include: opening the word line region and the bit line preset region of the transistor and then filling them with SOD technology; using CMP technology to polish the surface and terminate at the protective layer; using lithography technology to define the word line region; forming a word line hole penetrating the stacked structure in the word line region through photolithography etching; sequentially depositing a semiconductor thin film, an insulating layer thin film, and a conductive thin film around the inner peripheral wall of each word line hole to form the semiconductor layer 82, the gate insulating layer 81, and the word line 80 / gate 70, as Figure 7A 、 Figure 7B and Figure 7C shown.

[0146] In an exemplary embodiment, after forming the word line hole, a distance is maintained between the outer contour of the word line hole of the conductive layer 30 and the first branch 321 and the second branch 322, such that the first branch 321 and the second branch 322 of the first electrode 61 are connected by the conductive layer 30, and the conductive layer 30 connecting the first branch 321 and the second branch 322 can be formed as one of the first source / drain and the second source / drain of the transistor.

[0147] In an exemplary embodiment, the semiconductor layer 82 may adopt a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may adopt an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of this metal oxide semiconductor material in a weakly acidic or weakly alkaline solution is relatively slow. In an exemplary embodiment, the metal oxide semiconductor material may adopt oxides of In, Ga, Zn, Sn, etc. These metal oxide materials such as Indium Gallium Zinc Oxide (IGZO) can be used as the channel material.

[0148] In an exemplary embodiment, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x In y Zn z O a , Al x Sn y In z Zn a O d , Si x In y Zn z O a , Zn x Sn y O z , Al x Zn y Sn z O a , Ga x Zn y Sn z O a , Zr x Zn y Sn z O a , materials such as InGaSiO, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0149] In an exemplary embodiment, the gate insulating layer 81 may be a high-k dielectric layer, i.e., a dielectric layer with K≥3.9. The high-k dielectric layer can serve as a gate oxide. The gate insulating layer 81 may be any one or more of silicon oxide, aluminum oxide (Al2O3), hafnium oxide (HfO2).

[0150] In an exemplary embodiment, the word line 80 / gate 70 may be made of tungsten (W) or a composite metal such as TiN / W, or may be made of ITO.

[0151] In some embodiments of the present disclosure, forming the word line may include the following steps:

[0152] Forming a word line hole (not shown) through the stacked structure; by means of the formed word line hole, etching away part of the material of the conductive layer 30 in the first direction X horizontally at each exposed conductive layer 30 to form a horizontal trench (not shown), thereby exposing the upper and lower surfaces of each insulating layer 20 and the new sidewalls of the conductive layer 30; sequentially depositing a semiconductor thin film, an insulating layer thin film, and a conductive thin film on the sidewalls of the insulating layer 20 exposed in the word line hole, the surfaces of the insulating layer 20 exposed in the horizontal trench, and the sidewalls of the conductive layer 30 to form a preset semiconductor layer 82', a preset gate insulating layer 81', and a preset gate 70'; using wet etching to remove the material on the sidewalls of the conductive layer 30 and the insulating layer 20 in the word line hole, and forming the word line hole K again; continuing to etch away part of the material of the preset semiconductor layer 82' and the preset gate insulating layer 81' horizontally in the first direction X at each conductive layer 30 to form isolation trenches T4 (subsequently used to form the gate isolation layer), and forming isolation trenches T4 in each word line hole K; filling the isolation trenches T4 of each conductive layer with an insulating material and etching away the excess insulating material to make the sidewalls of the conductive layer 30 and the insulating layer 20 flush, forming the gate isolation layer 810, and then forming the semiconductor layer 82 and the gate insulating layer 81; filling the word line hole K1 with a conductive material to form the word line 80, the word line 80 having a vertical portion 710 extending vertically and an extending portion 720 located on the periphery of the vertical portion 710 and extending horizontally in the first direction X, and forming the gate isolation layer 810, as Figure 8A - Figure 8C shown. The transistor forms a gate with this specific structure and has a gate isolation layer, making it easier to remove parasitic MOS.

[0153] In an exemplary embodiment, the gate isolation layer 810 may be made of the same material as the insulating layer 20, such as silicon dioxide, but cannot be made of the same material as the gate insulating layer 81.

[0154] An exemplary embodiment of the present application further provides an electronic device, including the semiconductor structure provided by the exemplary embodiment of the present application as above.

[0155] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0156] Although the disclosed embodiments of the present application are as above, the content is only an embodiment adopted for the convenience of understanding the present application and is not intended to limit the present application. Any person skilled in the art within the scope of the present application may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate and at least one layer of memory cells disposed on the substrate, each layer of memory cells including a plurality of memory cells arranged along a second direction; The memory cell includes a transistor and a capacitor arranged along a first direction, the first direction intersecting the second direction and both being parallel to the substrate; Wherein the capacitor includes a first electrode having at least two branches.

2. The semiconductor structure according to claim 1, wherein The at least two branches are arranged at intervals in the second direction.

3. The semiconductor structure according to claim 1, characterized in that, Comprising: A stacked structure of insulating layers and conductive layers alternately stacked on the substrate, the stacked structure including a plurality of lateral conductive portions extending along the first direction and spaced apart in the second direction; A first trench penetrating the stacked structure and located between adjacent lateral conductive portions in the second direction; At least one second trench penetrating each of the lateral conductive portions and extending along the first direction; wherein the second trench divides the first electrode in the conductive layer into two branches.

4. The semiconductor structure according to claim 2, wherein The capacitor further includes a dielectric layer covering the inner sidewalls of the branches; different stacked memory cells share the dielectric layer.

5. The semiconductor structure according to claim 4, wherein The capacitor further includes a second electrode covering the dielectric layer, different stacked memory cells share the second electrode.

6. The semiconductor structure according to claim 5, wherein There is a common connection layer between a plurality of branches arranged along the second direction; the second electrode is connected to the common connection layer, and the materials of the second electrode and the common connection layer are different.

7. The semiconductor structure according to claim 1, wherein The transistor includes a gate, a gate insulating layer surrounding the gate, and a semiconductor layer surrounding the gate insulating layer, and the gate is a part of the corresponding word line.

8. The semiconductor structure according to claim 7, wherein The word line includes a vertical portion extending along the third direction and an extending portion extending from the vertical portion; the transistor further includes a gate isolation layer, and the gate isolation layer is located between the vertical portion and the semiconductor layer in the first direction.

9. The semiconductor structure according to claim 8, wherein The gate isolation layer includes a material different from that of the gate insulating layer.

10. The semiconductor structure according to claim 1 or 2, characterized in that, The first source / drain and the second source / drain of the transistor are located on both sides of the semiconductor layer along the first direction and are connected to the semiconductor layer; One of the first source / drain and the second source / drain of the transistor and the branches of the first electrode are of an integral structure.

11. The semiconductor structure according to claim 10, wherein, The stacked multiple layers of memory cells include insulating layers and conductive layers alternately stacked, and the region of the first electrode of the conductive layer includes a second trench located between two adjacent branches, and the thickness of the branch is equal to the thickness of the conductive layer.

12. The semiconductor structure according to claim 11, wherein, There is a first trench filled with an isolation layer between two adjacent memory cells in the second direction, and a third trench is provided in the isolation layer in the direction towards the substrate, and the third trench communicates with the second trench; The second trench and the third trench expose the sidewalls of the branches of the first electrode, and a dielectric layer of an integral structure and a second electrode of an integral structure are sequentially arranged in the second trench and the third trench; The second trench and the third trench are filled with a common connection layer connected to the second electrode.

13. The semiconductor structure according to claim 12, wherein It further includes a support frame, and the support frame includes the stacked first electrodes and the insulating layer between the first electrodes.

14. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Stacked memory cells, the memory cells including transistors and capacitors, the capacitors including a first electrode electrically connected to the transistors; Forming insulating layers and conductive layers that are alternately distributed along a third direction perpendicular to the substrate on the substrate to form a stacked structure; Patterning the stacked structure to form a plurality of lateral conductive portions that extend along a first direction and are spaced along a second direction, the first direction intersecting the second direction and both being perpendicular to the third direction; Forming a first trench that extends along the first direction between two adjacent lateral conductive portions in the second direction; Etching each of the lateral conductive portions and insulating layers stacked along the third direction to form at least one second trench that penetrates each of the lateral conductive portions and insulating layers and extends along the first direction, the second trench dividing the lateral conductive portions into at least two branch portions, and a length of the second trench along the first direction being less than a length of the first trench along the first direction; The at least two branch portions are the first electrodes.

15. The manufacturing method according to claim 14, characterized in that, After dividing the lateral conductive portions into at least two branch portions, it includes: Filling the first trench with an insulating material to form a first isolation layer; Etching and removing part of the material of the first isolation layer to form a third trench, a length of the third trench along the first direction being equal to a length of the second trench along the first direction; The second trench and the third trench expose sidewalls of the branch portions of the first electrode.

16. The manufacturing method according to claim 15, characterized in that, It further includes: Successively depositing a dielectric material film in the second trench and the third trench to form a dielectric layer of the capacitor, and depositing a conductive material film to form a second electrode of the capacitor.

17. The manufacturing method according to claim 16, characterized in that, It further includes: After forming the second electrode, continuing to deposit a conductive material film in the second trench and the third trench to cover the second electrode and fill the second trench and the third trench, forming a common connection layer, the common connection layer being different from the second electrode in material.

18. The manufacturing method according to claim 14, characterized in that, It further includes: Forming a word line hole that penetrates the stacked structure and extends along the third direction in a region of the lateral conductive portion away from the first electrode, and a conductive layer between an outer contour of the word line hole of the conductive layer and the branch portions includes a conductive layer connecting each of the branch portions of the first electrode, and the conductive layer connecting the branch portions is one of a first source / drain and a second source / drain of the transistor.

19. An electronic device, characterized in that, Including the semiconductor structure according to any one of claims 1-13, or manufactured by the manufacturing method according to any one of claims 14-18.

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