Memory element including word line structure having high dielectric constant gate dielectric layer and method of fabricating same

Abstract

A memory device includes: a semiconductor substrate having an active region; and a word line structure extending across the active region. The word line structure includes a metal gate electrode layer and a high dielectric constant gate dielectric layer surrounding the metal gate electrode layer. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and located on opposite sides of the word line structure. The memory element also includes a bit line structure disposed over the first source / drain region and electrically connected to the first source / drain region; and a capacitor disposed on the second source / drain region and electrically connected to the second source / drain region. The invention also relates to a manufacturing method of the memory element.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 18 / 414,599 (i.e., the priority date is "January 17, 2024"), the content of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to a memory element and a method of manufacturing the same. More particularly, it relates to a memory element including a word line structure having a high-k (high dielectric constant) gate dielectric layer and a method of manufacturing the same. Background Art

[0003] Due to their simple structure, dynamic random access memories (DRAMs) can provide more memory cells per unit chip area than other types of memories (e.g., static random access memories (SRAMs)). A dynamic random access memory is composed of a plurality of DRAM cells, where each dynamic random access memory cell includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor through a bit line (BL). During a write operation, the data to be written is provided on the bit line while the word line is asserted.

[0004] To meet the demand for larger storage capacities, the size of dynamic random access memory cells continues to shrink, resulting in a significant increase in the packaging density of these dynamic random access memories. However, the manufacturing and integration of memory elements involve many complex steps and operations. The integration in memory elements has become increasingly complex. The increasing complexity of the manufacturing and integration of memory elements may lead to defects. Therefore, there is a need to continuously improve the structure and manufacturing process of memory elements to address their defects and improve performance.

[0005] The discussion of the prior art paragraphs provides only background information. The statements in the discussion of the prior art paragraphs do not admit that the content disclosed in this paragraph constitutes the prior art of this disclosure, and any part of the discussion in the prior art paragraphs shall not be used as an admission that any part of this application, including the part in the discussion of the prior art paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0006] In one embodiment of the present disclosure, a memory element is provided. The memory element includes: a semiconductor substrate having an active region; and a word line structure extending across the active region. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure. The memory element further includes: a bit line structure disposed over the first source / drain region and electrically connected to the first source / drain region; and a capacitor disposed over the second source / drain region and electrically connected to the second source / drain region.

[0007] In one embodiment, the high-k gate dielectric layer has a first width above a top surface of the metal gate electrode layer and a second width below the top surface of the metal gate electrode layer, and wherein the second width is greater than the first width. In one embodiment, the memory element further includes: a bit line contact disposed between the first source / drain region and the bit line structure, wherein the bit line contact directly contacts the high-k gate dielectric layer. In one embodiment, the memory element further includes: a dielectric layer covering the word line structure, wherein a portion of the high-k gate dielectric layer is sandwiched between the dielectric layer and the bit line contact. In one embodiment, a portion of the dielectric layer is surrounded by the high-k gate dielectric layer, and a width of the portion of the dielectric layer is greater than a width of the metal gate electrode layer.

[0008] In one embodiment, the memory element further includes: a mask layer disposed between the second source / drain region and the capacitor, wherein the mask layer directly contacts the high-k gate dielectric layer. In one embodiment, the high-k gate dielectric layer has a third width adjacent to the mask layer and a fourth width adjacent to the second source / drain region, and wherein the fourth width is greater than the third width. In one embodiment, a top surface of the high-k gate dielectric layer is substantially flush with a top surface of the mask layer.

[0009] In another embodiment of the present disclosure, a memory element is provided. The memory element includes: a semiconductor substrate having an active region; and a word line structure extending across the active region. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure. The memory element further includes: a dielectric layer disposed on the semiconductor substrate and covering the word line structure. An interface between the dielectric layer and the high-k gate dielectric layer is substantially flush with an interface between the dielectric layer and the metal gate electrode layer. In addition, the memory element includes a bit line structure disposed on the dielectric layer and electrically connected to the first source / drain region; and a capacitor disposed on the dielectric layer and electrically connected to the second source / drain region.

[0010] In one embodiment, the high-k gate dielectric layer has a first width above a top surface of the metal gate electrode layer and a second width below the top surface of the metal gate electrode layer, and wherein the second width is greater than the first width. In one embodiment, the memory element further includes: a bit line contact passing through the dielectric layer to electrically connect to the first source / drain region and the bit line structure, wherein the bit line contact directly contacts the high-k gate dielectric layer.

[0011] In one embodiment, the memory element further includes: a mask layer disposed between the second source / drain region and the dielectric layer, wherein the mask layer directly contacts the high-k gate dielectric layer. In one embodiment, the high-k gate dielectric layer has a third width adjacent to the mask layer and a fourth width adjacent to the second source / drain region, and wherein the fourth width is greater than the third width. In one embodiment, a top surface of the high-k gate dielectric layer is substantially flush with a top surface of the mask layer. In one embodiment, the memory element further includes: a capacitor contact passing through the dielectric layer and the mask layer to electrically connect to the second source / drain region and the capacitor.

[0012] In another embodiment of the present disclosure, a method for manufacturing a memory element is provided. The method includes: forming a doped region in a semiconductor substrate; and performing a first etching process on the semiconductor substrate to form a trench. The trench extends across the doped region to form a first source / drain region and a second source / drain region on opposite sides of the trench. The method also includes forming a high-k dielectric material liner in the trench and filling the trench with a metal material. The method further includes performing a second etching process on the high-k dielectric material and the metal material to form a notch. The remaining portion of the high-k dielectric material and the remaining portion of the metal material respectively form a high-k gate dielectric layer of a word line structure and a metal gate electrode layer of the word line structure, and a width of the notch is greater than a width of the metal gate electrode layer. In addition, the method includes forming a bit line structure over the formation and electrically connecting to the first source / drain region; and forming a capacitor over the second source / drain region and electrically connecting to the second source / drain region.

[0013] In an embodiment, the high-k gate dielectric layer has a first width above a top surface of the metal gate electrode layer and a second width below the top surface of the metal gate electrode layer, and wherein the second width is greater than the first width. The method further includes forming a mask material over the semiconductor substrate and covering the doped region before performing the first etching process, and a remaining portion of the mask material forms a mask layer after performing the second etching process. In an embodiment, a top surface and a sidewall of the mask layer are covered by the high-k gate dielectric material before performing the second etching process. In an embodiment, the top surface of the mask layer is exposed after performing the second etching process.

[0014] In an embodiment, the method further includes: forming a dielectric layer over the semiconductor substrate after performing the second etching process, wherein a portion of the notch is filled by the dielectric layer. In an embodiment, a width of the portion of the dielectric layer is greater than a width of the metal gate electrode layer. In an embodiment, an interface between the dielectric layer and the high-k gate dielectric layer is substantially flush with an interface between the dielectric layer and the metal gate electrode layer. In an embodiment, the method further includes: forming a bit line contact through the dielectric layer to contact the first source / drain region, wherein the bit line contact directly contacts the high-k gate dielectric layer.

[0015] Embodiments of a memory element and a method of manufacturing the same are provided in the present disclosure. In some embodiments, the memory element includes a word line structure disposed in a semiconductor substrate. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. Accordingly, gate-to-substrate leakage current can be reduced while channel leakage current is suppressed and channel length is increased. As a result, the performance of the memory element can be improved.

[0016] The technical features and advantages of the present disclosure have been outlined quite widely above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be readily utilized as a basis for modifying or designing other structures or processes to achieve the same purposes as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The disclosure of the present application can be more fully understood when considering the embodiments and the claims in conjunction with the drawings. It should be noted that, in accordance with the standard industry practice, the features are not drawn to scale. For the sake of clarity in discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0018] Figure 1 is a top view illustrating a memory element of some embodiments;

[0019] Figure 2 is a cross-sectional view illustrating a memory element of some embodiments taken along the cut line A-A' in Figure 1 ;

[0020] Figure 3 is an enlarged view illustrating a part of a memory element of some embodiments in Figure 2 ;

[0021] Figure 4 is an enlarged view illustrating another part of a memory element of some embodiments in Figure 2 ;

[0022] Figure 5 is a flow chart illustrating a method of manufacturing a memory element of some embodiments;

[0023] Figure 6 is a top view illustrating an intermediate stage of forming a doped region in a semiconductor substrate during the formation of a memory element of some embodiments;

[0024] Figure 7 is a cross-sectional view illustrating some embodiments taken along the cut line A - A' in Figure 6 during an intermediate stage in the formation of the memory element;

[0025] Figure 8 is a top view illustrating an intermediate stage in the formation of a mask material and a patterned mask sequentially over a semiconductor substrate during the formation of the memory element in some embodiments;

[0026] Figure 9 is a cross-sectional view illustrating some embodiments taken along the cut line A - A' in Figure 8 during an intermediate stage in the formation of the memory element;

[0027] Figure 10 is a top view illustrating an intermediate stage in the formation of the memory element in some embodiments where the mask material and the semiconductor substrate are etched to form trenches across the doped regions and to form source / drain regions;

[0028] Figure 11 is a cross-sectional view illustrating some embodiments taken along the cut line A - A' in Figure 10 during an intermediate stage in the formation of the memory element;

[0029] Figure 12 is a top view illustrating an intermediate stage in the formation of the memory element in some embodiments where a high-k dielectric material is formed lining the trenches;

[0030] Figure 13 is a cross-sectional view illustrating some embodiments taken along the cut line A - A' in Figure 12 during an intermediate stage in the formation of the memory element;

[0031] Figure 14 is a cross-sectional view illustrating an intermediate stage in the formation of the memory element in some embodiments where the trenches are filled with a metal material;

[0032] Figure 15 is a top view illustrating an intermediate stage in the formation of the memory element in some embodiments where the high-k dielectric material and the metal material are recessed to form a word line structure;

[0033] Figure 16 is a cross-sectional view illustrating some embodiments taken along the cut line A - A' in Figure 15 during an intermediate stage in the formation of the memory element;

[0034] Figure 17 is an enlarged view illustrating Figure 16Part of the memory element of some embodiments;

[0035] Figure 18 Is a cross-sectional view, illustrating an intermediate stage of forming a dielectric layer to cover the word line structure during the formation of the memory element in some embodiments;

[0036] Figure 19 Is a top view, illustrating an intermediate stage of etching a dielectric layer to form a bit line contact opening during the formation of the memory element in some embodiments;

[0037] Figure 20 Is a cross-sectional view, illustrating Figure 19 An intermediate stage during the formation of the memory element in some embodiments taken along the cutting line A-A' in

[0038] Figure 21 Is a top view, illustrating an intermediate stage of forming a bit line contact, a bit line structure, and a dielectric spacer during the formation of the memory element in some embodiments;

[0039] Figure 22 Is a cross-sectional view, illustrating Figure 21 An intermediate stage during the formation of the memory element in some embodiments taken along the cutting line A-A' in

[0040] Figure 23 Is a top view, illustrating an intermediate stage of forming a dielectric layer around the bit line structure and removing the dielectric spacer to form an air gap during the formation of the memory element in some embodiments;

[0041] Figure 24 Is a cross-sectional view, illustrating Figure 23 An intermediate stage during the formation of the memory element in some embodiments taken along the cutting line A-A' in

[0042] Figure 25 Is a top view, illustrating an intermediate stage of forming a dielectric layer to cover the bit line structure and forming a capacitor contact opening during the formation of the memory element in some embodiments;

[0043] Figure 26 Is a cross-sectional view, illustrating Figure 25 An intermediate stage during the formation of the memory element in some embodiments taken along the cutting line A-A' in

[0044] Figure 27 Is a top view, illustrating an intermediate stage of forming a capacitor contact, forming a dielectric layer over the capacitor contact, and forming a capacitor opening in the dielectric layer during the formation of the memory element in some embodiments;

[0045] Figure 28 Is a cross-sectional view, illustrating Figure 27Intermediate stages during the formation of memory elements, taken along the cut line A-A' in some embodiments;

[0046] Figure 29 Is a partial schematic diagram illustrating an exemplary integrated circuit including an array of memory cells in some embodiments.

[0047] Wherein, the reference numerals are explained as follows:

[0048] 10: Method

[0049] 50: Memory cell

[0050] 51: Field effect transistor

[0051] 53: Capacitor

[0052] 55: Drain

[0053] 57: Source

[0054] 59: Gate

[0055] 100: Memory element

[0056] 101: Semiconductor substrate

[0057] 103: Isolation structure

[0058] 105: Active region

[0059] 107: Doped region

[0060] 109: Mask material

[0061] 109’: Mask layer

[0062] 109’S: Sidewall

[0063] 109’T: Top surface

[0064] 111: Patterned mask

[0065] 114: Opening

[0066] 116: Trench

[0067] 119a: Source / drain region

[0068] 119b: Source / drain region

[0069] 121: High-k dielectric material

[0070] 121’: High-k gate dielectric layer

[0071] 121’P: Portion

[0072] 121’T: Top surface

[0073] 123: Metal material

[0074] 123’: Metal gate electrode layer

[0075] 123’T: Top surface

[0076] 125: Character line structure

[0077] 128: Notch

[0078] 131: Dielectric layer

[0079] 131P: Portion

[0080] 134: Bit line contact opening

[0081] 137: Bit line contact

[0082] 141: Lower bit line layer

[0083] 143: Upper bit line layer

[0084] 145: Bit line structure

[0085] 147: Dielectric spacer

[0086] 149: Dielectric layer

[0087] 152: Air gap

[0088] 155: Dielectric layer

[0089] 158: Capacitive contact opening

[0090] 161: Capacitive contact

[0091] 163: Dielectric layer

[0092] 166: Capacitive opening

[0093] 171: Bottom electrode

[0094] 173: Dielectric layer

[0095] 175: Top electrode

[0096] 177: Capacitor

[0097] 1000: Memory element

[0098] BL: Bit line

[0099] INT1: Interface

[0100] INT2: Interface

[0101] P1: Portion

[0102] P2: Portion

[0103] P3: Portion

[0104] S11: Step

[0105] S13: Step

[0106] S15: Step

[0107] S17: Step

[0108] S19: Step

[0109] S21: Step

[0110] S23: Step

[0111] S25: Step

[0112] S27: Step

[0113] S29: Step

[0114] S31: Step

[0115] W1: First Width

[0116] W2: Second Width

[0117] W3: Third Width

[0118] W4: Fourth Width

[0119] W5: Fifth Width

[0120] W6: Sixth Width

[0121] WL: Word Line Detailed Implementation Manner

[0122] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following specific examples of components and configurations simplify the present disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming the first feature above or on top of the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse element symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations discussed.

[0123] Furthermore, for ease of description, spatially relative terms may be used herein, such as "below", "beneath", "lower", "above", "upper", or other similar terms, to describe the relative relationship of one element or feature depicted in the drawings to another element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0124] Figure 1 is a top view illustrating a memory element 100 of some embodiments, Figure 2 is a cross-sectional view illustrating along Figure 1 the memory element 100 of some embodiments taken along the section line A-A' in Figure 3 is an enlarged view illustrating Figure 2 a portion P1 of the memory element 100 of some embodiments in Figure 4 and Figure 2 is an enlarged view illustrating

[0125] As Figure 1 and Figure 2 shown, the memory element 100 includes a semiconductor substrate 101, an isolation structure 103 disposed in the semiconductor substrate 101 and defining a plurality of active regions 105, a plurality of word line structures 125 (i.e., gate structures) extending across the active regions 105, and a plurality of source / drain regions 119a and 119b separated by the word line structures 125 in the active regions 105. In some embodiments, each active region 105 includes two source / drain regions 119b and one source / drain region 119a disposed between the two source / drain regions 119b. In addition, each word line structure 125 includes a high-k (high dielectric constant) gate dielectric layer 121' and a metal gate electrode layer 123' surrounded by the high-k gate dielectric layer 121'.

[0126] In some embodiments, the memory element 100 includes a mask layer 109' disposed over the source / drain region 119b. In some embodiments, the memory element 100 includes a dielectric layer 131 covering the mask layer 109' and the word line structure 125, and a dielectric layer 149 disposed over the dielectric layer 131. In some embodiments, the memory element 100 includes a plurality of bit line contacts 137 that pass through the dielectric layer 131 to contact the source / drain region 119a, and a plurality of bit line structures 145 that pass through the dielectric layer 149 to contact the bit line contacts 137. In some embodiments, each bit line structure 145 includes a lower bit line layer 141 and an upper bit line layer 143 disposed over the lower bit line layer 141. In some embodiments, the bit line structure 145 is separated from the dielectric layer 149 by an air gap 152.

[0127] In addition, the memory element 100 includes a dielectric layer 155 disposed over the dielectric layer 149, a plurality of capacitor contacts 161 that pass through the dielectric layer 155, the dielectric layer 149, the dielectric layer 131, and the mask layer 109' to contact the source / drain region 119b, and a dielectric layer 163 disposed over the dielectric layer 155. According to some embodiments, the memory element 100 further includes a plurality of capacitors 177 disposed in the dielectric layer 163 and contacting the capacitor contacts 161, as Figure 1 and Figure 2 shown.

[0128] In some embodiments, each capacitor 177 includes a bottom electrode 171, a top electrode 175 disposed over and surrounded by the bottom electrode 171, and a dielectric layer 173 disposed between the bottom electrode 171 and the top electrode 175 and directly contacting the bottom electrode 171 and the top electrode 175. In some embodiments, the bit line structure 145 is electrically connected to the source / drain region 119a through the bit line contact 137, and the capacitor 177 is electrically connected to the source / drain region 119b through the capacitor contact 161. In some embodiments, the memory element 100 is part of a dynamic random access memory.

[0129] As Figure 3As shown, the high-k gate dielectric layer 121' of the word line structure 125 has a first width W1 above the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125, and has a second width W2 below the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125. In some embodiments, the second width W2 is greater than the first width W1. Additionally, according to some embodiments, the interface INT1 between the dielectric layer 131 and the high-k gate dielectric layer 121' of the word line structure 125 is substantially flush with the interface INT2 between the dielectric layer 131 and the metal gate electrode layer 123' of the word line structure 125. In the context of the present disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0130] As Figure 4 As shown, the high-k gate dielectric layer 121' of the word line structure 125 has a third width W3 above the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125, and has a fourth width W4 below the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125. In some embodiments, the fourth width W4 is greater than the third width W3. In some embodiments, the interface INT1 between the dielectric layer 131 and the high-k gate dielectric layer 121' of the word line structure 125 is substantially flush with the interface INT2 between the dielectric layer 131 and the metal gate electrode layer 123' of the word line structure 125. Additionally, according to some embodiments, the top surface 121'T of the high-k gate dielectric layer 121' of the word line structure 125 is substantially flush with the top surface 109'T of the mask layer 109'.

[0131] The present disclosure provides embodiments of a memory element 100 and a method of manufacturing the same. In some embodiments, the memory element 100 includes a word line structure 125 disposed in a semiconductor substrate 101, and the word line structure 125 includes a metal gate electrode layer 123' and a high-k gate dielectric layer 121' surrounding the metal gate electrode layer 123'. Accordingly, gate-to-substrate leakage current can be reduced while suppressing channel leakage current and increasing the channel length, which are advantages of the buried word line structure (i.e., the word line structure 125). Additionally, the air gap 152 can help reduce parasitic capacitance and accordingly improve device performance (e.g., by reducing signal noise). In this way, the performance of the memory element 100 can be improved.

[0132] Figure 5is a flowchart illustrating a manufacturing method 10 of a memory element 100 according to some embodiments, and this method 10 includes steps S11, step S13, step S15, step S17, step S19, step S21, step S23, step S25, step S27, step S29, and step S31. Figure 5 Steps S11 to S31 will be described in detail in conjunction with Figures 6 to 28 the following.

[0133] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 15 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 is a top view showing an intermediate stage during the formation of a memory element 100 according to some embodiments, and Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 are cross-sectional views showing an intermediate stage during the formation of a memory element 100 according to some embodiments. It should be noted that Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 16 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 are cross-sectional views taken along the Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 15 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 section line A - A' in Figure 17 is an enlarged view illustrating a part P3 of a memory element 100 according to some embodiments in Figure 16 .

[0134] As shown in Figure 6 and Figure 7As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials can include, but are not limited to, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide.

[0135] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a body semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which can include a substrate, a buried oxide layer located above the substrate, and a semiconductor layer located above the buried oxide layer. For example, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0136] Still referring to Figure 6 and Figure 7 , according to some embodiments, an isolation structure 103 is formed in the semiconductor substrate 101 to define a plurality of active regions 105, and the isolation structure 103 is a shallow trench isolation (STI) structure. In addition, the isolation structure 103 can include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and the formation of the isolation structure 103 can include forming a patterned mask (not shown) on the semiconductor substrate 101, using this patterned mask as a mask to etch the semiconductor substrate 101 to form an opening (not shown), depositing a dielectric material in the opening and on the semiconductor substrate 101, and planarizing this dielectric material until the semiconductor substrate 101 is exposed.

[0137] In addition, a plurality of doped regions 107 are formed in the active regions 105 defined by the isolation structure 103. The corresponding steps are as Figure 5as shown in step S11 of method 10. In some embodiments, the doped region 107 is formed by one or more ion implantation processes, and P-type dopants such as boron (B), gallium (Ga), or indium (In) or N-type dopants such as phosphorus (P) or arsenic (As) can be implanted into the active region 105 according to the conductivity type of the memory element 100 to form the doped region 107. Additionally, in subsequent processes, the doped region 107 will become the source / source region of the memory element 100.

[0138] According to some embodiments, after forming the doped region 107, a masking material 109 is formed over the semiconductor substrate 101, such as Figure 8 and Figure 9 shown. The corresponding steps are as Figure 5 shown in step S13 of method 10. In some embodiments, the isolation structure 103 and the doped region 107 are covered by the masking material 109. Thereafter, according to some embodiments, a patterned mask 111 having an opening 114 is formed over the masking material 109. In some embodiments, the masking material 109 is partially exposed by the opening 114 of the patterned mask 111.

[0139] In some embodiments, the masking material 109 includes silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or a combination thereof. In some embodiments, the masking material 109 and the patterned mask 111 include different materials such that the etching selectivity can be different from each other in subsequent etching processes. In some embodiments, the masking material 109 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable deposition processes.

[0140] According to some embodiments, next, using the patterned mask 111 as an etching mask, the masking material 109 and the semiconductor substrate 101 are etched to form a plurality of trenches 116, such as Figure 10 and Figure 11 shown. In some embodiments, these trenches 116 are parallel to each other. In some embodiments, the trenches 116 extend across the doped region 107 in the active region 105 to form source / drain regions 119a and 119b (the source / drain region 119a is referred to as the first source / drain region, and the source / drain region 119b is referred to as the second source / drain region).

[0141] In some embodiments, the source / drain regions 119b are located at opposite two ends of the active region 105, and the source / drain region 119a is located at the middle portion of the active region 105. In some embodiments, the remaining portion of the mask material 109 is referred to as the mask layer 109'. In some embodiments, the trench 116 is formed by a wet etching process, a dry etching process, or a combination thereof. The corresponding steps are as Figure 5 shown in step S15 of method 10 in

[0142] According to some embodiments, after the trench 116 is formed, the patterned mask 111 is removed, and a high-k dielectric material 121 is conformally deposited on this structure, such as Figure 12 and Figure 13 shown. The corresponding steps are as Figure 5 shown in step S17 of method 10 in

[0143] In some embodiments, the high-k dielectric material 121 is formed to line the trench 116. In some embodiments, the top surface 109’T and sidewalls 109’S of the mask layer 109’ are covered by the high-k dielectric material 121. In some embodiments, the high-k dielectric material 121 includes hafnium silicon oxynitride (HfSiON), hafnium oxynitride (HfON), other suitable dielectric materials with a dielectric constant (k) higher than that of silicon dioxide, or a combination thereof. In some embodiments, the high-k dielectric material 121 is formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes.

[0144] According to some embodiments, subsequently, a metal material 123 is formed on the high-k dielectric material 121, such as Figure 14 shown. In some embodiments, the remaining portion of the trench 116 is filled with the metal material 123. In some embodiments, the metal material 123 extends over the top surface 109’T of the mask layer 109’ (see Figure 13 ). The corresponding steps are as Figure 5 shown in step S19 of method 10 in

[0145] In some embodiments, the metal material 123 includes titanium nitride (TiN), tungsten (W), ruthenium (Ru), aluminum (Al), ruthenium-aluminum (RuAl) alloy, other suitable metals, or combinations thereof. In some embodiments, the metal material 123 is formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or other suitable deposition processes.

[0146] According to some embodiments, subsequently, the high-k dielectric material 121 and the metal material 123 are recessed to form a plurality of word line structures 125, as Figure 15 and Figure 16 shown. The corresponding steps are as shown in step S21 of method 10 in Figure 5 In some embodiments, by performing an etching process to partially remove the high-k dielectric material 121 and the metal material 123, and the remaining part 121' of the high-k dielectric material and the remaining part 123' of the metal material together form the word line structure 125 (the remaining part 121' of the high-k dielectric material is referred to as the high-k gate dielectric layer, and the remaining part 123' of the metal material is referred to as the metal gate electrode layer).

[0147] In some embodiments, after performing the etching process, the top surface 109'T of the mask layer 109' is exposed. In some embodiments, a notch 128 is formed above the word line structure 125. In some embodiments, the notch 128 has a fifth width W5, the metal gate layer 123' of the word line structure 125 has a sixth width W6, and the fifth width W5 is greater than the sixth width W6.

[0148] Figure 7 is an enlarged view illustrating a part P3 of the memory element 100 in some embodiments of Figure 16 As shown in Figure 17 the high-k gate dielectric layer 121' of the word line structure 125 has a first width W1 above the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125, and has a second width W2 below the top surface 123'T of the metal gate electrode layer 123' of the word line structure 125. In some embodiments, the second width W2 is greater than the first width W1.

[0149] According to some embodiments, next, a dielectric layer 131 is formed to cover the mask layer 109' and the word line structure 125, as Figure 18 shown. The corresponding steps are as shown in step S23 of method 10 in Figure 5 In some embodiments, the notch 128 is filled with a part of the dielectric layer 131, for example, the part 131P of the dielectric layer 131. In this case, for the sake of clarity of the disclosure, in Figure 18The boundary of the portion 131P of the dielectric layer 131 is represented by a dashed line in [reference]. There is no distinct interface in the dielectric layer 131.

[0150] According to some embodiments, each high-k gate dielectric layer 121' has a portion sandwiched between adjacent mask layers 109' and a portion of the dielectric layer 131 that fills the notch 128. For example, the portion 121'P of the high-k gate dielectric layer 121', as Figure 18 shown. In some embodiments, the portion 131P of the dielectric layer 131 has a fifth width W5, the metal gate electrode layer 123' of the word line structure 125 has a sixth width W6, and the fifth width W5 is greater than the sixth width W6. Additionally, in some embodiments, the dielectric layer 131 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectrics, or a combination thereof. Further, the dielectric layer 131 can be formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes.

[0151] According to some embodiments, subsequently, a plurality of bit line contact openings 134 are formed to expose the source / drain regions 119a, as Figure 19 and Figure 20 shown. The formation of the bit line contact openings 134 can include forming a patterned mask (not shown) over the dielectric layer 131 and etching the dielectric layer 131 by using the patterned mask as a mask. The etching process can be a wet etching process, a dry etching process, or a combination thereof. After forming the bit line contact openings 134, the patterned mask can be removed.

[0152] According to some embodiments, thereafter, a plurality of bit line contacts 137 are formed in the bit line contact openings 134, and a plurality of bit line structures 145 are formed over the bit line contacts 137, as Figure 21 and Figure 22 shown. The corresponding steps are as shown in steps S25 and S27 of method 10 in Figure 5 In some embodiments, each bit line structure 145 includes a lower bit line layer 141 and an upper bit line layer 143 disposed over the lower bit line layer 141. In some embodiments, the bit line structure 145 is electrically connected to the source / drain regions 119a.

[0153] In some embodiments, the bit line contact 137 includes polysilicon, tungsten, aluminum, copper (Cu), nickel (Ni), cobalt (Co), other suitable conductive materials, or combinations thereof. The formation of the bit line contact 137 may include depositing a bit line contact material (not shown) in the bit line contact opening 134 and on the dielectric layer 131, and performing a planarization process to remove the excess bit line contact material outside the bit line contact opening 134. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes. The planarization process may include a chemical mechanical polishing (CMP) process.

[0154] In addition, the formation of the bit line structure 145 may include forming a lower bit line material (not shown) on the dielectric layer 131, forming an upper bit line material (not shown) on the lower bit line material, forming a patterned mask (not shown) on the upper bit line material, and etching the upper bit line material and the lower bit line material using the patterned mask as a mask. In some embodiments, the remaining portion of the lower bit line material is referred to as the lower bit line layer 141, and the remaining portion of the upper bit line material is referred to as the upper bit line layer 143. After forming the bit line structure 145, the patterned mask may be removed. In some embodiments, the lower bit line layer 141 includes titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), other suitable conductive materials, or combinations thereof. In some embodiments, the upper bit line layer 143 includes tungsten, titanium, nickel, cobalt, other suitable conductive materials, or combinations thereof.

[0155] According to some embodiments, next, a plurality of dielectric spacers 147 are formed on the sidewalls of the bit line structure 145, as Figure 21 and Figure 22 shown. In some embodiments, the dielectric spacers 147 include a doped spin-on-glass (SOG) material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG). In some embodiments, the dielectric spacers 147 are formed by a deposition process and a subsequent planarization process. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes. The planarization process may include a chemical mechanical polishing process. The planarization process may be performed to expose the top surface of the bit line structure 145.

[0156] According to some embodiments, subsequently, a dielectric layer 149 is formed around the dielectric spacer 147 and the bit line structure 145, and the dielectric spacer 147 is removed to form an air gap 152 between the bit line structure 145 and the dielectric layer 149, as Figure 23 and Figure 24 shown. In some embodiments, the air gap 152 is formed on the sidewalls of the bit line structure 145, and the bit line structure 145 is separated from the dielectric layer 149 by the air gap 152.

[0157] In some embodiments, the dielectric layer 149 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof. In addition, the dielectric layer 149 is formed by a deposition process and a subsequent planarization process. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable deposition processes. The planarization process may include a chemical mechanical polishing process. After the planarization process, the top surface of the dielectric layer 149 is coplanar with the top surface of the bit line structure 145 and the top surface of the dielectric spacer 147.

[0158] In some embodiments, after the dielectric layer 149 is formed, the dielectric spacer 147 is removed by a vapor phase hydrofluoric acid (VHF) etching process. During the etching process, VHF is used as the etchant, and the dielectric spacer 147 has a high selectivity with respect to the dielectric layer 149. Therefore, the dielectric spacer 147 is removed by the etching process, and the dielectric layer 149 can be substantially left, thereby obtaining the air gap 152.

[0159] According to some embodiments, thereafter, a dielectric layer 155 is formed on the dielectric layer 149 to seal the air gap 152, and a plurality of capacitor contact openings 158 are formed to expose the source / drain regions 119b, as Figure 25 and Figure 26 shown. Some of the materials and processes used to form the dielectric layer 155 are similar to or the same as those used to form the dielectric layer 149, and will not be described in detail herein. In some embodiments, the dielectric layer 155 is formed by a spin coating process, and the air gap 152 having a high aspect ratio is sealed by the dielectric layer 155, and the air gap 152 is not filled by the dielectric layer 155 but remains therein.

[0160] In some embodiments, a capacitive contact opening 158 is formed through the dielectric layer 155, the dielectric layer 149, and the dielectric layer 131 and the mask layer 109' located above the source / drain region 119b. The formation of the capacitive contact opening 158 may include forming a patterned mask (not shown) on the dielectric layer 155, and etching the dielectric layer 155 by using the patterned mask as a mask. The etching process may be a wet etching process, a dry etching process, or a combination thereof. After forming the capacitive contact opening 158, the patterned mask may be removed.

[0161] According to some embodiments, next, a plurality of capacitive contacts 161 are formed in the capacitive contact opening 158, and a dielectric layer 163 is formed on the dielectric layer 155 to cover the capacitive contacts 161, as Figure 27 and Figure 28 shown. In some embodiments, the capacitive contacts 161 electrically connect the source / drain regions 119b to a subsequently formed capacitor. The corresponding steps are as shown in step S29 of method 10 in Figure 5 .

[0162] In some embodiments, the capacitive contacts 161 are made of a conductive material, for example, copper, tungsten, aluminum, titanium, tantalum, gold, silver, other suitable conductive materials, or a combination thereof. The capacitive contacts 161 may be formed by a deposition process and a subsequent planarization process. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or other suitable processes. The planarization process may be a chemical mechanical polishing process. Some of the materials and processes for forming the dielectric layer 163 are similar to or the same as those for forming the dielectric layer 155, and will not be described herein again.

[0163] Still referring to Figure 27 and Figure 28 , according to some embodiments, a plurality of capacitive openings 166 are formed through the dielectric layer 163 to expose the capacitive contacts 161. The formation of the capacitive openings 166 may include forming a patterned mask (not shown) on the dielectric layer 163, and etching the dielectric layer 163 by using the patterned mask as a mask to expose the capacitive contacts 161. The etching process may be a wet etching process, a dry etching process, or a combination thereof. After forming the capacitive openings 166, the patterned mask may be removed.

[0164] According to some embodiments, subsequently, still referring to Figure 1 and Figure 2 , a plurality of capacitors 177 are formed in the capacitive openings 166 in the dielectric layer 163. As described above, each capacitor 177 includes a bottom electrode 171, a top electrode 175, and a dielectric layer 173 sandwiched between the bottom electrode 171 and the top electrode 175. The corresponding steps are as shown in step S31 of method 10 in Figure 5 .

[0165] In some embodiments, the top electrode 175, the dielectric layer 173, and the bottom electrode 171 together form a capacitor 177 electrically connected to the source / drain region 119b. The formation of the capacitor 177 may include sequentially depositing a conductive material, a dielectric material, and another conductive material in the capacitor opening 166 (see Figure 27 and Figure 28 ) and extending over the dielectric layer 163, and performing a planarization process (e.g., a chemical mechanical polishing process) to remove the excess portions of the two conductive materials and the dielectric material.

[0166] In some embodiments, the bottom electrode 171 includes titanium nitride or other suitable conductive material. In some embodiments, the dielectric layer 173 includes a dielectric material, e.g., silicon dioxide, hafnium dioxide, aluminum oxide, zirconium dioxide, other suitable dielectric materials, or a combination thereof. In some embodiments, the top electrode 175 includes titanium nitride, low stress silicon germanium, other suitable conductive materials, or a combination thereof. After forming the capacitor 177, the memory element 100 is obtained. In some embodiments, the memory element 100 is part of a dynamic random access memory.

[0167] Figure 29 is a partial schematic diagram illustrating an exemplary integrated circuit including an array of memory cells 50, e.g., the memory element 1000, of some embodiments. In some embodiments, the memory element 1000 includes a dynamic random access memory. In some embodiments, the memory element 1000 includes a plurality of memory cells 50 arranged in a grid pattern and including a plurality of rows and a plurality of columns. The number of memory cells 50 may vary according to system requirements and manufacturing technology.

[0168] In some embodiments, each memory cell 50 includes an access element and a storage element. The access element is configured to provide controlled access to the storage element. In particular, according to some embodiments, the access element is a field effect transistor (FET) 51 and the storage element is a capacitor 53. In each memory cell 50, the field effect transistor 51 includes a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the field effect transistor 51, and the other terminal of the capacitor 53 may be electrically connected to ground. Further, in each memory cell 50, the gate 59 of the field effect transistor 51 is electrically connected to the word line WL, and the drain 55 of the field effect transistor 51 is electrically connected to the bit line BL.

[0169] As mentioned above, the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 is the source 57, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL is the drain 55. However, during read and write operations, the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 can be the drain, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL can be the source. That is, depending on the way the voltage applied to the source, drain, and gate controls the field-effect transistor 51, either terminal of the field-effect transistor 51 can be the source or the drain.

[0170] By controlling the voltage at the gate 59 via the word line WL, a potential can be generated across the two ends of the field-effect transistor 51 such that charge can flow from the drain 55 to the capacitor 53. Therefore, the charge stored in the capacitor 53 can be interpreted as a binary data value in the memory cell 50. For example, a positive charge stored in the capacitor 53 that is higher than the threshold voltage can be interpreted as a binary "1". If the charge in the capacitor 53 is below the threshold, a binary value of "0" is said to be stored in the memory cell 50.

[0171] The bit line BL is configured to read data from the memory cell 50 and write data to the memory cell 50. The word line WL is configured to activate the field-effect transistor 51 to access a specific column of the memory cell 50. Therefore, the memory 1000 also includes a peripheral circuit region, and the peripheral circuit region can include an address buffer, a column decoder, and a row decoder. The column decoder and the row decoder selectively access the memory cell 50 in response to an address signal provided to the address buffer during read, write, and refresh operations. The address signal is typically provided by an external controller, such as a microprocessor or another type of memory controller.

[0172] Referring again Figure 1 and Figure 2 , the memory element 100 is located in the array region. The array region can be any region of the memory cells 50 in the memory element 1000.

[0173] The present disclosure provides embodiments of a memory element 100 and a method of manufacturing the same. In some embodiments, the memory element 100 includes a word line structure 125 disposed in a semiconductor substrate 101, and the word line structure 125 includes a metal gate electrode layer 123' and a high-k gate dielectric layer 121' surrounding the metal gate electrode layer 123'. Therefore, the gate-to-substrate leakage current can be reduced while suppressing the channel leakage current and increasing the channel length, which are advantages of the buried word line structure (i.e., the word line structure 125). In addition, the air gap 152 can help reduce the parasitic capacitance and accordingly improve the device performance (e.g., by reducing the signal noise). In this way, the performance of the memory element 100 can be improved.

[0174] In one embodiment of the present disclosure, a memory element is provided. This memory element includes: a semiconductor substrate having an active region; and a word line structure extending across the active region. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure. The memory element further includes: a bit line structure disposed over the first source / drain region and electrically connected to the first source / drain region; and a capacitor disposed over the second source / drain region and electrically connected to the second source / drain region.

[0175] In one embodiment of the present disclosure, a memory element is provided. The memory element includes: a semiconductor substrate having an active region; and a word line structure extending across the active region. The word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure. The memory element further includes: a dielectric layer disposed over the semiconductor substrate and covering the word line structure. An interface between the dielectric layer and the high-k gate dielectric layer is substantially flush with an interface between the dielectric layer and the metal gate electrode layer. Additionally, the memory element includes a bit line structure disposed over the dielectric layer and electrically connected to the first source / drain region; and a capacitor disposed over the dielectric layer and electrically connected to the second source / drain region.

[0176] In yet another embodiment of the present disclosure, a method of manufacturing a memory element is provided. The method includes: forming a doped region in a semiconductor substrate; and performing a first etching process on the semiconductor substrate to form a trench. The trench extends across the doped region to form a first source / drain region and a second source / drain region on opposite sides of the trench. The method also includes forming a high-k dielectric material liner in the trench and filling the trench with a metal material. The method further includes performing a second etching process on the high-k dielectric material and the metal material to form a notch. The remaining portion of the high-k dielectric material and the remaining portion of the metal material respectively form a high-k gate dielectric layer of a word line structure and a metal gate electrode layer of the word line structure and a width of the notch is greater than a width of the metal gate electrode layer. Additionally, the method includes forming a bit line structure over the formation and electrically connected to the first source / drain region; and forming a capacitor over the second source / drain region and electrically connected to the second source / drain region.

[0177] Embodiments of the present disclosure have some advantageous features. By forming a word line structure with a high dielectric constant gate dielectric layer in the array region, it is possible to suppress the gate-to-substrate leakage current while suppressing the channel leakage current and increasing the channel length. In this way, the performance of the memory element can be improved.

[0178] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above-described processes can be implemented in different ways, and many of the above-described processes can be replaced by other processes or combinations thereof.

[0179] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: A semiconductor substrate having an active region; A word line structure extending across the active region, wherein the word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer; A first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure; A bit line structure disposed over the first source / drain region and electrically connected to the first source / drain region; and A capacitor disposed over the second source / drain region and electrically connected to the second source / drain region.

2. The memory element according to claim 1, wherein the high-k gate dielectric layer has a first width above a top surface of the metal gate electrode layer and a second width below the top surface of the metal gate electrode layer, and wherein the second width is greater than the first width.

3. The memory element according to claim 1, further comprising: A bit line contact disposed between the first source / drain region and the bit line structure, wherein the bit line contact directly contacts the high-k gate dielectric layer.

4. The memory element according to claim 3, further comprising: A dielectric layer covering the word line structure, wherein a portion of the high-k gate dielectric layer is sandwiched between the dielectric layer and the bit line contact.

5. The memory element according to claim 4, wherein a portion of the dielectric layer is surrounded by the high-k gate dielectric layer, and a width of the portion of the dielectric layer is greater than a width of the metal gate electrode layer.

6. The memory element according to claim 1, further comprising: A mask layer disposed between the second source / drain region and the capacitor, wherein the mask layer directly contacts the high-k gate dielectric layer.

7. The memory element according to claim 6, wherein the high-k gate dielectric layer has a third width adjacent to the mask layer and a fourth width adjacent to the second source / drain region, and wherein the fourth width is greater than the third width.

8. The memory element according to claim 6, wherein a top surface of the high-k gate dielectric layer is substantially flush with a top surface of the mask layer.

9. A memory element, comprising: A semiconductor substrate having an active region; A word line structure extending across the active region, wherein the word line structure includes a metal gate electrode layer and a high-k gate dielectric layer surrounding the metal gate electrode layer; A first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line structure; A dielectric layer disposed over the semiconductor substrate and covering the word line structure, wherein an interface between the dielectric layer and the high-k gate dielectric layer is substantially flush with an interface between the dielectric layer and the metal gate electrode layer; A bit line structure disposed over the dielectric layer and electrically connected to the first source / drain region; and A capacitor disposed over the dielectric layer and electrically connected to the second source / drain region.

10. The memory element as claimed in claim 9, wherein the high-k gate dielectric layer has a first width above a top surface of the metal gate electrode layer and a second width below the top surface of the metal gate electrode layer, and wherein the second width is greater than the first width.

11. The memory element as claimed in claim 9, further comprising: a bit line contact passing through the dielectric layer for electrically connecting to the first source / drain region and the bit line structure, wherein the bit line contact directly contacts the high-k gate dielectric layer.

12. The memory element as claimed in claim 9, further comprising: a mask layer disposed between the second source / drain region and the dielectric layer, wherein the mask layer directly contacts the high-k gate dielectric layer.

13. The memory element as claimed in claim 12, wherein the high-k gate dielectric layer has a third width adjacent to the mask layer and a fourth width adjacent to the second source / drain region, and wherein the fourth width is greater than the third width.

14. The memory element as claimed in claim 12, wherein a top surface of the high-k gate dielectric layer is substantially flush with a top surface of the mask layer.

15. The memory element as claimed in claim 12, further comprising: a capacitor contact passing through the dielectric layer and the mask layer for electrically connecting to the second source / drain region and the capacitor.

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