Memory device and operating method thereof

Abstract

The invention provides a memory device and an operating method thereof. The memory device includes a stacked structure, an insulating film, a conductive film, a pillar element, and a plurality of memory cells. The stack structure comprises a storage array stack and a stepped stack; an insulating film on the memory array stack; a conductive film on the stepped stack and on a sidewall of the insulating film; a pillar element on the stepped stack and extending through the conductive film; a plurality of memory cells are in the memory array stack and electrically connected to the pillar elements.

Description

Technical Field

[0001] The present invention relates to a storage device and an operation method thereof, and more particularly to a three-dimensional storage device and an operation method thereof. Background Art

[0002] Three-dimensional storage devices have a high bit density and thus have become the current technological mainstream. However, most three-dimensional storage devices still have some electrical problems. There is still a need to provide an improved three-dimensional storage device and a manufacturing method thereof. Summary of the Invention

[0003] The present invention provides a storage device and an operation method thereof. The component configuration of the storage device of the present invention can avoid the influence of component damage on the electrical performance of the storage device. Moreover, the storage device of the present invention can select a specific storage unit in a simple manner and perform operation modes such as reading, programming, or erasing on it.

[0004] According to an embodiment of the present invention, a storage device is provided. The storage device includes a stacked structure, an insulating film, a conductive film, a column element, and a plurality of storage units. The stacked structure includes a storage array stack and a stepped stack. The insulating film is on the storage array stack. The conductive film is on the stepped stack and on the sidewalls of the insulating film. The column element is on the stepped stack and extends through the conductive film. The plurality of storage units are in the storage array stack and are electrically connected to the column element.

[0005] According to an embodiment of the present invention, an operation method of a storage device is provided. The storage device includes a plurality of storage units, a plurality of bit lines electrically connected to the plurality of storage units, a plurality of word lines electrically connected to the plurality of storage units, and a plurality of word line switches electrically connecting the plurality of word lines and the plurality of storage units. The operation method of the storage device includes: applying a word line voltage to the word line electrically connected to the selected storage unit among the plurality of word lines, applying a control voltage to the word line switch electrically connected to the selected storage unit among the plurality of word line switches, and applying a bit line voltage to the bit line electrically connected to the selected storage unit among the plurality of bit lines to turn on the selected storage unit. Wherein applying a control voltage to the word line switch electrically connected to the selected storage unit makes the word line electrically connected to the selected storage unit in a conducting state. Applying a control voltage to the word line switch electrically connected to the selected storage unit does not change the conducting state of the plurality of bit lines.

[0006] In order to have a better understanding of the above and other aspects of the present invention, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0007] Figure 1A A schematic cross-sectional view of a storage device according to an embodiment of the present invention is shown;

[0008] Figure 1B Schematic perspective view showing a storage device according to an embodiment of the present invention;

[0009] Figure 1C Schematic perspective view showing a storage device according to another embodiment of the present invention;

[0010] Figure 1D Schematic cross-sectional view showing a storage device according to still another embodiment of the present invention;

[0011] Figure 1E Schematic perspective view showing a storage device according to still another embodiment of the present invention;

[0012] Figures 2 to 16 Method for manufacturing a storage device according to an embodiment of the present invention; and

[0013] Figures 17 to 31 Method for manufacturing a storage device according to another embodiment of the present invention.

[0014] Description of reference numerals

[0015] 10, 10’, 20: Storage device

[0016] 101: Substrate

[0017] 102, 102’: Stacked structure

[0018] 102A: Storage array stack

[0019] 102B: Stepped stack

[0020] 103: Conductive layer

[0021] 104, 1703A: Insulating layer

[0022] 105: Stepped conductive layer

[0023] 106, 1703B: Stepped insulating layer

[0024] 108: Insulating material film

[0025] 121, 122, 124, 125, 126, 122A: Insulating film

[0026] 122S: Sidewall

[0027] 123, 123’: Conductive film

[0028] 123L: Lower surface

[0029] 101U, 121U, 123U: Upper surface

[0030] 130, 130’: Column element

[0031] 130A: First column part

[0032] 130B, 130B’: Second column part

[0033] 130C: Third column part

[0034] 132: Dielectric element

[0035] 133, 133’: Channel element

[0036] 134: Dielectric column

[0037] 135: Pad

[0038] 151: Contact column

[0039] 152: Conductor

[0040] 160: Column structure

[0041] 161: Bi - directional material layer

[0042] 162: Second electrode layer

[0043] 163: Conductive column

[0044] 164: First electrode layer

[0045] 168: Landing pad

[0046] 170, 171: Slit

[0047] 203: Conductive material layer

[0048] 204, 1703: Insulating material layer

[0049] 560, 960, 1260, 1460, 1461, 2060, 2460, 2860, 3060, 3061: Hole

[0050] 1802: Insulating stack structure

[0051] 1802A: Insulating stack

[0052] 1802B: Step - shaped insulating stack

[0053] 2260: Notch

[0054] D1: First direction

[0055] D2: Second direction

[0056] D3: Third direction

[0057] E1: First end

[0058] E2: The second end portion Detailed implementation manners

[0059] The following presents relevant embodiments, in conjunction with the accompanying drawings, to describe in detail the storage device proposed by the present invention. The accompanying drawings are simplified to facilitate a clear description of the content of the embodiments, and the dimensional ratios in the drawings are not drawn in proportion to the actual products. Therefore, the description and the drawings are only used to describe the embodiments and are not intended to limit the protection scope of the present invention. The same or similar element symbols are used to represent the same or similar elements. Furthermore, the ordinal numbers such as "first", "second", "third", etc. used in the description and the claims are used to modify the elements, and they do not imply or represent that the elements have any previous ordinal numbers, nor do they represent the order of one element and another element or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name.

[0060] Please refer to Figure 1A and Figure 1B . Figure 1A FIG. shows a schematic cross-sectional view of a storage device 10 according to an embodiment. Figure 1B FIG. shows a schematic perspective view of a storage device 10 according to an embodiment. For simplicity of illustration, Figure 1B some of the elements shown in Figure 1A are omitted, and Figure 1A and Figure 1B the number of the same elements in

[0061] The storage device 10 includes a substrate 101, a stacked structure 102, an insulating material film 108, insulating films 121, 122, a conductive film 123, insulating films 124, 125, 126, a pillar element 130, a contact pillar 151, a wire 152, and a pillar structure 160. The stacked structure 102 is disposed on the substrate 101 along a first direction D1. The first direction D1 is, for example, a vertical direction or a longitudinal direction. The stacked structure 102 includes a storage array stack 102A and a stepped stack 102B. The storage array stack 102A and the stepped stack 102B can be disposed adjacent to each other. The storage array stack 102A and the stepped stack 102B do not overlap with each other in the first direction D1. In this embodiment, the storage array stack 102A and the stepped stack 102B are disposed along a second direction D2. In this embodiment, the storage array stack 102A and the stepped stack 102B do not overlap with each other in a third direction D3. The second direction D2 and the third direction D3 are, for example, a horizontal direction or a lateral direction. The first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. The storage array stack 102A includes a plurality of conductive layers 103 and a plurality of insulating layers 104 that are alternately stacked along the first direction D1. The plurality of conductive layers 103 isolate the plurality of insulating layers 104 from each other. The stepped stack 102B includes a plurality of stepped conductive layers 105 and a plurality of stepped insulating layers 106 that are alternately stacked along the first direction D1. The plurality of stepped conductive layers 105 isolate the plurality of stepped insulating layers 106 from each other. In the stepped stack 102B, the plurality of stepped conductive layers 105 can have different sizes; the size is, for example, an area in a plane formed by the second direction D2 and the third direction D3, or a width in the second direction D2, or a width in the third direction D3. For example, the area of the stepped conductive layer 105 in the plane formed by the second direction D2 and the third direction D3 gradually decreases from bottom to top along the first direction D1. For example, the area of the stepped conductive layer 105 located in a lower layer in the plane formed by the second direction D2 and the third direction D3 is larger than the area of the stepped conductive layer 105 located in a higher layer in the plane formed by the second direction D2 and the third direction D3. The conductive layer 103 of the storage array stack 102A can be electrically connected to the stepped conductive layer 105 of the stepped stack 102B. The insulating layer 104 of the storage array stack 102A and the stepped insulating layer 106 of the stepped stack 102B can be electrically insulated. The conductive layer 103 of the storage array stack 102A and the stepped conductive layer 105 of the stepped stack 102B can serve as a gate electrode structure of the storage device 10.

[0062] In one embodiment, the plurality of conductive layers 103 of the storage array stack 102A have a one-to-one correspondence with the plurality of stepped conductive layers 105 of the stepped stack 102B. In other words, a conductive layer 103 and the corresponding stepped conductive layer 105 may have the same height (or level) in the first direction D1. In one embodiment, the upper surface of the conductive layer 103 and the upper surface of the corresponding stepped conductive layer 105 may be coplanar. In one embodiment, the height of the conductive layer 103 in the first direction D1 may be less than the height of the corresponding stepped conductive layer 105 in the first direction D1. In one embodiment, the plurality of insulating layers 104 of the storage array stack 102A have a one-to-one correspondence with the plurality of stepped insulating layers 106 of the stepped stack 102B. In other words, an insulating layer 104 and the corresponding stepped insulating layer 106 may have the same height (or level) in the first direction D1. FIG. 1 shows five conductive layers 103 and five stepped conductive layers 105, but the present invention is not limited thereto. The conductive layer 103 and the stepped conductive layer 105 may have a greater number.

[0063] The insulating material film 108 is on the storage array stack 102A and the stepped stack 102B. The insulating material film 108 may cover the upper surface of the storage array stack 102A, the upper surface of the stepped stack 102B, and the sidewalls of the stepped stack 102B. The insulating films 121, 122, 124, 125, and 126 are arranged in sequence along the first direction D1 on the stack structure 102 and the insulating material film 108. In the first direction D1, the insulating film 121 may overlap the storage array stack 102A and the stepped stack 102B. The insulating film 122 and the conductive film 123 are on the insulating film 121. The insulating film 122 is on the storage array stack 102A. In the first direction D1, the insulating film 122 may overlap the storage array stack 102A. The insulating film 121 is between the insulating film 122 and the storage array stack 102A. The conductive film 123 is on the stepped stack 102B. In the first direction D1, the conductive film 123 may overlap the stepped stack 102B. The insulating film 121 is between the conductive film 123 and the stepped stack 102B. The conductive film 123 is on the sidewall 122S of the insulating film 122. The conductive film 123 may be adjacent to the insulating film 122. The conductive film 123 and the insulating film 122 may be arranged along the second direction D2. In one embodiment, the conductive film 123 and the insulating film 122 may have the same height (or level) in the first direction D1. The insulating film 124 is on the insulating film 122. The insulating film 122 is between the insulating film 124 and the insulating film 121. The insulating film 125 is on the insulating film 124. The insulating film 124 is between the insulating film 125 and the insulating film 122. The insulating film 126 is on the insulating film 125. The insulating film 125 is between the insulating film 126 and the insulating film 124. In the first direction D1, the insulating films 124, 125, and 126 may overlap the storage array stack 102A and the stepped stack 102B.

[0064] The storage device 10 may include one or more column elements 130. A plurality of column elements 130 may be dispersedly arranged. The column elements 130 are on the stepped stack 102B of the stack structure 102. The column elements 130 are on the stepped conductive layer 105 of the stepped stack 102B. The column elements 130 are electrically connected to the stepped conductive layer 105 and the conductive layer 103. The column elements 130 extend along the first direction D1 through the insulating material film 108, the insulating film 121, the conductive film 123, the insulating film 124, the insulating film 125, and the insulating film 126. The column element 130 includes a first column portion 130A, a second column portion 130B, and a third column portion 130C arranged in sequence from bottom to top along the first direction D1. The second column portion 130B is between the first column portion 130A and the third column portion 130C. The first column portion 130A, the second column portion 130B, and the third column portion 130C are electrically connected to each other. The first column portion 130A may extend along the first direction D1 through the insulating material film 108 and land on the stepped conductive layer 105. The first column portion 130A has a first end E1 and a second end E2 opposite to the first end E1. The first end E1 of the first column portion 130A is disposed on the upper surface of the stepped conductive layer 105 of the stepped stack 102B. The second end E2 of the first column portion 130A is connected to the second column portion 130B. The second column portion 130B is in the insulating film 121, the conductive film 123, and the insulating film 124. The second column portion 130B includes a dielectric element 132, a channel element 133, a dielectric column 134, and a pad 135. The dielectric element 132 is between the channel element 133 and the conductive film 123. The dielectric element 132 may be on the outer sidewall of the channel element 133. The dielectric element 132 may surround the channel element 133. The channel element 133 is between the dielectric element 132 and the dielectric column 134. The channel element 133 may be on the sidewall of the dielectric column 134. The channel element 133 may surround the dielectric column 134. The dielectric element 132 and the channel element 133 may have a tubular shape. The dielectric element 132 may electrically insulate the column element 130 from the conductive film 123. The dielectric element 132, the channel element 133, and the dielectric column 134 may extend along the first direction D1 beyond the upper surface 123U and the lower surface 123L of the conductive film 123. The pad 135 is on the channel element 133 and the dielectric column 134. The pad 135 is between the channel element 133 and the third column portion 130C. The third column portion 130C may extend along the first direction D1 through the insulating film 125 and the insulating film 126. The third column portion 130C may be electrically connected to the channel element 133 of the second column portion 130B through the pad 135 of the second column portion 130B. In one embodiment, the conductive film 123, the dielectric element 132, and the channel element 133 may form a transistor switch. The transistor switch formed by the conductive film 123, the dielectric element 132, and the channel element 133 may be used as a word line switch. The conductive film 123 may be used as the control electrode of the transistor. The dielectric element 132 may be used as the gate dielectric of the transistor.The conductive film 123 can be used as a word line selection line or a word plane for word lines.

[0065] The memory device 10 may include one or more pillar structures 160. The plurality of pillar structures 160 may be dispersedly arranged in the memory array stack 102A of the stack structure 102. The pillar structure 160 may extend along the first direction D1 through the memory array stack 102A, the insulating material film 108, the insulating film 121, the insulating film 122, the insulating film 124, and the insulating film 125. The pillar structure 160 may include a first electrode layer 164, a bi-directional material layer 161, a second electrode layer 162, a conductive pillar 163, and a landing pad 168. The bi-directional material layer 161 is interposed between the first electrode layer 164 and the second electrode layer 162. The second electrode layer 162 is interposed between the conductive pillar 163 and the bi-directional material layer 161. The first electrode layer 164 may be on the outer surface of the bi-directional material layer 161. The first electrode layer 164 may surround the bi-directional material layer 161. The bi-directional material layer 161 may be on the outer surface of the second electrode layer 162. The bi-directional material layer 161 may surround the second electrode layer 162. The second electrode layer 162 may be on the outer surface of the conductive pillar 163. The second electrode layer 162 may surround the conductive pillar 163. The first electrode layer 164, the bi-directional material layer 161, and the second electrode layer 162 may have a tubular shape. The landing pad 168 is on the first electrode layer 164, the bi-directional material layer 161, the second electrode layer 162, and the conductive pillar 163. The landing pad 168 may be electrically connected to the conductive pillar 163. The conductive pillar 163 can be used as a bit line of the memory device 10. In this embodiment, the upper surface of the pillar structure 160 (or the upper surface of the landing pad 168) is higher than the upper surface 123U of the conductive film 123 in the first direction D1. The pillar structure 160 may be electrically connected to the wire 152 through the contact pillar 151.

[0066] In other embodiments, the pillar structure 160 may not include the first electrode layer 164 and the second electrode layer 162. In other embodiments, the pillar structure 160 may not include one of the first electrode layer 164 and the second electrode layer 162.

[0067] The memory device 10 may include one or more contact pillars 151. The plurality of contact pillars 151 may be dispersedly arranged. The contact pillar 151 may extend along the first direction D1 through the insulating film 126. The contact pillar 151 is on the memory array stack 102A. The contact pillar 151 is on the conductive pillar 163. The contact pillar 151 is on the landing pad 168. The contact pillar 151 may be electrically connected to the conductive pillar 163 through the landing pad 168. In one embodiment, the contact pillar 151 and the conductive pillar 163 have a one-to-one correspondence, that is, the number of the contact pillar 151 and the conductive pillar 163 is the same and one contact pillar 151 is arranged on one conductive pillar 163.

[0068] The storage device 10 may include a plurality of conductive lines 152. The plurality of conductive lines 152 may be arranged along the second direction D2. The conductive lines 152 may extend along the third direction D3. The conductive lines 152 are on the insulating film 126. The conductive lines 152 may be electrically connected to the contact posts 151 and the third post portion 130C of the post element 130. A part of the plurality of conductive lines 152 is arranged on the stepped stack 102B and the conductive film 123, and is electrically connected to the second post portion 130B through the third post portion 130C of the post element 130. A part of the plurality of conductive lines 152 is arranged on the memory array stack 102A and the insulating film 122, and is electrically connected to the conductive post 163 through the contact post 151.

[0069] The storage device 10 may include a plurality of memory cells disposed in the memory array stack 102A. The memory cells may be defined at the intersections of the conductive posts 163 of the column structure 160 and the conductive layer 103 of the memory array stack 102A. The memory cells are electrically connected to the post element 130. The conductive posts 163 are electrically connected to the memory cells and may serve as bit lines for controlling the memory cells. The conductive layer 103 of the memory array stack 102A and the stepped conductive layer 105 of the stepped stack 102B may serve as word lines for electrically connecting the memory cells. The transistor switch formed by the conductive film 123, the dielectric element 132, and the channel element 133 may serve as a word line switch for electrically connecting the memory cells.

[0070] In one embodiment, the storage device 10 may include a drive circuit, such as a CMOS circuit, in a lower region of the substrate 101. The drive circuit and the stacked structure 102 may be located on opposite sides of the substrate 101.

[0071] Figure 1A Showing a stacked structure (such as the stacked structure 102), but the present invention is not limited thereto, and the storage device may have more than one stacked structure as Figure 1C shown. Figure 1C Schematic perspective view showing a storage device 10' including a plurality of stacked structures according to another embodiment.

[0072] The storage device 10' includes a stacked structure 102 and a stacked structure 102'. The stacked structure 102 can be adjacent to the stacked structure 102'. The stacked structure 102 and the stacked structure 102' can be arranged along the third direction D3. The storage device 10' can include a conductive film 123 and a conductive film 123'. The conductive film 123 can be adjacent to the conductive film 123'. The conductive film 123 and the conductive film 123' can be arranged along the third direction D3. In this embodiment, the storage device 10' can include a slit 170 and a slit 171. The slit 170 extends along the second direction D2 and isolates the stacked structure 102 from the stacked structure 102'. The slit 171 extends along the second direction D2 and isolates the conductive film 123 from the conductive film 123'. In one embodiment, the slits 170 and 171 can be filled with an insulating material to form insulating strips.

[0073] The structure of the stacked structure 102' can be similar to the structure of the stacked structure 102. The memory array stack 102A of the stacked structure 102 can be adjacent to the memory array stack of the stacked structure 102'. The stepped stack 102B of the stacked structure 102 can be adjacent to the stepped stack 102B' of the stacked structure 102'. In the first direction D1, the conductive film 123 can overlap the stepped stack 102B of the stacked structure 102, and the conductive film 123' can overlap the stepped stack 102B' of the stacked structure 102'.

[0074] Similar to the storage device 10, the storage device 10' further includes a substrate, an insulating material film, a plurality of insulating films on the stacked structure 102 and the stacked structure 102', at least one pillar element 130, at least one contact pillar 151, a plurality of wires 152, and at least one pillar structure 160. The structures of the substrate, the insulating material film, the plurality of insulating films on the stacked structure 102 and the stacked structure 102', and the pillar structure 160 of the storage device 10' can be respectively similar to the substrate 101, the insulating material film 108, the insulating films 121, 122, 124, 125, and 126, and the pillar structure 160 of the storage device 10 shown in FIGS. 1A to 1B. The pillar element 130 disposed on the stacked structure 102 can be electrically connected to the pillar element 130 disposed on the stacked structure 102' through the wire 152. The conductive pillar 163 of the pillar structure 160 disposed on the stacked structure 102 can be electrically connected to the conductive pillar 163 of the pillar structure 160 disposed on the stacked structure 102' through the wire 152. The storage device 10' has a higher storage density.

[0075] In other embodiments, the storage device of the present invention can have more than two stacked structures, and their structures can be in accordance with Figures 1A to 1C of the storage devices 10 and 10' and so on.

[0076] Please refer to Figure 1D and Figure 1E .Figure 1D FIG. 1 is a schematic cross-sectional view showing a storage device 20 according to an embodiment. Figure 1E FIG. 2 is a schematic perspective view showing a storage device 20 according to an embodiment. For simplicity of illustration, Figure 1E some components shown in Figure 1D are omitted, and Figure 1D and Figure 1E the number of the same components in Figure 1D and Figure 1E may be different. The storage device 20 may be a three-dimensional two-way threshold switch memory. Figure 1A The differences between the storage device 20 in Figure 1B and the storage device 10 in

[0077] are described as follows. The storage device 20 includes a plurality of column structures 160. A part of the plurality of column structures 160 can pass through the stepped stack 102B of the stack structure 102, and another part of the plurality of column structures 160 can pass through the memory array stack 102A of the stack structure 102. The column structures 160 in the stepped stack 102B may be electrically floating and can be regarded as virtual (dummy) column structures. The column structures 160 can serve as support elements. The column structures 160 in the memory array stack 102A may not pass through the insulating films 121, 122, 124, and 125. The contact pillars 151 can extend along the first direction D1 through the insulating films 121, 122, 124, 125, and 126 and are electrically connected to the column structures 160 in the memory array stack 102A. In this embodiment, the upper surface of the column structure 160 (or the upper surface of the landing pad 168) is lower than the lower surface 123L of the conductive film 123 in the first direction D1. The column element 130' of the storage device 20 includes a first column portion 130A, a second column portion 130B', and a third column portion 130C. The second column portion 130B' includes a dielectric element 132, a channel element 133', a dielectric column 134, and a pad 135. The material of the channel element 133' of the second column portion 130B' of the storage device 20 may be the same as or different from the material of the channel element 133 of the second column portion 130B of the storage device 10. Figures 1A to 1B The operation method of the storage device according to an embodiment of the present invention will be described below by taking the storage device 10 in

[0078] The steps of activating a selected memory cell include: applying a word line voltage to a word line electrically connected to a selected memory cell among multiple word lines of the memory device 10 (such as multiple conductive layers 103 of the memory array stack 102A and multiple stepped conductive layers 105 of the stepped stack 102B), applying a control voltage to a word line switch electrically connected to the word line of the selected memory cell among multiple word line switches (such as multiple transistor switches formed by the conductive film 123, the dielectric element 132, and the channel element 133), and applying a bit line voltage to a bit line electrically connected to the selected memory cell among multiple bit lines (such as multiple conductive posts 163) to activate the selected memory cell. Applying a control voltage to the word line switch electrically connected to the selected memory cell makes the word line electrically connected to the selected memory cell in a conductive state. Since the conductive post 163 of the memory device 10 does not pass through the conductive film 123, applying a control voltage to the word line switch electrically connected to the selected memory cell does not change the conductive state of the multiple bit lines. In the operation method of the memory device 10, applying a control voltage to the word line switch does not change the conductive states of the word line switch and the bit line simultaneously. The word line switch and the bit line can be controlled independently.

[0079] The steps of deactivating unselected memory cells include: applying a ground voltage to multiple word lines electrically connected to multiple unselected memory cells among multiple word lines of the memory device 10 (such as multiple conductive layers 103 of the memory array stack 102A and multiple stepped conductive layers 105 of the stepped stack 102B), applying a ground voltage to multiple word line switches electrically connected to the multiple word lines of the multiple unselected memory cells among multiple word line switches (such as multiple transistor switches formed by the conductive film 123, the dielectric element 132, and the channel element 133), and applying a ground voltage to multiple bit lines electrically connected to the multiple unselected memory cells among multiple bit lines (such as multiple conductive posts 163) to deactivate the multiple unselected memory cells.

[0080] For example, the storage device of the present invention can be operated by applying the voltages listed in Table 1 below. As shown in Table 1, in the RESET operation mode, a voltage of 1 / 2Vs (bit line voltage) can be applied to the bit line electrically connected to the selected storage cell, a voltage of -1 / 2Vs (word line voltage) can be applied to the word line electrically connected to the selected storage cell, and a voltage of Vs + 1 (control voltage) can be applied to the word line switch electrically connected to the selected storage cell to turn on the selected storage cell; a voltage of 0V (ground voltage) can be applied to the bit line electrically connected to the unselected storage cell, a voltage of 0V (ground voltage) can be applied to the word line electrically connected to the unselected storage cell, and a voltage of (ground voltage) can be applied to the word line switch electrically connected to the unselected storage cell to turn off the unselected storage cell. As shown in Table 1, in the SET operation mode, a voltage of -1 / 2Vs (bit line voltage) can be applied to the bit line electrically connected to the selected storage cell, a voltage of 1 / 2Vs (word line voltage) can be applied to the word line electrically connected to the selected storage cell, and a voltage of Vs + 1 (control voltage) can be applied to the word line switch electrically connected to the selected storage cell to turn on the selected storage cell; a voltage of 0V (ground voltage) can be applied to the bit line electrically connected to the unselected storage cell, a voltage of 0V (ground voltage) can be applied to the word line electrically connected to the unselected storage cell, and a voltage of (ground voltage) can be applied to the word line switch electrically connected to the unselected storage cell to turn off the unselected storage cell. As shown in Table 1, in the READ operation mode, a voltage of 1 / 2Vr (bit line voltage) can be applied to the bit line electrically connected to the selected storage cell, a voltage of -1 / 2Vr (word line voltage) can be applied to the word line electrically connected to the selected storage cell, and a voltage of Vs + 1 or Vr + 1 (control voltage) can be applied to the word line switch electrically connected to the selected storage cell to turn on the selected storage cell; a voltage of 0V (ground voltage) can be applied to the bit line electrically connected to the unselected storage cell, a voltage of 0V (ground voltage) can be applied to the word line electrically connected to the unselected storage cell, and a voltage of (ground voltage) can be applied to the word line switch electrically connected to the unselected storage cell to turn off the unselected storage cell. Vs can range from 2.5V to 9V, for example 5V. Vr can range from 1V to 6V, for example 3V. As shown in Table 1, the bias direction of the voltage (e.g., the first bit line voltage; 1 / 2Vs) applied to the bit line electrically connected to the selected storage cell in the RESET operation mode is opposite to the bias direction of the voltage (e.g., the second bit line voltage; -1 / 2Vs) applied to the bit line electrically connected to the selected storage cell in the SET operation mode. The bias direction of the voltage (e.g., the word line voltage; -1 / 2Vs) applied to the word line electrically connected to the selected storage cell in the RESET operation mode is opposite to the bias direction of the voltage (e.g., the word line voltage; 1 / 2Vs) applied to the word line electrically connected to the selected storage cell in the SET operation mode.

[0081] Table 1

[0082]

[0083]

[0084] In the storage device of the present invention, there is no bit line switch sharing a control electrode with the word line switch. Thus, during the operation of the storage device, applying a voltage to the control electrode of the word line switch will not affect the conduction state of the bit line. By applying voltages to the bit line, the word line, and the character plane (word line switch) respectively, a specific memory cell in the storage device can be selected, and operations such as reading, programming, or erasing can be performed on the selected memory cell.

[0085] Figures 2 to 16 Illustrates a manufacturing method of a storage device according to an embodiment.

[0086] Please refer to Figure 2 。 Figure 2 is a stage of the manufacturing method of the storage device. Provide a substrate 101. Form a plurality of conductive material layers 203 and a plurality of insulating material layers 204 stacked alternately along a first direction D1 on the upper surface 101U of the substrate 101. The first direction D1 can be the normal direction of the upper surface 101U of the substrate 101. In an embodiment, a plurality of conductive material layers 203 and a plurality of insulating material layers 204 can be formed on the upper surface 101U of the substrate 101 through a deposition process. The thickness of the lowermost insulating material layer 204 among the plurality of insulating material layers 204 in the first direction D1 can be greater than the thickness of the other insulating material layers 204 in the first direction D1. The topmost insulating material layer 204 among the plurality of insulating material layers 204 can be a hard mask layer. The substrate 101 can include doped or undoped semiconductor materials, dielectric materials, or conductive materials. In an embodiment, the substrate 101 can be a doped or undoped silicon substrate. In an embodiment, the substrate 101 can be an intermetal dielectric (IMD) or an interlayer dielectric (ILD) formed by a back end of line (BEOL) process. The conductive material layer 203 can include conductive materials such as carbon, titanium nitride, highly doped polysilicon (such as N+ polysilicon or P+ polysilicon), tantalum nitride, cobalt, silicon germanium alloy (SiGe x )), ruthenium, nickel, aluminum, etc. The insulating material layer 204 can include oxides such as silicon oxide.

[0087] Please refer to Figure 3 。 Figure 3 is a stage of the manufacturing method of the storage device. Form a stacked structure 102 on the substrate 101. In an embodiment, through an etching process, for Figure 2The multiple conductive material layers 203 and the multiple insulating material layers 204 shown are patterned to form a stacked structure 102 including a memory array stack 102A and a stepped stack 102B. The conductive material layer 203 defined as a part of the memory array stack 102A is the conductive layer 103. The conductive material layer 203 defined as a part of the stepped stack 102B is the stepped conductive layer 105. The insulating material layer 204 defined as a part of the memory array stack 102A is the insulating layer 104. The insulating material layer 204 defined as a part of the stepped stack 102B is the stepped insulating layer 106.

[0088] Please refer to Figure 4 。 Figure 4 is a stage of a method for manufacturing a memory device. An insulating material film 108 is formed on the stacked structure 102. In one embodiment, the insulating material film 108 can be formed on the stacked structure 102 by a deposition process. The insulating material film 108 can include an oxide, such as silicon oxide.

[0089] Please refer to Figure 5 。 Figure 5 is a stage of a method for manufacturing a memory device. A plurality of first pillar portions 130A are formed. The plurality of first pillar portions 130A can be dispersedly arranged on the stepped stack 102B of the stacked structure 102. The first pillar portions 130A extend along a first direction D1 through the insulating material film 108. The first pillar portions 130A are electrically connected to the stepped conductive layer 105 of the stepped stack 102B. In one embodiment, a part of the stepped stack 102B and a part of the insulating material film 108 can be removed by an etching process to form a plurality of holes 560. The plurality of holes 560 can be dispersedly arranged in the insulating material film 108. The holes 560 can expose the sidewalls of the insulating material film 108 and the upper surface of the stepped conductive layer 105. A conductive material can be filled in the holes 560 by a deposition process to form the first pillar portions 130A. The conductive material of the first pillar portions 130A can include tungsten. In one embodiment, before filling the conductive material in the holes 560, a barrier film can be formed on the sidewalls of the insulating material film 108 exposed by the holes 560 by a deposition process. The barrier film can include titanium nitride. In one embodiment, after filling the conductive material in the holes 560, the conductive material can be planarized by methods such as chemical mechanical polishing.

[0090] Please refer to Figure 6 。 Figure 6is a stage of the manufacturing method of the storage device. Insulating film 121 and insulating film 122A are formed. In one embodiment, insulating film 121 and insulating film 122A can be formed in sequence on insulating material film 108 and the first pillar portion 130A through a deposition process. Insulating film 121 and insulating film 122A may contain insulating materials such as silicon oxide, lithium titanate oxide (LTO), silicon nitride, hafnium oxide (HfO x )、hafnium zirconium oxide (HfZrO x )、silicon oxynitride (SiON x ).

[0091] Please refer to Figure 7 . Figure 7 is a stage of the manufacturing method of the storage device. Insulating film 122 is formed. In one embodiment, a part of insulating film 122A can be removed through an etching process to expose a part of the upper surface 121U of insulating film 121, and the remaining part of insulating film 122A is insulating film 122.

[0092] Please refer to Figure 8 . Figure 8 is a stage of the manufacturing method of the storage device. Conductive film 123 and insulating film 124 are formed. In one embodiment, conductive film 123 can be formed on the upper surface 121U of insulating film 121 and the sidewall 122S of insulating film 122 through a deposition process, and then insulating film 124 can be formed on insulating film 122 and conductive film 123 through a deposition process. Conductive film 123 may contain conductive materials such as tungsten, titanium nitride, tantalum nitride, ruthenium, cobalt, nickel, aluminum, doped polysilicon, silicon germanium (SiGe x ), carbon. Doped polysilicon may include polysilicon heavily doped with N-type impurities and polysilicon heavily doped with P-type impurities. In one embodiment, conductive film 123 may contain tungsten and titanium nitride. Insulating film 124 may contain insulating materials such as silicon oxide, lithium titanate oxide (LTO), silicon nitride, hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ), silicon oxynitride (SiON x ).

[0093] Please refer to Figure 9 . Figure 9This is a stage of the manufacturing method of a storage device. A plurality of holes 960 are formed. The plurality of holes 960 may be dispersedly arranged in the conductive film 123. The holes 960 extend along the first direction D1 through the insulating film 124, the conductive film 123, and the insulating film 121. The holes 960 expose the upper surface of the first pillar portion 130A, the side walls of the insulating film 121, the side walls of the conductive film 123, and the side walls of the insulating film 124. The positions of the holes 960 may correspond to the positions of the first pillar portions 130A. In one embodiment, portions of the insulating film 124, portions of the conductive film 123, and portions of the insulating film 121 may be removed by an etching process to form the plurality of holes 960.

[0094] Please refer to Figure 10 。 Figure 10 This is a stage of the manufacturing method of a storage device. A second pillar portion 130B is formed. In one embodiment, a gate dielectric may be filled in the holes 960 by a deposition process, and an anisotropic etching is performed on the gate dielectric to remove a part of the gate dielectric to form a dielectric element 132 having a tubular shape. A channel element 133 may be formed on the side walls of the dielectric element 132 by a deposition process. A dielectric pillar 134 may be formed on the side walls of the channel element 133 by a deposition process. The dielectric pillar 134 may fill the space surrounded by the channel element 133. A pad 135 may be formed on the upper surface of the dielectric element 132, the upper surface of the channel element 133, and the upper surface of the dielectric pillar 134 by a deposition process, thereby forming the second pillar portion 130B including the dielectric element 132, the channel element 133, the dielectric pillar 134, and the pad 135. The gate dielectric may include a dielectric material such as silicon oxide, lithium titanate oxide (LTO), silicon nitride, hafnium oxide (HfO x )), hafnium zirconium oxide (HfZrO x ), silicon oxynitride (SiON x ). The channel element 133 may include doped polysilicon, undoped polysilicon, or indium gallium zinc oxide (IGZO). The dielectric pillar 134 may include an oxide such as silicon oxide. The pad 135 may include a conductive material.

[0095] Please refer to Figure 11 。 Figure 11 This is a stage of the manufacturing method of a storage device. An insulating film 125 is formed. In one embodiment, the insulating film 125 may be formed on the insulating film 124 and the second pillar portion 130B by a deposition process. The insulating film 125 may include an insulating material such as silicon oxide, lithium titanate oxide (LTO), silicon nitride, hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ), silicon oxynitride (SiON x ).

[0096] Please refer to Figure 12 . Figure 12 This is a stage of the manufacturing method of a storage device. A plurality of holes 1260 are formed. The plurality of holes 1260 may be dispersedly arranged in the memory array stack 102A of the stack structure 102. The holes 1260 extend along the first direction D1 through the insulating film 125, the insulating film 124, the insulating film 122, the insulating film 121, the insulating material film 108, and the memory array stack 102A. The holes 1260 expose a part of the upper surface 101U of the substrate 101, the side walls of the memory array stack 102A of the stack structure 102, the side walls of the insulating material film 108, the side walls of the insulating film 121, the side walls of the insulating film 122, the side walls of the insulating film 124, and the side walls of the insulating film 125. In one embodiment, a part of the insulating film 125, a part of the insulating film 124, a part of the insulating film 122, a part of the insulating film 121, a part of the insulating material film 108, and a part of the memory array stack 102A may be removed by an etching process to form a plurality of holes 1260.

[0097] Please refer to Figure 13 . Figure 13 This is a stage of the manufacturing method of a storage device. A plurality of pillar structures 160 are formed. In one embodiment, a first electrode layer 164 may be formed on the upper surface 101U of the substrate 101 exposed by the holes 1260, the side walls of the memory array stack 102A, the side walls of the insulating material film 108, the side walls of the insulating film 121, the side walls of the insulating film 122, the side walls of the insulating film 124, and the side walls of the insulating film 125 by a deposition process. A two-way material layer 161 may be formed on the side walls of the first electrode layer 164 and the upper surface 101U of the substrate 101 exposed by the holes 1260 by a deposition process. A second electrode layer 162 may be formed on the side walls of the two-way material layer 161 and the upper surface 101U of the substrate 101 exposed by the holes 1260 by a deposition process. A conductive pillar 163 may be formed on the side walls of the second electrode layer 162 and the upper surface 101U of the substrate 101 exposed by the holes 1260 by a deposition process. A part of the first electrode layer 164, the two-way material layer 161, the second electrode layer 162, and the conductive pillar 163 may be removed by an etching process, and then a landing pad 168 may be formed on the remaining parts of the first electrode layer 164, the two-way material layer 161, the second electrode layer 162, and the conductive pillar 163 by a deposition process. Thus, a pillar structure 160 including the first electrode layer 164, the two-way material layer 161, the second electrode layer 162, the conductive pillar 163, and the landing pad 168 is formed. The conductive pillar 163 may fill the space surrounded by the second electrode layer 162.

[0098] The first electrode layer 164 and the second electrode layer 162 may comprise a conductive material, such as titanium nitride, tantalum nitride, titanium, cobalt, doped polysilicon, silicide, etc. The first electrode layer 164 and the second electrode layer 162 may comprise the same or different materials. In some embodiments, the first electrode layer 164 and the second electrode layer 162 may each independently be a C / TiN multilayer structure or composite material, or tantalum nitride, or a Ti / TaN multilayer structure or composite material, or cobalt, or N+ polysilicon, or P+ polysilicon, or silicide. The two-way material layer 161 may comprise a chalcogenide. In some embodiments, the two-way material layer 161 may be a Ge / As / Se multilayer structure or composite material, or a Ge / As / Se / Sn multilayer structure or composite material, or a Ge / As / Si / Se / Te / S multilayer structure or composite material, or a Ge / As / SiTe / S / Sn multilayer structure or composite material, or a Si / Te / As / Se / Si multilayer structure or composite material. The conductive pillar 163 may comprise a conductive material, such as titanium nitride, tantalum nitride, cobalt, tungsten, copper, ruthenium, aluminum, silicide, etc. In some embodiments, the conductive pillar 163 may comprise a TiN / TaN multilayer structure or composite material. The landing pad 168 may comprise a conductive material, such as titanium nitride, tantalum nitride, tungsten, copper, cobalt, aluminum, doped polysilicon, silicide, etc. In some embodiments, the landing pad 168 may comprise or be a TiN / W / Cu multilayer structure or composite material.

[0099] In other embodiments, the pillar structure 160 may not include the first electrode layer 164 and / or the second electrode layer 162, so that the steps of forming the first electrode layer 164 and / or the second electrode layer 162 may be omitted.

[0100] Please refer to Figure 14 . Figure 14is a stage of a method for manufacturing a storage device. An insulating film 126, a plurality of holes 1460, and a plurality of holes 1461 are formed. The insulating film 126 is on the insulating film 125 and the column structure 160. The plurality of holes 1460 may be dispersedly disposed on the stepped stack 102B of the stack structure 102. The holes 1460 extend along a first direction D1 through the insulating film 125 and the insulating film 126. The holes 1460 expose the upper surface of the pad 135 of the second column portion 130B, the sidewalls of the insulating film 125, and the sidewalls of the insulating film 126. The plurality of holes 1461 may be dispersedly disposed on the storage array stack 102A of the stack structure 102. The holes 1461 extend along the first direction D1 through the insulating film 126. The holes 1461 expose the upper surface of the landing pad 168 of the column structure 160 and the sidewalls of the insulating film 126. In one embodiment, the insulating film 126 may be formed on the insulating film 125 and the column structure 160 by a deposition process, and then a portion of the insulating film 125 and a portion of the insulating film 126 may be removed by an etching process to form the plurality of holes 1460 and 1461. The insulating film 126 may include an insulating material such as silicon oxide, lithium titanate oxide (LTO), silicon nitride, hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ), silicon oxynitride (SiON x ).

[0101] Please refer to Figure 15 . Figure 15 is a stage of a method for manufacturing a storage device. A contact column 151 and a third column portion 130C are formed. In one embodiment, the third column portion 130C may be formed in the holes 1460 by a deposition process, and the contact column 151 may be formed in the holes 1461 by a deposition process. The contact column 151 and the third column portion 130C may include a conductive material such as doped or undoped polysilicon, metal.

[0102] Please refer to Figure 16 . Figure 16 is a stage of a method for manufacturing a storage device. A wire 152 is formed. The wire 152 may be formed on the upper surface of the contact column 151 and the upper surface of the third column portion 130C by a deposition process. The position of the wire 152 may correspond to the positions of the contact column 151 and the third column portion 130C. The wire 152 may include a conductive material.

[0103] In one embodiment, by performing the method exemplarily illustrated in Figures 2 to 16 , the storage device 10 as shown in Figure 1A and Figure 1B can be obtained. In one embodiment, the method illustrated in Figures 2 to 16 employs a high-temperature process to form the second column portion 130B so that a larger current can pass through the channel element 133 of the second column portion 130B.

[0104] Figures 17 to 31 Illustrates a manufacturing method of a storage device according to another embodiment.

[0105] Please refer to Figure 17 . Figure 17 This is a stage of the manufacturing method of the storage device. Provide a substrate 101. Form a plurality of insulating material layers 1703 and a plurality of insulating material layers 204 that are alternately stacked along a first direction D1 on the upper surface 101U of the substrate 101. The first direction D1 can be the normal direction of the upper surface 101U of the substrate 101. In one embodiment, a plurality of insulating material layers 1703 and a plurality of insulating material layers 204 can be formed on the upper surface 101U of the substrate 101 through a deposition process. The thickness of the lowermost insulating material layer 204 among the plurality of insulating material layers 204 in the first direction D1 can be greater than the thickness of the other insulating material layers 204 in the first direction D1. The topmost insulating material layer 204 among the plurality of insulating material layers 204 can be a hard mask layer. The insulating material layer 1703 can include a nitride, such as silicon nitride.

[0106] Please refer to Figure 18 . Figure 18 This is a stage of the manufacturing method of the storage device. Form an insulating stack structure 1802 on the substrate 101. In one embodiment, the plurality of insulating material layers 1703 and the plurality of insulating material layers 204 shown in FIG. 17 can be patterned through an etching process to form an insulating stack structure 1802 including an insulating stack 1802A and a stepped insulating stack 1802B. The insulating material layer 1703 defined as a part of the insulating stack 1802A is the insulating layer 1703A. The insulating material layer 1703 defined as a part of the stepped insulating stack 1802B is the stepped insulating layer 1703B. The insulating material layer 204 defined as a part of the insulating stack 1802A is the insulating layer 104. The insulating material layer 204 defined as a part of the stepped insulating stack 1802B is the stepped insulating layer 106. The insulating stack 1802A includes alternately stacked insulating layers 1703A and insulating layers 104. The stepped insulating stack 1802B includes alternately stacked stepped insulating layers 1703B and stepped insulating layers 106.

[0107] Please refer to Figure 19 . Figure 19 This is a stage of the manufacturing method of the storage device. Form an insulating material film 108 on the insulating stack 1802A and the stepped insulating stack 1802B. In one embodiment, an insulating material film 108 can be formed on the insulating stack 1802A and the stepped insulating stack 1802B through a deposition process.

[0108] Please refer to Figure 20 .Figure 20 This is a stage of the manufacturing method of a storage device. A plurality of holes 2060 are formed. The plurality of holes 2060 can be dispersedly arranged in the insulating stack 1802A and the stepped insulating stack 1802B. The holes 2060 extend along the first direction D1 through the insulating material film 108, the insulating stack 1802A, and the stepped insulating stack 1802B. The holes 2060 expose a part of the upper surface 101U of the substrate 101, the side walls of the insulating stack 1802A, the side walls of the stepped insulating stack 1802B, and the side walls of the insulating material film 108. In one embodiment, a part of the insulating stack 1802A, a part of the stepped insulating stack 1802B, and a part of the insulating material film 108 can be removed through an etching process to form a plurality of holes 2060.

[0109] Please refer to Figure 21 。 Figure 21 This is a stage of the manufacturing method of a storage device. A plurality of column structures 160 are formed. In one embodiment, the first electrode layer 164, the two-way material layer 161, the second electrode layer 162, the conductive column 163, and the landing pad 168 can be sequentially formed in the holes 2060 through a deposition process and an etching process to form the column structure 160. In other embodiments, the column structure 160 may not include the first electrode layer 164 and / or the second electrode layer 162, so the steps of forming the first electrode layer 164 and / or the second electrode layer 162 can be omitted.

[0110] Please refer to Figure 22 。 Figure 22 This is a stage of the manufacturing method of a storage device. The insulating layer 1703A and the stepped insulating layer 1703B are removed to form a notch 2260. The column structure 160 can serve as a support element of the structure to avoid collapse. In one embodiment, the insulating layer 1703A between the plurality of insulating layers 104 and the stepped insulating layer 1703B between the plurality of stepped insulating layers 106 can be removed through an etching process to form the notch 2260 and retain the insulating layer 104 and the stepped insulating layer 106.

[0111] Please refer to Figure 23 。 Figure 23 This is a stage of the manufacturing method of a storage device. A plurality of conductive layers 103 and a plurality of stepped conductive layers 105 are formed. In one embodiment, a plurality of conductive layers 103 and a plurality of stepped conductive layers 105 can be formed in the notch 2260 through a deposition process, thereby forming a stacked structure 102 including a storage array stack 102A and a stepped stack 102B.

[0112] Please refer to Figure 24 。 Figure 24This is a stage in the manufacturing method of a storage device. A plurality of first pillar portions 130A are formed. In one embodiment, a portion of the stepped stack 102B and a portion of the insulating material film 108 may be removed through an etching process to form a plurality of holes 2460; then, a conductive material may be filled in the holes 2460 through a deposition process to form the first pillar portions 130A. The plurality of holes 2460 may be dispersedly arranged in the insulating material film 108. The holes 2460 may expose the sidewalls of the insulating material film 108 and the upper surface of the stepped conductive layer 105. In one embodiment, before filling the conductive material in the holes 2460, a barrier film may be formed on the sidewalls of the insulating material film 108 exposed by the holes 2460 through a deposition process. The barrier film may include titanium nitride. In one embodiment, after filling the conductive material in the holes 2460, the conductive material may be planarized by methods such as chemical mechanical polishing. In this embodiment, the upper surface of the pillar structure 160 may be coplanar with the upper surface of the first pillar portions 130A.

[0113] Please refer to Figure 25 。 Figure 25 This is a stage in the manufacturing method of a storage device. An insulating film 121 and an insulating film 122A are formed. In one embodiment, the insulating film 121 and the insulating film 122A may be sequentially formed on the insulating material film 108, the first pillar portions 130A, and the pillar structure 160 through a deposition process.

[0114] Please refer to Figure 26 。 Figure 26 This is a stage in the manufacturing method of a storage device. An insulating film 122 is formed. In one embodiment, a portion of the insulating film 122A may be removed through an etching process to expose a portion of the upper surface 121U of the insulating film 121 and form the insulating film 122.

[0115] Please refer to Figure 27 。 Figure 27 This is a stage in the manufacturing method of a storage device. A conductive film 123 and an insulating film 124 are formed. In one embodiment, the conductive film 123 may be formed on the upper surface 121U of the insulating film 121 and the sidewalls 122S of the insulating film 122 through a deposition process, and then the insulating film 124 may be formed on the insulating film 122 and the conductive film 123 through a deposition process.

[0116] Please refer to Figure 28 。 Figure 28This is a stage of the manufacturing method of a storage device. A plurality of holes 2860 are formed. The plurality of holes 2860 may be dispersedly arranged in the conductive film 123. The holes 2860 extend along the first direction D1 through the insulating film 124, the conductive film 123, and the insulating film 121. The holes 2860 expose the upper surface of the first pillar portion 130A, the side walls of the insulating film 121, the side walls of the conductive film 123, and the side walls of the insulating film 124. The positions of the holes 2860 may correspond to the positions of the first pillar portions 130A. In one embodiment, portions of the insulating film 124, portions of the conductive film 123, and portions of the insulating film 121 may be removed through an etching process to form the plurality of holes 2860.

[0117] Please refer to Figure 29 。 Figure 29 This is a stage of the manufacturing method of a storage device. A second pillar portion 130B' is formed. In one embodiment, a gate dielectric may be filled in the holes 2860 through a deposition process, and an anisotropic etching is performed on the gate dielectric to remove a portion of the gate dielectric to form a dielectric element 132 having a tubular shape; then a channel element 133' may be formed on the side walls of the dielectric element 132 through a deposition process; then a dielectric pillar 134 may be formed on the side walls of the channel element 133'; then a pad 135 may be formed on the upper surfaces of the dielectric element 132, the upper surface of the channel element 133', and the upper surface of the dielectric pillar 134, thereby forming the second pillar portion 130B' including the dielectric element 132, the channel element 133', the dielectric pillar 134, and the pad 135. The dielectric pillar 134 may fill the space surrounded by the channel element 133'. The channel element 133' may include indium gallium zinc oxide (IGZO).

[0118] Please refer to Figure 30 。 Figure 30is a stage of a method for manufacturing a storage device. An insulating film 125, an insulating film 126, a contact post 151, and a third column portion 130C are formed. In one embodiment, the insulating film 125 and the insulating film 126 can be sequentially formed on the upper surface of the insulating film 124 and the second column portion 130B' through a deposition process; then, part of the insulating film 125 and part of the insulating film 126 can be removed through an etching process to form a plurality of holes 3060, and part of the insulating film 121, part of the insulating film 122, part of the insulating film 124, part of the insulating film 125, and part of the insulating film 126 can be removed through an etching process to form a plurality of holes 3061. The plurality of holes 3060 can be dispersedly arranged in the insulating film 125 and the insulating film 126 and located on the stepped stack 102B of the stack structure 102. The holes 3060 extend along the first direction D1 through the insulating film 125 and the insulating film 126. The holes 3060 expose the upper surface of the second column portion 130B', the side walls of the insulating film 125, and the side walls of the insulating film 126. The positions of the holes 3060 can correspond to the positions of the second column portion 130B'. The plurality of holes 3061 can be dispersedly arranged in the insulating film 121, the insulating film 122, the insulating film 124, the insulating film 125, and the insulating film 126 and located on the storage array stack 102A of the stack structure 102. The holes 3061 extend along the first direction D1 through the insulating film 121, the insulating film 122, the insulating film 124, the insulating film 125, and the insulating film 126. The holes 3061 expose the upper surface of the column structure 160, the side walls of the insulating film 121, the side walls of the insulating film 122, the side walls of the insulating film 124, the side walls of the insulating film 125, and the side walls of the insulating film 126. The positions of the holes 3061 can correspond to the positions of the column structure 160 in the storage array stack 102A. In one embodiment, the third column portion 130C can be formed in the holes 3060 through a deposition process, and the contact post 151 can be formed in the holes 3061. Thus, a column element 130' including a first column portion 130A, a second column portion 130B', and a third column portion 130C is formed.

[0119] Please refer to Figure 31 。 Figure 31 is a stage of a method for manufacturing a storage device. A wire 152 is formed. The wire 152 can be formed on the upper surface of the contact post 151 and the upper surface of the third column portion 130C through a deposition process. The position of the wire 152 can correspond to the positions of the contact post 151 and the third column portion 130C.

[0120] In one embodiment, by implementing the method exemplarily illustrated in Figures 17 to 31 , a storage device 20 as shown in Figure 1D and Figure 1E can be obtained. In one embodiment, the method illustrated in Figures 17 to 31 adopts a low-temperature process to form the second column portion 130B' (i.e.,Figures 17 to 31 the temperature of the process for forming the second pillar portion 130B’ in the method is less than Figures 2 to 16 (the temperature of the process for forming the second pillar portion 130B in the method), so as to avoid damaging the bi-directional material layer 161 in the pillar structure 160 due to high temperature and avoid the reduction of the electrical performance of the storage device 20 caused by the damage of the bi-directional material layer 161.

[0121] In one embodiment, Figure 1C the manufacturing method of the storage device 10’ shown may be similar to Figures 2 to 16 the manufacturing method described or Figures 17 to 31 the manufacturing method described.

[0122] The storage device of the present invention includes a conductive film on a stepped stack, and the conductive film does not extend above the storage array stack. The conductive film serves only as a word line selection line for word lines and not as a serial selection line for memory cells. The storage device does not include a serial selection switch and a word line switch sharing a control electrode. The conductive film of the storage device can serve as a character plane, and the control electrodes of multiple word line switches are electrically connected to the character plane (or can be understood as having a common control electrode). Through such a configuration, specific memory cells in the storage device can be selected by applying voltages to the bit line, word line, and character plane respectively, and operations such as reading, programming, or erasing can be performed on them. Moreover, the component configuration of the storage device is such that the pillar structure can be formed after the transistor switch formed by the conductive film, dielectric element, and channel element. Therefore, the high-temperature process for the transistor switch formed by the conductive film, dielectric element, and channel element is not applied to the pillar structure, which can avoid damaging the bi-directional material layer in the pillar structure due to high temperature and avoid the reduction of the electrical performance of the device caused by component damage. In particular, transistor switches containing polysilicon usually require the use of high-temperature processes, and the storage device of the present invention can avoid damaging the bi-directional material layer in the pillar structure by the high-temperature process for polysilicon. In addition, the present invention also provides another storage device in which the pillar structure is formed before the transistor switch. In such a storage device, the transistor switch can use indium gallium zinc oxide (IGZO) instead of polysilicon, and the high-temperature process for polysilicon can be omitted, thereby avoiding damaging the bi-directional material layer in the pillar structure by the high-temperature process.

[0123] It should be noted that the above-mentioned drawings, structures, and steps are used to describe some embodiments or application examples of the present invention. The present invention is not limited to the scope and application aspects of the above-mentioned structures and steps. Embodiments with different structural aspects, such as known components with different internal components, can be applied, and the example structures and steps can be adjusted according to the actual application requirements. Therefore, the structure of the drawings is only used for illustration and not for limiting the present invention. Those with ordinary knowledge should know that in the process of applying the relevant structures and steps of the present invention, such as the arrangement or configuration of relevant components and layers in a semiconductor structure, or the details of manufacturing steps, etc., may be adjusted and changed according to the actual application state requirements.

[0124] In summary, although the present invention has been disclosed above in embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the appended claims.

Claims

1. A storage device, comprising: A stacked structure, comprising a storage array stack and a stepped stack; An insulating film on the storage array stack; A conductive film on the stepped stack and on a sidewall of the insulating film; A column element on the stepped stack and extending through the conductive film; And A plurality of storage cells in the storage array stack and electrically connected to the column element.

2. The storage device according to claim 1, wherein the column element comprises a dielectric element and a channel element, the dielectric element is between the channel element and the conductive film, the column element extends through the conductive film along a first direction, the insulating film overlaps the storage array stack in the first direction, and the conductive film overlaps the stepped stack in the first direction.

3. The storage device according to claim 1, further comprising: A column structure, comprising a bi-directional material layer and extending through the storage array stack.

4. The storage device according to claim 3, wherein the column structure comprises a first electrode layer and a second electrode layer, and the bi-directional material layer is between the first electrode layer and the second electrode layer.

5. The storage device according to claim 1, wherein when operating the storage device to turn on a selected storage cell among these storage cells, a bias direction of a voltage applied to a bit line electrically connected to the selected storage cell in an erase RESET operation mode is opposite to a bias direction of a voltage applied to the bit line electrically connected to the selected storage cell in a program SET operation mode.

6. An operation method of a storage device, the storage device comprising a plurality of storage cells, a plurality of bit lines electrically connected to these storage cells, a plurality of word lines electrically connected to these storage cells, and a plurality of word line switches electrically connecting the plurality of word lines and these storage cells, the operation method comprising: Applying a word line voltage to a word line among the plurality of word lines that is electrically connected to a selected storage cell among these storage cells, applying a control voltage to a word line switch among the plurality of word line switches that is electrically connected to the selected storage cell, and applying a bit line voltage to a bit line among the plurality of bit lines that is electrically connected to the selected storage cell, to turn on the selected storage cell, Wherein applying the control voltage to the word line switch electrically connected to the selected storage cell makes the word line electrically connected to the selected storage cell in a conductive state, and applying the control voltage to the word line switch electrically connected to the selected storage cell does not change the conductive state of the plurality of bit lines.

7. The operation method according to claim 6, further comprising: Applying a ground voltage to a plurality of word lines among the plurality of word lines that are electrically connected to a plurality of unselected storage cells among these storage cells, applying a ground voltage to a plurality of word line switches among the plurality of word line switches that are electrically connected to these unselected storage cells, and applying a ground voltage to a plurality of bit lines among these bit lines that are electrically connected to these unselected storage cells, to turn off these unselected storage cells.

8. The operation method according to claim 6, wherein the storage device comprises a plurality of bi-directional material layers surrounding the plurality of bit lines.

9. The operating method according to claim 6, wherein the storage device comprises: a stacked structure including a memory array stack and a stepped stack; an insulating film on the memory array stack; a conductive film on the stepped stack and on a sidewall of the insulating film; and a pillar element on the stepped stack and extending through the conductive film, wherein the memory cells are in the memory array stack and are electrically connected to the pillar element.

10. The operating method according to claim 6, wherein the bit line voltage includes a first bit line voltage and a second bit line voltage. The first bit line voltage is applied to the bit line among the plurality of bit lines that is electrically connected to the selected memory cell to turn on the selected memory cell for a RESET operation mode, and the second bit line voltage is applied to the bit line among the plurality of bit lines that is electrically connected to the selected memory cell to turn on the selected memory cell for a SET operation mode. A bias direction of the first bit line voltage is opposite to a bias direction of the second bit line voltage.

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