Single-grid multi-time programmable memory and manufacturing method thereof

Abstract

The invention discloses a single-grid multi-time programmable memory and a manufacturing method thereof.The single-grid multi-time programmable memory comprises a memory cell array and a peripheral circuit, the memory cell array comprises at least one single-grid multi-time programmable memory cell, and each single-grid multi-time programmable memory cell comprises a memory device, at least one single-grid multi-time programmable memory cell array, at least one single-grid multi-time programmable memory cell array, at least one single-grid multi-time programmable memory cell array and at least one single-grid multi-time programmable memory cell array, the peripheral circuit comprises a first switching device and a second switching device, and the working voltage borne by the first switching device is larger than that borne by the second switching device; the memory device, the first switching device and the second switching device respectively comprise a structure of a first semiconductor structure unit, and the doping concentration of a lightly doped drain region in the memory device is greater than that of a lightly doped drain region in the first switching device, so that the programming / erasing operation efficiency of the memory device is improved; the working voltage of programming / erasing of the memory device is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a single-gate multi-programmable memory and a manufacturing method thereof. Background Art

[0002] As an important non-volatile memory, the multi-programmable memory (MTP Memory) is widely used in microcontrollers, sensors, radio frequency identification and other fields due to its characteristics of repeatable erasing and long-term data retention. Among them, the single-gate multi-programmable memory that is fully compatible with the CMOS process has a lower cost and a wider application range.

[0003] However, with the rapid development of the Internet of Things, embedded systems and intelligent terminal devices, the user's demand for non-volatile memory is increasing day by day. Therefore, how to improve the programming / erasing efficiency of the single-gate multi-programmable memory has become a research direction for those skilled in the art. Summary of the Invention

[0004] In view of the above problems, the present application provides a single-gate multi-programmable memory and a manufacturing method thereof to achieve the purpose of improving the programming / erasing efficiency of the single-gate multi-programmable memory. The specific solutions are as follows:

[0005] A single-gate multi-programmable memory includes: a plurality of first semiconductor structure units, and each first semiconductor structure unit includes:

[0006] A first gate structure located on the first surface of the substrate, the first gate structure includes a first gate oxide layer and a first gate stacked in a direction away from the substrate, and a first sidewall located on the side surface of the first stacked structure formed by the first gate oxide layer and the first gate;

[0007] A first source region and a first drain region located in the substrate and opposite to each other on both sides of the first gate structure;

[0008] A lightly doped drain region and a halo doping region located in the substrate and below the first sidewall, and the halo doping region is located on the side of the lightly doped drain region away from the first sidewall;

[0009] The single-gate multi-programmable memory includes: a memory cell array and a peripheral circuit, and the peripheral circuit is used to control the working state of the memory cell array; wherein, the memory cell array includes at least one single-gate multi-programmable memory cell, and the single-gate multi-programmable memory cell includes: a memory device; the peripheral circuit includes a first switching device and a second switching device, and the working voltage that the first switching device can withstand is greater than the working voltage that the second switching device can withstand;

[0010] The storage device, the first switching device, and the second switching device all include the structure of the first semiconductor structure unit, and the doping concentration of the lightly doped drain region in the storage device is greater than that of the lightly doped drain region in the first switching device.

[0011] Optionally, the doping concentration of the lightly doped drain region in the storage device is not less than that of the lightly doped drain region in the second switching device.

[0012] Optionally, the doping concentration of the lightly doped drain region in the storage device is equal to that of the lightly doped drain region in the second switching device.

[0013] Optionally, the doping concentrations of the first source region and the first drain region in the storage device are greater than those of the first source region and the first drain region in the first switching device.

[0014] Optionally, it further includes at least one second semiconductor structure unit, and the second semiconductor structure unit includes:

[0015] A second gate structure located on the first surface of the substrate, the second gate structure includes a second gate oxide layer and a second gate stacked along the direction away from the substrate, and a second sidewall located on the side surface of the second stacked structure formed by the second gate oxide layer and the second gate;

[0016] Located in the substrate, opposite to the second source region and the second drain region on both sides of the second gate structure, the second source region and the second drain region extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through;

[0017] The single-gate multi-programmable memory cell further includes: a capacitor device, the capacitor device includes the structure of the second semiconductor structure unit, and there is no halo doping region in the corresponding substrate region of the capacitor device.

[0018] Optionally, the channel length of the capacitor device is less than the channel length of the storage device.

[0019] A manufacturing method of a single-gate multi-programmable memory, including:

[0020] Forming a plurality of first stacked structures on the first surface of the substrate, the first stacked structures include a first gate oxide layer and a first gate stacked;

[0021] In the substrate, forming a lightly doped drain region and a halo doping region in the regions on both sides opposite to the first stacked structure, and the halo doping region is located on the side of the lightly doped drain region away from the first surface of the substrate;

[0022] On the first surface of the substrate, a first sidewall is formed above the lightly doped drain region, and the first sidewall covers the side surfaces of the first stacked structure;

[0023] In the substrate, a first source region and a first drain region are formed on two opposite sides of the first sidewall;

[0024] The single-gate multi-programmable memory includes: a memory cell array and a peripheral circuit, and the peripheral circuit is used to control the working state of the memory cell array; wherein, the memory cell array includes at least one single-gate multi-programmable memory cell, and the single-gate multi-programmable memory cell includes: a memory device; the peripheral circuit includes a first switching device and a second switching device, and the working voltage that the first switching device can withstand is greater than the working voltage that the second switching device can withstand; the doping concentration of the lightly doped drain region in the memory device is greater than the doping concentration of the lightly doped drain region in the first switching device.

[0025] Optionally, in the substrate, forming a lightly doped drain region and a halo doping region in regions on two opposite sides of the first stacked structure includes:

[0026] Using a first mask layer, performing lightly doped drain ion implantation and halo ion implantation on a first region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device, and the first region includes the region where the lightly doped drain region and the halo doping region of the first switching device are to be formed;

[0027] Using a second mask layer, performing lightly doped drain ion implantation and halo ion implantation on a second region of the substrate to form the lightly doped drain region and the halo doping region of the second switching device and the lightly doped drain region and the halo doping region of the memory device, and the second region includes the region where the lightly doped drain region and the halo doping region of the second switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the memory device are to be formed.

[0028] Optionally, it further includes:

[0029] Performing a logical operation on the first mask layer layer and the first identification layer in the layout design file to generate the first mask layer;

[0030] Performing a logical operation on the second mask layer layer and the first identification layer in the layout design file to generate the second mask layer;

[0031] Among them, the implantation region corresponding to the first mask layer pattern is the first implantation region, the implantation region corresponding to the second mask layer pattern is the second implantation region, the implantation region corresponding to the first identification pattern is the third implantation region, the third implantation region is located within the first implantation region, the implantation region of the first mask layer is the region of the first implantation region excluding the third implantation region, and the implantation region of the second mask layer is the sum of the second implantation region and the third implantation region.

[0032] Optionally, within the substrate, forming lightly doped drain regions and halo doped regions on opposite sides of the first stacked structure includes:

[0033] Using a third mask layer, performing lightly doped drain ion implantation and halo ion implantation on a third region of the substrate to form the lightly doped drain region and halo doped region of the first switching device and the halo doped region of the storage device, where the third region includes the regions where the lightly doped drain region and halo doped region of the first switching device are to be formed and the regions where the lightly doped drain region and halo doped region of the storage device are to be formed;

[0034] Using a fourth mask layer, performing lightly doped drain ion implantation and halo ion implantation on a fourth region of the substrate to form the lightly doped drain region and halo doped region of the second switching device, where the fourth region includes the regions where the lightly doped drain region and halo doped region of the second switching device are to be formed;

[0035] Using a fifth mask layer, performing re-lightly doped drain ion implantation on a fifth region of the substrate to form the lightly doped drain region of the storage device, the third region includes the fifth region, and the fifth region is the region where the lightly doped drain region of the storage device is to be formed.

[0036] Optionally, within the substrate, forming a first source region and a first drain region on opposite sides of the first sidewall includes:

[0037] Using a sixth mask layer, performing ion implantation on a sixth region of the substrate to form a first source region and a first drain region on opposite sides of the first sidewall.

[0038] Optionally, within the substrate, forming a first source region and a first drain region on opposite sides of the first sidewall further includes:

[0039] Using a seventh mask layer, performing ion implantation on the first source region and the first drain region of the storage device again to increase the doping concentration of the first source region and the first drain region of the storage device.

[0040] Optionally, it further includes:

[0041] Form at least one second stacked structure on a first surface of a substrate, where the second stacked structure includes a second gate oxide layer and a second gate stacked on top of each other;

[0042] On the first surface of the substrate, form a second sidewall on a side of the second stacked structure;

[0043] In the substrate, form a second source region and a second drain region on two sides opposite to the second sidewall, where the second source region and the second drain region extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel through;

[0044] The single-gate multi-programmable memory cell further includes: a capacitor device, where the capacitor device includes the second stacked structure, the second sidewall, and the second source region and the second drain region located on two sides opposite to the second sidewall, and there is no halo doping region in a substrate region corresponding to the capacitor device.

[0045] The single-gate multi-programmable memory and its manufacturing method provided by embodiments of the present application can improve the programming / erasing operation efficiency of the memory device, reduce the working voltage of programming / erasing of the memory device, and are compatible with existing CMOS manufacturing processes, with relatively low costs. Description of the Drawings

[0046] In combination with the drawings and with reference to the following specific embodiments, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more obvious. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0047] Figure 1 It is a schematic diagram of a partial structure of a single-gate multi-programmable memory provided by the present application;

[0048] Figure 2 It is a schematic diagram of the structure of a single-gate multi-programmable memory cell in a single-gate multi-programmable memory provided by the present application;

[0049] Figure 3 It is a flowchart of a manufacturing method of a single-gate multi-programmable memory provided by the present application;

[0050] Figure 4 It is a flowchart of another manufacturing method of a single-gate multi-programmable memory provided by the present application. Detailed Embodiments

[0051] The embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0052] Without departing from the spirit or scope of the present application, various modifications and variations can be made in the present application, which will be obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the embodiments of the present application can be combined with each other without conflict.

[0053] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0054] As described in the background art section, how to improve the programming / erasing efficiency of single-gate multi-programmable memories has become a research direction for those skilled in the art.

[0055] In view of this, an embodiment of the present application provides a single-gate multi-programmable memory, as Figure 1 shown, including at least one first semiconductor structure unit 10, and the first semiconductor structure unit 10 includes:

[0056] A first gate structure located on the first surface of the substrate 100, the first gate structure including a first gate oxide layer 111 and a first gate 112 stacked in a direction away from the substrate 100, and a first sidewall 12 located on the side of the first stacked structure 11 formed by the first gate oxide layer 111 and the first gate 112;

[0057] A first source region 15 and a first drain region 16 located in the substrate 100 and opposite to each other on both sides of the first gate structure;

[0058] A lightly doped drain region 13 and a halo doping region 14 located in the substrate 100 and below the first sidewall 12, the halo doping region 14 being located on the side of the lightly doped drain region 13 away from the first sidewall 13. Specifically, the lightly doped drain region 13 and the halo doping region 14 are located between the first source region 15 and the first drain region 16, and in the direction perpendicular to the first surface of the substrate 100, neither the lightly doped drain region 13 nor the halo doping region 14 overlaps with the first stacked structure 11.

[0059] It should be noted that, in the embodiments of the present application, the lightly doped drain region is an LDD (Lightly Doped Drain) region, which is formed by performing LDD ion implantation in the substrate and is used to reduce the hot carrier effect during device operation and optimize device reliability; the halo doping region is a halo implantation region, which is formed by performing halo ion implantation on the substrate and is used to suppress the short-channel effect and enhance the device's resistance to drain-induced barrier lowering (DIBL).

[0060] In this embodiment, the single-gate multi-programmable memory includes: a memory cell array and a peripheral circuit. The peripheral circuit is used to provide control signals to the memory cell array and control the operating state of the memory cell array. Specifically, in this embodiment, the memory cell array includes at least one single-gate multi-programmable memory cell. The single-gate multi-programmable memory cell includes a memory device. The peripheral circuit includes a first switching device and a second switching device. Among them, the operating voltage that the first switching device can withstand is greater than the operating voltage that the second switching device can withstand, that is, the first switching device is a high-voltage device, and the second switching device is a low-voltage device.

[0061] In this embodiment, the memory device, the first switching device, and the second switching device all include the structure of the first semiconductor structure unit, that is, the memory device, the first switching device, and the second switching device all adopt the structure of the first semiconductor structure unit. That is, among the multiple first semiconductor structure units, some first semiconductor structure units are used as memory devices, some first semiconductor structure units are used as first switching devices, and some first semiconductor structure units are used as second switching devices. Among them, the doping concentration of the lightly doped drain region in the first switching device is lower than the doping concentration of the lightly doped drain region in the second switching device.

[0062] As Figure 2 shown, Figure 2 shows a schematic structural diagram of a single-gate multi-programmable memory cell in a single-gate multi-programmable memory. The single-gate multi-programmable memory cell 200 includes a memory device 201 and a capacitor device 202. Among them, the gate G1 of the memory device 201 and the gate G2 of the capacitor device 202 are connected and in a floating state. Its working principle is: by changing the charge stored in the floating gate, the conductive characteristics of the memory device 201 are changed, so as to change the data stored in the memory device 201, and further realize the programming or erasing of the data in the memory device 201.

[0063] During specific operation, in the single-gate multi-programmable memory cell, the voltage difference between the source terminal VS electrically connected to the source region S1 and the drain terminal VBL electrically connected to the drain region D1 in the memory device 201 can generate a lateral electric field. The voltage differences between the gate G1 and the source terminal VS, between the gate G1 and the drain terminal VBL, and between the gate G1 and the substrate 100 can generate a longitudinal electric field. Under the action of the lateral and longitudinal electric fields, hot electrons or holes in the memory device 201 tunnel through the gate oxide layer into or out of the gate G1 to change the charge stored in the floating gate, thereby changing the conductive characteristics of the memory device 201 and further changing the data stored in the memory device 201 to achieve data programming or erasure. It should be noted that the programming process of the single-gate multi-programmable memory cell is a process in which hot electrons enter the floating gate of the memory device; the erasure process of the single-gate multi-programmable memory cell is a process in which electrons escape from the floating gate of the memory device, or a process in which hot holes enter the floating gate of the memory device and recombine with the electrons in the floating gate.

[0064] Specifically, the more electrons stored on the gate in the memory device, the higher the threshold voltage of the memory device. The single-gate multi-programmable memory cell presents a programmed state, and the data stored in it is "0"; the fewer electrons stored on the gate in the memory device, the lower the threshold voltage of the memory device. The single-gate multi-programmable memory cell presents an erasable state, and the data stored in it is "1".

[0065] It should be noted that in this embodiment, the doping concentration of the lightly doped drain region in the memory device is greater than that of the lightly doped drain region in the first switching device, that is, the doping concentration of the lightly doped drain region in the memory device is greater than that of the lightly doped drain region in the high-voltage device in the peripheral circuit. By increasing the doping concentration of the lightly doped drain region in the memory device, the electric field intensity near the drain region in the memory device is enhanced, so that the carriers (electrons or holes) in the memory device can more efficiently tunnel through the first gate oxide layer into the floating gate (i.e., the first gate) under the action of the lateral and longitudinal electric fields. It should be noted that a stronger electric field not only increases the rate of carrier injection but also increases the tunneling probability, thus significantly improving the efficiency of the programming / erasure operation of the memory device and shortening the time required for charge injection.

[0066] Moreover, the fact that the doping concentration of the lightly doped drain region in the memory device is greater than that of the lightly doped drain region in the first switching device will significantly increase the effective tunneling electric field intensity of the first drain region of the memory device under the same applied voltage, so as to achieve an equivalent charge injection effect at a lower voltage and greatly reduce the voltage requirement for the programming / erasure operation.

[0067] Optionally, in an embodiment of the present application, the doping concentration of the lightly doped drain region in the storage device is 1 to 100 times, excluding 1 and including 100, the doping concentration of the lightly doped drain region in the first switching device. However, the present application does not limit this, and it depends on the specific situation.

[0068] Optionally, in an embodiment of the present application, the doping concentration of the lightly doped drain region in the storage device is not less than the doping concentration of the lightly doped drain region in the second switching device, that is, the doping concentration of the lightly doped drain region in the storage device is not less than the doping concentration of the lightly doped drain region in the low-voltage device in the peripheral circuit. Thus, the doping concentration of the lightly doped drain region in the storage device is relatively high, which improves the programming / erasing operation efficiency of the storage device and reduces the voltage of the programming / erasing operation of the storage device.

[0069] Based on the above embodiments, in an embodiment of the present application, the doping concentration of the lightly doped drain region in the storage device is equal to the doping concentration of the lightly doped drain region in the second switching device, so that the doping of the lightly doped drain region in the storage device can be formed simultaneously with the doping of the lightly doped drain region in the second switching device. Thus, on the basis of increasing the concentration of the lightly doped drain region in the storage device, the process flow and process cost of manufacturing the single-gate multi-programmable memory are not increased. However, the present application does not limit this, and it depends on the specific situation.

[0070] Based on any of the above embodiments, in an embodiment of the present application, the doping concentrations of the first source region and the first drain region in the storage device are greater than those of the first source region and the first drain region in the first switching device. By increasing the doping concentrations of the first source region and the first drain region in the storage device, the carrier concentration and the transverse electric field intensity near the first drain region in the storage device are enhanced. Thus, in the programming / erasing operation of the storage device, more electrons or holes that can be injected into the floating gate (the first gate of the storage device) can be provided by using a higher carrier density. At the same time, the stronger transverse electric field can accelerate the kinetic energy of the carriers, making it easier for them to tunnel through the first gate oxide layer of the storage device, significantly improving the rate of charge injection / escape from the floating gate (i.e., the first gate) of the storage device, and thus greatly improving the operation efficiency.

[0071] Moreover, the doping concentrations of the first source region and the first drain region in the storage device being greater than those of the first source region and the first drain region in the first switching device can optimize the electric field distribution. Under the same applied voltage, a steeper potential gradient is formed between the drain region and the channel in the storage device, and the local electric field intensity is significantly enhanced. Thus, carriers can achieve an equivalent charge injection effect at a lower voltage, reducing the voltage of the programming / erasing operation of the storage device.

[0072] Optionally, the doping concentrations of the first source region and the first drain region in the storage device are 1 to 100 times, excluding 1 and including 100, the concentrations of the first source region and the first drain region in the first switching device. However, the present application does not make any limitation in this regard and it depends on specific circumstances.

[0073] Optionally, in the embodiments of the present application, the doping concentrations of the first source region and the first drain region in the first switching device and the second switching device are the same. However, the present application does not make any limitation in this regard and it depends on specific circumstances.

[0074] It should be noted that, in this embodiment, the single-gate multi-programmable memory cell further includes a capacitor device. By applying a voltage to the source terminal and the drain terminal of the capacitor device, a voltage is coupled to the floating gate of the capacitor device, that is, the floating gate of the storage device, so as to assist the storage device to perform electron / hole tunneling during the programming / erasing operation. It should be noted that the higher the capacitance coupling efficiency of the capacitor device, the higher the efficiency of the storage device during the programming / erasing operation.

[0075] The inventors have found through research that if the NMOS capacitor is placed in the N-well to increase the area of the capacitor device and thus increase the coupling efficiency of the capacitor device, the area of the memory cell will be significantly increased; if the coupling efficiency of the capacitor device is increased by adding N+ implantation in the channel on the substrate surface to realize source-drain connection, a mask plate needs to be added during the manufacturing process of the single-gate multi-programmable memory, thus increasing the process cost.

[0076] In view of this, on the basis of any of the above embodiments, in an embodiment of the present application, continue as Figure 1 described, the single-gate multi-programmable memory further includes: at least one second semiconductor structure unit 20, and the second semiconductor structure unit 20 includes:

[0077] A second gate structure located on the first surface of the substrate 100, the second gate structure includes a second gate oxide layer 211 and a second gate 212 stacked in a direction away from the substrate 100, and a second sidewall 22 located on the side of the second stacked structure 21 formed by the second gate oxide layer 211 and the second gate 212;

[0078] A second source region 23 and a second drain region 24 located in the substrate 100 and relatively located on both sides of the second gate structure, the second source region 23 and the second drain region 24 extend towards each other in the substrate 100 and meet below the second gate oxide layer 21 to form source-drain channel penetration.

[0079] In this embodiment, as Figure 1 and Figure 2As shown, the capacitor device 202 includes the structure of the second semiconductor structure unit 20, that is, the capacitor device 202 adopts the structure of the second semiconductor structure unit 20, so as to extend towards each other in the substrate 100 through the second source region 23 and the second drain region 24 and meet below the second gate oxide layer to form a source-drain channel punch-through, increasing the capacitive coupling efficiency of the capacitor device 202, thereby improving the efficiency when the storage device 201 performs programming / erasing operations.

[0080] It should be noted that when the second source region and the second drain region of the capacitor device do not punch through, the capacitor device operates in the cut-off region, and the equivalent capacitance is mainly composed of the capacitance generated by the overlapping region between the second source region of the capacitor device and the second gate and the capacitance generated by the overlapping region between the second drain region of the capacitor device and the second gate. The capacitance value is small, and it is specifically determined mainly by the overlapping area between the second gate and the second source region / second drain region and the thickness of the second gate oxide layer; after the second source region and the second drain region of the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, the equivalent capacitance of the capacitor device is the intrinsic capacitance between the second gate and the channel corresponding to the second gate, and its dielectric is the second gate oxide layer. The capacitance value is large, and this capacitance directly determines the control ability of the second gate over the channel corresponding to the second gate. The larger the capacitance value, the higher the voltage efficiency coupled to the floating gate (the first gate of the storage device), and the higher the efficiency of the programming / erasing operation of the storage device.

[0081] It should be noted that in this embodiment, there is no halo doping region in the substrate region corresponding to the capacitor device, that is, there is no halo implantation region in the capacitor device. By reducing the halo implantation region in the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device, and further improving the efficiency when the storage device performs programming / erasing operations.

[0082] Optionally, in an embodiment of the present application, there is also no lightly doped drain region in the substrate region corresponding to the capacitor device to reduce the process cost of the single-gate multi-programmable memory. However, the present application does not make any limitations in this regard. In other embodiments of the present application, a lightly doped drain region may also be provided in the substrate region corresponding to the capacitor device, depending on the specific situation. It should be noted that compared with the absence of a lightly doped drain region in the substrate region corresponding to the capacitor device, setting a lightly doped drain region in the substrate region corresponding to the capacitor device will add a mask layer to the manufacturing process of the single-gate multi-programmable memory.

[0083] In another embodiment of the present application, the channel length of the capacitor device is less than that of the storage device. By shortening the channel length of the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device and further improving the efficiency of the storage device when performing programming / erasing operations.

[0084] In yet another embodiment of the present application, there is no halo implantation region in the capacitor device, and the channel length of the capacitor device is less than that of the storage device. By reducing the halo implantation region in the capacitor device and shortening the channel length of the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device and further improving the efficiency of the storage device when performing programming / erasing operations. However, the present application does not limit this, and it depends on the specific situation.

[0085] Correspondingly, the embodiment of the present application also provides a manufacturing method for a single-gate multi-programmable memory. It should be noted that the manufacturing method for this single-gate multi-programmable memory is compatible with the existing CMOS manufacturing process, as Figure 3 shown, this manufacturing method includes:

[0086] S1: Form a plurality of first stacked structures on the first surface of the substrate. The first stacked structure includes a first gate oxide layer and a first gate stacked on top of each other.

[0087] S2: In the substrate, form a lightly doped drain region and a halo doping region in the areas on both sides opposite to the first stacked structure. The halo doping region is located on the side of the lightly doped drain region away from the first surface of the substrate.

[0088] It should be noted that in the embodiment of the present application, the lightly doped drain region is an LDD (Lightly Doped Drain) region, which is formed by performing LDD ion implantation in the substrate and is used to reduce the hot carrier effect during device operation and optimize device reliability; the halo doping region is a halo implantation region, which is formed by performing halo ion implantation on the substrate and is used to suppress the short-channel effect and enhance the device's resistance to drain-induced barrier lowering (DIBL).

[0089] In this embodiment, the single-gate multi-programmable memory includes a memory cell array and a peripheral circuit. The peripheral circuit is configured to provide control signals to the memory cell array and control the operating state of the memory cell array. Specifically, in this embodiment, the memory cell array includes at least one single-gate multi-programmable memory cell. The single-gate multi-programmable memory cell includes a memory device. The peripheral circuit includes a first switching device and a second switching device. Among them, the operating voltage that the first switching device can withstand is greater than the operating voltage that the second switching device can withstand. That is, the first switching device is a high-voltage device, and the second switching device is a low-voltage device.

[0090] In this embodiment, the memory device, the first switching device, and the second switching device all include the structure of the first semiconductor structure unit. That is, the memory device, the first switching device, and the second switching device all adopt the structure of the first semiconductor structure unit. That is, among the multiple first semiconductor structure units, some first semiconductor structure units are used as memory devices, some first semiconductor structure units are used as first switching devices, and some first semiconductor structure units are used for second switching devices. Among them, the doping concentration of the lightly doped drain region in the first switching device is lower than the doping concentration of the lightly doped drain region in the second switching device.

[0091] It should be noted that, in this embodiment, the doping concentration of the lightly doped drain region in the memory device is greater than the doping concentration of the lightly doped drain region in the first switching device. That is, the doping concentration of the lightly doped drain region in the memory device is greater than the doping concentration of the lightly doped drain region of the high-voltage device in the peripheral circuit. By increasing the doping concentration of the lightly doped drain region of the memory device, the electric field intensity near the drain region in the memory device is enhanced, so that the carriers (electrons or holes) in the memory device can more efficiently tunnel through the first gate oxide layer of the memory device into the floating gate (i.e., the first gate) under the action of the lateral electric field and the longitudinal electric field. It should be noted that a stronger electric field not only increases the rate of carrier injection but also increases the tunneling probability, thus significantly improving the efficiency of the programming / erasing operation of the memory device and shortening the time required for charge injection.

[0092] Moreover, the doping concentration of the lightly doped drain region in the memory device being greater than the doping concentration of the lightly doped drain region in the first switching device will significantly increase the effective tunneling electric field intensity of the first drain region of the memory device under the same applied voltage, so as to achieve an equivalent charge injection effect at a lower voltage and greatly reduce the voltage requirements for the programming / erasing operation.

[0093] Optionally, in an embodiment of the present application, the doping concentration of the lightly doped drain region in the storage device is not less than the doping concentration of the lightly doped drain region in the second switching device, that is, the doping concentration of the lightly doped drain region in the storage device is not less than the doping concentration of the lightly doped drain region in the low-voltage device in the peripheral circuit, so that the doping concentration of the lightly doped drain region in the storage device is relatively high, improving the programming / erasing operation efficiency of the storage device and reducing the voltage of the programming / erasing operation of the storage device.

[0094] Based on the above embodiment, in an embodiment of the present application, the doping concentration of the lightly doped drain region in the storage device is equal to the doping concentration of the lightly doped drain region in the second switching device, so that the doping of the lightly doped drain region in the storage device can be formed simultaneously with the doping of the lightly doped drain region in the second switching device. Thus, on the basis of increasing the concentration of the lightly doped drain region in the storage device, the process flow and process cost during the fabrication of the single-gate multi-programmable memory are not increased. However, the present application does not limit this, and it depends on the specific situation.

[0095] Optionally, in an embodiment of the present application, when the doping concentration of the lightly doped drain region in the storage device is equal to the doping concentration of the lightly doped drain region in the second switching device, in the substrate, the formation of the lightly doped drain region and the halo doping region on the two opposite sides of the first stacked structure includes:

[0096] Using a first mask layer, performing lightly doped drain ion implantation and halo ion implantation on a first region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device, where the first region includes the region where the lightly doped drain region and the halo doping region of the first switching device are to be formed;

[0097] Using a second mask layer, performing lightly doped drain ion implantation and halo ion implantation on a second region of the substrate to form the lightly doped drain region and the halo doping region of the second switching device and the lightly doped drain region and the halo doping region of the storage device, where the second region includes the region where the lightly doped drain region and the halo doping region of the second switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the storage device are to be formed.

[0098] In this embodiment, the second region includes the region where the lightly doped drain region and the halo doping region of the second switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the storage device are to be formed, that is, the lightly doped drain region of the second switching device and the lightly doped drain region of the storage device are implanted simultaneously, so that on the basis of increasing the concentration of the lightly doped drain region in the storage device, the process flow and process cost during the fabrication of the single-gate multi-programmable memory are not increased.

[0099] It should be noted that, in this embodiment, the lightly doped drain region and the halo doping region of the first switching device are formed by using the same mask layer; the lightly doped drain region and the halo doping region of the memory device and the lightly doped drain region and the halo doping region of the second switching device are formed by using the same mask layer. Among them, the lightly doped drain region of the memory device and the lightly doped drain region of the second switching device are formed simultaneously, and the halo doping region of the memory device and the halo doping region of the second switching device are formed simultaneously.

[0100] Optionally, in an embodiment of the present application, by using a first mask layer, a lightly doped drain ion implantation and a halo ion implantation are performed on a first region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device, where the first region includes a region where the lightly doped drain region and the halo doping region of the first switching device are to be formed; and, by using a second mask layer, a lightly doped drain ion implantation and a halo ion implantation are performed on a second region of the substrate to form the lightly doped drain region and the halo doping region of the second switching device and the lightly doped drain region and the halo doping region of the memory device. Before the second region includes a region where the lightly doped drain region and the halo doping region of the second switching device are to be formed and a region where the lightly doped drain region and the halo doping region of the memory device are to be formed, the method further includes:

[0101] Performing a logical operation on the first mask layer layer and the first identification layer in the layout design file to generate the first mask layer;

[0102] Performing a logical operation on the second mask layer layer and the first identification layer in the layout design file to generate the second mask layer;

[0103] Among them, the injection region corresponding to the first mask layer layer is a first injection region A, the injection region corresponding to the second mask layer layer is a second injection region B, the injection region corresponding to the first identification layer is a third injection region M, and the third injection region M is located within the first injection region A. Then, the injection region of the first mask layer is the region in the first injection region excluding the third injection region, that is, A - M, and the injection region of the second mask layer is the sum of the second injection region and the third injection region, that is, B + M.

[0104] It can be seen that when the lightly doped drain regions of the second switching device and the memory device are formed simultaneously by injection, the corresponding mask layers can be obtained by performing a logical operation on the first mask layer layer, the second mask layer layer, and the first identification layer in the layout design file, without changing the current process flow of the single-gate multi-programmable memory, and the cost is relatively low.

[0105] In other embodiments of the present application, the formation of the second mask layer may also not perform a logical operation on the second mask layer pattern and the first identification pattern in the layout design file to generate the second mask layer. Instead, the area of the second mask layer pattern may be directly enlarged so that it extends to cover the lightly doped drain region and the halo doping region of the memory device. The present application does not limit this, and it depends on the specific situation.

[0106] In another embodiment of the present application, the doping concentration of the lightly doped drain region in the memory device is greater than the doping concentration of the lightly doped drain region in the second switching device. In this embodiment, after using the second mask layer to perform lightly doped drain ion implantation and halo ion implantation on the second region of the substrate to form the lightly doped drain region and the halo doping region of the second switching device and the lightly doped drain region and the halo doping region of the memory device, forming the lightly doped drain region and the halo doping region in the regions on the opposite sides of the first stacked structure further includes:

[0107] Using the eighth mask layer to perform secondary ion implantation on the lightly doped drain region of the memory device to increase the doping concentration of the lightly doped drain region of the memory device, so that the doping concentration of the lightly doped drain region of the memory device is greater than the doping concentration of the lightly doped drain region of the second switching device.

[0108] It should be noted that the above embodiments describe the formation process of the lightly doped drain region and the halo doping region of the first switching device, the second switching device, and the memory device by taking the formation process of the lightly doped drain region of the memory device as at least partially being carried out simultaneously with the formation process of the lightly doped drain region of the second switching device as an example. However, the present application does not limit this. In other embodiments of the present application, the formation process of the lightly doped drain region of the memory device may also be carried out independently of the formation process of the lightly doped drain region of the second switching device, depending on the specific situation.

[0109] Optionally, in an embodiment of the present application, forming the lightly doped drain region and the halo doping region in the regions on the opposite sides of the first stacked structure in the substrate includes:

[0110] Using the third mask layer to perform lightly doped drain ion implantation and halo ion implantation on the third region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device and the halo doping region of the memory device. The third region includes the region where the lightly doped drain region and the halo doping region of the first switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the memory device are to be formed;

[0111] Using a fourth mask layer, perform lightly doped drain ion implantation and halo ion implantation on a fourth region of the substrate to form a lightly doped drain region and a halo doped region of the second switching device, where the fourth region includes the region where the lightly doped drain region and the halo doped region of the second switching device are to be formed;

[0112] Using a fifth mask layer, perform another lightly doped drain ion implantation on a fifth region of the substrate to form a lightly doped drain region of the storage device, where the third region includes the fifth region, and the fifth region is the region where the lightly doped drain region of the storage device is to be formed.

[0113] In this embodiment, the first ion implantation of the lightly doped drain region of the storage device and the ion implantation of the lightly doped drain region of the first switching device are formed simultaneously. At this time, the doping concentration of the lightly doped drain region of the storage device is the same as that of the lightly doped drain region of the first switching device. In order to make the doping concentration of the lightly doped drain region of the storage device greater than that of the lightly doped drain region of the first switching device, after the lightly doped drain region of the first switching device is formed, the fifth mask layer is used to perform ion implantation again on the region of the substrate where the lightly doped drain region of the storage device is to be formed, so that the doping concentration of the lightly doped drain region of the storage device is greater than that of the lightly doped drain region of the first switching device.

[0114] It should be noted that compared with using the second mask layer to perform ion implantation on the second region of the substrate to form the lightly doped drain region of the second switching device and the lightly doped drain region of the storage device, using the third mask layer and the fifth mask layer to form the lightly doped drain region of the storage device, one more mask layer needs to be added in the manufacturing process of the single-gate multi-programmable memory. Correspondingly, the process flow and process cost of the manufacturing method of the single-gate multi-programmable memory will increase.

[0115] S3: On the first surface of the substrate, form a first sidewall above the lightly doped drain region, and the first sidewall covers the side surfaces of the first stacked structure.

[0116] S4: In the substrate, form a first source region and a first drain region on two sides opposite to the first sidewall.

[0117] Specifically, in an embodiment of the present application, within the substrate, forming a first source region and a first drain region on two opposite sides of the first sidewall includes: using a sixth mask layer to perform ion implantation on a sixth region of the substrate to form a first source region and a first drain region on two opposite sides of the first sidewall. It should be noted that in this embodiment, the first source region and the first drain region are relatively located on two sides of the lightly doped drain region and the halo doping region; the sixth region includes the first source region and the first drain region of the first switching device, the first source region and the first drain region of the second switching device, and the first source region and the first drain region of the storage device. Optionally, the doping concentrations of the first source region and the first drain region of the first switching device are the same as those of the first source region and the first drain region of the second switching device.

[0118] Based on the above embodiment, in an embodiment of the present application, the doping concentrations of the first source region and the first drain region of the storage device are the same as those of the first source region and the first drain region of the first switching device. In another embodiment of the present application, the doping concentrations of the first source region and the first drain region in the storage device are greater than those of the first source region and the first drain region in the first switching device. By increasing the doping concentrations of the first source region and the first drain region in the storage device, the carrier concentration and the lateral electric field strength near the first drain region in the storage device are enhanced. Thus, in the programming / erasing operation of the storage device, more electrons or holes that can be injected into the floating gate (the first gate of the storage device) can be provided using a higher carrier density. At the same time, the stronger lateral electric field can accelerate the kinetic energy of the carriers, making it easier for them to tunnel through the first gate oxide layer of the storage device, significantly improving the rate of charge injection / escape from the floating gate (i.e., the first gate) of the storage device, thereby greatly improving the operation efficiency.

[0119] Moreover, the doping concentrations of the first source region and the first drain region in the storage device being greater than those of the first source region and the first drain region in the first switching device can optimize the electric field distribution. Under the same applied voltage, a steeper potential gradient is formed between the first drain region and the channel in the storage device, and the local electric field strength is significantly enhanced. As a result, carriers can achieve an equivalent charge injection effect at a lower voltage, reducing the voltage of the programming / erasing operation of the storage device.

[0120] It should be noted that the doping concentrations of the first source region and the first drain region in the storage device are greater than those of the first source region and the first drain region in the first switching device. When the first source region and the first drain region are formed on both sides opposite to the first sidewall in the substrate, the method further includes: using a seventh mask layer to perform ion implantation on the first source region and the first drain region of the storage device again to increase the doping concentrations of the first source region and the first drain region of the storage device, so that the doping concentrations of the first source region and the first drain region of the storage device are greater than those of the first source region and the first drain region of the first switching device.

[0121] It should be noted that in this embodiment, the single-gate multi-programmable memory cell further includes a capacitor device. The capacitor device couples a voltage to the floating gate of the capacitor device, that is, the floating gate of the storage device, by applying voltages to the source terminal and the drain terminal of the capacitor device, thereby assisting the storage device to perform electron / hole tunneling during the programming / erasing operation. It should be noted that the higher the capacitance coupling efficiency of the capacitor device, the higher the efficiency of the storage device during the programming / erasing operation.

[0122] Optionally, in an embodiment of the present application, as Figure 4 shown, the method further includes:

[0123] S5: Form at least one second stacked structure on the first surface of the substrate. The second stacked structure includes a second gate oxide layer and a second gate stacked. Optionally, the second stacked structure and the first stacked structure are formed simultaneously to simplify the process flow of the manufacturing method of the single-gate multi-programmable memory.

[0124] S6: Form a second sidewall on the side of the second stacked structure on the first surface of the substrate. Optionally, the second sidewall and the first sidewall are formed simultaneously to simplify the process flow of the manufacturing method of the single-gate multi-programmable memory.

[0125] S7: Form a second source region and a second drain region on both sides opposite to the second sidewall in the substrate. The second source region and the second drain region extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel through. Optionally, the second source region and the second drain region located on both sides opposite to the second sidewall and the first source region and the first drain region located on both sides opposite to the first sidewall are formed simultaneously to simplify the process flow of the manufacturing method of the single-gate multi-programmable memory.

[0126] It should be noted that in this embodiment, the capacitor device includes the second stacked structure, the second sidewall, and the second source region and the second drain region located on both sides opposite to the second sidewall. The second source region and the second drain region extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel through.

[0127] Comparing the manufacturing processes of the first switching device, the second switching device, and the storage device, there is no formation of lightly doped drain regions and halo doped regions in the manufacturing process of the capacitor device. By reducing the halo implantation region in the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device and further improving the efficiency when the storage device performs programming / erasing operations.

[0128] In another embodiment of the present application, the channel length of the capacitor device is less than the channel length of the storage device. By shortening the channel length of the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device and further improving the efficiency when the storage device performs programming / erasing operations.

[0129] In yet another embodiment of the present application, there are no lightly doped drain regions and halo implantation regions in the capacitor device, and the channel length of the capacitor device is less than the channel length of the storage device. By reducing the halo implantation region in the capacitor device and shortening the channel length of the capacitor device, the second source region and the second drain region in the capacitor device extend towards each other in the substrate and meet below the second gate oxide layer to form a source-drain channel punch-through, thereby increasing the capacitive coupling efficiency of the capacitor device and further improving the efficiency when the storage device performs programming / erasing operations. However, the present application does not limit this, and it depends on the specific situation.

[0130] During the manufacturing process of traditional single-gate multi-programmable memories, halo implantation regions are also provided in the capacitor device. Moreover, during the manufacturing process of traditional single-gate multi-programmable memories, the halo implantation regions of the capacitor device and the halo implantation regions of high-voltage devices are formed simultaneously. In order not to change the process of the single-gate multi-programmable memory, using the process of the existing single-gate multi-programmable memory to manufacture the single-gate multi-programmable memory provided in the embodiments of the present application, the manufacturing method further includes:

[0131] Perform a logical operation on the first mask layer and the second identification layer in the layout design file to generate the first mask layer. Among them, the implantation region corresponding to the first mask layer is the first implantation region A, the implantation region of the second identification layer is the fourth implantation region N, the first implantation region A includes the regions of the halo implantation regions to be formed under the first sidewall and under the second sidewall in the traditional single-gate multi-programmable memory, and the fourth implantation region N is the region of the halo implantation region to be formed under the second sidewall in the traditional single-gate multi-programmable memory. In the embodiments of the present application, the implantation region corresponding to the first mask layer is the region of the first implantation region excluding the fourth implantation region, that is, A - N.

[0132] It should be noted that in this embodiment, in the actual manufacturing process, the implantation region corresponding to the first mask layer is A - M - N, where the first implantation region A is the implantation region corresponding to the first mask layer, the third implantation region M is the implantation region corresponding to the first identification layer, and the region of the fourth implantation region N is the region of the halo implantation region to be formed under the second sidewall in the traditional single-gate multi-programmable memory.

[0133] It can be seen that the manufacturing method of the single-gate multi-programmable memory provided by the embodiments of the present application can use logical operations to prevent the region under the second sidewall from being ion-implanted when the halo implantation region under the first sidewall is ion-implanted, and does not change the process of the single-gate multi-programmable memory.

[0134] It can be seen that the single-gate multi-programmable memory and its manufacturing method provided by the embodiments of the present application can improve the programming / erasing operation efficiency of the storage device, reduce the working voltage of the programming / erasing of the storage device, and are compatible with the existing COMS manufacturing process, with a lower cost. It should be noted that in this embodiment, the storage device and the capacitor device can be PMOS devices or NMOS devices, and the present application does not make any limitations in this regard, which depends on the specific situation. Optionally, when the storage device and the capacitor device are PMOS devices, the lightly doped drain region is an N-type doped region, and the halo doped region is a P-type doped region; when the storage device and the capacitor device are NMOS devices, the lightly doped drain region is a P-type doped region, and the halo doped region is an N-type doped region.

[0135] In addition, the embodiments of the present application also provide an operation method for a single-gate multi-programmable memory.

[0136] Optionally, in an embodiment of the present application, when both the storage device and the capacitor device are NMOS devices, in this embodiment, when performing a programming operation, continue as Figure 2As shown, the operation method includes: grounding the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, setting the voltage terminal VS corresponding to the first source region of the storage device to 0V, applying a high voltage to the voltage terminal (i.e., the bit line voltage terminal) VBL corresponding to the first drain region of the storage device, and applying a high voltage to the control gate voltage terminal (i.e., the terminal where voltages are applied to the second source region and the second drain region that form a coupling capacitance with its second gate in the capacitor device) VCG, so that hot electrons in the first source region or the first drain region in the storage device tunnel onto the floating gate (i.e., the first gate) of the storage device, increasing the threshold voltage of the storage device.

[0137] In another embodiment of the present application, when both the storage device and the capacitor device are NMOS devices, in this embodiment, when performing a programming operation, the operation method includes:

[0138] Grounding the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, applying a high voltage to the voltage terminal VS corresponding to the first source region of the storage device, setting the voltage terminal (i.e., the bit line voltage terminal) VBL corresponding to the first drain region of the storage device to 0V, and applying a high voltage to the control gate voltage terminal VCG, so that hot electrons in the first source region or the first drain region in the storage device tunnel onto the floating gate (i.e., the first gate) of the storage device, increasing the threshold voltage of the storage device.

[0139] Based on any of the above embodiments, in an embodiment of the present application, when both the storage device and the capacitor device are NMOS devices, in this embodiment, when performing an erasing operation, the operation method includes:

[0140] Grounding the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, setting the voltage terminal VS corresponding to the first source region of the storage device to 0V or in a floating state, applying a high voltage to the voltage terminal (i.e., the bit line voltage terminal) VBL corresponding to the first drain region of the storage device, and applying 0V or a negative voltage or setting it in a floating state to the control gate voltage terminal (i.e., the terminal where voltages are applied to the second source region and the second drain region that form a coupling capacitance with its second gate in the capacitor device) VCG, so that electrons on the floating gate (i.e., the first gate) of the storage device escape from the first gate of the storage device, or so that hot holes in the storage device enter the floating gate of the storage device and recombine with electrons in the floating gate, reducing the threshold voltage of the storage device.

[0141] In another embodiment of the present application, when both the storage device and the capacitor device are NMOS devices, in this embodiment, when performing an erasing operation, the operation method includes:

[0142] Ground the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, apply a high voltage to the voltage terminal VS corresponding to the first source region of the memory device, set the voltage terminal VBL corresponding to the first drain region of the memory device (i.e., the bit line voltage terminal) to 0V or in a floating state, and apply 0V or a negative voltage or set the control gate voltage terminal VCG (i.e., the terminal where voltage is applied to the second source region and the second drain region that form a coupling capacitance with the second gate in the capacitor device) in a floating state, so that electrons on the floating gate (i.e., the first gate) of the memory device escape from the floating gate of the memory device, or so that hot holes in the memory device enter the floating gate of the memory device and recombine with electrons in the floating gate, reducing the threshold voltage of the memory device.

[0143] In another embodiment of the present application, when both the memory device and the capacitor device are PMOS devices, in this embodiment, when performing a programming operation, the operation method includes: applying a high voltage to the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, setting the voltage terminal VS corresponding to the first source region of the memory device to 0V, applying a high voltage to the voltage terminal VBL corresponding to the first drain region of the memory device (i.e., the bit line voltage terminal), and applying a medium voltage to the control gate voltage terminal VCG (i.e., the terminal where voltage is applied to the second source region and the second drain region that form a coupling capacitance with the second gate in the capacitor device), so that hot electrons in the first source region or the first drain region in the memory device tunnel onto the floating gate (i.e., the first gate) of the memory device, reducing the threshold voltage of the memory device.

[0144] In another embodiment of the present application, when both the memory device and the capacitor device are PMOS devices, in this embodiment, when performing a programming operation, the operation method includes:

[0145] Apply a high voltage to the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, apply a high voltage to the voltage terminal VS corresponding to the first source region of the memory device, set the voltage terminal VBL corresponding to the first drain region of the memory device (i.e., the bit line voltage terminal) to 0V, and apply a medium voltage to the control gate voltage terminal VCG, so that hot electrons in the first source region or the first drain region in the memory device tunnel onto the floating gate (i.e., the first gate) of the memory device, reducing the threshold voltage of the memory device.

[0146] Based on any of the above embodiments, in an embodiment of the present application, when both the memory device and the capacitor device are PMOS devices, in this embodiment, when performing an erase operation, the operation method includes:

[0147] Apply a high voltage to the voltage terminal VB corresponding to the substrate in the single-gate multi-programmable memory, apply a high voltage or set it to a floating state to the voltage terminal VS corresponding to the first source region of the memory device, apply 0V to the voltage terminal (i.e., the bit line voltage terminal) VBL corresponding to the first drain region of the memory device, and apply 0V or a negative voltage or set it to a floating state to the control gate voltage terminal (i.e., the terminal where voltage is applied to the second source region and the second drain region that form a coupling capacitance with its second gate in the capacitor device) VCG terminal, so that electrons on the floating gate (i.e., the first gate) of the memory device escape from the floating gate of the memory device, or so that hot holes in the memory device enter the floating gate of the memory device and recombine with electrons in the floating gate, increasing the threshold voltage of the memory device.

[0148] In another embodiment of the present application, when both the memory device and the capacitor device are PMOS devices, in this embodiment, when performing an erase operation, the operation method includes:

[0149] Ground the voltage terminal VB of the substrate in the single-gate multi-programmable memory, apply 0V voltage to the voltage terminal VS corresponding to the first source region of the memory device, apply a high voltage or set it to a floating state to the voltage terminal (i.e., the bit line voltage terminal) VBL corresponding to the first drain region of the memory device, and apply 0V or a negative voltage or set it to a floating state to the control gate voltage terminal (i.e., the terminal where voltage is applied to the source region and the drain region that form a coupling capacitance with its second gate in the capacitor device) VCG terminal, so that electrons on the floating gate (i.e., the first gate) of the memory device escape from the floating gate of the memory device, or so that hot holes in the memory device enter the floating gate of the memory device and recombine with electrons in the floating gate, increasing the threshold voltage of the memory device.

[0150] It should be noted that the "high voltage" is the forward bias voltage required to drive carriers to tunnel through the gate oxide layer, and the specific value is determined according to the process node and device parameters; the "medium voltage" is the intermediate voltage between the high voltage and the ground potential, which is used to adjust the floating gate coupling efficiency; "floating" means that the corresponding port is in a high impedance state or has no external potential driving state.

[0151] In summary, the single-gate multi-programmable memory provided by the embodiments of the present application can improve the efficiency of programming / erasing operations, reduce the operating voltage of programming / erasing operations, and improve the reliability of storage units.

[0152] In this specification, each embodiment is described in a progressive, or parallel, or progressive and parallel combination manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.

[0153] It should be noted that in the description of this application, it is to be understood that the descriptions of the drawings and embodiments are illustrative rather than restrictive. It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0154] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A single-gate multi-programmable memory, characterized in that, Comprising: A plurality of first semiconductor structure units, the first semiconductor structure units comprising: A first gate structure located on a first surface of a substrate, the first gate structure comprising a first gate oxide layer and a first gate stacked in a direction away from the substrate, and a first sidewall located on a side surface of a first stacked structure formed by the first gate oxide layer and the first gate; A first source region and a first drain region located in the substrate and opposite to two sides of the first gate structure; A lightly doped drain region and a halo doping region located in the substrate and below the first sidewall, the halo doping region being located on a side of the lightly doped drain region away from the first sidewall; The single-gate multi-programmable memory comprises: a memory cell array and a peripheral circuit, the peripheral circuit being configured to control an operating state of the memory cell array; wherein, the memory cell array comprises at least one single-gate multi-programmable memory cell, the single-gate multi-programmable memory cell comprising: a memory device; the peripheral circuit comprises a first switching device and a second switching device, and an operating voltage that the first switching device can withstand is greater than an operating voltage that the second switching device can withstand; The memory device, the first switching device and the second switching device all comprise the structure of the first semiconductor structure unit, and a doping concentration of the lightly doped drain region in the memory device is greater than a doping concentration of the lightly doped drain region in the first switching device.

2. The single-gate multi-programmable memory according to claim 1, wherein The doping concentration of the lightly doped drain region in the memory device is not less than the doping concentration of the lightly doped drain region in the second switching device.

3. The single-gate multi-programmable memory according to claim 2, characterized in that, The doping concentration of the lightly doped drain region in the memory device is equal to the doping concentration of the lightly doped drain region in the second switching device.

4. The single-gate multi-programmable memory according to claim 1, wherein The doping concentrations of the first source region and the first drain region in the memory device are greater than the concentrations of the first source region and the first drain region in the first switching device.

5. The single-gate multi-programmable memory according to claim 1, characterized in that, Further comprising at least one second semiconductor structure unit, the second semiconductor structure unit comprising: A second gate structure located on the first surface of the substrate, the second gate structure comprising a second gate oxide layer and a second gate stacked in a direction away from the substrate, and a second sidewall located on a side surface of a second stacked structure formed by the second gate oxide layer and the second gate; A second source region and a second drain region located in the substrate and opposite to two sides of the second gate structure, the second source region and the second drain region extending towards each other in the substrate and meeting below the second gate oxide layer to form a source-drain channel punch-through; The single-gate multi-programmable memory cell further comprises: a capacitor device, the capacitor device comprising the structure of the second semiconductor structure unit, and a halo doping region is not provided in a corresponding substrate region of the capacitor device.

6. The single-gate multi-programmable memory according to claim 5, wherein, A channel length of the capacitor device is less than a channel length of the memory device.

7. A manufacturing method of a single-gate multi-time programmable memory, characterized in that, Comprising: Forming a plurality of first stacked structures on a first surface of a substrate, the first stacked structures comprising a first gate oxide layer and a first gate stacked; Forming a lightly doped drain region and a halo doping region in regions on two opposite sides of the first stacked structure in the substrate, the halo doping region being located on a side of the lightly doped drain region away from the first surface of the substrate; On the first surface of the substrate, a first sidewall is formed above the lightly doped drain region, and the first sidewall covers the side surfaces of the first stacked structure; In the substrate, a first source region and a first drain region are formed on two opposite sides of the first sidewall; The single-gate multi-programmable memory includes: a memory cell array and a peripheral circuit, and the peripheral circuit is used to control the working state of the memory cell array; wherein, the memory cell array includes at least one single-gate multi-programmable memory cell, and the single-gate multi-programmable memory cell includes: a memory device; the peripheral circuit includes a first switching device and a second switching device, and the working voltage that the first switching device can withstand is greater than the working voltage that the second switching device can withstand; the doping concentration of the lightly doped drain region in the memory device is greater than the doping concentration of the lightly doped drain region in the first switching device.

8. The manufacturing method according to claim 7, characterized in that, In the substrate, the regions on two opposite sides of the first stacked structure form a lightly doped drain region and a halo doping region, including: Using a first mask layer, performing lightly doped drain ion implantation and halo ion implantation on a first region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device, and the first region includes the region where the lightly doped drain region and the halo doping region of the first switching device are to be formed; Using a second mask layer, performing lightly doped drain ion implantation and halo ion implantation on a second region of the substrate to form the lightly doped drain region and the halo doping region of the second switching device and the lightly doped drain region and the halo doping region of the memory device, and the second region includes the region where the lightly doped drain region and the halo doping region of the second switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the memory device are to be formed.

9. The manufacturing method according to claim 8, characterized in that, It further includes: Performing a logical operation on the first mask layer pattern and the first identification layer pattern in the layout design file to generate the first mask layer; Performing a logical operation on the second mask layer pattern and the first identification layer pattern in the layout design file to generate the second mask layer; Wherein, the injection region corresponding to the first mask layer pattern is a first injection region, the injection region corresponding to the second mask layer pattern is a second injection region, the injection region corresponding to the first identification layer pattern is a third injection region, the third injection region is located within the first injection region, the injection region of the first mask layer is the region of the first injection region excluding the third injection region, and the injection region of the second mask layer is the sum of the second injection region and the third injection region.

10. The manufacturing method according to claim 7, characterized in that, In the substrate, the regions on two opposite sides of the first stacked structure form a lightly doped drain region and a halo doping region, including: Using a third mask layer, performing lightly doped drain ion implantation and halo ion implantation on a third region of the substrate to form the lightly doped drain region and the halo doping region of the first switching device and the halo doping region of the memory device, and the third region includes the region where the lightly doped drain region and the halo doping region of the first switching device are to be formed and the region where the lightly doped drain region and the halo doping region of the memory device are to be formed; Using a fourth mask layer, perform lightly doped drain ion implantation and halo ion implantation on a fourth region of the substrate to form a lightly doped drain region and a halo doped region of the second switching device, where the fourth region includes a region where the lightly doped drain region and the halo doped region of the second switching device are to be formed; Using a fifth mask layer, perform another lightly doped drain ion implantation on a fifth region of the substrate to form a lightly doped drain region of the storage device, where the third region includes the fifth region, and the fifth region is a region where the lightly doped drain region of the storage device is to be formed.

11. The manufacturing method according to claim 7, characterized in that, Forming a first source region and a first drain region on two opposite sides of the first sidewall within the substrate includes: Using a sixth mask layer, perform ion implantation on a sixth region of the substrate to form a first source region and a first drain region on two opposite sides of the first sidewall.

12. The manufacturing method according to claim 11, characterized in that, Forming a first source region and a first drain region on two opposite sides of the first sidewall within the substrate further includes: Using a seventh mask layer, perform ion implantation on the first source region and the first drain region of the storage device again to increase the doping concentration of the first source region and the first drain region of the storage device.

13. The manufacturing method according to claim 7, wherein Further included is: Forming at least one second stacked structure on a first surface of the substrate, where the second stacked structure includes a second gate oxide layer and a second gate arranged in a stacked manner; Forming a second sidewall on a side surface of the second stacked structure on the first surface of the substrate; Forming a second source region and a second drain region on two opposite sides of the second sidewall within the substrate, where the second source region and the second drain region extend towards each other within the substrate and meet below the second gate oxide layer to form a source-drain channel punchthrough; The single-gate multi-programmable memory cell further includes: a capacitor device, where the capacitor device includes the second stacked structure, the second sidewall, and the second source region and the second drain region located on two opposite sides of the second sidewall, and there is no halo doped region in the corresponding substrate region of the capacitor device.

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