Method of forming array of vertically extending strings of memory cells

Abstract

A method of forming an array of vertically extending strings of memory cells includes forming and removing a portion of a lower stacked memory cell material across individual substrates in individual lower channel openings. A capping material is formed in a lowest portion of the individual lower channel openings to cover the individual substrates of the individual lower channel openings. Upper channel openings are formed in the upper stack to the lower channel openings to form interconnected channel openings, the interconnected channel openings respectively including one of the individual lower channel openings and individual ones of the upper channel openings. A portion of an upper stacked memory cell material is formed and removed across the individual substrates in the individual upper channel openings. After the removal of the portion of the upper stacked memory cell material, the capping material is removed from the interconnected channel opening.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application of a Chinese patent application with the application number 201910786746.2, the application date of August 23, 2019, and the invention title of "Method for Forming a Vertically Extended String Array of Memory Cells". Technical Field

[0003] The embodiments disclosed herein relate to methods for forming vertically extended string arrays of programmable memory cells and methods for forming vertically extended string arrays of memory cells. Background Art

[0004] A memory is an integrated circuit and is used in a computer system to store data. Memories can be fabricated as one or more arrays of individual memory cells. Digital lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines) can be used to write to or read from the memory cells. Sense lines can conductively interconnect the memory cells along the columns of the array, and access lines can conductively interconnect the memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

[0005] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memories are conventionally designated as memories having a retention time of at least about 10 years. Volatile memories dissipate and are thus refreshed / rewritten to maintain data storage. Volatile memories can have a retention time of milliseconds or less. In any case, the memory cells are configured to hold or store stored content in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0006] Field effect transistors are electronic components that can be used in memory cells. These transistors include a pair of conductive source / drain regions having a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely blocked. Field effect transistors can also include additional structures, such as reversible programmable charge storage regions that are part of the gate structure between the gate insulator and the conductive gate.

[0007] A flash memory is a type of memory and is widely used in modern computers and devices. For example, a modern personal computer may store its BIOS on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to use flash memory in the form of solid state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0008] NAND can be the basic architecture of an integrated flash memory. A NAND cell device includes at least one select device serially coupled to a serial combination of memory cells (and the serial combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement that includes vertically stacked memory cells, each of the vertically stacked memory cells including a reversibly programmable vertical transistor. Control circuitry or other circuitry can be formed beneath the vertically stacked memory cells. Summary of the Invention

[0009] In one aspect, a method of forming an array of vertically extending strings of memory cells is provided. The method includes: forming and removing a portion of lower stacked memory cell material across an individual substrate in an individual lower channel opening; forming a capping material in a lowest portion of the individual lower channel opening to cover the individual substrate of the individual lower channel opening; forming upper channel openings in an upper stack to reach the lower channel openings to form interconnected channel openings, each of the interconnected channel openings including one of the individual lower channel openings and an individual upper channel opening in the upper stack; forming and removing a portion of upper stacked memory cell material across an individual substrate in the individual upper channel opening; after the removal of the portion of the upper stacked memory cell material, removing the capping material from the interconnected channel openings; after the removal of the capping material, forming transistor channel material in an upper portion of the interconnected channel openings; after forming the transistor channel material, replacing upper stack and lower stack sacrificial materials with control gate material having ends corresponding to control gate regions of individual memory cells; and forming charge storage material between the transistor channel material and the control gate regions, forming insulating charge transfer material between the transistor channel material and the charge storage material, and forming charge blocking regions between the charge storage material and the individual control gate regions.

[0010] In another aspect, a method of forming a vertically-extended string array of memory cells is provided. The method includes: forming a lower stack including vertically alternating insulating layers and word line layers, the lower stack insulating layers including a first lower stack insulating material, the lower stack word line layers including a second lower stack material having a composition different from that of the first lower stack material, lower channel openings being in the lower stack; forming lower stack memory cell material across a substrate of individual ones of the lower channel openings and along sidewalls of the individual lower channel openings; removing a portion of the lower stack memory cell material across the individual substrates in the individual lower channel openings; forming a sacrificial capping material in a lowest portion of the individual lower channel openings to cover the individual substrates of the individual lower channel openings; forming an upper stack over the lower stack, the upper stack including vertically alternating insulating layers and word line layers, the upper stack insulating layers including a first upper stack insulating material, the upper stack word line layers including a second upper stack material having a composition different from that of the first upper stack material; forming upper channel openings in the upper stack to reach the lower channel openings to form interconnected channel openings, the interconnected channel openings respectively including one of the individual lower channel openings and an individual upper channel opening in the individual upper channel openings; forming upper stack memory cell material across a substrate of individual ones of the upper channel openings and along sidewalls of the individual upper channel openings; removing a portion of the upper stack memory cell material across the individual substrates in the individual upper channel openings; after the removal of the portion of the upper stack memory cell material, removing the sacrificial capping material from the interconnected channel openings; after the removal of the sacrificial capping material, forming transistor channel material vertically along vertically alternating layers in an upper portion of the interconnected channel openings; after forming the transistor channel material, replacing the second upper stack material and the second lower stack material of the word line layers with control gate material, the control gate material having ends corresponding to control gate regions of individual memory cells; and forming the word line layer to include charge storage material between the transistor channel material and the control gate regions, insulating charge transfer material between the transistor channel material and the charge storage material, and charge blocking regions between the charge storage material and the individual control gate regions.

[0011] In yet another aspect, a method of forming a vertically-extended string array of memory cells is provided.The method includes: forming a lower stack including vertically alternating insulating layers and word line layers, the lower stack insulating layers including a first lower stack insulating material, the lower stack word line layers including a second lower stack material having a composition different from that of the first lower stack insulating material, with lower channel openings in the lower stack; forming at least one of the following: (a) a lower stack charge blocking material in an individual lower channel opening of the lower channel openings, across the substrate of the individual lower channel opening, and along the sidewalls of the individual lower channel opening, or (b) a lower stack charge storage material in the individual lower channel opening, across the substrate of the individual lower channel opening, and along the sidewalls of the individual lower channel opening; removing a portion of at least one of (a) and (b) across an individual substrate in the substrate of the individual lower channel opening; after removing the portion of at least one of (a) and (b), filling the remaining volume of the lower channel opening with a sacrificial capping material; forming an upper stack above the lower stack, the upper stack including vertically alternating insulating layers and word line layers, the upper stack insulating layers including a first upper stack insulating material, the upper stack word line layers including a second upper stack material having a composition different from that of the first upper stack insulating material; forming upper channel openings in the upper stack to reach the sacrificial capping material in the individual lower channel openings to form interconnected channel openings, the interconnected channel openings respectively including one of the individual lower channel openings and an individual upper channel opening in the upper channel openings; forming at least one of the following: (c) an upper stack charge blocking material in an individual upper channel opening of the upper channel openings, across the substrate of the individual upper channel opening, and along the sidewalls of the individual upper channel opening, or (d) an upper stack charge storage material in the individual upper channel opening, across the substrate of the individual upper channel opening, and along the sidewalls of the individual upper channel opening; removing a portion of at least one of (c) and (d) across an individual substrate in the substrate of the individual upper channel opening; after the removal of the portion of at least one of (c) and (d), removing the sacrificial capping material from the interconnected channel openings; vertically forming transistor channel material in an upper portion of the interconnected channel openings along the vertically alternating layers in the upper stack; after forming the transistor channel material, replacing the second upper stack material and the second lower stack material of the word line layers with a control gate material having ends corresponding to control gate regions of individual memory cells; and forming the word line layers to include a charge storage material between the transistor channel material and the control gate regions, an insulating charge transfer material between the transistor channel material and the charge storage material, and a charge blocking region between the charge storage material and the individual control gate regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic cross-sectional view of a portion of a substrate being processed according to an embodiment of the present invention and is taken along line 1-1 in Figure 2 .

[0013] Figure 2 is a view taken along line 2-2 in Figure 1 .

[0014] Figure 3 is a view of the substrate at a processing step after the processing step shown in Figure 2 . Figure 2 substrate.

[0015] Figure 4 is a view of the substrate at a processing step after the processing step shown in Figure 3 . Figure 3 substrate.

[0016] Figure 5 is a view of the substrate at a processing step after the processing step shown in Figure 4 . Figure 4 substrate.

[0017] Figure 6 is a view of the substrate at a processing step after the processing step shown in Figure 5 . Figure 5 substrate.

[0018] Figure 7 is a view of the substrate at a processing step after the processing step shown in Figure 6 . Figure 6 substrate.

[0019] Figure 8 is a view of the substrate at a processing step after the processing step shown in Figure 7 . Figure 7 substrate.

[0020] Figure 9 is a view of the substrate at a processing step after the processing step shown in Figure 8 . Figure 8 substrate.

[0021] Figure 10 is a view of the substrate at a processing step after the processing step shown in Figure 9 . Figure 9 substrate.

[0022] Figure 11 is a view of the substrate at a processing step after the processing step shown in Figure 10 . Figure 10 substrate.

[0023] Figure 12 is the Figure 11 view of the substrate after the processing steps shown, and is taken along line 12-12 in Figure 11 . Figure 13 .

[0024] Figure 13 is a view taken along line 13-13 in Figure 12 .

[0025] Figure 14 is the Figure 13 view of the substrate after the processing steps shown, Figure 13 .

[0026] Figure 15 is the Figure 14 view of the substrate after the processing steps shown, Figure 14 .

[0027] Figure 16 is the Figure 15 view of the substrate after the processing steps shown, and is taken along line 16-16 in Figure 15 . Figure 17 .

[0028] Figure 17 is a view taken along line 17-17 in Figure 16 .

[0029] Figure 17A is an enlarged view of a portion of the substrate as shown in Figure 17 .

[0030] Figure 18 is the Figure 16 view of the substrate after the processing steps shown, and is taken along line 18-18 in Figure 16 . Figure 19 .

[0031] Figure 19 is a view taken along line 19-19 in Figure 18 . DETAILED DESCRIPTION

[0032] Embodiments of the present invention cover methods of forming vertical extended string arrays of programmable transistors and / or memory cells, such as arrays of NAND or other memory cells with peripheral control circuitry (e.g., CMOS under-array) below the array. Embodiments of the present invention cover so-called "post-gate" or "replace-gate" processing. Refer to Figures 1 to 19 for a description of example embodiments, which may be considered a "post-gate" or "replace-gate" process.

[0033] Figure 1 and 2 shows a substrate structure 10 during a process of forming a vertical extension string array 12 of transistors and / or memory cells. The substrate structure 10 includes a base substrate 11, which has any one or more of conductive / conductor / conduction (i.e., electrically in this document), semiconductive / semiconductor / semiconduction, or insulating / insulator / insulation (i.e., electrically in this document) materials. Various materials are vertically formed on the base substrate 11. The materials can be Figure 1 and 2 beside, vertically inside, or vertically outside the depicted materials. For example, other parts of an integrated circuit or fully manufactured components can be provided above, around, or somewhere inside the base substrate 11. Control circuits and / or other peripheral circuits for operating components within the vertical extension string array (e.g., array 12) of memory cells can also be fabricated, and the circuits can or cannot be fully or partially within the array or sub-array. Additionally, multiple sub-arrays can be fabricated and operated independently of each other, in tandem, or in other ways. In this document, a "sub-array" can also be regarded as an array.

[0034] The substrate structure 10 includes a lower stack 18, which includes insulating layers 20 and word line layers 22 that are vertically alternating directly above an exemplary conductive doped semiconductor material 16 (e.g., conductive doped polysilicon). The conductive material 16 can include a part of a control circuit (e.g., the array bottom peripheral circuit) for controlling read and write access to transistors and / or memory cells to be formed within the array 12. The lower stack insulating layer 20 includes a lower stack first insulating material 24 (e.g., silicon dioxide). The lower stack word line layer 22 includes a lower stack second material 26 (e.g., silicon nitride, and in any case, it can be fully or partially sacrificial) having a composition different from that of the lower stack first material 24. Lower channel openings 25 (e.g., by dry anisotropic etching) have been formed in the alternating layers 20, 22 and can have individual bases 21 within the material 16.

[0035] By way of example only, the lower channel openings 25 are shown arranged in a staggered row group or column of four openings 25 per row. Any alternative existing or future developed arrangement and configuration may be used. The use of "row" and "column" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along said "rows" and "columns". "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. In any case, the rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and the columns may be the same. Additionally, the rows and columns may intersect each other at 90° or at one or more other angles. Other circuitry, which may or may not be part of the peripheral circuitry, may be present between the conductive doped semiconductor material 16 and the stack 18.

[0036] Reference Figure 3 , the lower stack memory cell material 30 has been formed within the lower channel openings 25 across the individual substrates 21 and along the sidewalls of the lower channel openings 25. In the context of this document, "memory cell material" is any material that includes the operating materials in a completed memory cell configuration, and by way of example only, includes any one or more of gate material, source / drain material, charge blocking material, charge storage material, charge transfer material, gate dielectric, and channel material. In one embodiment, the memory cell material 30 includes at least one of (a) a lower stack charge blocking material or (b) a lower stack charge storage material (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.). In one such embodiment, the memory cell material includes (a). In one such embodiment, the memory cell material includes (b). In one such embodiment, the memory cell material includes (a) and (b). The memory cell material 30 may be formed, for example, by depositing a thin layer thereof on the lower stack 18 and within the individual lower channel openings 25 and then planarizing this material at least back to the vertical outermost surface of the stack 18.

[0037] Reference Figure 4 , a portion (e.g., a lateral central portion and / or a radial central portion) of the lower stack memory cell material 30 across the individual substrates 21 in the individual lower channel openings 25 has been removed. By way of example, this may be formed by performing a maskless anisotropic etch of the material 30 using one or more etching chemical reactions, and this etching may be performed without first removing such material from a horizontal surface located on top of the lower stack 18, as Figure 3 shown.

[0038] Reference Figure 5, a sacrificial capping material 27 (e.g., alumina and / or photoresist) has been formed in the lowest portion of the individual lower channel openings 25 to cover the individual substrates 21 of the individual lower channel openings 25. In one embodiment and as shown, radially inside the lower stacked memory cell material 30, the remaining volume of the lower channel openings 25 (e.g., after the instance process shown in Figure 4 )(i.e., completely) is filled with the sacrificial capping material 27. In one embodiment and as shown, the capping material 27 is formed to have a flat top surface 23. The lower stacked memory cell material 30 may also have a flat top surface 19, and it is vertically coincident with the top surface 23 of the lower stacked memory cell material 30.

[0039] Reference Figure 6 , an upper stack 35 has been formed above the lower stack 18. The upper stack 35 includes vertically alternating insulating layers 20 and word line layers 22. In one embodiment, the upper stack insulating layer 20 includes an insulating upper stack first material 24 (which may have the same or different composition as the lower stack first material 24), and the upper stack word line layer 22 includes an upper stack second material 26 having a composition different from that of the upper stack first material 24 (which may have the same or different composition as the lower stack second material 26). Only a few layers 20, 22 in each of the upper and lower stacks are shown, but it is likely that there are more (e.g., dozens, hundreds, etc.) layers in each stack, and the stacks do not need to have the same number of layers relative to each other.

[0040] See Figure 7 , an upper channel opening 37 has been formed in the upper stack 35 to reach the lower channel opening 25 to form an interconnected channel opening 47, and the interconnected channel opening respectively includes one of the individual upper channel openings in the individual lower channel opening 25 and the upper channel opening 37. The upper channel opening 37 can be regarded as including an individual substrate 39. In one embodiment and as shown, the upper channel opening 37 has been formed (e.g., by dry anisotropic etching) to the sacrificial capping material 27, thereby having an upper channel opening substrate 39 including the capping material 27. In one embodiment and as shown, radially inside the lower stacked memory cell material 30, the capping material 27 is vertically recessed so that the lower channel opening 25 is not filled.

[0041] In one embodiment, the capping material 27 is formed to initially have a flat top surface 23 ( Figure 5 ), and the flat top surface subsequently becomes non-planar as shown, for example, by over-etching into the sacrificial material 27, as Figure 7shown. In one embodiment and as shown, a lateral center portion 28 (e.g., a radial center portion) of the capping material substrate 39 of the upper channel opening 37 is formed to have a top surface that is lower than the top surface of the lateral outer portion 33 (e.g., the radial outer portion) of the capping material 27. In one embodiment and as shown, the top surface of the lateral center portion 28 is not horizontal and is curved as shown in one such embodiment. In one embodiment, the top surface of the lateral outer portion 33 is not horizontal and is curved in one such embodiment.

[0042] Referring Figure 8 , the upper stacked memory cell material 30 has been formed across the individual substrates 39 and along the sidewalls of the individual upper channel openings 37. The upper stacked memory cell material 30 may have the same or a different composition than the lower stacked memory cell material 30. In any case, in one embodiment, the upper stacked memory cell material 30 includes at least one of (c) an upper stacked charge blocking material or (d) an upper stacked charge storage material (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.). In one such embodiment, the memory cell material includes (c). In one such embodiment, the memory cell material includes (d). In one such embodiment, the memory cell material includes (c) and (d). The upper stacked memory cell material 30 may be formed, for example, by depositing a thin layer thereof on the upper stack 35 and within the individual upper channel openings 37 and then planarizing this material at least back to the vertical outermost surface of the stack 35.

[0043] Referring Figure 9 , a portion of the upper stacked memory cell material 30 across the individual substrates 39 in the individual upper channel openings 37 has been removed (e.g., by maskless anisotropic etching).

[0044] Referring Figure 10 , the sacrificial capping material 27 (not shown) has been removed from the interconnected channel openings 47 (e.g., by wet or dry selective etching).

[0045] Referring Figure 11 , and in the case where, for example, the memory cell material 30 includes a charge blocking material, a charge storage material 32 has been formed vertically along the alternating layers 20, 22 and the charge blocking material 30 in the interconnected channel openings 47. An insulating charge transfer material 34 has been formed along the alternating layers 20, 22 and the charge storage material 32 in the interconnected channel openings 47. By way of example, the charge transfer material 34 may be a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides (e.g., silicon dioxide).

[0046] The transistor channel material 36 has been formed vertically (i.e., at least) along the upper stack 35 (i.e., at least) in the upper (i.e., at least) of the interconnected channel openings 47. In one embodiment and as shown, the transistor channel material 36 is formed simultaneously in the upper channel opening 37 and the lower channel opening 25 of the interconnected channel openings 47. Example channel materials 36 include suitably doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called Group III / Group V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of the materials 30, 32, 34, and 36 is 25 to 100 angstroms. The interconnected channel openings 47 are shown to include a radially centered solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially centered portion within the interconnected channel openings 47 may include void space (not shown) and / or be void of solid material (not shown).

[0047] Reference Figure 12 and 13 , horizontally extended ( Figure 12 ) trenches 40 have been formed (e.g., by anisotropic etching) into the upper stack 35 and the lower stack 18, and in one embodiment into the conductively doped semiconductor material 16 (i.e., at least to the material 16). The side edges of the trenches 40 can be used at least in part to define the side edges of a word line (e.g., an access or control gate line, and Figure 12 and 13 not shown in ) as described below.

[0048] Reference Figure 14 , the upper stack second material 26 (not shown) and the lower stack second material 26 (not shown) of the word line layer 22 are selectively etched relative to the insulating upper stack first material 24 and selectively relative to the insulating lower stack first material 24. In the case where the second material 26 includes silicon nitride and the first material 24 includes silicon dioxide, an example etching chemistry is a liquid or vapor phase etching where H3PO4 is the main etchant.

[0049] Reference Figure 15 , the control gate material 48 (i.e., a conductive material) has been formed through the trenches 40 into the word line layer 22 to be vertically between the insulating upper stack first materials 24 of the upper stack alternating layers 20 and vertically between the insulating lower stack first materials 24 of the lower stack alternating layers 20. Any suitable conductive material can be used, such as one or both of a metallic material and / or a conductively doped semiconductor material.

[0050] Reference Figure 16 , 17With respect to FIGS. 17A, control gate material 48 has been removed from individual trenches 40. This gives rise to the formation of word lines 29 and vertical extension strings 49 of individual programmable transistors and / or memory cells 56. In one embodiment and as shown, string 49 is formed vertically or within 10° of vertical. The approximate locations of the programmable transistors and / or memory cells 56 are indicated by brackets in Figure 17A and some are indicated by dashed outlines in Figure 16 and 17 where the transistors and / or memory cells 56 are substantially circular or annular in the depicted example. The control gate material 48 has ends 50 corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56 ( Figure 17A ). In the depicted embodiment, the control gate regions 52 include individual portions of the individual word lines 29.

[0051] A charge blocking region (e.g., charge blocking material 30) is disposed between the charge storage material 32 and the individual control gate regions 52. The charge blocking member can have the following functions in a memory cell: in the program mode, the charge blocking member can prevent charge carriers from passing from the charge storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in the erase mode, the charge blocking member can prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member can be used to block charge migration between the control gate region of an individual memory cell and the charge storage material. The illustrated example charge blocking region includes insulator material 30. As another example, the charge blocking region can include a lateral (e.g., radial) outer portion of the charge storage material (e.g., material 32) where such charge storage material is insulating (e.g., in the case where there is no different composition material between the insulating charge storage material 32 and the conductive material 48). In any case, as an additional example, the interface between the charge storage material and the conductive material of the control gate can be sufficient to act as a charge blocking region in the absence of any separately formed insulator material 30. Further, the interface between the conductive material 48 and the material 30 (when present) in combination with the insulator material 30 can together act as a charge blocking region and alternatively or additionally can be a lateral outer region of an insulating charge storage material (e.g., silicon nitride material 32).

[0052] Referring to Figure 18 and 19 , an insulating material liner 55 has been formed on the sidewalls of the individual trenches 40 and vertically along the sidewalls in such trenches (e.g., silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, combinations thereof, etc.). Another material 57 (dielectric and / or silicon-containing, e.g., polysilicon) has been formed vertically along the insulating material liner 55 and across between the insulating material liners in the individual trenches 40.

[0053] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "over", "under", "beneath", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and the substrate can be processed relative thereto during manufacturing, and vertical is a direction generally orthogonal thereto. The reference to "exactly horizontal" refers to a direction along the main substrate surface (i.e., not forming a degree with the surface) and the substrate can be processed relative thereto during manufacturing. In addition, as used herein, "vertical" and "horizontal" are directions that are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "extending vertically" refer to a direction that deviates from exactly horizontal by at least 45°. Further, with respect to a field effect transistor, "vertically extending", "extending vertically", "extending horizontally", and "horizontally extending" refer to the orientation of the channel length of the transistor along which current flows between the source / drain regions during operation. For a bipolar junction transistor, "vertically extending", "extending vertically", "extending horizontally", and "horizontally extending" refer to the orientation of the base length along which current flows between the emitter and the collector during operation.

[0054] In addition, "directly above" and "directly below" require that there be at least some lateral overlap (i.e., horizontally) between the two stated regions / materials / components relative to each other. Additionally, the use of "above" without "directly" in front only requires that a portion of the stated region / material / component above another stated region / material / component be vertically outside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap between the two stated regions / materials / components). Similarly, the use of "below" without "directly" in front only requires that a portion of the stated region / material / component below another stated region / material / component be vertically inside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap between the two stated regions / materials / components).

[0055] Any of the materials, regions, and structures described herein can be homogeneous or heterogeneous and can be continuous or discontinuous over any overlying material in any case. In cases where one or more example compositions are provided for any material, the material can include such one or more compositions, consist essentially of such one or more compositions, or consist of such one or more compositions. In addition, unless otherwise specified, any suitable or yet-to-be-developed technique can be used to form each material, examples of which are atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0056] In addition, "thickness" when used alone (without a directional adjective in front) is defined as the average straight-line distance perpendicular to the closest surface of the adjacent material or adjacent region having a different composition and passing through a given material or region. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If the thickness is variable, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those portions of the two stated materials or regions that can be directly adjacent to each other be chemically and / or physically different, for example, in the case where such materials or regions are not homogeneous. If the two stated materials or regions are not directly adjacent to each other, then in the case where such materials or regions are not homogeneous, "different composition" only requires that those portions of the two stated materials or regions that are closest to each other be chemically and / or physically different. In this document, materials, regions, or structures "directly abut" another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures relative to each other. In contrast, "above", "on", "adjacent to", "along", and "abut" without "positive" in front cover "directly abut" and configurations in which intervening materials, regions, or structures result in no physical contact between the stated materials, regions, or structures relative to each other.

[0057] In this document, if in normal operation, current can flow continuously from one region-material-component to another region-material-component, and the flow is mainly through the movement of the subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the region-material-components are "electrically coupled" relative to each other. Another electronic component can be between the region-material-components and be electrically coupled to the region-material-components. In contrast, when region-material-components are said to be "directly electrically coupled", there is no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled region-material-components.

[0058] In addition, "metallic material" is any one or combination of elemental metals, mixtures or alloys of two or more elemental metals, and any conductive metal compound.

[0059] In this document, "selectivity" with respect to etching, removal, and / or formation is an action in which a stated material is acted upon relative to another stated material at a ratio of at least 2:1 by volume.

[0060] Unless otherwise indicated, the use of "or" herein covers either and both.

[0061] Summary

[0062] In some embodiments, a method of forming a vertically-extended string array of memory cells includes forming and removing a portion of a lower stacked memory cell material across an individual substrate in an individual lower channel opening. A capping material is formed in a lowest portion of the individual lower channel opening to cover the individual substrate of the individual lower channel opening. An upper channel opening is formed in an upper stack to reach the lower channel opening to form an interconnected channel opening, the interconnected channel opening respectively including one of the individual lower channel opening and an individual upper channel opening in the upper stack. A portion of an upper stacked memory cell material across an individual substrate in the individual upper channel opening is formed and removed. After the removal of the portion of the upper stacked memory cell material, the capping material is removed from the interconnected channel opening. After the removal of the capping material, transistor channel material is formed in an upper portion of the interconnected channel opening. After forming the transistor channel material, the upper stack and lower stack sacrificial materials are replaced with a control gate material having ends corresponding to control gate regions of individual memory cells. Charge storage material is formed between the transistor channel material and the control gate region. Insulating charge transfer material is formed between the transistor channel material and the charge storage material. A charge blocking region is between the charge storage material and the individual control gate regions.

[0063] In some embodiments, a method of forming a vertically-extended string array of memory cells includes forming a lower stack that includes vertically alternating insulating layers and word line layers. The lower stack insulating layers include an insulating lower stack first material. The lower stack word line layers include a lower stack second material having a composition different from the composition of the lower stack first material. Lower channel openings are in the lower stack. Lower stack memory cell material is formed across the substrate of individual lower channel openings in the lower channel openings and along the sidewalls of the individual lower channel openings. A portion of the lower stack memory cell material across the individual substrate in the substrate of the individual lower channel openings is removed. A sacrificial capping material is formed in the lowest portion of the individual lower channel openings to cover the individual substrate of the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack includes vertically alternating insulating layers and word line layers. The upper stack insulating layers include an insulating upper stack first material. The upper stack word line layers include an upper stack second material having a composition different from the composition of the upper stack first material. Upper channel openings are formed in the upper stack to reach the lower channel openings to form interconnected channel openings, the interconnected channel openings respectively including one of the individual lower channel openings and an individual upper channel opening in the individual upper channel openings. Upper stack memory cell material is formed across the substrate of individual upper channel openings in the upper channel openings and along the sidewalls of the individual upper channel openings. A portion of the upper stack memory cell material across the individual substrate in the substrate of the individual upper channel openings is removed. After removing the portion of the upper stack memory cell material, the sacrificial capping material is removed from the interconnected channel openings. After removing the sacrificial capping material, transistor channel material is formed vertically along the vertically alternating layers in the upper portion of the interconnected channel openings. After forming the transistor channel material, the upper stack second material and the lower stack second material of the word line layer are replaced with control gate material. The control gate material has ends corresponding to the control gate regions of individual memory cells. The word line layer is formed to include charge storage material between the transistor channel material and the control gate region, insulating charge transfer material between the transistor channel material and the charge storage material, and charge blocking regions between the charge storage material and the individual control gate regions.

[0064] In some embodiments, a method of forming a vertically-extended string array of memory cells includes forming a lower stack including vertically alternating insulating layers and word line layers. The lower stack insulating layers include an insulating lower stack first material. The lower stack word line layers include a lower stack second material having a composition different from that of the lower stack first material. Lower channel openings are in the lower stack. Form at least one of the following: (a) a lower stack charge blocking material in an individual lower channel opening of the lower channel openings, across a substrate of the individual lower channel opening, and along sidewalls of the individual lower channel opening, or (b) a lower stack charge storage material in an individual lower channel opening, across a substrate of the individual lower channel opening, and along sidewalls of the individual lower channel opening. Remove a portion of at least one of (a) and (b) across an individual substrate in the substrate of the individual lower channel opening. After removing the portion of at least one of (a) and (b), fill a remaining volume of the lower channel openings with a sacrificial capping material. An upper stack is formed above the lower stack. The upper stack includes vertically alternating insulating layers and word line layers. The upper stack insulating layers include an insulating upper stack first material. The upper stack word line layers include an upper stack second material having a composition different from that of the upper stack first material. Upper channel openings are formed in the upper stack to reach the sacrificial capping material in the individual lower channel openings to form interconnected channel openings, each of the interconnected channel openings including one of an individual lower channel opening and an individual upper channel opening in the individual upper channel openings. Form at least one of the following: (c) an upper stack charge blocking material in an individual upper channel opening of the upper channel openings, across a substrate of the individual upper channel opening, and along sidewalls of the individual upper channel opening, or (d) an upper stack charge storage material in an individual upper channel opening, across a substrate of the individual upper channel opening, and along sidewalls of the individual upper channel opening. Remove a portion of at least one of (c) and (d) across an individual substrate in the substrate of the individual upper channel opening. After removing the portion of at least one of (c) and (d), remove the sacrificial capping material from the interconnected channel openings. Transistor channel material is formed vertically along vertically alternating layers in the upper stack in an upper portion of the interconnected channel openings. After forming the transistor channel material, replace the upper stack second material and the lower stack second material of the word line layers with a control gate material. The control gate material has ends corresponding to control gate regions of individual memory cells. The word line layers are formed to include a charge storage material between the transistor channel material and the control gate regions, an insulating charge transfer material between the transistor channel material and the charge storage material, and a charge blocking region between the charge storage material and the individual control gate regions.

[0065] As provided, the subject matter disclosed herein has been described in more or less specific language with respect to structural and method features. However, it should be understood that the claims are not limited to the specific features shown and described, since the devices disclosed herein include example embodiments. Accordingly, the claims have the full scope as literally stated and should be construed appropriately under the doctrine of equivalents.

Claims

1. A method of forming a vertically-extended string array of memory cells, comprising: forming and removing a charge blocking material of a lower stack memory cell material across an individual substrate in an individual lower channel opening; forming a capping material in a lowest portion of the individual lower channel opening to cover the individual substrate of the individual lower channel opening; forming upper channel openings in an upper stack to reach the lower channel openings to form interconnected channel openings, the interconnected channel openings each including one of the individual lower channel openings and an individual upper channel opening in the upper channel openings, wherein a substrate of the upper channel opening is formed to include the capping material, the forming of the upper channel opening includes etching, and the etching also etches the capping material to vertically recess the capping material radially inward of the lower stack memory cell material to leave the lower channel opening unfilled; forming and removing a charge blocking material of an upper stack memory cell material across an individual substrate in an individual upper channel opening; after the removing of the portion of the upper stack memory cell material, removing the capping material from the interconnected channel openings; after the removing of the capping material, forming a charge storage material, an insulating charge transfer material, and a transistor channel material in the interconnected channel openings, wherein the charge storage material is formed between the transistor channel material and a control gate region, the insulating charge transfer material is formed between the transistor channel material and the charge storage material, and the charge blocking material is formed between the charge storage material and each of the control gate regions; and after forming the transistor channel material, replacing upper stack and lower stack sacrificial materials with a control gate material having ends corresponding to the control gate regions of the individual memory cells.

2. The method according to claim 1, comprising forming the capping material and the lower stack memory cell material to have vertically coincident top planar surfaces.

3. The method according to claim 1, comprising forming the capping material to fill the lower channel opening radially inward of the lower stack memory cell material.

4. The method according to claim 3, comprising, in a process sequence: forming the capping material to initially fill the lower channel opening radially inward of the lower stack memory cell material; and vertically recessing the capping material radially inward of the lower stack memory cell material to leave the lower channel opening unfilled.

5. The method according to claim 1, comprising forming the lower channel opening and the upper channel opening to have the same size and no variation in a vertical direction.

6. The method according to claim 1, comprising forming the capping material to have a flat top surface.

7. The method according to claim 6, comprising, in a process sequence: forming the capping material to initially have a flat top surface; and rendering the flat top surface of the capping material non-planar.

8. The method according to claim 7, comprising forming the substrate of the upper channel opening to include the covering material, the forming of the substrate of the upper channel opening causing the flat top surface of the covering material to present as non-planar.

9. The method according to claim 1, comprising forming the substrate of the upper channel opening to include the covering material.

10. The method according to claim 9, comprising forming a lateral central portion of the covering material substrate of the upper channel opening to have a top surface that is lower than the top surface of the lateral outer portion of the covering material.

11. The method according to claim 10, wherein the top surface of the lateral central portion is not horizontal.

12. The method according to claim 11, wherein the top surface of the lateral central portion is curved.

13. The method according to claim 10, wherein the top surface of the lateral outer portion is not horizontal.

14. The method according to claim 13, wherein the top surface of the lateral outer portion is curved.

15. The method according to claim 1, wherein the covering material comprises at least one of photoresist and alumina.

16. The method according to claim 15, wherein the covering material comprises photoresist.

17. The method according to claim 15, wherein the covering material comprises alumina.

18. The method according to claim 1, wherein the forming of the transistor channel material forms the transistor channel material simultaneously in both the upper channel opening and the lower channel opening of the channel opening of the interconnect.

19. A method of forming a vertical array of vertically extending memory cell strings, comprising: forming a lower stack including vertically alternating insulating layers and word line layers, the lower stack insulating layers including a first lower stack insulating material, the lower stack word line layers including a second lower stack material having a composition different from that of the first lower stack insulating material, lower channel openings being in the lower stack; forming lower stack memory cell material across the substrate of individual lower channel openings in the lower channel openings and along the sidewalls of the individual lower channel openings; removing a charge blocking material of the lower stack memory cell material across the individual substrates in the individual lower channel openings; forming a sacrificial covering material in the lowest portion of the individual lower channel openings to cover the individual substrates of the individual lower channel openings; forming an upper stack over the lower stack, the upper stack including vertically alternating insulating layers and word line layers, the upper stack insulating layers including a first upper stack insulating material, the upper stack word line layers including a second upper stack material having a composition different from that of the first upper stack insulating material; An upper channel opening is formed in the upper stack to reach the lower channel opening to form an interconnected channel opening, the interconnected channel opening respectively including one of the individual lower channel openings and an individual upper channel opening in the upper channel openings, wherein a base of the upper channel opening is formed to include the capping material, the formation of the upper channel opening includes etching, and the etching also etches the capping material to vertically recess the capping material radially inside the lower stack memory cell material so that the lower channel opening is not filled; An upper stack memory cell material is formed across a base of an individual upper channel opening in the upper channel openings and along sidewalls of the individual upper channel openings; A charge blocking material of the upper stack memory cell material across an individual base in the bases of the individual upper channel openings is removed; After the removal of the portion of the upper stack memory cell material, the sacrificial capping material is removed from the interconnected channel opening; After the removal of the sacrificial capping material, a charge storage material, an insulating charge transfer material, and a transistor channel material are formed in the interconnected channel opening vertically along vertically alternating layers in the upper stack, wherein the charge storage material is formed between the transistor channel material and a control gate region, the insulating charge transfer material is formed between the transistor channel material and the charge storage material, and the charge blocking material is formed between the charge storage material and an individual one of the control gate regions; And After the transistor channel material is formed, the upper stack second material and the lower stack second material of the word line layer are replaced with a control gate material, the control gate material having ends corresponding to the control gate regions of individual memory cells.

20. A method of forming a vertically extending string array of memory cells, comprising: Forming a lower stack including vertically alternating insulating layers and word line layers, the lower stack insulating layers including an insulating lower stack first material, the lower stack word line layers including a lower stack second material having a composition different from that of the lower stack first material, lower channel openings being in the lower stack; Forming at least one of (a): a lower stack charge blocking material in an individual lower channel opening in the lower channel openings and across a base of the individual lower channel opening and along sidewalls of the individual lower channel opening, or (b): a lower stack charge storage material in the individual lower channel opening and across the base of the individual lower channel opening and along sidewalls of the individual lower channel opening; Removing at least one of (a) and (b) across an individual base in the bases of the individual lower channel openings; After removing the portion of at least one of (a) and (b), filling a remaining volume of the lower channel opening with a sacrificial capping material; An upper stack is formed over the lower stack, the upper stack including vertically alternating insulating layers and word line layers, the upper stack insulating layers including a first upper stack insulating material and the upper stack word line layers including a second upper stack material having a composition different from that of the first upper stack material; Upper channel openings are formed in the upper stack to reach the sacrificial capping material in the respective lower channel openings to form interconnected channel openings, the interconnected channel openings each including one of the respective lower channel openings and a respective upper channel opening in the upper channel openings, wherein a base of the upper channel openings is formed to include the capping material, the forming of the upper channel openings including etching that also etches the capping material to recess the capping material vertically radially inward of the lower stack memory cell material such that the lower channel openings are not filled; Form at least one of the following: (c) an upper stack charge blocking material in a respective upper channel opening of the upper channel openings, across a base of the respective upper channel opening, and along sidewalls of the respective upper channel opening, or (d) an upper stack charge storage material in the respective upper channel opening, across a base of the respective upper channel opening, and along sidewalls of the respective upper channel opening; Remove the at least one of (c) and (d) across a respective base in the base of the respective upper channel openings; After the removing of the at least one of (c) and (d), remove the sacrificial capping material from the interconnected channel openings; After removing the sacrificial capping material, a charge storage material, an insulating charge transfer material, and a transistor channel material are formed vertically in the interconnected channel openings along vertically alternating layers in the upper stack, wherein the charge storage material is formed between the transistor channel material and a control gate region, the insulating charge transfer material is formed between the transistor channel material and the charge storage material, and the charge blocking material is formed between the charge storage material and respective ones of the control gate regions; and After forming the transistor channel material, replace the second upper stack material of the word line layer and the second lower stack material with a control gate material having an end corresponding to the control gate region of the respective memory cell.

21. The method of claim 20, wherein at least one of the forming (a) or (b) forms (a).

22. The method of claim 20, wherein at least one of the forming (a) or (b) forms (b).

23. The method of claim 20, wherein at least one of the forming (a) or (b) forms (a) and (b).

24. The method of claim 20, wherein at least one of the forming (c) or (d) forms (c).

25. The method of claim 20, wherein at least one of the forming (c) or (d) forms (d).

26. The method according to claim 20, wherein at least one of said forming (c) or (d) is forming (c) and (d).

Images