Multi-stage logic built-in self-test observation scanning technology

Abstract

A circuit includes a scan chain including scan cells and one or more observation scan chains. The scan chain includes scan units. The one or more observation scan chains include observation scan units. Testing the circuit includes a scan capture phase and an observation scan phase. During a scan capture phase, the scan unit and the observation scan unit alternately operate in a shift mode and a capture mode. During an observation scan phase, the scan unit operates in a shift mode and the observation scan unit operates in a shift observation mode.

Description

Technical Field

[0001] The disclosed technology relates to the field of circuit testing. Various embodiments of the disclosed technology may be particularly applicable to improving test coverage and reducing test application time. Background Art

[0002] Since its inception nearly five decades ago, scan has become one of the most influential and industry-proven structured design for test (DFT) techniques. It allows direct access to the storage elements of a circuit under test (CUT) by forming a shift register using the storage elements of the CUT in test mode. An automatic test equipment (ATE) or other test vector source provides serial input to the scan chain, and then the same ATE or a test response compressor captures the test responses leaving the scan chain through the serial output of the scan chain. Since all scan cells are typically controlled by a single scan enable signal, the scan chains are functionally indistinguishable, that is, they either shift data in and out or capture test responses. Therefore, the high controllability and observability of internal nodes make it possible to automatically generate high-quality test vectors and debug the detected defects. In addition, the simple structure of the scan chain enables it to be automatically stitched and inserted with the support of electronic design automation (EDA) tools.

[0003] With the firm establishment of the scan-based test paradigm, several more advanced DFT techniques have also been proposed. Notably, many logic built-in self-test (LBIST) schemes use scan as their operational baseline to achieve high-quality testing with a limited amount of test data. Typically, these solutions include a pseudo-random pattern generator (PRP) that feeds the scan chain and a multiple-input signature register (MISR) that compresses the shifted-out responses. The same rule applies to test data compression, in which case the PRPG is usually replaced by an on-chip test data decompressor.

[0004] The disadvantages of scan-based testing are mainly related to the fact that all scan chains are filled with test vectors before the application of test vectors. Therefore, the vast majority of the test time is spent on shifting test data. Consider a design with a 100-cell long scan chain. Applying 10,000 double-capture test vectors will require 1,000,000 shift cycles and 20,000 capture cycles. Thus, the percentage of cycles actually used for testing (applying test stimuli and capturing test responses) is as low as 2%. In terms of test time, the result is even worse because the scan shift frequency is typically much lower than the frequency of the capture (functional) mode. In logic BIST, the test time efficiency can be even lower. A typical scan shift frequency is in the tens of megahertz, while the functional clock frequency can be as high as several gigahertz. Therefore, 99.99% of the test time can be spent on scan shifting.

[0005] The increasing electronics in vehicles enable advanced safety functions, new information and entertainment services, and higher energy efficiency. Integrated circuits in the automotive electronics market must meet strict quality and reliability requirements, which are mainly driven by safety standards such as ISO26262 and Automotive Safety Integrity Level (ASIL) objectives. ISO 26262 compliance requires more advanced test solutions. In particular, for integrated circuits to reach the necessary reliability level, the LBIST function should be able to address the challenges posed by automotive parts and support multiple on-site test requirements, including the ability to run periodic tests during functional operation. Due to strict limitations on power-on or idle periods, these periodic tests must be completed in a short time. Therefore, it is beneficial to develop test techniques that can shorten the test application time without having an adverse impact on the fault coverage. One of the main potential factors leading to low fault coverage or high vector counts is the unknown state (X) captured by scan cells. For safety-critical devices that must perform self-testing during system operation, it is desirable to prevent all X bits from reaching the test response compressor. Summary of the Invention

[0006] Aspects of the disclosed technology relate to multi-stage observation scan techniques. In one aspect, there is a circuit including: a scan chain including scan cells configured to operate in a shift mode or a capture mode based on a scan enable signal, the parallel outputs of the scan cells being coupled to functional circuitry of the circuit; one or more observation scan chains including observation scan cells configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal and an observation scan enable signal, the outputs of the observation scan cells not being coupled to the functional circuitry of the circuit; and a test controller including circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuit, the test including a scan capture phase and an observation scan phase, during the scan capture phase, the scan cells and the observation scan cells alternately operate in the shift mode and the capture mode, and during the observation scan phase, the scan cells operate in the shift mode and the observation scan cells operate in the shift observation mode.

[0007] The number of test vectors in the observation scan capture phase can be less than or equal to the number of test vectors in the scan phase.

[0008] The circuit may further include: a pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains; and a test compressor configured to compress test responses shifted out from the scan chain and the one or more observation scan chains.

[0009] Each observation scan cell may include: a state element; and a selection and combination circuit including: a combination circuit configured to combine signals from the serial input port of each observation scan cell and signals from the parallel input port of each observation scan cell to generate an observation scan signal; and a selection circuit configured to select, based on the scan enable signal and the observation scan enable signal, an input signal for the state element from the signals from the serial input port, the signals from the parallel input port, and the observation scan signal. The combination circuit may include an XOR gate. The state element may be a flip-flop. The selection circuit includes a 2-to-1 multiplexer and two AND gates.

[0010] The selection and combination circuit may further include: another combination circuit configured to combine signals from the parallel input port and the output signal of the state element to generate a capture-accumulation signal, wherein the selection circuit is configured to select, based on the scan enable signal and the observation scan enable signal, an input signal for the state element from the signals from the serial input port, the signals from the parallel input port, the observation scan signal, and the capture-accumulation signal.

[0011] In another aspect, there is one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method including: creating the above-mentioned circuit in a circuit design.

[0012] In yet another aspect, there is also a method including: testing a circuit, where the circuit includes a scan chain and one or more observation scan chains, the scan chain includes scan cells, the one or more observation scan chains include observation scan cells, and where the testing includes a scan capture phase and an observation scan phase, during the scan capture phase, the scan cells and the observation scan cells alternately operate in a shift mode and a capture mode, and during the observation scan phase, the scan cells operate in a shift mode and the observation scan cells operate in a shift-observation mode.

[0013] The appended independent claims and dependent claims set forth certain inventive aspects. The features in the dependent claims may be appropriately combined with the features in the independent claims and the features in other dependent claims, not merely as explicitly listed in the claims.

[0014] Certain objects and advantages of various inventive aspects have been described above herein. Of course, it should be understood that not all of these objects or advantages may be achieved with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or implemented in a manner that achieves or optimizes one advantage or a group of advantages taught herein, without necessarily achieving other objectives or advantages taught or implied herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 An example test architecture that may be implemented according to various embodiments of the disclosed technology is shown.

[0016] Figure 2 An example of a conventional scan cell is shown.

[0017] Figure 3 An example of an observation scan cell that may be implemented according to various embodiments of the disclosed technology is shown.

[0018] Figure 4 Shows a summary of Figure 3 a table of four operating modes in which the observation scan cell in may operate and the associated settings for two control signals.

[0019] Figure 5 Shows how the X bits captured by a conventional scan cell when using an observation scan system can corrupt the observation scan cell.

[0020] Figure 6Shows a multi - stage observation scan scheme that can be employed in various embodiments of the disclosed technology to reduce the impact of X bits.

[0021] Figure 7A Shows a table displaying the characteristics of four industrial designs and the X - state injection and the resulting corruption of the observation scan chain under a single - phase observation scan scheme.

[0022] Figure 7B Shows a display for Figure 7A a table of the number of test vectors required to achieve 90% test coverage for the four industrial designs shown in

[0023] Figure 8 Shows an example block diagram of an observation scan unit that can be implemented in various embodiments of the disclosed technology.

[0024] Figure 9 Shows an example block diagram of another observation scan unit that can be implemented in various embodiments of the disclosed technology.

[0025] Figure 10 Shows a programmable computer system that can employ various embodiments of the disclosed technology. Detailed Description

[0026] General Considerations

[0027] Aspects of the disclosed technology relate to multi - stage observation scan techniques. In the following description, for purposes of explanation, numerous details are set forth. However, one of ordinary skill in the art will recognize that the disclosed technology can be practiced without these specific details. In other instances, well - known features are not described in detail to avoid obscuring the technology of the disclosure.

[0028] Certain techniques described herein can be implemented by software instructions stored on a computer - readable medium, software instructions executed on a computer, or some combination of both. For example, certain disclosed techniques can be implemented as part of an electronic design automation (EDA) tool. These methods can be executed on a single computer or on networked computers.

[0029] Although, for convenience of presentation, the operations of the disclosed methods are described in a particular order of precedence, it should be understood that this description covers rearrangements, unless the specific language set forth below requires a particular order. For example, in some cases, operations described in sequence can be rearranged or performed concurrently. In addition, for the sake of brevity, the flowcharts and block diagrams disclosed generally do not show the various ways in which the particular methods can be used in combination with other methods.

[0030] A detailed description of a method or apparatus sometimes uses terms such as "combine", "generate", and "operate" to describe the function / structure of the disclosed method or apparatus. Such terms are high-level abstract concepts. The actual operations or function / structures corresponding to these terms will vary according to the specific implementation, and those of ordinary skill in the art can easily identify them.

[0031] As used in this disclosure, the singular forms "a", "an", and "the" include plural forms unless the context clearly dictates otherwise. Additionally, the term "comprising" means "including". Also, unless the context otherwise provides, the term "coupled" means an electrical or electromagnetic connection or link, including a direct connection or direct link, as well as an indirect connection or indirect link through one or more intermediate elements that do not affect the intended operation of the circuit.

[0032] Furthermore, as used herein, the term "design" is intended to encompass data that describes an entire integrated circuit device. However, the term is also intended to encompass smaller data sets that describe one or more components (e.g., a portion of an integrated circuit device) of the entire device.

[0033] Test design, scan-based testing, test compression, logic BIST, and test points

[0034] The reduction of feature sizes increases the probability that integrated circuit manufacturing defects will cause chip failures. Very small defects may cause transistors or interconnects to malfunction. Even a single malfunctioning transistor or wire can cause the entire chip to malfunction. However, manufacturing defects are inevitable whether the manufacturing process is in the prototype stage or in mass production. Therefore, it is necessary to test the chips during the manufacturing process. Diagnosing faulty chips is also required to improve and maintain manufacturing yield.

[0035] Testing generally involves applying a set of test stimuli (test vectors) to the circuit under test and then analyzing the response generated by the circuit under test. Functional testing attempts to verify whether the circuit under test operates according to its functional specifications, while structural testing attempts to determine whether the circuit under test has been correctly assembled from a number of low-level building blocks as specified in the structural netlist, and whether these low-level building blocks and their wiring connections have been manufactured without defects. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should operate properly. Structural testing is widely adopted at least in part because it allows test (test vector) generation to focus on a relatively small number of relatively simple circuit elements, rather than having to deal with the exponentially exploding variety of functional states and state transitions.

[0036] To develop and apply test vectors more easily, certain testability features are added to the circuit design, which is called test design or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan test scheme, all or most of the internal sequential state elements (latches, flip-flops, etc.) in the circuit design can be controlled and observed through a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form a scan chain - a serial shift register for shifting in test vectors and shifting out test responses. Scan cells can operate according to their original functional purpose (functional / task mode) or be scanned as cells in the scan chain (scan mode). A widely used type of scan cell includes an edge-triggered flip-flop with a bidirectional multiplexer for data input. The bidirectional multiplexer is usually controlled by a single control signal called scan_enable, which selects the input signal for the scan cell from either the scan signal input port or the system signal input port. The scan signal input port is usually connected to the output of another scan cell, while the system signal input port is connected to the functional logic. Scan cells can serve as both control points and observation points. Control points can be used to set specific logic values at certain locations in the circuit under test, thereby activating faults and propagating error values to the observation points. Scan testing allows the test equipment to access deeply embedded gates through the primary input / output and / or certain physical test points and eliminates the need for complex state transition sequences when trying to control or observe what is happening to certain internal circuit elements.

[0037] Test vectors for scan testing are usually generated through an automatic test vector generation (ATPG) process. ATPG typically focuses on a set of faults derived from a gate-level fault model. Defects are the imperfections that occur during the manufacturing process of the device. A fault model is a description of how the defect changes the design behavior. In other words, a defect is a flaw or physical defect that may cause a fault. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. Fault activation establishes a signal value opposite to the value generated by the fault at the fault site. Fault propagation forwards the fault effect by sensitizing the path from the fault site to a scan cell or the primary output. If the test response value captured by the scan cell or the primary output is different from the expected value, it indicates that the test vector has detected the fault at the site. The goal of ATPG is to find a test vector that, when applied to the circuit, enables the tester to distinguish the correct circuit behavior from the faulty circuit behavior caused by one or more specific faults. The effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of vectors generated (test vector count), and the fault coverage and the number of generated vectors should be proportional to the test application time. Here, the fault coverage is defined as the ratio of the number of detected faults to the total number of faults.

[0038] The most commonly used fault model in practice is the single stuck - at fault model. In this model, a signal line in the circuit is assumed to be stuck at a fixed logic value, independent of the circuit inputs. The stuck - at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause the circuit to malfunction based on the circuit's timing. They are caused by the finite rise and fall time periods of signals in gates and the propagation delays of the interconnections between gates. Transition faults are adopted because of their simplicity in modeling point defects that affect the delay at the input or output of a gate. In scan - based testing, transition faults are associated with an extra delay sufficient to make the delay of any path through the fault site exceed the clock period.

[0039] During the circuit design and manufacturing process, manufacturing tests screen out defective chips (dies). However, the tests themselves do not identify the reasons for the unacceptable low or fluctuating yield that is observable. Physical failure analysis (PFA) can examine the faulty chips to locate one or more positions of the defects and find the root cause. The process typically involves etching away some layers and then imaging the silicon surface using a scanning electron microscope or a focused ion beam system. This PFA process is labor - intensive and time - consuming. To facilitate the PFA process, diagnostic methods are usually employed to narrow down the possible locations of the one or more defects based on the analysis of the fault log (fault file, failure file). The fault log usually contains the time (e.g., test cycle) when the test failed, the location (e.g., on what tester channel), and the manner (e.g., at what logic value), as well as which test vectors produce the expected test response. The layout information of the circuit design can also be used to further reduce the number of defect suspects.

[0040] Test application in chip manufacturing testing is usually performed by an automatic test equipment (ATE) (a type of tester). Scan - based testing consumes a large amount of storage space and test time of the ATE. The data volume increases with the increase in the number of logic gates on the chip, as does the number of scan cells. However, practical considerations and ATE specifications often limit the number of pins available for scan input / output and the maximum scan frequency. Reducing the amount of test data that needs to be loaded into the ATE and ultimately into the circuit under test is highly desirable. Fortunately, test vectors can be compressed, mainly because usually only 1% - 5% of the test vector bits are significant bits (bits of interest), while the rest are non - significant bits (don't - care bits). Non - significant bits can take any value and have no impact on the fault coverage. Test compression can also take advantage of the fact that test cubes are often highly correlated. A test cube is a deterministic test vector in which the don't - care bits are not filled by the ATPG. The correlation exists because the faults in the circuit are structurally related.

[0041] Various test compression techniques have been developed. Generally, additional on-chip hardware is inserted before and after the scan chain. The hardware added before the scan chain (the decompressor) is configured to decompress the test stimuli from the ATE, while the hardware added after the scan chain (the compressor) is configured to compress the test responses captured by the scan chain. The decompressor expands the data from n tester channels to fill a scan chain larger than n. The increase in the number of scan chains shortens each scan chain, thereby reducing the number of clock cycles required to shift in each test vector. Thus, for a given test data bandwidth, test compression can not only reduce the amount of data stored on the tester, but also shorten the test time.

[0042] Embedded deterministic testing (EDT) is an example of a test compression technique. The EDT-based compression technique consists of two complementary parts: the hardware embedded on the chip and the deterministic ATPG software that uses the embedded hardware to generate compressed vectors. The EDT hardware has a continuous flow decompressor. The EDT compression of test cubes is performed by treating the external test data as boolean variables. The scan cells are conceptually filled with symbolic expressions that are linear functions of the input variables injected into the decompressor. In the case where the decompressor includes a ring generator and an associated phase shifter, a set of linear equations corresponding to the scan cells whose values are specified can be used. The compressed vectors can be determined by solving the system of equations. If the compressed vectors thus determined are scanned into the decompressor, the bits specified by the ATPG will be generated accordingly. The unspecified bits will be set to pseudo-random values based on the decompressor architecture. For more details on EDT-based compression and decompression, see: J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. CAD, vol. 23, pp. 776 - 792, May 2004, and U.S. Patents 6,327,687; 6,353,842; 6,539,409; 6,543,020; 6,557,129; 6,684,358; 6,708,192; 6,829,740; 6,874,109; 7,093,175; 7,111,209; 7,260,591; 7,263,641; 7,478,296; 7,493,540; 7,500,163; 7,506,232; 7,509,546; 7,523,372; 7,653,851, all of which are incorporated herein by reference.

[0043] Logic Built-In Self-Test (Logic BIST) is a DFT technique that allows a circuit to self-test using embedded test logic without an external tester. Classic Logic BIST applications include detecting infant mortality defects during burn-in testing, enabling the use of low-cost and / or low-speed testers that only provide power and clock signals, and performing in-system self-testing in the aerospace / defense, automotive, telecommunications, and healthcare industries to improve system reliability. A typical Logic BIST system includes a test vector generator for automatically generating test vectors, a test response analyzer (compressor) for compressing test responses into signatures, and a Logic BIST controller for coordinating BIST operations and providing pass / fail indications. A pseudo-random vector generator (PRPG), a commonly used test vector generator, can be constructed from a linear feedback shift register (LFSR) or a cellular automaton. To increase fault coverage, a weighted LFSR can be employed. Another approach is to combine random test vectors with deterministic vectors in some way, as the BIST logic can be used to process compressed test vectors that are generated deterministically and stored on-chip.

[0044] All of the above processes, including design-for-test insertion, test vector generation, test compression, and test point insertion, are typically done by various electronic design automation tools, such as the Tessent family of software tools from Siemens Industry Software in Plano, Texas.

[0045] Observation scan architecture

[0046] Figure 1 An example test architecture 100 is shown that can be implemented in accordance with various embodiments of the disclosed technology. Test architecture 100 includes a scan chain 110, one or more observation scan chains 150, and a test controller 160. Scan chain 110 can be composed of conventional scan cells. The conventional scan cells can be configured to operate in a shift mode or a capture mode based on a scan enable signal generated by test controller 160. Figure 2 An example of a conventional scan cell 200 is shown. Scan cell 200 includes a state element 210 and a bidirectional multiplexer 220. State element 210 can be implemented using edge-triggered flip-flops. Bidirectional multiplexer 220 selects a signal from either the serial input port 230 of scan cell 200 or the parallel input port 240 of scan cell 200 as the data input signal for state element 210. This selection is based on a scan enable signal provided from the scan enable port 250 of scan cell 200. Serial input port 230 can be coupled to another scan cell in the same scan chain as scan cell 200 (e.g., Figure 1the output of one of the scan chains 110 in [description], and the parallel input port 240 may be coupled to the functional circuit 270.

[0047] When the scan enable signal 250 selects the serial input port 230 as the data input signal for the state element 210, the scan unit 200 operates in the shift mode; when the scan enable signal 250 selects the parallel input port 240 as the data input signal for the state element 210, the scan unit 200 operates in the capture mode. The scan unit 200 taps into two outputs: a serial output 260, which may be coupled to the serial input port of the next scan unit in the scan chain; and a parallel output 280, which may be coupled to the functional circuit 270. In this setup, even in the shift mode, the data bits stored in the state element 110 are continuously applied to the functional circuit 270.

[0048] Return reference Figure 1 , one or more observation scan chains 150 may be composed of observation scan units. The observation scan units may be configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal used by the scan chain 120 and another control signal called the observation scan enable signal. The observation scan enable signal may also be generated by the test controller 160. The test controller 160 may use a counter to facilitate the generation of the observation scan enable signal based on the scan enable signal. Figure 3 An example of an observation scan unit 300 is shown, which may be implemented according to various embodiments of the disclosed technology. The observation scan unit 300 includes a state element 310 and a selection and combination circuit 320. The state element 310 may be implemented using edge-triggered flip-flops. The selection and combination circuit 320 includes a combination circuit 321 and a selection circuit 325. The combination circuit 321 is configured to combine the signal “s” from the serial input port 330 of the observation scan unit 300 with the signal “d” from the parallel input port 340 of the observation scan unit 300 to generate the signal “s + d”. The serial input port 330 may be coupled to the output of another scan unit (e.g., Figure 1 one of the one or more observation scan chains 150 in [description]), and the parallel input port 340 may be coupled to the functional circuit 390.

[0049] The selection and combination circuit 320 may further include another combinational circuit 323 configured to combine the signal "d" from the parallel input port 340 with the signal "Q" from the output 370 of the state element 310 to generate the signal "d + Q". If the selection and combination circuit 320 does not have the combinational circuit 323, the selection circuit 325 is configured to select the input signal of the state element 310 from the signal "s", the signal "d", and the signal "s + d". If there is the combinational circuit 323, the signal "s + Q" can also be a fourth signal that can be selected by the selection circuit 325. This selection is based on two control signals: the scan enable signal from the scan enable port 360 of the observation scan unit 300 and the observation scan enable signal from the observation scan enable port of the observation scan unit 300. It should be noted that although the selection circuit 325 is shown receiving signals from the combinational circuit 321 and the combinational circuit 323, some parts of the selection circuit 325 can output signals to any one or both of them. An example of this will be discussed later.

[0050] Based on these two control signals, if the selection and combination circuit 320 does not have the combinational circuit 323, the observation scan unit 300 can operate in one of the above three modes (shift mode, capture mode, and shift-observation mode). Otherwise, the observation scan unit 300 can also operate in the capture-accumulation mode. Figure 4 A table is shown that summarizes the four modes in which the observation scan unit 300 can operate and the associated settings of the two control signals. For example, when the observation scan enable signal is not activated, the operation of the observation scan unit 300 is similar to that of the Figure 2 scan unit 200 in, performing a shift operation or a capture operation based on the scan enable signal during testing. Different from the scan unit 200, in either of these two operations, the data bits stored in the observation scan unit 300 are not applied to the functional circuit 390. This is because the observation scan unit 300 does not have the same parallel output as the Figure 2 scan unit 200 in to inject the stored bits. When the observation scan enable signal is activated, the observation scan unit 300 can capture the test response bits based on the scan enable signal and combine them with the stored bits (capture-accumulation) or capture the test response (shift-observation) in each shift clock cycle. Similarly, the stored bits do not affect the functional circuit 390.

[0051] Return to reference Figure 1, the test architecture 100 may further include a pseudo-random pattern generator (PRPG) 130 and a test response compressor 140. The pseudo-random pattern generator 130 is configured to generate test vectors for testing the circuit, and its output is coupled to the serial input of the scan chain 110 and one or more observation scan chains 150. The test response compressor 140 is configured to compress the test response, and its input is coupled to the serial outputs of the scan chain 110 and one or more observation scan chains 150.

[0052] The pseudo-random pattern generator 130 may be constructed by a linear feedback shift register (LFSR) or a cellular automaton. A ring generator is a linear finite state machine that can be derived by changing the canonical form (external feedback, internal feedback) of a linear feedback shift register while maintaining its transition function. The pseudo-random pattern generator 130 may include a ring generator and a phase shifter. The phase shifter may include XOR gates and may extend the limited output of the ring generator to drive a large number of scan chains 150 and one or more observation scan chains 150. The test decompressor used in embedded deterministic testing (EDT) may also be implemented using a ring generator and a phase shifter. Therefore, manufacturing test and in-system test can share the same hardware to reduce the test circuit overhead. The pseudo-random pattern generator 130 may be configured as a test decompressor during deterministic testing immediately after chip manufacturing is completed, and then reconfigured as a pseudo-random pattern generator for in-system testing after the chip is installed in a system (e.g., an automobile).

[0053] The test response compressor 140 may include a temporal test response compression circuit, such as a multiple input signature register (MISR). The test response compressor 140 may further include a spatial test response compression circuit, such as one or more XOR gate networks. The test response compressor 140 may further include an X masking circuit configured to mask the X bits in the test response.

[0054] The test architecture 100 can be utilized to shorten the test application time by configuring one or more observation scan chains 150 to operate in a shift observation mode test while the scan chain 110 performs a normal shift operation. The varying contents of the scan cells in the scan chain 110 become the excitation for the feed circuit in each clock cycle, while the observation scan cells in one or more observation scan chains 150 capture and accumulate the test response in each clock cycle. By allowing the scan chain 110 to capture the test response after the shift operation loads the test vector, the test architecture 100 can also retain the benefits of the traditional shift-by-shift test method.

[0055] To improve test coverage, appropriate test point locations can be determined by searching internal lines of propagation paths that have low observability but are preferred for a large number of faults, such as observation points coupled to one or more observation scan chains 150. Additionally, control points coupled to scan chain 110 are selected by also considering whether they can improve the propagation of faults to observation points driven by per-clock tests, thereby increasing their detection probability.

[0056] X - Tolerance and Multi - Phase Observation Scans

[0057] The X state appears in circuit design due to: non - scan flip - flops, uninitialized storage elements, floating buses, bus contention, internal tri - state logic, unencapsulated analog modules, false paths, cross - domain paths, or paths with timing closure issues. The X state may cause unknown bits (X - bits) to appear in test responses, severely degrading test quality. Typically, test response compressors employ a mechanism to mask X - bits, which is called X - masking. Not all X - bits captured in scan cells are masked in subsequent manufacturing tests. Designers usually attempt to balance on - chip test logic complexity, collateral damage caused by inadvertently masking non - X - bits, resulting test coverage and test time, and test data required to control X - masking. On the other hand, in - system test setups need to control scan selection with minimal data volume without compromising high test quality. For safety - critical devices that must perform self - tests during system operation, it is usually necessary to prevent all X - bits from reaching the test response compressor. This is especially true for compressors that include multi - input signature registers, where feedback in the multi - input signature register can cause X - bits to spread rapidly, rendering the entire test useless.

[0058] The test compressor can employ an X - masking circuit to mask X - bits in test responses based on masking information stored in registers. A simple method for X - masking is to mask any scan chain that captures at least one X - bit. This may result in low fault coverage or high vector counts because many useful test response bits will also be masked. To address this problem, the X - masking circuit can be configured to mask X - bits in each shift - clock - cycle mode, thereby masking only certain bits output from the scan chain but allowing other bits to be compressed. However, both of these methods are not very effective for observation scan techniques. Any X - bit captured by a regular scan cell in a regular scan chain may propagate into the circuit during the shift operation and corrupt more observation scan units in the observation scan chain operating in shift - observe mode.

[0059] Figure 5The observation scan system 500 is used to show how the X bits captured by a conventional scan unit can corrupt the observation scan unit. The observation scan system 500 includes a conventional scan chain 511 - 514, an observation scan chain 520, a pseudo - random vector generator 530 configured to generate test vectors, and a multi - input signature register 540 as a test response compressor. During a capture operation, three scan units 521, 523, and 524 in the scan chains 511, 513, and 514 respectively capture X bits. As previously discussed, these captured X bits are continuously applied to the functional circuit through the parallel output ports of the scan units in the scan chains 511, 513, and 514 in a shift mode. Thus, these X bits may cause some X states to be captured by the observation scan units in the observation scan chain 520. Masking the observation scan chain will lose the benefits of the observation scan technique.

[0060] According to various embodiments of the disclosed technology, a multi - stage observation scan scheme can be employed to reduce the impact of X bits. Figure 6 An example of such a multi - stage observation scan scheme is shown. The multi - stage observation scan scheme may include two stages: a scan capture stage 610 and an observation scan stage 620. In the scan capture stage 610, the scan units in the conventional scan chain 630 and the observation scan units in the observation scan chain 640 alternately operate in a shift mode and a capture mode. In the shift mode, test vectors are shifted into the scan chain 630, and in the capture mode, the scan units in the scan chain 630 capture test responses. Then, the scan chain 630 switches back to the shift mode, shifts out the captured test responses, and simultaneously shifts in the next test vector. Different from the scan units in the conventional scan chain 630, the observation scan units in the observation scan chain 640 do not participate in applying test vectors to the circuit because they do not have parallel output ports. They also do not capture test responses in the shift mode. However, the observation scan units in the observation scan chain 640 can also capture test responses in the capture mode.

[0061] In the observation scan stage 620, the scan units in the conventional scan chain 630 operate in the shift mode, while the observation scan units in the observation scan chain 640 operate in a shift - observation mode. In this stage, the conventional scan chain 630 continuously applies test stimuli to the circuit, while the observation scan chain 640 continuously captures the corresponding test responses. Timing - anomalous paths are the main source of X states, so X states are rarely generated in the shift mode. Even if an observation scan unit captures an X bit, the X bit will not propagate back to the circuit to corrupt other observation scan units. Therefore, most of the outputs of the observation scan chain 640 do not need to be masked, and the observation scan stage 620 can retain the benefits of the observation scan technique. According to certain embodiments of the disclosed technology, the number of test vectors in the observation scan capture stage can be less than or equal to the number of test vectors in the scan stage.

[0062] Figure 7A A table is shown that displays the characteristics of four industrial designs and the X-state injection and resulting corruption of the observation scan chain under a single-phase observation scan scheme. Each of the four industrial designs D1, D2, D3, and D4 has approximately 1 million to 3 million gates and 1,254, 1,255, 2,502, and 528 scan chains, respectively. Among these scan chains, there are 34, 39, 74, and 7 observation scan chains, respectively. In the single-phase observation scan scheme, the regular scan chains operate alternately in the shift mode and the capture mode, while the observation scan chains operate alternately in the shift-observation mode and the capture-accumulation mode. As shown in the sixth column, a small amount of random X is injected in each of the four designs. As a result, 1% - 2.5% of the regular scan chains captured the X-bit, but 57% - 94% of the observation scan chains captured the X-bit. This indicates that the X-state has a significant adverse impact on the single-phase observation scan scheme because most of the observation scan chains have to be masked.

[0063] Figure 7B A table is shown that displays Figure 7A the number of test vectors required to achieve 90% test coverage for the four industrial designs in different test schemes and / or conditions. Column B shows the number of test vectors required under the condition of neither injecting the X-state nor using the observation scan chain. Column C shows the number of test vectors required under the condition of not injecting the X-state but using the observation scan chain. Column D calculates the ratio of column B to column C, which shows that using the observation scan chain can reduce the vector count by more than 7 times for designs other than design 4.

[0064] Column E shows the test vector count under the condition of injecting the X-state but not using the observation scan chain. Column F shows the test vector count under the condition of injecting the X-state and using the observation scan chain in a two-phase observation scan scheme. Columns G and H list the ratios of column E to column F and column B to column F, respectively. Column G shows a significant reduction in the vector count when using the two-phase observation scan scheme. This cannot be achieved when using the single-phase observation scan scheme. Even compared with the regular LBST run without the X-state, for designs D1 - D3, using the two-phase observation scan scheme can achieve a reduction in the vector count by more than 2.5 times. For design D4, compared with the regular LBIST run without any X-state, the two-phase observation scan scheme only requires an increase of approximately 15% in the vectors.

[0065] Example of an observation scan cell architecture

[0066] Figure 8 A block diagram example of an observation scan unit 800 is shown, and the observation scan unit 800 can be implemented according to various embodiments of the disclosed technology. With Figure 3Similar to the observation scan unit 300 in [reference], the observation scan unit 800 includes a status element 810 and a selection and combination circuit 820. The status element 810 can be implemented using a flip-flop. The selection and combination circuit 820 includes two logic XOR gates 830 and 840, which are respectively used as Figure 3 the combination circuit 321 and the combination circuit 323 shown in [reference]. The XOR gate 930 can generate a first signal by combining the signal from the scan input port (SI) 870 of the observation scan unit 800 with the signal from the functional circuit input port (D) 860 (also known as the parallel input port) of the observation scan unit 800. The XOR gate 840 can generate a second signal by combining the signal from the functional circuit input port (D) 860 of the observation scan unit 800 with the output signal (Q) 815 of the status element 810. The selection and combination circuit 820 further includes a four-to-one multiplexer 850, which is used as Figure 3 the selection circuit 325 shown in [reference]. The four-to-one multiplexer 850 can select the input signal of the status element 810 from the following four signals based on the two selection input signals M1 (880) and M2 (890) of the observation scan unit 800: the first signal, the second signal, the signal from the scan input port (SI) 870 of the observation scan unit 800, and the signal from the functional circuit input port (D) 860 of the observation scan unit 800. The selection input signals M1 (880) and M2 (890) can be respectively Figure 4 the scan enable signal and the observation scan enable signal in [reference].

[0067] When the signal from the scan input port (SI) 830 of the observation scan unit 800 is selected, the observation scan unit 800 operates in the normal shift mode. When the signal from the functional circuit input port (D) 840 of the observation scan unit 800 is selected, the observation scan unit 800 operates in the normal capture mode or the circuit function mode. When the first signal is selected, the observation scan unit 800 accumulates the circuit test response during the shift mode of the normal scan unit, corresponding to Figure 4 the shift observation mode shown in [reference]. When the second signal is selected, the observation scan unit 800 accumulates the circuit test response during the capture mode of the normal scan unit, corresponding to Figure 4 the capture-accumulation mode shown in [reference].

[0068] Figure 9 FIG. [reference] shows another example of a block diagram of an observation scan unit 900, which can be implemented according to various embodiments of the disclosed technology. Similar to the observation scan unit 800, the observation scan unit 900 includes a status element 910 and a selection and combination circuit 915. Similarly to the observation scan unit 800, the selection and combination circuit 915 includes two logic XOR gates 940 and 930, which are respectively used asFigure 3 the combinational circuits 321 and 323 shown in. Unlike Figure 8 the selection and combination circuit 820 in, the selection and combination circuit 915 uses two AND gates 923 and 925 and a two-to-one multiplexer 920 (instead of a single four-to-one multiplexer 850) to perform the selection function.

[0069] When the selection input signal M2 (950) is 0, the outputs of both AND gate 923 and AND gate 925 are 0. Therefore, the outputs of XOR gate 940 and XOR gate 930 will follow the signals from the scan input port (SI) 980 and the functional circuit input port (D) 970 respectively. Another selection input signal M1 (960) will determine whether the signal at the scan input port (SI) 980 or the signal at the functional circuit input port (D) 970 drives the state element 910. These two operating modes correspond to the traditional shift mode and the traditional capture mode respectively.

[0070] When the selection input signal M2 (950) is 1, the outputs of AND gate 923 and AND gate 925 are the signal from the output port (Q) 990 of the state element 910 and the signal from the functional circuit input port (D) 970 respectively. Therefore, XOR gate 940 and XOR gate 930 respectively combine the signal from the functional circuit input port (D) 970 with the signal from the scan input port (SI) 980 and the signal from the output port of the state element 910. The selection input signal M1 (960) can determine whether the previous combined signal or the latter combined signal drives the state element 910, which respectively correspond to Figure 4 the shift-observation mode and the capture-accumulation mode in.

[0071] Example computing environment

[0072] Certain embodiments of the disclosed technology related to inserting a test circuit into a design can be implemented by a computing device (such as a programmable computer) executing software instructions. Figure 10 shows an illustrative example of such a programmable computer (computing device 1001). As shown, the computing device 1001 includes a computing unit 1003, and the computing unit 1003 has a processing unit 1005 and a system memory 1007. The processing unit 1005 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 1007 can include a read-only memory (ROM) 1009 and a random access memory (RAM) 1011. Those of ordinary skill in the art can understand that both the read-only memory (ROM) 1009 and the random access memory (RAM) 1011 can store software instructions for the processing unit 1005 to execute.

[0073] The processing unit 1005 and the system memory 1007 are directly or indirectly connected to one or more peripheral devices via a bus 1013 or an alternative communication structure. For example, the processing unit 1005 or the system memory 1007 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" disk drive 1015, a removable disk drive 1017, an optical disk drive 1019, or a flash memory card 1021. The processing unit 1005 and the system memory 1007 can also be directly or indirectly connected to one or more input devices 1023 and one or more output devices 1025. The input devices 1023 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output devices 1025 can include, for example, a display, a printer, and a speaker. In various examples of the computer 1001, one or more of the peripheral devices 1015 - 1025 can be installed internally together with the computing unit 1003. Additionally, one or more of the peripheral devices 1015 - 1025 can be located outside the housing of the computing unit 1003 and connected to the bus 1013 through, for example, a Universal Serial Bus (USB) connection.

[0074] In certain embodiments, the computing unit 1003 can be directly or indirectly connected to one or more network interfaces 1027 for communicating with other devices that make up a network. The network interface 1027 converts data and control signals from the computing unit 1003 into network information according to one or more communication protocols (such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP)). In addition, the interface 1027 can also employ any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. These network interfaces and protocols are well known in the art and thus will not be discussed in detail herein.

[0075] It should be understood that the computer 1001 is illustrated only as an example and is not intended to be limiting. Various embodiments of the disclosed technology can be implemented using one or more computing devices that include Figure 10 the components of the illustrated computer 1001, or include only Figure 10 a subset of the illustrated components, or include an alternative combination of components, including Figure 10 components not shown. For example, various embodiments of the disclosed technology can be implemented using a multi - processor computer, multiple single - processor and / or multi - processor computers arranged in a network, or some combination of both.

[0076] Conclusion

[0077] Although the disclosed technology has been described with specific examples including the presently preferred modes of implementing the disclosed technology, those skilled in the art will appreciate that there are many variations and permutations of the above-described systems and techniques, and these variations and permutations fall within the spirit and scope of the disclosed technology set forth in the appended claims. For example, although two examples of the selection and combination circuitry in the scanning unit ([ Figure 3 and Figure 5 ) have been used to describe the disclosed technology, it should be understood that the various examples of the disclosed technology may be implemented using a selection and combination circuitry having a topology different from the topology shown in Figure 3 and Figure 5 .

Claims

1. A circuit, comprising: A scan chain including scan cells configured to operate in a shift mode or a capture mode based on a scan enable signal, and parallel outputs of the scan cells are coupled to functional circuitry of the circuit; One or more observation scan chains including observation scan cells configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal and an observation scan enable signal, and outputs of the observation scan cells are not coupled to the functional circuitry of the circuit; And A test controller including circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuit, the test including a scan capture phase and an observation scan phase, during which the scan cells and the observation scan cells alternately operate in the shift mode and the capture mode, and during which the scan cells operate in the shift mode and the observation scan cells operate in the shift observation mode.

2. The circuit according to claim 1, wherein, The number of test vectors in the observation scan capture phase is less than or equal to the number of test vectors in the scan phase.

3. The circuit of claim 1, further comprising: A pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains; And A test compressor configured to compress test responses shifted out of the scan chain and the one or more observation scan chains.

4. The circuit according to claim 1, wherein, Each of the observation scan cells includes: A state element; and A selection and combination circuit including: A combination circuit configured to combine signals from a serial input port of each of the observation scan cells with signals from a parallel input port of each of the observation scan cells to generate an observation scan signal, and A selection circuit configured to select an input signal of the state element from signals from the serial input port, signals from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal.

5. The circuit according to claim 4, wherein, The selection and combination circuit further includes: Another combination circuit configured to combine signals from the parallel input port with an output signal of the state element to generate a capture-accumulation signal, wherein the selection circuit is configured to select the input signal of the state element from signals from the serial input port, signals from the parallel input port, the observation scan signal, and the capture accumulation signal based on the scan enable signal and the observation scan enable signal.

6. The circuit according to claim 4, wherein, The combination circuit includes an XOR gate.

7. The circuit according to claim 4, wherein, The state element is a flip-flop.

8. The circuit according to claim 4, wherein, The selection circuit includes a 2-to-1 multiplexer and two AND gates.

9. One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: Creating a circuit in circuit design, the circuit including: A scan chain including scan cells configured to operate in a shift mode or a capture mode based on a scan enable signal, and parallel outputs of the scan cells are coupled to functional circuitry of the circuit; One or more observation scan chains, which include observation scan cells configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal and the observation scan enable signal, and the output of the observation scan cells is not coupled to the functional circuitry of the circuit; and A test controller, which includes circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuit, the test including a scan capture phase and an observation scan phase, during the scan capture phase, the scan cells and the observation scan cells alternately operate in the shift mode and the capture mode, and during the observation scan phase, the scan cells operate in the shift mode and the observation scan cells operate in the shift observation mode.

10. One or more computer-readable media as recited in claim 9, wherein, The number of test vectors in the observation scan capture phase is less than or equal to the number of test vectors in the scan phase.

11. One or more computer-readable media as recited in claim 9, wherein, The circuit further includes: A pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains; and A test compressor configured to compress test responses shifted out from the scan chain and the one or more observation scan chains.

12. The one or more computer-readable media according to claim 9, wherein, Each of the observation scan cells includes: A state element; and A selection and combination circuit, which includes: A combination circuit configured to combine signals from the serial input port of each observation scan cell and signals from the parallel input port of each observation scan cell to generate an observation scan signal, and A selection circuit configured to select an input signal for the state element from signals from the serial input port, signals from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal.

13. One or more computer-readable media as recited in claim 12, wherein, The selection and combination circuit further includes: Another combination circuit configured to combine signals from the parallel input port and the output signal of the state element to generate a capture-accumulation signal, wherein the selection circuit is configured to select an input signal for the state element from signals from the serial input port, signals from the parallel input port, the observation scan signal, and the capture accumulation signal based on the scan enable signal and the observation scan enable signal.

14. One or more computer-readable media as recited in claim 12, wherein, The combination circuit includes an XOR gate.

15. One or more computer-readable media as recited in claim 12, wherein, The state element is a flip-flop.

16. One or more computer-readable media as recited in claim 12, wherein, The selection circuit includes a 2-to-1 multiplexer and two AND gates.

17. A method, including: Testing a circuit, wherein the circuit includes a scan chain and one or more observation scan chains, the scan chain includes scan cells, and the one or more observation scan chains include observation scan cells, and wherein the test includes a scan capture phase and an observation scan phase, during the scan capture phase, the scan cells and the observation scan cells alternately operate in a shift mode and a capture mode, and during the observation scan phase, the scan cells operate in the shift mode and the observation scan cells operate in a shift observation mode.

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