Memory cell array with row direction gap between erase gate line and dummy floating gate

Abstract

A memory cell array having rows and columns of memory cells, where respective ones of the memory cells include: spaced apart source and drain regions formed in a semiconductor substrate, where a channel region extends between the source and drain regions; a floating gate over a first portion of the channel region; a select gate over a second portion of the channel region; and an erase gate over the source region. The tape region is disposed between the first plurality of columns and the second plurality of columns. For a row of memory cells, a dummy floating gate is disposed in the band region, an erase gate line electrically connects the erase gates of the memory cells in the row and in the first plurality of columns together, where the erase gate line is aligned with the dummy floating gate, and the erase gate line is aligned with the dummy floating gate. There is a row-direction gap between the erase gate line and the dummy floating gate.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Patent Application No. 18 / 104,228, filed on January 31, 2023, entitled "Memory Cell Array With Row Direction Gap Between Erase Gate Lines and Dummy Floating Gates". Technical Field

[0003] The present invention relates to non - volatile memory devices, and more particularly to improving the stability of memory cell current during read operations. Background Art

[0004] Non - volatile memory devices are well - known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four - gate memory cell configuration. Specifically, the present application's Figure 1 shows a split - gate memory cell 10 having spaced - apart source region 14 and drain region 16 formed in a silicon semiconductor substrate 12. A channel region 18 of the semiconductor substrate is defined between the source region 14 / drain region 16. A floating gate 20 is disposed over a first portion of the channel region 18 and is insulated from the first portion (and controls its conductivity) (and is partially located over the source region 14 and insulated therefrom). A control gate 22 is disposed over the floating gate 20 and is insulated therefrom. A select gate 24 is disposed over a second portion of the channel region 18 and is insulated from the second portion (and controls its conductivity). The select gate 24 is laterally adjacent to the floating gate 20 and may include an upper portion that extends upward and is over the control gate 22. An erase gate 26 is disposed over the source region 14 and is insulated therefrom, and is laterally adjacent to the floating gate 20, wherein an upper portion that extends upward and is over the floating gate 20 forms a notch 27 facing the edge of the floating gate 20. The notch 27 and the edge of the floating gate 20 may be insulated from each other by a tunnel oxide layer 28. The memory cells 10 may be arranged in pairs, as Figure 1 shown, where two memory cells 10 share a common source region 14.

[0005] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26, and / or source region 14 / drain region 16 to program the memory cell 10 (i.e., inject electrons into the floating gate 20), erase the memory cell 10 (i.e., remove electrons from the floating gate 20 through the tunnel oxide 28), and read the memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 to determine the programmed state of the floating gate 20).

[0006] Memory cell 10 can be operated digitally, where the memory cell 10 is set to one of only two possible states: a programmed state and an erased state. The memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and optionally a negative voltage to the control gate 22 to cause electrons to tunnel from the floating gate 20 to the erase gate 26 through the tunnel oxide layer 28 (putting the floating gate 20 in a more positively charged state - the erased state). The memory cell 10 can be programmed by applying a positive voltage to the control gate 22, erase gate 26, select gate 24, and source region 14 and applying a current to the drain region 16. Then, electrons will flow from the drain region 16 to the source region 14 along the channel region 18, where some of the electrons become accelerated and heated, whereby they are injected onto the floating gate 20 by hot electron injection (putting the floating gate in a more negatively charged state - the programmed state). The memory cell 10 can be read by applying a positive voltage to the select gate 24 (turning on the portion of the channel region under the select gate 24) and the drain region 16 (and optionally on the erase gate 26 and / or control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (erased), the memory cell 10 will conduct, and current will flow from the source region 14 to the drain region 16 (i.e., the memory cell 10 is sensed to be in its erased "1" state based on the sensed current). If the floating gate 20 is negatively charged (programmed), the channel region 18 under the floating gate 20 is turned off, preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on no current).

[0007] The following table provides non - limiting examples of erase, program, and read voltages:

[0008] Table 1

[0009] WL(SG) BL (Drain) Source EG CG Erase 0V 0V 0V 11.5V 0V Program 1V 1 μA 4.5V 4.5V 10.5V Read Vcc 0.6V 0V 0V Vcc

[0010] Memory cell 10 can alternatively operate in an analog manner, where the memory state of the memory cell (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can continuously change anywhere from a fully erased state (least electrons on the floating gate) to a fully programmed state (most electrons on the floating gate), or just a portion of that range. This means that the cell storage is analog, which allows for very precise and individual adjustment of each memory cell 10 in the memory cell array. Alternatively, the memory can be operated as an MLC (multi-level cell), where the MLC is configured to be programmed to one of a number of discrete values (such as 16 or 64 different values). In the case of analog or MLC programming, the programming voltage is applied only for a limited time or as a series of pulses until the desired programming state is achieved. In the case of multiple programming pulses, an intermediate read operation between the programming pulses can be used to determine whether the desired programming state has been achieved (in which case programming stops) or not (in which case programming continues).

[0011] Memory cells 10 can be arranged in an array (i.e., in rows and columns). As Figure 1 shown, each pair of memory cells 10 shares a common source region 14 and a common erase gate 26. As Figure 2 shown in the array layout of Figure 1 shown, the pairs of memory cells 10 shown can be arranged end-to-end in columns, where two adjacent pairs of memory cells can share a common drain region 16. The source regions 14 for the rows of the memory cell pairs can be formed as a continuous source line 14a of diffusion regions in the semiconductor substrate 12, which electrically connects all the source regions 14 for the rows of the memory cell pairs together. The control gates 22 for the rows of the memory cells 10 can be formed as a continuous control gate line 22a made of a conductive material (such as polysilicon), which electrically connects all the control gates 22 for the rows of the memory cells together. The select gates 24 for the rows of the memory cells 10 can be formed as a continuous select gate line 24a (which can also be referred to as a word line) made of a conductive material (such as polysilicon), which electrically connects all the select gates 24 for the rows of the memory cells together. The erase gates 26 for the rows of the memory cells 10 can be formed as a continuous erase gate line 26a made of a conductive material (such as polysilicon), which electrically connects all the erase gates 26 for the rows of the memory cells together. The floating gates 20 can be formed of a conductive material such as polysilicon.

[0012] The respective lines that need to be periodically connected to the array. Summary of the Invention

[0013] The above problems and requirements are solved by a memory cell array including a plurality of memory cells arranged in rows and columns, wherein a respective one of the memory cells includes: spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between the source and drain regions; a floating gate disposed above a first portion of the channel region and insulated therefrom; a select gate disposed above a second portion of the channel region and insulated therefrom; and an erase gate disposed above the source region and insulated therefrom. A strip region is disposed between a first plurality of columns of the memory cells and a second plurality of columns of the memory cells. For a row of the memory cells, a dummy floating gate is provided, which is disposed in the strip region, above the substrate and insulated therefrom, and is disposed between two of the memory cells in the row of the memory cells, and a first erase gate line that electrically connects the erase gates of the memory cells in the row of the memory cells and in the first plurality of columns of the memory cells together, wherein the first erase gate line is aligned with the dummy floating gate and has a first row-direction gap between the first erase gate line and the dummy floating gate.

[0014] The memory cell array includes a plurality of memory cells arranged in rows and columns, wherein a respective one of the memory cells includes: spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between the source and drain regions; a floating gate disposed above a first portion of the channel region and insulated therefrom; a select gate disposed above a second portion of the channel region and insulated therefrom; and an erase gate disposed above the source region and insulated therefrom. A strip region is disposed between a first plurality of columns of the memory cells and a second plurality of columns of the memory cells. For a first row and a second row of the memory cells, a first dummy floating gate is provided, which is disposed in the strip region, above the substrate and insulated therefrom, and is disposed between two of the memory cells in the first row of the memory cells; a second dummy floating gate is provided, which is disposed in the strip region, above the substrate and insulated therefrom, and is disposed between two of the memory cells in the second row of the memory cells; a first erase gate line that electrically connects the erase gates of the memory cells in the first row and the second row and in the first plurality of columns of the memory cells together, and the first erase gate line is aligned with the first dummy floating gate and has a first row-direction gap between the first erase gate line and the first dummy floating gate, and the first erase gate line is aligned with the second dummy floating gate and has a second row-direction gap between the first erase gate line and the second dummy floating gate.

[0015] Other objects and features of the present disclosure will become apparent by reviewing the specification, claims, and drawings. Description of the Drawings

[0016] Figure 1 is a side cross-sectional view of a pair of conventional memory cells.

[0017] Figure 2 is a layout diagram showing a conventional layout of respective lines of a memory cell array.

[0018] Figure 3 is a layout diagram showing a layout of respective lines and zones of a memory cell array.

[0019] Figure 4 is a partial layout diagram showing a layout of one of the zones in respective lines and zones of a memory cell array.

[0020] Figure 5 is a partial layout diagram showing a row direction overlap between one of the erase gate lines and one of the dummy floating gates in the erase gate lines.

[0021] Figure 6 is a partial layout diagram showing a row direction gap between one of the erase gate lines and one of the dummy floating gates in the erase gate lines.

[0022] Figure 7 is a layout diagram showing a layout of respective lines and zones of a memory cell array, having a row direction gap between the erase gate line and the dummy memory cell.

[0023] Figure 8 is a side cross-sectional view of an alternative example of a memory cell.

[0024] Figure 9 shows Figure 8 a layout diagram of respective lines and zones of a memory cell array of, having a row direction gap between the erase gate line and the dummy memory cell. Detailed Description

[0025] Periodic zones may be incorporated into the memory cell array to provide space and access to connect to respective lines of the memory cell array. Figure 3 shows a memory array similar to Figure 1 a memory cell 10 of, where like element numbers refer to like elements. Figure 3 The memory array of includes a first zone 30, a second zone 32, and a third zone 34. Each zone is an area between two columns in a column 36 of the memory cell 10. In Figure 3In the example, three columns 36 of memory cells 10 are shown disposed between respective bands, however, the number of columns 36 of memory cells 10 between respective bands may vary.

[0026] Bands 30, 32, 34 provide regions between columns of memory cells 36 in which vertical contacts extending downward from higher level metal layers (in which signal lines may be formed) that are in electrical contact with various lines of the memory array may be formed. For example, in the first band 30, a vertical contact 38 extends downward from an upper metal layer and is in electrical contact with a select gate line (word line) 24a, and a vertical contact 40 extends downward from an upper metal layer and is in electrical contact with a source line 14a. In Figure 3 the example, each source line 14a electrically connects the source regions 14 of two rows of memory cells together (and extends across bands 30, 32, 34). Each erase gate line 26a electrically connects the erase gates of memory cells in two adjacent rows of memory cells together. To provide access to the source line 14a, a portion of the erase gate line 26a at the center of the first band 30 is removed (e.g., by etching) such that the vertical contact 40 can be in electrical contact with the source line 14a without being in electrical contact with the erase gate line 26a (i.e., the vertical contact is electrically connected to the source line and is disposed in the first band 30 and between the erase gate lines 26a). In the second band 32, a vertical contact 40 extends downward from an upper metal layer and is in electrical contact with a source line 14a. To provide access to the source line 14a, a portion of the erase gate line 26a at the center of the second band 32 is removed (e.g., by etching) such that the vertical contact 40 can be in electrical contact with the source line 14a without being in electrical contact with the erase gate line 26a (i.e., the vertical contact is electrically connected to the source line and is disposed in the first band 30 and between the erase gate lines 26a). In the third band 34, a vertical contact 44 extends downward from an upper metal layer and is in electrical contact with a tab portion 22b (i.e., widened portion) of a control gate line 22a, and a vertical contact 40 extends downward from an upper metal layer and is in electrical contact with a source line 14a. To provide access to the source line 14a, a portion of the erase gate line 26a at the center of the third band 34 is removed (e.g., by etching) such that the vertical contact 40 can be in electrical contact with the source line 14a without being in electrical contact with the erase gate line 26a (i.e., the vertical contact is electrically connected to the source line and is disposed in the first band 30 and between the erase gate lines 26a). Because the diffusion regions in the semiconductor substrate 12 (which forms the source line 14a) have less conductivity than the metal lines to which the source line is connected, the vertical contacts 40 of the source line 14a may be included in all three bands 30, 32, 34.

[0027] For ease of fabrication and to maintain the polysilicon density in stripes 30, 32, 34 relative to the columns of memory cells, dummy floating gates 20a may be formed in stripes 30, 32, 34, as Figure 3 shown. The dummy floating gates 20a may be formed in portions where the control gate lines 22a in stripes 30, 32, 34 overlap underlying diffusion regions in the semiconductor substrate 12, and may be made of the same conductive material (such as polysilicon) as the floating gates 20 and have the same overall configuration as the floating gates 20 (i.e., disposed above and insulated from the substrate). For any given stripe and row of memory cells, there may be a dummy floating gate 20a disposed in the stripe and between two memory cells 10 in that row of memory cells. As part of the process of forming the floating gates 20, forming the dummy floating gates 20a simplifies fabrication and increases reliability and yield by making the density of the conductive material in stripes 30, 32, 34 closer to the density of the memory cell columns.

[0028] The inventors have found that the proximity of the erase gate lines 26a to the dummy floating gates 20a can cause capacitive coupling between them, which in turn may interfere with the programmed states of adjacent memory cells. For example, as Figure 4 shown, a memory cell 10n having a floating gate 20n is adjacent to a stripe 30 having a dummy floating gate 20a, which in turn is adjacent to a memory cell 10m having a floating gate 20m. The erase gate line 26a extends partially into the stripe 30 such that the erase gate line 26a partially overlaps the dummy gate 20a in the row direction at both ends of the dummy floating gate 20a (referred to herein as row direction overlap, RDO), as Figures 4 to 5As shown. As used herein, row direction overlap RDO relates to how each erase gate line 26a aligns with a corresponding dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one of the two vertical lines aligning with the edge of the dummy floating gate 20a and the other of the two vertical lines aligning with the edge of an adjacent erase gate line 26a, indicating the overlap of these two features in the row direction (even though these elements are separated from each other in the column direction and thus there is no actual physical overlap). The row direction overlap RDO results in excessive capacitive coupling between the dummy floating gate 20a and the erase gate line 26a, such that erasing or programming the memory cell 10n may interfere with the programmed state of the memory cell 10m. For example, erasing the floating gate 20n of the memory cell 10n may at least partially erase the dummy floating gate 20a, which in turn may at least partially erase the floating gate 20m of the memory cell 10m and / or cause data retention leakage in both the floating gates 20n and 20m. Additionally, programming the floating gate 20n may partially program the dummy floating gate 20a, which in turn may cause the partially programmed dummy floating gate 20a to interfere with the programmed state of the floating gate 20m of the memory cell 10m.

[0029] The inventors have determined that reconfiguring the alignment of the erase gate line 26a near the strip of the corresponding dummy floating gate 20a to replace the row direction overlap RDO between the dummy floating gate 20a and the corresponding erase gate line 26a with a row direction gap RDG between the dummy floating gate 20a and the erase gate line 26a can result in a significant reduction in the unintended change in the programmed state of the dummy floating gate 22a and thus a significant reduction in the interference with the programmed state of the floating gates 20 of nearby memory cells. As used herein, the row direction gap RDG relates to how each erase gate line 26a aligns with a corresponding dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one of the two vertical lines aligning with the edge of the dummy floating gate 20a and the other of the two vertical lines aligning with the edge of the corresponding adjacent erase gate line 26a, indicating the gap between these two features in the row direction, as Figure 6 and Figure 7 shown. For any given dummy floating gate 20a in a row of the rows of the memory cells 10, there is a first row direction gap RDG with respect to the first erase gate line 26a (e.g., to the left or right of the dummy erase gate 20a), and a second row direction gap RDG with respect to the second erase gate line 26a (e.g., to the other of the left or right of the dummy erase gate 20a), as Figure 6 and Figure 7As shown. The first row-direction gap and the second row-direction gap on either side of the dummy floating gate 20a can be, but need not be, of the same size. In the case where the edge is not linear, the vertical line will intersect the farthest point at which the corresponding dummy floating gate 20a extends in the row direction towards the corresponding adjacent memory cell column, and the corresponding erase gate line 26a extends in the row direction towards the center of the zone. Aligning the erase gate line 26a with the dummy floating gate 20a having a row gap RDG means that there is no row-direction overlap RDO in this alignment (i.e., the row-direction gap RDG and the row-direction overlap RDO are mutually exclusive).

[0030] It has been further determined that the minimum value of the row-direction gap RDG for achieving improved performance can be associated with the thickness of the tunnel oxide layer 28, because it has been found that the larger the tunnel oxide, the larger the row-direction gap should be. Specifically, the thickness of the tunnel oxide layer 28 can be selected according to the erase operation voltage applied to the erase gate, and thus indicates the potential capacitive coupling between the erase gate line 26a and the dummy floating gate 20a. The electric field near the tunnel oxide can be expressed as:

[0031]

[0032] where V is the voltage across the tunnel oxide, and t ox is the tunnel oxide thickness. The Fowler Nordheim tunneling current density J can be expressed as:

[0033]

[0034] where A, B are constants, and V is the erase voltage applied to the erase gate line during the erase operation. In order to reduce the Fowler Nordheim current density between the dummy floating gate 20a and the erase gate line 26a to a low or insignificant amount, the row-direction gap RDG can be sufficient to reduce the likelihood of tunneling between the dummy floating gate 20a and the erase gate line 26a. It has been determined that providing a row-direction gap RDG that is at least twice the thickness of the tunnel oxide layer 28 ensures that any Fowler Nordheim current density between the dummy floating gate 20a and the erase gate line 26a is a low or insignificant amount. Making the row-direction gap RDG at least twice the thickness of the tunnel oxide layer 28 also ensures that the desired and effective row-direction gap RDG is maintained when the size of the device is scaled down.

[0035] A row-direction gap RDG that is at least twice the thickness of the tunnel oxide layer 28 can be implemented in a non-volatile memory cell configuration that deviates from Figure 1 the non-volatile memory cell configuration. Specifically, Figure 8 is shown similar toFigure 1 A memory cell of a memory cell, but omitting the control gate. Figure 9 shows Figure 8 A memory cell array of, having a row direction gap RDG between the erase gate line 26a and the dummy memory cell 20a.

[0036] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but covers any and all variations within the scope of any claims. For example, the references to the present invention herein are not intended to limit the scope of any claim or claim term, but only to refer to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values described above are merely exemplary and should not be considered as limiting the claims. Additionally, as is apparent from the claims and the specification, unless otherwise stated, not all method steps may need to be performed in the specific order shown or required.

Claims

1. A memory cell array, the memory cell array comprising: A plurality of memory cells, the plurality of memory cells being arranged in rows and columns, wherein a respective one of the memory cells includes: source and drain regions spaced apart and formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above a first portion of the channel region and insulated from the first portion; a select gate disposed above a second portion of the channel region and insulated from the second portion; and an erase gate disposed above the source region and insulated from the source region; A strip region, the strip region being disposed between a first plurality of columns of the memory cells and a second plurality of columns of the memory cells; and For a row of the rows of the memory cells: A dummy floating gate, the dummy floating gate being disposed in the strip region, above the substrate and insulated from the substrate, and disposed between two of the memory cells in the row of the memory cells; and A first erase gate line, the first erase gate line electrically connecting the erase gates of the memory cells in the row of the memory cells and in the first plurality of columns of the memory cells together, wherein the first erase gate line is aligned with the dummy floating gate and has a first row direction gap between the first erase gate line and the dummy floating gate.

2. The memory cell array according to claim 1, the memory cell array further comprising: A second erase gate line, the second erase gate line electrically connecting the erase gates of the memory cells in the row of the memory cells and in the second plurality of columns of the memory cells together, wherein the second erase gate line is aligned with the dummy floating gate and has a second row direction gap between the second erase gate line and the dummy floating gate.

3. The memory cell array according to claim 2, the memory cell array further comprising: A source line, the source line electrically connecting the source regions of the memory cells in the row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the source line extends across the strip region; And A vertical contact, the vertical contact being electrically connected to the source line and disposed in the strip region and between the first erase gate line and the second erase gate line.

4. The memory cell array according to claim 1, the memory cell array further comprising: A select gate line, the select gate line electrically connecting the select gates of the memory cells in the row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the select gate line extends across the strip region; And A vertical contact, the vertical contact being electrically connected to the select gate line and disposed in the strip region.

5. The memory cell array according to claim 1, wherein the corresponding one of the memory cells further includes a control gate disposed above the floating gate and insulated from the floating gate.

6. The memory cell array according to claim 5, the memory cell array further comprising: A control gate line that electrically connects the control gates of the memory cells in one row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the control gate line extends across the zone; And A vertical contact that is electrically connected to the control gate line and is disposed in the zone.

7. The memory cell array according to claim 1, wherein: The erase gate of the memory cells in one row of the memory cells and in the first plurality of columns of the memory cells is insulated from the corresponding floating gate by a tunnel oxide layer having a thickness; Wherein the first row direction gap is at least twice the thickness of the tunnel oxide layer.

8. The memory array cell according to claim 2, wherein: The erase gate of the memory cells in one row of the memory cells and in the second plurality of columns of the memory cells is insulated from the corresponding floating gate by a tunnel oxide layer having a thickness; Wherein the second row direction gap is at least twice the thickness of the tunnel oxide layer.

9. A memory cell array, the memory cell array comprising: A plurality of memory cells arranged in rows and columns, wherein a corresponding one of the memory cells includes: spaced source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed above a first portion of the channel region and insulated from the first portion; a select gate disposed above a second portion of the channel region and insulated from the second portion; and an erase gate disposed above the source region and insulated from the source region; A zone disposed between the first plurality of columns of the memory cells and the second plurality of columns of the memory cells; and For the first row of the memory cells and the second row of the memory cells: A first dummy floating gate disposed in the zone, above the substrate and insulated from the substrate, and disposed between two of the memory cells in the first row of the memory cells; A second dummy floating gate disposed in the zone, above the substrate and insulated from the substrate, and disposed between two of the memory cells in the second row of the memory cells; A first erase gate line that electrically connects the erase gates of the memory cells in the first row and the second row and in the first plurality of columns of the memory cells together, and The first erase gate line is aligned with the first dummy floating gate, having a first row-direction gap therebetween, and the first erase gate line is aligned with the second dummy floating gate, having a second row-direction gap therebetween.

10. The memory cell array according to claim 9, wherein the memory cell array further comprises: A second erase gate line that electrically connects the erase gates of the memory cells in the first row and the second row of the memory cells and in the second plurality of columns of the memory cells together, wherein the second erase gate line is aligned with the first dummy floating gate, having a third row-direction gap therebetween, and the second erase gate line is aligned with the second dummy floating gate, having a fourth row-direction gap therebetween.

11. The memory cell array according to claim 10, wherein the memory cell array further comprises: A source line that electrically connects the source regions of the memory cells in the first row and the second row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the source line extends across the band; and A vertical contact that is electrically connected to the source line and is disposed in the band and between the first erase gate line and the second erase gate line.

12. The memory cell array according to claim 9, wherein the memory cell array further comprises: A first select gate line that electrically connects the select gates of the memory cells in the first row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the first select gate line extends across the band; A first vertical contact that is electrically connected to the first select gate line and is disposed in the band; A second select gate line that electrically connects the select gates of the memory cells in the second row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the second select gate line extends across the band; and A second vertical contact that is electrically connected to the second select gate line and is disposed in the band.

13. The memory cell array according to claim 9, wherein the corresponding one memory cell in the memory cells further comprises a control gate disposed above the floating gate and insulated from the floating gate.

14. The memory cell array according to claim 13, wherein the memory cell array further comprises: A first control gate line that electrically connects the control gates of the memory cells in the first row of the memory cells and the memory cells in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the first control gate line extends across the strip; A first vertical contact that is electrically connected to the first control gate line and is disposed in the strip; A second control gate line that electrically connects the control gates of the memory cells in the second row of the memory cells and the memory cells in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the second control gate line extends across the strip; and A second vertical contact that is electrically connected to the second control gate line and is disposed in the strip.

15. The memory cell array according to claim 9, wherein: The erase gates of the memory cells in the first row and the second row of the memory cells and the memory cells in the first plurality of columns of the memory cells are insulated from the corresponding floating gates by a tunnel oxide layer having a thickness; Wherein the first row direction gap is at least twice the thickness of the tunnel oxide layer, and the second row direction gap is at least twice the thickness of the tunnel oxide layer.

16. The memory array cell according to claim 10, wherein: The erase gates of the memory cells in the first row and the second row of the memory cells and the memory cells in the second plurality of columns of the memory cells are insulated from the corresponding floating gates by a tunnel oxide layer having a thickness; Wherein the third row direction gap is at least twice the thickness of the tunnel oxide layer, and the fourth row direction gap is at least twice the thickness of the tunnel oxide layer.

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