An array of memory cells having a row-direction gap between erase gate lines and dummy floating gates

Abstract

A memory cell array having rows and columns of memory cells, wherein each memory cell includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate over a first portion of the channel region; a select gate over a second portion of the channel region; and an erase gate over the source region. A strip is disposed between a first plurality of columns and a second plurality of columns. For a row of memory cells, a dummy floating gate is disposed in the strip, and an erase gate line electrically connects the erase gates of the memory cells in that row and in the first plurality of columns together, wherein the erase gate line is aligned with the dummy floating gate and has a row-direction gap between the erase gate line and the dummy floating gate.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Patent Application No. 18 / 104,228, filed January 31, 2023, entitled "Memory CellArray With RowDirection Gap Between Erase Gate Lines and Dummy Floating Gates". Technical Field

[0003] The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations. Background Technology

[0004] Non-volatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration. Specifically, this application… Figure 1 A split-gate memory cell 10 is shown, having spaced-apart source regions 14 and drain regions 16 formed in a silicon semiconductor substrate 12. A channel region 18 of the semiconductor substrate is defined between the source region 14 and the drain region 16. A floating gate 20 is disposed above and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and is partially located above and insulated from) the source region 14). A control gate 22 is disposed above and insulated from the floating gate 20. A select gate 24 is disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18. The select gate 24 is laterally adjacent to the floating gate 20 and may include an upper portion extending upward and above the control gate 22. An erase gate 26 is disposed above and insulated from the source region 14 and laterally adjacent to the floating gate 20, wherein the upper portion extending upward and above the floating gate 20 forms a notch 27 facing the edge of the floating gate 20. The notch 27 and the edge of the floating gate 20 are insulated from each other by a tunnel oxide layer 28. Memory cells 10 can be arranged in pairs, such as Figure 1 As shown, two memory cells 10 share a common source region 14.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source region 14 / drain region 16 to program the memory cell 10 (i.e., inject electrons into the floating gate 20), erase the memory cell 10 (i.e., remove electrons from the floating gate 20 through the tunnel oxide 28), and read the memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 to determine the programming state of the floating gate 20).

[0006] Memory cell 10 can be operated digitally, wherein memory cell 10 is configured to only one of two possible states: a programming state and an erase state. Memory cell 10 is erased by applying a high positive voltage to erase gate 26 and optionally a negative voltage to control gate 22, causing electrons to tunnel through tunnel oxide layer 28 from floating gate 20 to erase gate 26 (putting floating gate 20 in a more positively charged state—the erase state). Memory cell 10 can be programmed by applying positive voltages to control gate 22, erase gate 26, select gate 24, and source region 14, and by applying current to drain region 16. Electrons then flow along channel region 18 from drain region 16 to source region 14, some of which become accelerated and heated, thereby being injected into floating gate 20 via hot electron injection (putting floating gate in a more negatively charged state—the programming state). Memory cell 10 can be read by applying a positive voltage to select gate 24 (which turns on the channel region below select gate 24) and drain region 16 (and optionally erase gate 26 and / or control gate 22) and sensing the current flowing through channel region 18. If floating gate 20 is positively charged (erased), memory cell 10 will be turned on, and current will flow from source region 14 to drain region 16 (i.e., memory cell 10 is sensed to be in its erase "1" state based on the sensed current). If floating gate 20 is negatively charged (programmed), channel region 18 below floating gate 20 is turned off, thereby preventing any current flow (i.e., memory cell 10 is sensed to be in its programmed "0" state based on no current).

[0007] The following table provides non-limiting examples of erasing, programming, and reading voltages:

[0008] Table 1

[0009] WL(SG) BL (Drain) Source EG CG erase 0V 0V 0V 11.5V 0V programming 1V 1μA 4.5V 4.5V 10.5V Read Vcc 0.6V 0V 0V Vcc

[0010] Memory cell 10 may alternatively operate in an analog manner, wherein the memory state of the memory cell (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can change continuously anywhere from a fully erased state (few electrons on the floating gate) to a fully programmed state (maximum number of electrons on the floating gate), or only a portion of that range. This means that cell storage is analog, which allows for very precise and individual adjustments to each memory cell 10 in the memory cell array. Alternatively, the memory can be operated as an MLC (Multi-Level Cell), wherein the MLC is configured to be programmed to one of many discrete values ​​(such as 16 or 64 different values). In the case of analog or MLC programming, the programming voltage is applied only for a finite time or as a series of pulses until the desired programming state is achieved. In the case of multiple programming pulses, an intermediate read operation between programming pulses can be used to determine whether the desired programming state has been achieved (in which case programming stops) or has not been achieved (in which case programming continues).

[0011] Memory cells 10 can be arranged in an array (i.e., arranged in rows and columns). For example... Figure 1 As shown, each pair of memory cells 10 shares a common source region 14 and a common erase gate 26. (As...) Figure 2 As shown in the array layout, Figure 1 The memory cells 10 shown can be arranged end-to-end in columns, where two adjacent pairs of memory cells can share a common drain region 16. The source regions 14 of a row for a pair of memory cells can be formed as continuous source lines 14a of a diffusion region in the semiconductor substrate 12, electrically connecting all source regions 14 of the row for the pair of memory cells together. The control gates 22 of a row for memory cells 10 can be formed as continuous control gate lines 22a made of a conductive material (such as polysilicon), electrically connecting all control gates 22 of the row for memory cells together. The select gates 24 of a row for memory cells 10 can be formed as continuous select gate lines 24a (also referred to as word lines) made of a conductive material (such as polysilicon), electrically connecting all select gates 24 of the row for memory cells together. The erase gates 26 of a row for memory cells 10 can be formed as continuous erase gate lines 26a made of a conductive material (such as polysilicon), electrically connecting all erase gates 26 of the row for memory cells together. The floating gate 20 may be formed of a conductive material such as polysilicon.

[0012] It needs to be periodically connected to the individual lines of the array. Summary of the Invention

[0013] The aforementioned problems and requirements are addressed by a memory cell array comprising a plurality of memory cells arranged in rows and columns. Each memory cell includes: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region. A stripe is disposed between a first plurality of columns and a second plurality of columns of the memory cells. For a row of memory cells, a dummy floating gate is provided, which is disposed in the strip area, above the substrate and insulated from the substrate, and between two memory cells in that row of memory cells, and a first erase gate line is provided, which electrically connects the erase gates of memory cells in that row of memory cells and in a first plurality of columns of memory cells together, wherein the first erase gate line is aligned with the dummy floating gate and there is a first row direction gap between the first erase gate line and the dummy floating gate.

[0014] The memory cell array includes a plurality of memory cells arranged in rows and columns. A corresponding memory cell includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region. A stripe is disposed between a first plurality of columns and a second plurality of columns of memory cells. For the first row and the second row of memory cells, a first dummy floating gate is disposed in the strip area, above the substrate and insulated from the substrate, and disposed between two memory cells in the first row of memory cells; a second dummy floating gate is disposed in the strip area, above the substrate and insulated from the substrate, and disposed between two memory cells in the second row of memory cells; a first erase gate line electrically connects the erase gates of memory cells in the first row and the second row and in the first plurality of columns of memory cells together, and the first erase gate line is aligned with the first dummy floating gate, with a first row direction gap between the first erase gate line and the first dummy floating gate, and the first erase gate line is aligned with the second dummy floating gate, with a second row direction gap between the first erase gate line and the second dummy floating gate.

[0015] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0016] Figure 1 It is a side cross-sectional view of a pair of conventional memory cells.

[0017] Figure 2 This is a layout diagram showing the conventional arrangement of the lines in a memory cell array.

[0018] Figure 3 It is a layout diagram showing the arrangement of the lines and stripes of the memory cell array.

[0019] Figure 4 This is a partial layout diagram showing the layout of one of the lines and stripes in the memory cell array.

[0020] Figure 5 This is a partial layout diagram showing the row-direction overlap between an erase gate line and a dummy floating gate in the erase gate line and the dummy floating gate.

[0021] Figure 6 This is a partial layout diagram showing the row-direction gap between one of the erase gate lines and one of the dummy floating gates.

[0022] Figure 7 It is a layout diagram showing the arrangement of the lines and stripes of the memory cell array, wherein there is a row-direction gap between the erase gate line and the dummy memory cell.

[0023] Figure 8 This is a side sectional view of an alternative example of a memory cell.

[0024] Figure 9 It is shown Figure 8 A layout diagram of the individual lines and stripes of the memory cell array, wherein there is a row-direction gap between the erase gate line and the dummy memory cell. Detailed Implementation

[0025] Periodic stripes can be incorporated into the memory cell array to provide space and pathways to connect to the individual lines of the memory cell array. Figure 3 It shows something similar to Figure 1 The memory array of memory cells 10, wherein the same element number points to the same element. Figure 3 The memory array includes a first stripe 30, a second stripe 32, and a third stripe 34. Each stripe is the area between two columns in the column 36 of the memory cell 10. Figure 3The example shows three columns 36 of memory cells 10 arranged between corresponding stripes; however, the number of columns 36 of memory cells 10 between corresponding stripes may vary.

[0026] Strips 30, 32, and 34 provide regions between columns of memory cells 36, in which vertical direct contacts can be formed extending downwards from higher-level metal layers (where signal lines can be formed), these higher-level metal layers making electrical contact with various lines of the memory array. For example, in the first strip 30, vertical direct contacts 38 extend downwards from the upper metal layer and make electrical contact with the select gate line (word line) 24a, and vertical direct contacts 40 extend downwards from the upper metal layer and make electrical contact with the source line 14a. Figure 3 In the example, each source line 14a electrically connects the source regions 14 of two rows of memory cells together (and extends across bands 30, 32, 34). Each erase gate line 26a electrically connects the erase gates of memory cells in two adjacent rows of memory cells together. To provide a path to the source line 14a, a portion of the erase gate line 26a at the center of the first band 30 is removed (e.g., by etching), such that the vertical direct contact 40 can make electrical contact with the source line 14a but not with the erase gate line 26a (i.e., the vertical direct contact is electrically connected to the source line and disposed in the first band 30 and between the erase gate lines 26a). In the second band 32, the vertical direct contact 40 extends downward from the upper metal layer and makes electrical contact with the source line 14a. To provide a path to the source line 14a, the portion of the erase gate line 26a at the center of the second band region 32 is removed (e.g., by etching), such that the vertical direct contact 40 can make electrical contact with the source line 14a but not with the erase gate line 26a (i.e., the vertical direct contact is electrically connected to the source line and disposed in the first band region 30 and between the erase gate lines 26a). In the third band region 34, the vertical direct contact 44 extends downward from the upper metal layer and makes electrical contact with the tab portion 22b (i.e., the widened portion) of the control gate line 22a, and the vertical direct contact 40 extends downward from the upper metal layer and makes electrical contact with the source line 14a. To provide a path to the source line 14a, the portion of the erase gate line 26a at the center of the third band region 34 is removed (e.g., by etching), such that the vertical direct contact 40 can make electrical contact with the source line 14a but not with the erase gate line 26a (i.e., the vertical direct contact is electrically connected to the source line and disposed in the first band region 30 and between the erase gate lines 26a). Because the diffusion region in the semiconductor substrate 12 (which forms the source line 14a) is less conductive than the metal line to which the source line is connected, the vertical direct contact 40 of the source line 14a can be included in all three band regions 30, 32, and 34.

[0027] To facilitate manufacturing and maintain the polysilicon density in stripes 30, 32, and 34 relative to the columns of memory cells, a dummy floating gate 20a can be formed in stripes 30, 32, and 34, such as... Figure 3 As shown. A dummy floating gate 20a may be formed in the portion where the control gate line 22a of the strips 30, 32, 34 overlaps with the lower diffusion region in the semiconductor substrate 12, and may be made of the same conductive material (such as polysilicon) as the floating gate 20, and have the same overall configuration as the floating gate 20 (i.e., disposed above and insulated from the substrate). For any given strip and row of memory cells, a dummy floating gate 20a may exist disposed in the strip and between two memory cells 10 in that row of memory cells. Forming the dummy floating gate 20a as part of the process of forming the floating gate 20 simplifies manufacturing and increases reliability and yield by making the density of the conductive material in the strips 30, 32, 34 closer to the density of the memory cell column.

[0028] The inventors have discovered that the proximity of the erase gate line 26a and the dummy floating gate 20a can cause capacitive coupling between them, which may in turn interfere with the programming state of adjacent memory cells. For example, as Figure 4 As shown, a memory cell 10n with a floating gate 20n is adjacent to a strip 30 with a dummy floating gate 20a, which in turn is adjacent to a memory cell 10m with a floating gate 20m. An erase gate line 26a extends partially into the strip 30 such that the erase gate line 26a partially overlaps the dummy floating gate 20a in the row direction at both ends of the dummy floating gate 20a (referred to herein as row direction overlap, RDO), as... Figures 4 to 5As shown. As used herein, row-direction overlap (RDO) relates to how each erase gate line 26a is aligned with its corresponding dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one of which is aligned with the edge of the dummy floating gate 20a, and the other of which is aligned with the edge of the adjacent erase gate line 26a, indicating the overlap of these two features in the row direction (even though these elements are separated from each other in the column direction, and therefore there is no actual physical overlap). Row-direction overlap (RDO) results in excessive capacitive coupling between the dummy floating gate 20a and the erase gate line 26a, such that erasing or programming memory cell 10n may interfere with the programming state of memory cell 10m. For example, erasing the floating gate 20n of memory cell 10n may at least partially erase the dummy floating gate 20a, which in turn may at least partially erase the floating gate 20m of memory cell 10m and / or cause data retention leakage for both floating gates 20n and 20m. In addition, the programmable floating gate 20n can partially program the dummy floating gate 20a, which in turn can cause the partially programmed dummy floating gate 20a to interfere with the programming state of the floating gate 20m of the memory cell 10m.

[0029] The inventors have determined that reconfiguring the alignment of the erase gate line 26a near the corresponding dummy floating gate 20a band area, replacing the row direction overlap RDO between the dummy floating gate 20a and the corresponding erase gate line 26a with the row direction gap RDG between the dummy floating gate 20a and the corresponding erase gate line 26a, can result in a significant reduction in unintended changes to the programming state of the dummy floating gate 22a, and thus a significant reduction in interference with the programming state of the floating gate 20 of the nearby memory cells. As used herein, the row direction gap RDG relates to how each erase gate line 26a is aligned with the corresponding dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one of which is aligned with the edge of the dummy floating gate 20a, and the other of which is aligned with the edge of the corresponding adjacent erase gate line 26a, indicating the gap between these two features in the row direction, such as... Figure 6 and Figure 7 As shown. For any given dummy floating gate 20a in a row of memory cell 10, there is a first row direction gap RDG relative to the first erase gate line 26a (e.g., to the left or right side of the dummy erase gate 20a), and a second row direction gap RDG relative to the second erase gate line 26a (e.g., to the other side of the left or right side of the dummy erase gate 20a), as shown. Figure 6 and Figure 7As shown. The first row direction gap and the second row direction gap on either side of the dummy floating gate 20a can be, but do not have to be, the same size. In the case that the edge is not linear, the vertical line will intersect at the farthest point, at which the corresponding dummy floating gate 20a extends in the row direction toward the corresponding adjacent column of memory cells, and the corresponding erase gate line 26a extends in the row direction toward the center of the stripe. Aligning the erase gate line 26a with the dummy floating gate 20a having the row gap RDG means that the alignment has no row direction overlap RDO (i.e., the row direction gap RDG and the row direction overlap RDO are mutually exclusive).

[0030] It has been further determined that the minimum row direction gap (RDG) used to achieve improved performance can be correlated with the thickness of the tunnel oxide layer 28, as it has been found that the larger the tunnel oxide layer, the larger the row direction gap should be. Specifically, the thickness of the tunnel oxide layer 28 can be selected based on the erase operation voltage applied to the erase gate, and thus indicates the potential capacitive coupling between the erase gate line 26a and the dummy floating gate 20a. Electric field near the tunnel oxide. It can be represented as:

[0031]

[0032] Where V is the voltage across the tunnel oxide, and t ox This refers to the thickness of the tunnel oxide layer. The current density J in the Fowler-Nordheim tunneling can be expressed as:

[0033]

[0034] Where A and B are constants, and V is the erase voltage applied to the erase gate line during the erase operation. To reduce the Fowler-Nordheim current density between the dummy floating gate 20a and the erase gate line 26a to a low or insignificant amount, the row direction gap RDG is sufficient to reduce the possibility of tunneling between the dummy floating gate 20a and the erase gate line 26a. It has been determined that providing a row direction gap RDG at least twice the thickness of the tunnel oxide layer 28 ensures that any Fowler-Nordheim current density between the dummy floating gate 20a and the erase gate line 26a is a low or insignificant amount. Making the row direction gap RDG at least twice the thickness of the tunnel oxide layer 28 also ensures that the desired and effective row direction gap RDG is maintained when the device size is scaled down.

[0035] A row-direction gap RDG having a thickness of at least twice that of the tunnel oxide layer 28 can be offset from Figure 1 Implemented in the non-volatile memory cell configuration. Specifically, Figure 8 It shows something similar to Figure 1 The memory cell is a memory cell, but the control gate is omitted. Figure 9 It shows Figure 8 The memory cell array has a row direction gap RDG between the erase gate line 26a and the dummy memory cell 20a.

[0036] It should be understood that the invention is not limited to the embodiments described above and shown herein, but covers any and all variations within the scope of any of the claims. For example, references to the invention herein are not intended to limit the scope of any claims or claim terminology, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and numerical values ​​described above are merely illustrative and should not be construed as limiting the claims. Furthermore, as will be apparent from the claims and description, unless otherwise stated, not all method steps may need to be performed in the specific order shown or required.

Claims

1. A memory cell array, the memory cell array comprising: A plurality of memory cells are arranged in rows and columns, wherein a corresponding memory cell includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region. A stripe, wherein the stripe is disposed between a first plurality of columns and a second plurality of columns of the memory cell; and For one row of the rows of the memory cell: A dummy floating gate is disposed in the strip region, above the substrate and insulated from the substrate, and positioned between two memory cells in the row of the memory cells. A first erase gate line electrically connects the erase gates of the memory cells in one row and in one of the first plurality of columns of the memory cells, wherein the first erase gate line is aligned with the dummy floating gate and has a first row-direction gap between the first erase gate line and the dummy floating gate.

2. The memory cell array according to claim 1, further comprising: The second erase gate line electrically connects the erase gates of the memory cells in the row of the memory cell and in the second plurality of columns of the memory cell, wherein the second erase gate line is aligned with the dummy floating gate and has a second row direction gap between the second erase gate line and the dummy floating gate.

3. The memory cell array according to claim 2, further comprising: A source line electrically connects the source regions of the memory cells in a row and in the first and second plurality of columns of the memory cells, wherein the source line extends across the band region; and A vertical direct contact, which is electrically connected to the source line, and is disposed in the band region between the first erase gate line and the second erase gate line.

4. The memory cell array according to claim 1, further comprising: Select gate lines electrically connect the select gates of memory cells in a row and in the first and second plurality of columns of the memory cells, wherein the select gate lines extend across the band region; and A vertical direct contact, which is electrically connected to the select gate line and disposed in the band region.

5. The memory cell array of claim 1, wherein a corresponding memory cell in the memory cells further includes a control gate disposed above the floating gate and insulated from the floating gate.

6. The memory cell array according to claim 5, further comprising: A control gate line electrically connects the control gates of the memory cells in a row and in the first and second plurality of columns of the memory cells, wherein the control gate line extends across the band region; and A vertical direct contact, which is electrically connected to the control gate line and disposed in the band region.

7. The memory cell array according to claim 1, wherein: The erase gate of the memory cell in the row of the memory cell and in the first plurality of columns of the memory cell is insulated from the corresponding floating gate by a tunnel oxide layer having a thickness. The first row directional gap is at least twice the thickness of the tunnel oxide layer.

8. The memory cell array according to claim 2, wherein: The erase gate of the memory cell in the row of the memory cell and in the second plurality of columns of the memory cell is insulated from the corresponding floating gate by a tunnel oxide layer having a thickness. The second row directional gap is at least twice the thickness of the tunnel oxide layer.

9. A memory cell array, the memory cell array comprising: A plurality of memory cells are arranged in rows and columns, wherein a corresponding memory cell includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region. A stripe, wherein the stripe is disposed between a first plurality of columns and a second plurality of columns of the memory cell; and For the first row and the second row of the memory cells: A first dummy floating gate is disposed in the band region, above the substrate and insulated from the substrate, and is positioned between two memory cells in the first row of the memory cells. A second dummy floating gate is disposed in the band region, above the substrate and insulated from the substrate, and is positioned between two memory cells in the second row of the memory cells. A first erase gate line electrically connects the erase gates of the memory cells in the first row and second row and in the first plurality of columns of the memory cells together. The first erase gate line is aligned with the first dummy floating gate, and there is a first row direction gap between the first erase gate line and the first dummy floating gate. The first erase gate line is also aligned with the second dummy floating gate, and there is a second row direction gap between the first erase gate line and the second dummy floating gate.

10. The memory cell array according to claim 9, further comprising: A second erase gate line electrically connects the erase gates of the memory cells in the first row and the second row and the second plurality of columns of the memory cells together, wherein the second erase gate line is aligned with the first dummy floating gate, a third row direction gap is provided between the second erase gate line and the first dummy floating gate, and the second erase gate line is aligned with the second dummy floating gate, a fourth row direction gap is provided between the second erase gate line and the second dummy floating gate.

11. The memory cell array according to claim 10, further comprising: Source lines electrically connect the source regions of the memory cells in the first and second rows and in the first and second columns of the memory cells, wherein the source lines extend across the band regions; and A vertical direct contact, which is electrically connected to the source line, and is disposed in the band region between the first erase gate line and the second erase gate line.

12. The memory cell array according to claim 9, further comprising: A first select gate line electrically connects the select gates of the memory cells in the first row and in the first and second plurality of columns of the memory cells, wherein the first select gate line extends across the band region. A first vertical direct contact is electrically connected to the first selected gate line and is disposed in the band region; A second select gate line electrically connects the select gates of the memory cells in the second row and in the first and second plurality of columns of the memory cells together, wherein the second select gate line extends across the band region; and The second vertical direct contact is electrically connected to the second select gate line and is disposed in the band region.

13. The memory cell array of claim 9, wherein a corresponding memory cell in the memory cells further includes a control gate disposed above the floating gate and insulated from the floating gate.

14. The memory cell array according to claim 13, further comprising: A first control gate line electrically connects the control gates of the memory cells in the first row and in the first and second plurality of columns of the memory cells together, wherein the first control gate line extends across the band region. A first vertical direct contact is electrically connected to the first control gate line and is disposed in the band area; A second control gate line electrically connects the control gates of the memory cells in the second row of the memory cells and in the first plurality of columns and the second plurality of columns of the memory cells together, wherein the second control gate line extends across the band region; and The second vertical direct contact is electrically connected to the second control gate line and is disposed in the band region.

15. The memory cell array according to claim 9, wherein: The erase gate of the memory cell in the first row and the second row and in the first plurality of columns of the memory cell is insulated from the corresponding floating gate by a tunnel oxide layer having a thickness. The first row directional gap is at least twice the thickness of the tunnel oxide layer, and the second row directional gap is at least twice the thickness of the tunnel oxide layer.

16. The memory cell array according to claim 10, wherein: The erase gates of the memory cells in the first and second rows and in the second plurality of columns of the memory cells are insulated from the corresponding floating gates by a tunnel oxide layer having a thickness. The third row directional gap is at least twice the thickness of the tunnel oxide layer, and the fourth row directional gap is at least twice the thickness of the tunnel oxide layer.

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