Semiconductor package
By stacking bare chips vertically inside the package and connecting with plated sidewalls, the problem of component wiring imbalance in chip embedding technology is solved, and efficient electrical and thermal performance improvements are achieved.
Patent Information
- Application Number
- CN202280100786.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-10-23
- Filing Date
- 2022-12-23
- Publication Date
- 2025-07-18
AI Technical Summary
Existing chip embedding technologies have challenges in balancing wiring between components in 2D configurations and multi-bare chip configurations, especially while reducing parasitic inductance and improving electrical performance, it is difficult to effectively balance signal connections between components.
Using a new chip embedding process, the bare chips are stacked vertically and installed inside the package. Through the plating sidewall connection and the PCB manufacturing process, the connection between the bare chip and the package base surface is optimized, the balanced connection between the parallel components is achieved, and partial shielding is provided in the half-bridge configuration.
Improves the electrical performance of the module, shortens the current path length, balances the source, drain and gate connections, enhances thermal performance, and supports efficient heat dissipation of multi-baric chip packages.
Smart Images
Figure CN120345062A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip embedding and packaging for power packaging. Specifically, the present invention relates to a semiconductor package and a second semiconductor package including the semiconductor package. For example, a 90-degree flipped power package is disclosed to enable modular vertical assembly of power electronic modules. Background Art
[0002] Chip embedding technology is a relatively new packaging technology and is currently also used for power packaging. The main benefit of the embedding technology is that it supports reducing parasitic inductance, maximizing the electrical performance of the module, while reducing the package size.
[0003] The main reasons for the reduction of parasitic effects and the improvement of electrical performance are the short and effective Cu-to-Cu interconnections between the embedded components and the PCB and between the components. Although chip embedding (CE) can be used to reduce the parasitic effects described above, ordinary chip embedding technology faces similar challenges as other traditional packaging technologies, namely balancing the signals between components in a multi-die configuration. In most cases, balancing the wiring between components in a 2D configuration and a multi-die configuration can be very challenging. Summary of the Invention
[0004] The present invention provides a solution to overcome the above problems of packaging and chip embedding technologies, specifically balancing the wiring between components in a 2D configuration and a multi-die configuration.
[0005] The above and other objects and goals are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description, and the drawings.
[0006] The present invention presents a novel high-performance single-die or multi-die package, in which the embedded dies are stacked and vertically mounted inside the final package. The final package can be hereinafter referred to as the second semiconductor package. The manufacturing can be done horizontally by the following operations: stacking several layers with embedded components on top of each other using a normal CE / ECP embedding process, and connecting the layers to the plated sidewalls during embedding using a normal PCB manufacturing process.
[0007] The solution presented in the present invention supports improving the electrical performance of the module by shortening and optimizing the connection between the die and the package footprint and balancing the connections between, for example, parallel components.
[0008] Using the solution presented in the present invention, a fully balanced power package can be fabricated with power die chips connected in parallel or in a half-bridge configuration (or other configurations possibly). The components are mounted vertically inside the final package, and multiple components can be stacked together. In the case of a parallel die package, the solution supports minimizing the current path length and fully balancing the source, drain, and gate connections (the current paths to the source and gate pads or to the two drain pads are symmetric). In a half-bridge configuration, the high side (HS) and low side (LS) switches are embedded in different layers stacked on top of each other. A structure is disclosed that supports minimizing the distance between the drain and source connections and maximizing the line width, and optimizing and minimizing the Vin and Vswh or Pgnd and Vswh connection paths according to the configuration. In a half-bridge configuration, the presented solution also supports partial shielding. The disclosed solution also supports improving the thermal performance of the package, while the heat generated can be conducted away from the power die chips through the sidewalls of the package.
[0009] The present invention presents the features and structure of a multi-die package module with stacked and rotated 90-degree wiring, and how to fabricate such a module.
[0010] A laminate-based package is provided that includes one or more stacked power die chips. The package is rotated 90 degrees so that the power die chips are vertically located inside the package, and the package has at least one partially metallized sidewall that will serve as a pad.
[0011] Embodiments of the present invention can be implemented based on the following:
[0012] (1) Embedding one or more power die chips into the laminate using CE / ECP technology.
[0013] (2) Stacking several laminates with or without embedded components together and connecting them to each other through plated vias or slots.
[0014] (3) Separating the package using a slicing or cutting process so that one side of the plated via or slot is exposed.
[0015] (4) Flipping the package 90 degrees before mounting it onto a PCB board.
[0016] (5) Placing the die chips vertically inside the package.
[0017] (6) The package can contain one, two, or several layers with embedded die chips.
[0018] The package can be used like a normal power package (such as a power package with parallel power die chips). For example, the module can adopt a half-bridge configuration.
[0019] The techniques described in this invention can be applied to single and parallel (multiple) devices, integrated power stages / converters, such as buck, boost, buck / boost converters, half-bridge stages, etc. This invention provides a general solution applicable to a variety of power electronic circuits and components.
[0020] Specifically, the disclosed solution can be applied to power die packages for single die, multi-die, parallel die, half-bridge, power stage, DrMOS, and other types of power modules. The solution can be applied to Si, SiC, GaN, or other wide-bandgap semiconductors and ultra-wide-bandgap materials, such as Ga2O3.
[0021] The solution can be applied to lateral, vertical, and semi-vertical current flow devices. The solution can be applied with or without integrated passive devices and / or logic dies (such as drivers, controllers, etc.). The solution can also be used for other types of die-less modules.
[0022] The following terms, abbreviations, and symbols will be used:
[0023] PCB Printed Circuit Board
[0024] PTH Plated Through Hole
[0025] CE Chip Embedding
[0026] ECP Embedded Component / Chip Package
[0027] LTI Lead Tip Inspection
[0028] FR-4: The composite material is a widely used PCB laminate. It consists of epoxy resin reinforced with woven fiberglass.
[0029] CE / ECP: Chip Embedding or Embedded Component Packaging is a packaging technology in which a die, usually with a Cu metallization layer, is embedded inside the PCB material and connected to the Cu wiring on the package through plated micro-vias.
[0030] PTH: Mechanical or laser drilling, usually with 20μm to 30μm of Cu plating on the sidewalls.
[0031] LTI: Lead Tip Inspection is a method especially used in the automotive field, which supports the inspection of the soldering quality of all connections through optical inspection. The pads on the package are exposed on the side of the package, so that the solder can be wetted and have a rounded corner on the side wall.
[0032] In the present invention, chip embedding technology is described. There are several different types of embedding processes available: In a typical chip embedding process, electronic components (chips, capacitors, resistors, etc.) are placed in the openings of the central layer of the PCB, or are soldered on two or more layers of the PCB. The actual embedding inside the final PCB can be performed by laminating FR4 prepreg or other polymer sheets above and below the central layer holding the components to be embedded. The electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the internal lamination layers and then laminating the PCB layers together. In a more advanced embedding technology, the components can be electrically connected through current-filled micro-vias, which is more robust because there is no reflow of solder inside the package or the board, and this must be taken into account when other components are mounted on the outer layer of the PCB through an additional reflow process. The micro-vias are usually formed by laser drilling from the top surface through the thin lamination layer to the active chip pads or the terminals of the embedded component package after lamination.
[0033] When using plated through-holes, the inner wall of the hole is covered with a thin copper (Cu) layer, which makes the entire inner hole area conductive. This conductivity establishes an electrical connection between different Cu layers and / or components and Cu traces. It also enhances the mechanical stability and reduces the overall resistance to support smooth current flow. The average Cu plating thickness is at least 20 μm. As electronic components become more and more integrated and complex, double-sided and multi-layer PCBs are developed with plated through-holes so that components can be connected to the required layers when needed.
[0034] In the present invention, sidewall connections are described. These sidewall connections can be plated and arranged on the outer surface of the package. To manufacture these sidewall connections, PCB processes can be used. At the panel level, before plating / separation, large plated through-holes can be mechanically drilled along the package contour, or elliptical slots can be mechanically milled. After drilling / milling, electroless and electroplating processes can be applied to plate a metal layer, such as a metal layer of 20 μm to 30 μm Cu, on the through-holes or elliptical slots. Then, during the separation of the panel into individual packages, the plated through-holes or slots can be cut in half, so that a part of the through-hole or slot remains on one side of the cut, and the other part remains on the opposite side of the cut, where the cutting line defines the package contour.
[0035] According to a first aspect, the present invention relates to a semiconductor package, comprising: at least one integrated circuit, including at least one first connection terminal and at least one second connection terminal for electrical connection of the at least one integrated circuit; a sealant that seals at least a portion of the at least one integrated circuit, the sealant including a first major surface and a second major surface opposite the first major surface, and one or more sidewalls between the first major surface and the second major surface; a first metal layer disposed on a portion of a first sidewall of the one or more sidewalls of the sealant, wherein the first metal layer forms a first connector for electrically connecting the at least one first connection terminal of the at least one integrated circuit; a second metal layer disposed on another portion of the first sidewall of the sealant, wherein the second metal layer forms a second connector for electrically connecting the at least one second connection terminal of the at least one integrated circuit; wherein the first connector and the second connector of the semiconductor package are configured to be connected to respective metal traces of a printed circuit board (PCB).
[0036] Such a semiconductor package provides the technical advantages of a fully balanced power package, in which integrated circuits (such as power die) can be connected in parallel or in a half-bridge configuration or other configurations. The components can be vertically mounted inside the final package (hereinafter also referred to as the second semiconductor package), and multiple components can be stacked together. In the case of a parallel die package, the semiconductor package supports minimizing the current path length and fully balancing the source, drain, and gate connections, since the current paths to the source and gate pads or to the two drain pads are symmetric. In a half-bridge configuration, the high side (HS) and low side (LS) switches can be embedded in different layers stacked on top of each other. The semiconductor package supports minimizing the distance between the drain and source connections and maximizing the line width, and optimizing and minimizing the Vin and Vswh or Pgnd and Vswh connection paths according to the configuration. In a half-bridge configuration, the semiconductor package also supports partial shielding. The semiconductor package also supports improving the thermal performance of the package, while the heat generated can be conducted away from the power die through the package sidewalls.
[0037] The at least one integrated circuit can be a vertical device, such as as Figure 1 shown, or a lateral device, such as as Figure 10 shown. The device can have three terminals, but only two of them are described here.
[0038] In an exemplary implementation of the semiconductor package, the first major surface and the second major surface form two major regions of the semiconductor package, and the area covered by each major region is larger than the area of any one of the side walls of the sealant. Therefore, the semiconductor package can be manufactured as a planar package having two major surfaces and flat side walls between the major surfaces. This manufacturing can be efficiently carried out by using normal PCB manufacturing techniques.
[0039] In an exemplary implementation of the semiconductor package, the first metal layer is placed on the portion of the first side wall and on a part of the first major surface; and / or the second metal layer is placed on the other portion of the first side wall and on the other part of the first major surface. Therefore, the first metal layer and the second metal layer can be electrically contacted from both sides of the semiconductor package. In addition, there is a large contact area that extends to both sides of the package for contacting the first metal layer and the second metal layer and the corresponding connection terminals.
[0040] In an exemplary implementation of the semiconductor package, the first metal layer is placed on the edge portion of the sealant, and the edge portion includes the portion of the first side wall, the portion of the first major surface, and a part of the second side wall adjacent to the first side wall; and / or the second metal layer is placed on the other edge portion of the sealant, and the other edge portion includes the other portion of the first side wall, the other part of the first major surface, and a part of the third side wall opposite to the second side wall. The corresponding terminals of the integrated circuit can be electrically contacted from three sides of the semiconductor package. A large contact area can be used to contact the corresponding terminals, thus enabling a flexible contact design.
[0041] In an exemplary implementation of the semiconductor package, the sealant includes two or more PCB layers, and each PCB layer has a first major PCB surface and a second major PCB surface opposite to the first major PCB surface; the first major PCB surfaces and the second major PCB surfaces of the two or more PCB layers are arranged parallel to the first major surface and the second major surface of the sealant. Therefore, the semiconductor package can be produced as a multi-layer PCB board, can be vertically mounted, and can achieve symmetric double-sided cooling for the semiconductor package. The vertical direction is the direction relative to the vertical axis of the PCB (e.g., the axis perpendicular to the mounted PCB) on which the semiconductor package (e.g., the multi-layer PCB board) will be mounted.
[0042] In an exemplary implementation of a semiconductor package, the semiconductor package includes: at least one first via for routing at least one third connection terminal of a first integrated circuit to a portion of the second metal layer disposed on the first major surface; at least one second via for routing at least one first connection terminal of the first integrated circuit to a portion of the first metal layer disposed on the second major surface. The vias can route the connection terminals of the integrated circuit to the respective first and second major surfaces of the encapsulant for external connection to a mounted PCB.
[0043] In an exemplary implementation of a semiconductor package, the semiconductor package includes: at least one first via for routing at least one third connection terminal of a first integrated circuit to a portion of the second metal layer disposed on the first major surface; at least one second via for routing at least one second connection terminal of a second integrated circuit to a portion of the second metal layer disposed on the second major surface. The vias can route the connection terminals of the integrated circuit to the respective first and second major surfaces of the encapsulant for external connection to a mounted PCB.
[0044] In an exemplary implementation of a semiconductor package, the first integrated circuit and the second integrated circuit form a parallel die configuration. Thus, in the parallel die configuration, the semiconductor package supports minimizing the current path length and fully balancing the source, drain, and gate connections because the current paths to the two drain pads are symmetric.
[0045] In an exemplary implementation of a semiconductor package, the semiconductor package includes: at least one first via for routing at least one third connection terminal of a first integrated circuit to a portion of the second metal layer disposed on the first major surface; at least one third via for routing at least one first connection terminal of a second integrated circuit to a portion of the first metal layer disposed on the second major surface. Thus, an IC having three connection terminals (such as a MOSFET or an IGBT) can be fully balanced in such a semiconductor package. This enables the semiconductor package to be advantageously applied to a plurality of power electronic circuits and components, such as integrated power stages or converters, such as buck, boost, buck / boost converters, half-bridge stages, etc.
[0046] In an exemplary implementation of a semiconductor package, the first integrated circuit and the second integrated circuit form a half-bridge configuration. In the half-bridge configuration, the semiconductor package supports minimizing the current path length and fully balancing the source, drain, and gate connections because the current paths to the source and gate pads are symmetric.
[0047] In an exemplary implementation of a semiconductor package, at least the first integrated circuit and the second integrated circuit are stacked between the first major surface and the second major surface of the encapsulant. Such a configuration provides the advantage that two integrated circuits can be stacked on top of each other. This enables the two integrated circuits to have a symmetric orientation with respect to each other, thereby allowing a reduction in the impact of parasitic components in the assembly. Since the ICs have symmetry and the same wire length, the impact of parasitic components can be compensated for.
[0048] In an exemplary implementation of a semiconductor package, the aspect ratio of each of the stacked integrated circuits in the stacked integrated circuits is greater than 1. This improves the heat dissipation effect. Due to the non-uniformity of the drain-source on-resistance (Rdson) caused by the heat distribution, the Rdson in a semiconductor device is higher at the center of the bare die and lower at the edges. This characteristic applies to any semiconductor device, specifically lateral devices and vertical devices. For example, the center of the bare die is hot and the edges are cold. An aspect ratio greater than 1 can improve the heat dissipation effect.
[0049] According to a second aspect, the present invention relates to a second semiconductor package, comprising: the semiconductor package according to the first aspect described above; a printed circuit board (PCB), comprising a first metal trace and a second metal trace; the semiconductor package is mounted on the PCB through a first sidewall, a first connector of the PCB is connected to the first metal trace, and a second connector of the PCB is connected to the second metal trace of the PCB.
[0050] The PCB on which the semiconductor package is mounted can be a flat plate having a major surface, and both the first metal trace and the second metal trace are printed or attached to the major surface.
[0051] Such a second semiconductor package, also referred to as a "final product", provides a fully balanced power package, in which integrated circuits (such as power bare dies) can be connected in parallel or in a half-bridge configuration or other configurations. Components can be vertically mounted inside the final package, and multiple components can be stacked together. The semiconductor package supports minimizing the current path length and fully balancing the source, drain, and gate connections because the current path is symmetric. The second semiconductor package supports improving the thermal performance of the package, while the heat generated can be conducted away from the power bare die from the side of the package.
[0052] In an exemplary implementation of the second semiconductor package, each of the first major surface and the second major surface of the sealant forms an angle with the major surface of the PCB, and the angle is within a threshold range of about 90 degrees. This means that the sealant is arranged at an angle of 90 degrees with respect to the PCB surface, including a small deviation from 90°. Therefore, the semiconductor package according to the first aspect can be vertically mounted inside the final package (second semiconductor package), and multiple such semiconductor packages can be stacked together.
[0053] In an exemplary implementation of the second semiconductor package, the at least one integrated circuit includes a first major die surface and a second major die surface opposite the first major die surface; the first major die surface and the second major die surface form an angle with the major surface of the PCB, and the angle is within a threshold range of about 90 degrees. This means that the die is arranged at an angle of 90 degrees with respect to the PCB surface, including a small deviation from 90°. The integrated circuit can be vertically mounted inside the semiconductor package and inside the final package, and multiple such integrated circuits can be stacked together.
[0054] In an exemplary implementation of the second semiconductor package, the first metal layer is placed on the portion of the first sidewall and on a part of the first major surface; and / or solder fillets are applied to the first sidewall and the first major surface for electrically and mechanically connecting the semiconductor package to the PCB. The filled solder provides a large electrical contact covering the first major surface and the first sidewall. This achieves mechanical stability and improves electrical and thermal conductivity.
[0055] Embodiments of the present invention may include the following features:
[0056] (i) Flip the die and the package by 90 degrees. Thus, a small, effective, short, large cross-sectional and symmetric connection is provided between the die and the base surface.
[0057] (ii) Use a plated sidewall as the base surface. Thus, the package base surface can be located on the sidewall of the package and supports flipping the package by 90 degrees before assembly. The base surface extending to the sidewall of the package supports LTI inspection.
[0058] (iii) Balanced and symmetric source, drain, and gate connections. This improves efficiency and switching behavior.
[0059] In the following text, embodiments of the present invention are described. Embodiment 1 presents a solution for manufacturing a half-bridge module. Embodiment 2 presents a solution for manufacturing parallel power bare chips. Embodiment 3 presents a solution for how to divide a gallium nitride (GaN) bare chip into smaller strip-sized bare chips and connect multiple smaller GaN bare chips in parallel within a package. Embodiment 4 presents a manufacturing process for how these stacked and 90-degree flipped power components or modules can be manufactured. The ideas presented in the present invention are not limited to these embodiments, and other types of configurations can also be manufactured, such as power stages / DrMOS (driver + LS and HS mosfets), etc. Brief Description of the Drawings
[0060] Other embodiments of the present invention will be described in conjunction with the following drawings, wherein:
[0061] Figure 1 A side view and a cross-sectional view (AB) of a semiconductor package 100 vertically mounted on a PCB 190 provided by the present invention are shown;
[0062] Figure 2 Shows Figure 1 A 3D view of the PCB-mounted semiconductor package 100;
[0063] Figure 3 Cross-sectional views of different embodiments 100a, 100b, 100c, 100d of a semiconductor package vertically mounted on a PCB are shown;
[0064] Figure 4 Two side views 400a, 400b of a half-bridge semiconductor package and two side views 400c, 400d after a 90-degree flip are shown;
[0065] Figure 5 A schematic diagram of an exemplary process flow 500 for producing an embedded power center layer provided by the present invention is shown;
[0066] Figure 6 A schematic diagram of an exemplary process flow 600 for manufacturing a semiconductor package 100 provided by the present invention is shown;
[0067] Figure 7 Different side views of a parallel bare chip package 710 provided by an embodiment are shown, where the bare chips face the same direction;
[0068] Figure 8 Different side views of a parallel bare chip package 810 provided by an embodiment are shown, where the bare chips face different directions;
[0069] Figure 9Shows different side views of a half - bridge package 910 provided by an embodiment;
[0070] Figure 10 Shows a cross - sectional view of a lateral semiconductor device 1000 provided by an embodiment;
[0071] Figure 11 Shows a schematic diagram of a standard square - sized layout 1102 of a power device and an improved rectangular layout 1103 of a power device provided by the present invention;
[0072] Figure 12 Shows a side view 1201, a cross - section 1202, and a base surface 1203 of a semiconductor package with parallel bare chips provided by an embodiment. Detailed Description of the Invention
[0073] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification, and in which are shown by way of illustration specific aspects in which the invention may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.
[0074] It should be understood that the notes related to the described method are equally applicable to the device or system corresponding to the method for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include units for performing the described method step, even if such units are not explicitly described or illustrated in the figures. Additionally, it should be understood that unless otherwise explicitly stated, the features of the various exemplary aspects described herein may be combined with each other.
[0075] Figure 1 Shows a side view and a cross - sectional view (AB) of a semiconductor package 100 vertically mounted on a PCB 190 provided by the present invention.
[0076] The semiconductor package 100 includes: at least one integrated circuit 140, a sealant 150, a first metal layer 110, and a second metal layer 120.
[0077] The at least one integrated circuit 140 includes at least one first connection terminal 141 and at least one second connection terminal 143 for electrical connection of the at least one integrated circuit 140.
[0078] The sealant 150 seals at least a portion of at least one integrated circuit 140. The sealant 150 includes a first major surface 150a and a second major surface 150b opposite to the first major surface 150a, and one or more sidewalls 151, 152, 153, 154 between the first major surface 150a and the second major surface 150b, as visible from Figure 1 as shown.
[0079] The first metal layer 110 is placed on a portion of the first sidewall 151 of one or more sidewalls 151, 152, 153, 154 of the sealant 150. The first metal layer 110 forms a first connector 181 for electrically connecting at least one first connection terminal 141 of at least one integrated circuit 140.
[0080] The second metal layer 120 is placed on another portion of the first sidewall 151 of the sealant 150. The second metal layer 120 forms a second connector 182 for electrically connecting at least one second connection terminal 143 of at least one integrated circuit 140.
[0081] The first connector 181 and the second connector 182 of the semiconductor package 100 are used to connect to corresponding metal traces 191, 192 of a printed circuit board (PCB) 190, as visible from Figure 1 as shown.
[0082] At least one integrated circuit 140 can be a vertical device, such as Figure 1 shown, or a lateral device, such as Figure 10 shown. The device can have three terminals, but only two of them are introduced here.
[0083] The first major surface 150a and the second major surface 150b form two major regions of the semiconductor package 100, and the area covered by each major region is larger than that of any one of the sidewalls of the sealant 150.
[0084] The first metal layer 110 can be placed on a portion of the first sidewall 151 and a portion of the first major surface 150a.
[0085] Similarly, the second metal layer 120 can be placed on another portion of the first sidewall 151 and another portion of the first major surface 150a.
[0086] The first metal layer 110 can be placed on an edge portion of the sealant 150, and the edge portion includes a portion of the first sidewall 151, a portion of the first major surface 150a, and a portion of the second sidewall 152 adjacent to the first sidewall 151, as visible from the left side view of Figure 1 as shown.
[0087] Similarly, the second metal layer 120 can be placed on another edge portion of the sealant 150, which includes another portion of the first sidewall 151, another portion of the first main surface 150a, and a portion of the third sidewall 153 opposite to the second sidewall 152, as visible from Figure 1 the left side view of
[0088] The sealant 150 can include two or more PCB layers, each PCB layer having a first main PCB surface and a second main PCB surface opposite to the first main PCB surface.
[0089] The first main PCB surface and the second main PCB surface in the two or more PCB layers can be arranged parallel to the first main surface 150a and the second main surface 150b of the sealant 150.
[0090] The semiconductor package can include: at least one first via 113 for routing at least one third connection terminal 142 of the first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a, as visible from Figure 1 the right side view of
[0091] As visible from Figure 1 the right side view of, the semiconductor package can include: at least one second via 111 for routing at least one first connection terminal 141 of the first integrated circuit 140 to a portion of the first metal layer 110 placed on the second main surface 150b.
[0092] The semiconductor package 100 can include: at least one first via 113 for routing at least one third connection terminal 142 of the first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a, as visible from Figure 1 the right side view of
[0093] The semiconductor package 100 can include: at least one second via 116 for routing at least one second connection terminal 162 of the second integrated circuit 160 to a portion of the second metal layer 120 placed on the second main surface 150b, as visible from Figure 1 the right side view of
[0094] The first integrated circuit 140 and the second integrated circuit 160 can form a parallel bare die configuration.
[0095] The semiconductor package 100 can include: at least one first via 113 for routing at least one third connection terminal 142 of the first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a, as visible fromFigure 1 visible in the right side view of
[0096] At least one third via 114 can be used to route at least one first connection terminal 161 of the second integrated circuit 160 to a portion of the first metal layer 110 disposed on the second main surface 150b.
[0097] The first integrated circuit 140 and the second integrated circuit 160 can form a half-bridge configuration.
[0098] At least the first integrated circuit 140 and the second integrated circuit 160 can be stacked between the first main surface 150a and the second main surface 150b of the encapsulant 150, as visible from Figure 1 the right side view of
[0099] The aspect ratio of each stacked integrated circuit in the stacked integrated circuits can be greater than or equal to 1. In this configuration (without GaN), the aspect ratio can be 1.
[0100] Figure 1 A second semiconductor package 200, also referred to as the final product, is also shown.
[0101] The second semiconductor package includes: the semiconductor package 100 as described above; a printed circuit board (PCB) 190 including a first metal trace 191 and a second metal trace 192.
[0102] The semiconductor package 100 is mounted on the PCB 190 through a first sidewall 151. A first connector 181 of the PCB 190 is connected to the first metal trace 191, and a second connector 182 of the PCB 190 is connected to the second metal trace 192 of the PCB 190.
[0103] Each of the first main surface 150a and the second main surface 150b of the encapsulant 150 can form an angle with the main surface 195 of the PCB 190, and the angle is within a threshold range of about 90 degrees.
[0104] This means that the encapsulant 150 is arranged at a 90-degree angle to the PCB surface 195, including a small deviation from 90°.
[0105] At least one integrated circuit 140 includes a first main bare chip surface 140a and a second main bare chip surface 140b opposite to the first main bare chip surface 140a. Both the first main bare chip surface 140a and the second main bare chip surface 140b can form an angle with the main surface 195 of the PCB 190, and the angle is within a threshold range of about 90 degrees.
[0106] This means that the bare die is arranged at a 90-degree angle to the PCB surface 195, including a small deviation from 90°.
[0107] The first metal layer 110 can be placed on a part of the first sidewall 151 and a part of the first main surface 150a. Solder fillets 201 can be applied to the first sidewall 151 and the first main surface 150a for electrically and mechanically connecting the semiconductor package 100 to the PCB 190.
[0108] Figure 2 Shows Figure 1 a 3D view of the PCB-mounted semiconductor package 100.
[0109] Figure 2 An embodiment of manufacturing a laminate-based package 100 is shown, which has at least partially metallized sidewalls that can be used as pads. The package 100 can be mounted on a substrate 190, such as a PCB, such that it is flipped 90 degrees (the bare die is vertically inside the package), and the metallized sidewalls are used as pads. The package can include one, two, or several layers with an embedded bare die.
[0110] For example, the pads can be located under the flipped package and at both ends of the flipped package.
[0111] As can be seen from Figure 2 the semiconductor package 100 is vertically mounted on the PCB 190.
[0112] The first metal layer 110 can be placed on a part of the first sidewall 151 and a part of the first main surface 150a. Solder fillets 201 can be applied to the first sidewall 151 and the first main surface 150a or the first sidewall 151 and the second main surface 150b (as Figure 2 shown) for electrically and mechanically connecting the semiconductor package 100 to the PCB 190.
[0113] Figure 3 Cross-sectional views of different embodiments 100a, 100b, 100c, 100d of the semiconductor package vertically mounted on the PCB 190 are shown.
[0114] For all four embodiments, the configuration of the connection terminals corresponds to Figure 1 the configuration of the connection terminals shown.
[0115] Figure 3 Different stacking options and configurations are presented. In addition to the power bare die (also called an integrated circuit here), the package can also include other components, such as drivers, passive devices, etc. The pads can be located under and at both ends of the 90-degree flipped package.
[0116] In a first configuration of semiconductor package 100a, a single die configuration is shown, where the source and drain pads of the die are routed to opposite sides of the flip package. The package may include two or more PCB layers.
[0117] In this first configuration, semiconductor package 100a includes at least one first via 113 for routing a third connection terminal 142 of a single integrated circuit 140 to a portion of a second metal layer 120 placed on a first main surface 150a.
[0118] In this first configuration, semiconductor package 100a includes at least one second via 111 for routing a first connection terminal 141 of a single integrated circuit 140 to a portion of a first metal layer 110 placed on a second main surface 150b.
[0119] In a second configuration of semiconductor package 100b, a multi-die configuration is shown, including three or more dies (or integrated circuits). The dies may be connected in parallel or in other configurations.
[0120] In a third configuration of semiconductor package 100c, a dual-die configuration is shown, where two dies are located within the same package and the dies face different directions. The third configuration shows a parallel die configuration, but it may also be a half-bridge configuration.
[0121] In this third configuration, semiconductor package 100c includes at least one first via 113 for routing at least one third connection terminal 142 of a first integrated circuit 140 to a portion of a second metal layer 120 placed on a first main surface 150a.
[0122] In this third configuration, semiconductor package 100c includes at least one second via 116 for routing at least one second connection terminal 162 of a second integrated circuit 160 to a portion of the second metal layer 120 placed on a second main surface 150b.
[0123] As described above, the first integrated circuit 140 and the second integrated circuit 160 may form a parallel die configuration.
[0124] In a fourth configuration of semiconductor package 100d, a dual-die configuration is shown, where two dies are located within the same package and the dies face the same direction. The third configuration shows a half-bridge configuration. The routing in the figure can be applied to a parallel die configuration, but it can also be applied to a half-bridge configuration.
[0125] In this fourth configuration, the semiconductor package 100d includes at least one first via 113 for routing at least one third connection terminal 142 of the first integrated circuit 140 to a portion of the second metal layer 120 disposed on the first major surface 150a.
[0126] In this fourth configuration, the semiconductor package 100d includes at least one third via 114 for routing at least one first connection terminal 161 of the second integrated circuit 160 to a portion of the first metal layer 110 disposed on the second major surface 150b.
[0127] As described above, the first integrated circuit 140 and the second integrated circuit 160 may form a parallel die configuration (shown here), but they may also form a half - bridge configuration (not shown here).
[0128] Figure 4 Two side views 400a, 400b of a half - bridge semiconductor package and two side views 400c, 400d after a 90 - degree flip are shown. The half - bridge semiconductor package corresponds to the first embodiment of the semiconductor package described above.
[0129] In this example of a stacked half - bridge module, the high side (HS) 401 and the low side (LS) 402 are in different layers and are connected together with a plated sidewall 403 and optionally with a plated - through hole (PTH). After embedding and PCB fabrication, the module is separated and mounted on the final PCB board by flipping the module 90°. The pads are on one side of the module and may also extend to other sides. In side view 400c, two gate pads are labeled GL (gate low side) and GH (gate high side), and terminals VSWH, PGND, and VIN are shown.
[0130] In this first embodiment, a half-bridge package is presented. At least one power die is embedded in a PCB layer, and at least two of these layers are stacked together with the embedded die. The connection between the HS power die and the LS power die can be performed using a plated PTH or a slot that is cut in half during package separation. If needed, additional vias or hybrid bonding can be used to make the connection between the HS and LS more effective. Between the power PCB layers with power dies, additional PCB layers can be added, and these additional PCB layers can include Cu structures or embedded Cu blocks to improve thermal performance. After separation, the module is flipped 90° and mounted on a PCB so that the die is vertically located inside the package. To make the base surface flat, for example, additional wiring or other processes can be used to remove the PCB area between the Cu slots of the wiring. Different kinds of processes for manufacturing plated sidewall connections exist in the PCB industry, and in the present invention, these processes can be used to manufacture plated sidewall connections.
[0131] Figure 5 A schematic diagram of an exemplary process flow 500 for producing an embedded power core provided by the present invention is shown.
[0132] Figure 5 It is shown that at least two power dies 140 are embedded in separate PCB core layers laminated relative to each other, and the components are connected together and connected to the base surface by plated sidewall connections. The plated sidewall connections can be manufactured using plated PTH and ordinary PTH and / or wiring processes. Figure 5 An example of a manufacturing process for how a core layer with embedded components can be manufactured is presented.
[0133] In the embedding process as Figure 5 exemplarily shown, a chip die with a Cu metallization layer is embedded into an opening in the core layer. The opening in the core layer (with or without Cu) can be achieved by, for example, laser cutting (wiring, punching, etc. can also be used). A tape is laminated on the bottom side of the core layer, the die is placed in the opening, and is connected to the tape by a pick-and-place machine.
[0134] After the die is placed, a prepreg sheet and a Cu foil are pre-laminated on the top side of the core layer using a vacuum laminator. Then the adhesive tape is removed, and another prepreg and Cu foil are laminated on the bottom side (during the second lamination, the pre-laminated prepreg is also fully cured). After lamination, vias leading to the die are drilled from both sides using a laser drill. The die is connected, and the vias are filled using electroless and electroplating. Finally, the Cu is structured by photolithography and etching processes.
[0135] This is just an example of a typical embedding process. Other types of embedding processes can also be used. Pre-packaged dies can also be embedded instead of chip dies.
[0136] The processing flow 500 includes multiple processing steps or processing blocks and can be described as follows.
[0137] The first step 501 may include: providing a printed circuit board (PCB), a central layer 520, such as an FR4 laminate, having a top surface and a bottom surface opposite to the top surface.
[0138] The second steps 502, 503 may include: cutting at least one opening 521 in the PCB central layer 520, the at least one opening 521 extending from the top side to the bottom side of the PCB central layer 520. For example, this can be achieved by mechanical drilling, laser cutting, punching, routing, etc.
[0139] The third step 504 may include: connecting an adhesive tape 522 to the PCB central layer 520, for example, by tape lamination, the adhesive tape 522 covering at least one opening 521 of the PCB central layer 520 from the bottom side.
[0140] The fourth step 505 may include: placing at least one electronic chip (e.g., the integrated circuit 140 as shown above) Figures 1 to 4 inside at least one opening 521 of the PCB central layer 520 and connecting at least one electronic chip 140 to the adhesive tape 522.
[0141] The fifth step 506 may include: applying a first laminate layer 523 on the top side of the PCB central layer 520 to form an embedded component package embedding at least one electronic chip 140, the embedded component package 550 including a top side above the top side of the PCB central layer 520 and a bottom side below the bottom side of the PCB central layer 520; and connecting a first metal foil 524, such as a Cu foil connected by lamination, on the top side of the embedded component package 550.
[0142] The sixth step 507 may include: removing the adhesive tape 522 from the bottom side of the embedded component package 550, applying a second laminate layer 525 on the bottom side of the embedded component package 550, and connecting a second metal foil 526, such as a Cu foil connected by lamination, on the bottom side of the embedded component package 550.
[0143] The seventh step 508 may include: cutting at least one micro via 527 in the embedded component package 550, for example, by micro via drilling, to expose at least one first connection terminal of at least one electronic chip 140, e.g., at least one first connection terminal 141 as shown Figures 1 to 4 in.
[0144] The eighth step 509 may include: disposing a photoresist layer 527 on the top side and / or bottom side of the embedded component package 550, for example, by photolithography, and forming one or more openings in the photoresist layer to form a photoresist pattern 528 on the top side and / or bottom side of the embedded component package 550.
[0145] The ninth step 510 may include: metal plating the top side or the bottom side of the embedded component package 550, for example, by pattern plating, to provide electrical and thermal connections for at least one first connection terminal 141 of at least one electronic chip 140 according to the photoresist pattern 528 on the top side or the bottom side of the embedded component package. It should be noted that the structuring at this stage may be completed on only one side, which can be the top side or the bottom side. The structuring of the second side can be carried out after laminating the two layers together. In some cases, both sides can be structured simultaneously. For example, three or more layers are stacked together, or additional stacked layers are laminated on both sides of the package subsequently. For example, see Figure 6 the lamination 601 in
[0146] The tenth step 511 may include: removing the photoresist layer 527 and a part of the first metal foil 524 covered by the photoresist layer from the top side of the embedded component package, and removing (for example, by etching) the photoresist layer and a part of the second metal foil covered by the photoresist layer from the bottom side of the embedded component package 550.
[0147] Figure 6 Fig. shows a schematic diagram of an exemplary process flow 600 for manufacturing the semiconductor package 100 provided by the present invention.
[0148] This process flow 600 corresponds to the fourth embodiment of the above semiconductor package.
[0149] At least two power die chips are embedded in separate PCB cores, and these central layers are laminated together, and the die chips are connected to the plated PTH or slots that are cut in half during the separation of the package. For example, wiring can be used instead of slicing.
[0150] The first steps in the manufacturing process are the lamination 601, 602 and stacking 603 steps, where two central layers with embedded die chips, such as those manufactured as described above with reference to Figure 5 manufacturing (a normal CE / ECP embedding process can be used), are laminated together using a normal PCB vacuum lamination process. The lamination can have additional stacked layers 601 or no stacked layers 602. The lamination can include at least the following layers:
[0151] (1) Cu foil 621, (not required if the central layer with the embedded die chip is structured only from one side);
[0152] (2) Prepreg 622 (not required if the central layer embedding the bare chip is structured from only one side);
[0153] (3) The first embedded central layer with the bare chip 623 embedded;
[0154] (4) Prepreg;
[0155] (5) Additional central layer with or without Cu (to increase the package thickness or improve the wiring ability or thermal performance);
[0156] (6) Prepreg 624;
[0157] (7) The second embedded central layer with the bare chip 625 embedded (can be multiplied many times as needed);
[0158] (8) Cu foil 627, (not required if the central layer embedding the bare chip is structured from only one side);
[0159] (9) Prepreg 626 (not required if the central layer embedding the bare chip is structured from only one side);
[0160] After lamination 603, mechanical drilled vias or wiring slot openings 630 are fabricated (604) on the edge region of the module. After the drilling step, Cu is plated (631) on the sidewalls of the PTH or the slot by normal electroless and electroplating processes 605, and the Cu layer is constructed by normal photolithography and etching processes 606. The package is separated by mechanical slicing or other package separation processes. Slicing starts from the center line 632 of the plated PTH / slot such that one side of the plated sidewall is exposed. Additional wiring processes can be used at least on the base surface side to remove the laminated bridges between the slots to make the base surface flat, easier for assembly and soldering. After separation, the package is flipped (607) 90 degrees so that the bare chips inside the package are vertical.
[0161] At Figure 6 the lower right side of, the 90 - degree flipped package is shown to have a bare chip metallization layer 641, micro - vias 642, and a bare chip profile 643.
[0162] The process of manufacturing a stacked package can use normal PCB and chip embedding processes. This can be used for several different types of packages, such as parallel common source or drain packages, half-bridge packages. Although the die sizes of the half-bridge packages in the figures are the same, the HS die and LS die can also have different sizes. It can also be used for single die and other types of multi-die packages. Various different types of chip embedding or package embedding processes can be used to manufacture a layer with embedded components laminated together. Due to the plated sidewall connection, the component can be flipped 90 degrees, welding is easier, lead tip inspection (LTI) can be performed, and reliability is improved. Due to the large plated sidewall area, the Cu cross-section increases, resulting in a higher current-carrying capacity of the Cu wire and a lower current density. The metallized sidewalls can also be used for effective heat dissipation. 3D stacking can minimize the package size and increase the power density. Package flipping can shorten the signal length from the die to the base surface and balance the connections.
[0163] Figure 7 Different side views of a parallel die package 710 provided by one embodiment are shown, where the dies face the same direction.
[0164] Figure 7 A cross-sectional view of the parallel die package 710 is shown at the bottom. From Figure 7 the left side to the right side of, four different layers L1, L2, L3, and L4 are shown.
[0165] The first layer L1 shows the first metallization layer 701 of the die and the solder mask SM1 706 above the first metallization layer 701.
[0166] The second layer L2 shows the second metallization layer 702 of the die.
[0167] The third layer L3 shows the third metallization layer 703 of the die.
[0168] The fourth layer L4 shows the fourth metallization layer 704 of the die and the solder mask SM2 705 below the fourth metallization layer 704.
[0169] The structure of the parallel die package 710 can correspond to the structure described above in conjunction with Figures 1 to 4 the above.
[0170] Figure 8 Different side views of a parallel die package 810 provided by one embodiment are shown, where, in one example, the dies face different directions. This is just an example, and the metallization and wiring can be done in various different ways.
[0171] Figure 8The bottom shows a cross-sectional view of the parallel bare die package 810. From Figure 8 the left side to the right side of
[0172] the first layer L1 shows the first metallization layer 801 of the bare die, and the solder mask SM1 806 above the first metallization layer 801.
[0173] The second layer L2 shows the second metallization layer 802 of the bare die.
[0174] The third layer L3 shows the third metallization layer 803 of the bare die.
[0175] The fourth layer L4 shows the fourth metallization layer 804 of the bare die and the solder mask SM2 805 below the fourth metallization layer 804.
[0176] The structure of the parallel bare die package 810 can correspond to the structure described above in connection with Figures 1 to 4 the structure.
[0177] Figure 9 The different side views of the half-bridge package 910 provided by one embodiment are shown.
[0178] Figure 9 The bottom shows a cross-sectional view of the half-bridge package 910. From Figure 9 the left side to the right side of
[0179] the first layer L1 shows the first metallization layer 901 of the bare die, and the solder mask SM1 906 above the first metallization layer 901.
[0180] The second layer L2 shows the second metallization layer 902 of the bare die.
[0181] The third layer L3 shows the third metallization layer 903 of the bare die.
[0182] The fourth layer L4 shows the fourth metallization layer 904 of the bare die and the solder mask SM2 905 below the fourth metallization layer 904.
[0183] The structure of the parallel bare die package 810 can correspond to the structure described above in connection with Figures 1 to 4 the structure.
[0184] Figure 10 The cross-sectional view of the lateral semiconductor device 1000 provided by one embodiment is shown.
[0185] The lateral semiconductor device 1000 includes a source terminal 1001, a gate terminal 1003, and a drain terminal 1002 that are placed on one side of the bare chip. Due to the high voltage at the drain terminal 1002, the distance Lgs 1011 between the source terminal 1001 and the gate terminal 1003 is much smaller than the distance Lgd 1012 between the gate terminal 1003 and the drain terminal 1002.
[0186] This lateral power device is inherently restricted by electro-migration (EM) 1010 on the drain side. The mean time to failure can be described by Figure 10 Black's Law as described in
[0187] The lateral semiconductor device 1000 corresponds to the third embodiment of the above semiconductor package.
[0188] The third embodiment describes techniques for how to improve the yield, reliability (electro-migration), and electrical and thermal performance of GaN components. It can be understood that GaN technology is taken as an example here, but it can be extended to any semiconductor device, technology, and concept.
[0189] Figure 11 A schematic diagram showing the standard square size layout 1102 of the power device provided by the present invention and the improved rectangular layout 1103 of the power device is shown.
[0190] The main idea of the above third embodiment is to change the layout configuration of the power semiconductor device, as Figure 11 shown, where GaN HEMT is taken as an example. The standard layout 1102 of the power device is square / rectangular in shape. The reason for this shape is to generate the maximum bare chip size suitable for a given package in order to maximize the current density and cost per bare chip. This leads to three main problems:
[0191] (1) Uneven heat dissipation: Due to the square layout, the temperature of the device is always higher at the center of the bare chip and lower at the periphery during operation. This uneven thermal distribution changes the on-resistance of the bare chip (the center on-resistance is high)
[0192] (2) Electro-migration: To extract drain, source, and gate currents from any power semiconductor device, metal tracks are used. These metal tracks (especially the source and drain tracks) experience high current density; this causes the metal to degrade due to electro-migration (following Figure 10 Black's Law as shown). Since electro-migration depends on current density and temperature (see Figure 10(Black's Law in ), so heat dissipation in the bare chip / device is crucial for keeping the bare chip / device within an acceptable range of electromigration. In a standard square bare chip, the electromigration at the center of the bare chip is poor (because the temperature is high), but the electromigration at the periphery is also good because the current density is high.
[0193] (3) Yield and defect density: The defect density of semiconductor technology (especially emerging technologies) is uncontrolled and high; this not only causes high yield losses during the manufacturing and screening of products, but also leads to a large number of products being returned from the market over time due to device defects. The impact of defect density on large-sized bare chips is greater than that on small-sized bare chips (when the area is small, the probability of defects is small). However, as mentioned above: maximizing the area is crucial for achieving the required current density.
[0194] To overcome the above three problems, a technique is presented to divide the large-sized bare chip 1110 into multiple high-aspect-ratio rectangular bare chips 1111, 1112, 1113, 1114 as shown; stack them and install them in parallel (as described in Embodiments 2 and 3). It should be noted that as shown, dividing into four strips is only exemplary. More or fewer than four strips can also be implemented. The resulting packaged device is as shown. Figure 11 shown; stack them and install them in parallel (as described in Embodiments 2 and 3). It should be noted that as shown, dividing into four strips is only exemplary. More or fewer than four strips can also be implemented. The resulting packaged device is as shown. Figure 11 shown, dividing into four strips is only exemplary. More or fewer than four strips can also be implemented. The resulting packaged device is as shown. Figure 11 shown.
[0195] In addition to the improvements made, Embodiment 3 supports the application of redundancy in highly demanding applications such as space and automotive. Moreover, different from standard devices, in standard devices, defects can cause the destruction of the entire product. In this case, since several bare chips are in parallel, if one bare chip is defective, the remaining bare chips can still be used.
[0196] Embodiment 3 can have the following advantages:
[0197] (1) It can achieve the same current capacity and area as a standard bare chip;
[0198] (2) Due to the relaxation of the thermal boundary, heat dissipation is improved;
[0199] (3) The constraints of electromigration can be reduced (the same at the edge and the center);
[0200] (4) In terms of technology (foundry processing), small bare chips are easier to manufacture, thus improving the yield and reducing the defect density, etc.;
[0201] (5) In terms of packaging, the terminal connections can be balanced and the signal lengths are symmetric;
[0202] (6) It can improve the product's functionality (only partially damaged). It can be used as redundancy in highly sensitive applications.
[0203] Figure 12 A side view 1201, a cross-section 1202, and a base surface 1203 of a semiconductor package with parallel bare chips provided by an embodiment are shown. Such a semiconductor device with parallel bare chips corresponds to the second embodiment of the above semiconductor package.
[0204] In this second embodiment, a technique for paralleling multiple power bare chips 1210, 1211, 1212, 1213, 1214 is presented. At least one power bare chip 1210 is embedded in the PCB layer 1220, and two or more layers are stacked with the embedded bare chip. For example, these power bare chips can be GaN power bare chips.
[0205] The connection between the embedded bare chips is made using plated-through vias 1220 or PTHs that are cut in half during package separation. If necessary, additional vias or hybrid bonding can be used to improve the connection between the parallel source pads and drain pads.
[0206] Between the power PCB layers with power bare chips, additional PCB layers that can include Cu structures or embedded Cu blocks can be added to improve thermal performance. After separation, the module is flipped 90° and mounted on the PCB so that the bare chips are vertically located inside the package.
[0207] To make the base surface flat, for example, additional wiring or other processes can be used to remove the PCB area between the Cu slots of the wiring. For this purpose, there are different types of processes in the PCB industry. The advantage of this technique is that all connections between the source, drain, and gate are symmetric and well-balanced.
[0208] Although a particular feature or aspect of the present invention may have been disclosed only in connection with one of several implementations, such a feature or aspect can be combined with one or more other features or aspects in other implementations, as long as it is needed or advantageous for any given or specific application. Additionally, to a certain extent, when the terms "comprising", "having", "including" or other variations of these words are used in the detailed description or claims, such terms are similar to the term "including" and all mean including. Similarly, the terms "exemplary", "for example" are only meant as examples and not the best or optimal. The terms "coupled" and "connected" and their derivatives can be used. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or whether they are not in direct contact with each other.
[0209] Although specific aspects have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent implementations may be made without departing from the scope of the invention from the specific aspects shown and described. This application is intended to cover any modifications or variations of the specific aspects discussed herein.
[0210] Although the elements in the following claims are recited in a particular order with corresponding labels, these elements need not be implemented in that particular order unless the claim recitation implies a specific order for implementing some or all of these elements.
[0211] In light of the above guidance, many alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that there are many applications of the invention other than those described herein. Although the invention has been described with reference to one or more specific embodiments, those skilled in the art will recognize that many changes can be made to the invention without departing from its scope. Accordingly, it should be understood that the invention may be implemented in ways different from those specifically described herein, so long as it is within the scope of the appended claims and their equivalents.
Claims
1. A semiconductor package (100), characterized in that, Comprising: At least one integrated circuit (140), including at least one first connection terminal (141) and at least one second connection terminal (143) for electrical connection of the at least one integrated circuit (140); A sealant (150) that seals at least a portion of the at least one integrated circuit (140), the sealant (150) including a first major surface (150a) and a second major surface (150b) opposite to the first major surface (150a), and one or more side walls (151 to 154) between the first major surface (150a) and the second major surface (150b); A first metal layer (110) placed on a portion of a first side wall (151) of the one or more side walls (151 to 154) of the sealant (150), wherein the first metal layer (110) forms a first connector (181) for electrically connecting the at least one first connection terminal (141) of the at least one integrated circuit (140); A second metal layer (120) placed on another portion of the first side wall (151) of the sealant (150), wherein the second metal layer (120) forms a second connector (182) for electrically connecting the at least one second connection terminal (143) of the at least one integrated circuit (140); Wherein, the first connector (181) and the second connector (182) of the semiconductor package (100) are for connection to corresponding metal traces (191, 192) of a printed circuit board (PCB) (190).
2. The semiconductor package (100) according to claim 1, characterized in that The first major surface (150a) and the second major surface (150b) form two major regions of the semiconductor package (100), and the area covered by each major region is larger than the area of any one of the side walls of the sealant (150).
3. The semiconductor package (100) according to claim 1 or 2, characterized in that The first metal layer (110) is placed on the portion of the first side wall (151) and a portion of the first major surface (150a); and / or The second metal layer (120) is placed on the another portion of the first side wall (151) and another portion of the first major surface (150a).
4. The semiconductor package (100) according to claim 3, characterized in that The first metal layer (110) is placed on an edge portion of the sealant (150), the edge portion including the portion of the first side wall (151), the portion of the first major surface (150a), and a portion of a second side wall (152) adjacent to the first side wall (151); and / or The second metal layer (120) is placed on another edge portion of the sealant (150), and the another edge portion includes the another part of the first sidewall (151), the another part of the first main surface (150a), and a part of a third sidewall (153) opposite to the second sidewall (152).
5. The semiconductor package (100) according to any one of the above claims, wherein the sealant (150) includes two or more PCB layers, and each PCB layer has a first main PCB surface and a second main PCB surface opposite to the first main PCB surface; the first main PCB surfaces and the second main PCB surfaces of the two or more PCB layers are arranged parallel to the first main surface (150a) and the second main surface (150b) of the sealant (150).
6. The semiconductor package (100a) according to any one of the above claims, characterized in that, Comprising: at least one first via (113) for routing at least one third connection terminal (142) of the first integrated circuit (140) to a part of the second metal layer (120) placed on the first main surface (150a); at least one second via (111) for routing at least one first connection terminal (141) of the first integrated circuit (140) to a part of the first metal layer (110) placed on the second main surface (150b).
7. The semiconductor package (100c) according to any one of claims 1 to 6, characterized in that, Comprising: at least one first via (113) for routing at least one third connection terminal (142) of the first integrated circuit (140) to a part of the second metal layer (120) placed on the first main surface (150a); at least one second via (116) for routing at least one second connection terminal (162) of the second integrated circuit (160) to a part of the second metal layer (120) placed on the second main surface (150b).
8. The semiconductor package (100c) according to claim 7, wherein the first integrated circuit (140) and the second integrated circuit (160) form a parallel die configuration.
9. The semiconductor package (100d) according to any one of claims 1 to 6, characterized in that, Comprising: at least one first via (113) for routing at least one third connection terminal (142) of the first integrated circuit (140) to a part of the second metal layer (120) placed on the first main surface (150a); at least one third via (114) for routing at least one first connection terminal (161) of the second integrated circuit (160) to a part of the first metal layer (110) placed on the second main surface (150b).
10. The semiconductor package (100d) according to claim 9, wherein the first integrated circuit (140) and the second integrated circuit (160) form a half-bridge configuration.
11. The semiconductor package (100) according to any one of claims 6 to 10, wherein At least the first integrated circuit (140) and the second integrated circuit (160) are stacked between the first major surface (150a) and the second major surface (150b) of the sealant (150).
12. The semiconductor package (100) according to any one of claims 6 to 11, wherein the aspect ratio of each of the stacked integrated circuits in the stacked integrated circuits is greater than 1.
13. A second semiconductor package (200), characterized in that, Comprising: the semiconductor package (100) according to any one of the above claims; a printed circuit board (PCB) (190), comprising a first metal trace (191) and a second metal trace (192); the semiconductor package (100) is mounted on the PCB (190) through the first sidewall (151), the first connector (181) of the PCB (190) is connected to the first metal trace (191) and the second connector (182) of the PCB (190) is connected to the second metal trace (192) of the PCB (190).
14. The second semiconductor package (200) according to claim 13, wherein each of the first major surface (150a) and the second major surface (150b) of the sealant (150) forms an angle with the major surface (195) of the PCB (190), and the angle is within a threshold range of about 90 degrees.
15. The second semiconductor package (200) according to claim 13 or 14, wherein the at least one integrated circuit (140) includes a first major bare chip surface (140a) and a second major bare chip surface (140b) opposite to the first major bare chip surface (140a); the first major bare chip surface (140a) and the second major bare chip surface (140b) form an angle with the major surface (195) of the PCB (190), and the angle is within a threshold range of about 90 degrees.
16. The second semiconductor package (200) according to any one of claims 13 to 15, wherein the first metal layer (110) is placed on the portion of the first sidewall (151) and a part of the first major surface (150a); a soldering fillet (201) is applied to the first sidewall (151) and the first major surface (150a) for electrically and mechanically connecting the semiconductor package (100) to the PCB (190).