Three-dimensional memory devices including composite dielectric isolation structures in step regions and methods of forming same

Abstract

A three-dimensional memory device includes a laterally spaced vertical stack of conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between adjacent pairs of vertical stacks. The composite dielectric isolation structure includes at least one etchback stepped dielectric material portion, and can further include at least one fin insulating support structure or a vertical stack of dielectric material plates.

Description

[0001] Related Applications

[0002] This application claims the priority benefit of U.S. Provisional Patent Application No. 63 / 492,566, filed Mar. 28, 2023, and U.S. Provisional Patent Application No. 63 / 492,569, filed Mar. 28, 2023. The entire contents of these U.S. Provisional Patent Applications are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three-dimensional memory devices including a composite dielectric isolation structure in a stepped region and methods of forming the same. Background Art

[0004] A three-dimensional memory device including a three-dimensional vertical NAND string having one bit per cell is disclosed in an article by T. Endoh et al., titled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" (IEDM Proc. (2001) 33-36). Summary of the Invention

[0005] According to an embodiment of the present disclosure, a three-dimensional memory device includes: insulating layers that are vertically spaced apart from each other and continuously extend laterally between a first type-one lateral isolation trench filling structure and a second type-one lateral isolation trench filling structure, the first type-one lateral isolation trench filling structure and the second type-one lateral isolation trench filling structure extending laterally along a first horizontal direction and being laterally spaced apart from each other along a second horizontal direction; a first conductive layer that is vertically interleaved with the insulating layer and contacts the first type-one lateral isolation trench filling structure; a second conductive layer that is vertically interleaved with the insulating layer and contacts the second type-one lateral isolation trench filling structure; and a composite dielectric isolation structure that is located between the first conductive layer and the second conductive layer and includes a re-entrant stepped dielectric material portion, a vertical stack of dielectric material plates, and a pair of type-two lateral isolation trench filling structures that are laterally spaced apart along the first horizontal direction.

[0006] According to another aspect of the present disclosure, a three-dimensional memory device is provided. The three-dimensional memory device includes: an insulating layer that is vertically spaced apart from each other and extends continuously laterally between a first first-type lateral isolation trench filling structure and a second first-type lateral isolation trench filling structure. The first first-type lateral isolation trench filling structure and the second first-type lateral isolation trench filling structure extend laterally along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction; a first conductive layer that is vertically interleaved with the insulating layer and contacts the first first-type lateral isolation trench filling structure; a second conductive layer that is vertically interleaved with the insulating layer and contacts the second first-type lateral isolation trench filling structure; and a composite dielectric isolation structure that is located between the first conductive layer and the second conductive layer. The composite dielectric isolation structure includes a re-entrant stepped dielectric material portion and a pair of fin-type insulating support structures. Each fin-type insulating support structure includes a corresponding vertically extending insulating core and a corresponding vertical stack of insulating fins that extend laterally outward from the corresponding vertically extending insulating core.

[0007] According to still another aspect of the present disclosure, a three-dimensional memory device is provided. The three-dimensional memory device includes: a first alternating stack of a first insulating layer and a first conductive layer and a second alternating stack of a second insulating layer and a second conductive layer. The first alternating stack and the second alternating stack are located between a pair of first-type lateral isolation trench filling structures. The pair of first-type lateral isolation trench filling structures extend laterally along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction; and a composite dielectric isolation structure that is located between the first alternating stack and the second alternating stack and includes: a pair of re-entrant stepped dielectric material portions, an insulating support structure including a vertical insulating wall portion located between the pair of re-entrant stepped dielectric material portions, and a pair of second-type lateral isolation trench filling structures that are laterally spaced apart along the first horizontal direction by the insulating support structure.

[0008] In accordance with yet another aspect of the present disclosure, a method includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a lateral isolation trench through the alternating stack, wherein the lateral isolation trench includes a first type of lateral isolation trench that extends continuously laterally along a first horizontal direction through a contact region and a plurality of pairs of second type of lateral isolation trenches that are staggered with the first type of lateral isolation trench along a second horizontal direction, wherein each pair of the second type of lateral isolation trenches is laterally spaced apart from each other by a gap along the first horizontal direction, and the gap is located within the contact region; forming an etch stop liner at an end portion of the second type of lateral isolation trench that is located within the contact region, such that the etch stop liner is absent from a plurality of portions of the second type of lateral isolation trench that are remote from the contact region and the etch stop liner is absent within the first type of lateral isolation trench; and replacing a plurality of portions of the sacrificial material layer with a conductive layer, wherein each vertical stack of the conductive layer is formed between the nearest first type of lateral isolation trench within the first type of lateral isolation trench and the nearest pair of the second type of lateral isolation trenches within the plurality of pairs of the second type of lateral isolation trenches, and does not extend laterally along the second horizontal direction farther than the nearest first type of lateral isolation trench and the nearest pair of the second type of lateral isolation trenches.

[0009] In accordance with another aspect of the present disclosure, a method includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a cavity through the alternating stack; forming fin grooves around the cavity by isotropically laterally recessing the sacrificial material layer; forming fin-type insulating support structures within the volume of the fin grooves and the cavity; forming a lateral isolation trench through the alternating stack, wherein the lateral isolation trench includes a first type of lateral isolation trench that extends laterally along a first horizontal direction through a contact region and a plurality of pairs of second type of lateral isolation trenches that are staggered with the first type of lateral isolation trench along a second horizontal direction, wherein each pair of the second type of lateral isolation trenches is laterally spaced apart from each other along the first horizontal direction by at least one of the fin-type insulating support structures within the fin-type insulating support structures; forming a laterally extending cavity by performing an isotropic etching process that isotropically recesses the sacrificial material layer by providing an isotropic etchant into the first type of lateral isolation trench and the plurality of pairs of the second type of lateral isolation trenches; and forming a vertical stack of a conductive layer within the laterally extending cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a plan view of an exemplary semiconductor die including a plurality of three-dimensional memory array regions in accordance with an embodiment of the present disclosure.

[0011] Figure 2A first exemplary structure for forming a semiconductor die after forming an optional semiconductor device, an optional underlying dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, and an alternating layer stack of an insulating layer and a sacrificial material layer, in accordance with a first embodiment of the present disclosure, in Figure 1 a vertical cross-sectional view of region M1 in

[0012] Figure 3A a vertical cross-sectional view of a first exemplary structure after forming a stepped cavity, in accordance with a first embodiment of the present disclosure.

[0013] Figure 3B is Figure 3A a top cross-sectional view of a first exemplary structure of Figure 3A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0014] Figure 3C is a vertical cross-sectional view along the Figure 3B vertical plane C-C' of

[0015] Figure 4A a vertical cross-sectional view of a first exemplary structure after forming an etch-back stepped dielectric material portion, in accordance with a first embodiment of the present disclosure.

[0016] Figure 4B is Figure 4A a top cross-sectional view of a first exemplary structure of Figure 4A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0017] Figure 5A a vertical cross-sectional view of a first exemplary structure after forming a support pillar structure, in accordance with a first embodiment of the present disclosure.

[0018] Figure 5B is Figure 5A a top cross-sectional view of a first exemplary structure of Figure 5A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0019] Figure 6A a vertical cross-sectional view of a first exemplary structure after forming a memory opening, in accordance with a first embodiment of the present disclosure.

[0020] Figure 6B is Figure 6A a top cross-sectional view of a first exemplary structure of Figure 6A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0021] Figures 7A to 7F a sequential vertical cross-sectional view of a region around a memory opening during formation of a memory opening fill structure, in accordance with a first embodiment of the present disclosure.

[0022] Figure 8A A vertical cross-sectional view of a first exemplary structure after forming a memory opening filling structure according to a first embodiment of the present disclosure.

[0023] Figure 8B is Figure 8A A top cross-sectional view of the first exemplary structure of. The vertical plane A-A' is Figure 8A The cutting plane of the vertical cross-sectional view of.

[0024] Figure 9A A vertical cross-sectional view of a first exemplary structure after forming a lateral isolation trench according to a first embodiment of the present disclosure.

[0025] Figure 9B is Figure 9A A top cross-sectional view of the first exemplary structure of. The vertical plane A-A' is Figure 9A The cutting plane of the vertical cross-sectional view of.

[0026] Figure 9C is along Figure 9B A vertical cross-sectional view along the vertical plane C-C' of.

[0027] Figure 10A A vertical cross-sectional view of a first exemplary structure after forming an etch stop layer according to a first embodiment of the present disclosure.

[0028] Figure 10B is Figure 10A A top cross-sectional view of the first exemplary structure of. The vertical plane A-A' is Figure 10A The cutting plane of the vertical cross-sectional view of.

[0029] Figure 11A A vertical cross-sectional view of a first exemplary structure after patterning the etch stop layer according to a first embodiment of the present disclosure.

[0030] Figure 11B is Figure 11A A top cross-sectional view of the first exemplary structure of. The vertical plane A-A' is Figure 11A The cutting plane of the vertical cross-sectional view of.

[0031] Figure 12A A vertical cross-sectional view of a first exemplary structure after removing the patterned photoresist layer according to a first embodiment of the present disclosure.

[0032] Figure 12B is Figure 12A A top cross-sectional view of the first exemplary structure of. The vertical plane A-A' is Figure 12A The cutting plane of the vertical cross-sectional view of.

[0033] Figure 12C is a horizontal cross-sectional view of a first exemplary structure along the Figure 12A horizontal plane C-C'.

[0034] Figure 12D is a horizontal cross-sectional view of a first exemplary structure along the Figure 12A horizontal plane D-D'.

[0035] Figure 13A is a vertical cross-sectional view of a first exemplary structure after forming a laterally extending cavity according to a first embodiment of the present disclosure.

[0036] Figure 13B is Figure 13A a top cross-sectional view of a first exemplary structure. The vertical plane A-A' is Figure 13A the cutting plane of the vertical cross-sectional view.

[0037] Figure 13C is a horizontal cross-sectional view of a first exemplary structure along the Figure 13A horizontal plane C-C'.

[0038] Figure 13D is a horizontal cross-sectional view of a first exemplary structure along the Figure 13A horizontal plane D-D'.

[0039] Figure 13E is a horizontal cross-sectional view of a first exemplary structure along the Figure 13A horizontal plane E-E'.

[0040] Figure 13F is a vertical cross-sectional view of a first exemplary structure along the Figure 13B vertical plane F-F'.

[0041] Figure 13G is a vertical cross-sectional view of a first exemplary structure along the Figure 13B vertical plane G-G'.

[0042] Figure 13H is a vertical cross-sectional view of a first exemplary structure along the Figure 13B vertical plane H-H'.

[0043] Figure 14A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to a first embodiment of the present disclosure.

[0044] Figure 14B is Figure 14A a top cross-sectional view of a first exemplary structure. The vertical plane A-A' is Figure 14A the cutting plane of the vertical cross-sectional view.

[0045] Figure 14C is a horizontal cross-sectional view of a first exemplary structure along the Figure 14A horizontal plane C-C'.

[0046] Figure 14D is a horizontal cross-sectional view of a first exemplary structure along the Figure 14A horizontal plane D-D'.

[0047] Figure 14E is a horizontal cross-sectional view of a first exemplary structure along the Figure 14A horizontal plane E-E'.

[0048] Figure 14F is a vertical cross-sectional view of a first exemplary structure along the Figure 14E vertical plane F-F'.

[0049] Figure 14G is a vertical cross-sectional view of a first exemplary structure along the Figure 14B vertical plane G-G'.

[0050] Figure 14H is a vertical cross-sectional view of a first exemplary structure along the Figure 14B vertical plane H-H'.

[0051] Figure 15A is a vertical cross-sectional view of a first exemplary structure after removing the horizontal extension of the etch stop layer according to the first embodiment of the present disclosure.

[0052] Figure 15B is Figure 15A a top-down cross-sectional view of a first exemplary structure. The vertical plane A-A' is Figure 15A the cutting plane of the vertical cross-sectional view.

[0053] Figure 16A is a vertical cross-sectional view of a first exemplary structure after forming a lateral isolation trench filling structure according to the first embodiment of the present disclosure.

[0054] Figure 16B is Figure 16A a top-down cross-sectional view of a first exemplary structure. The vertical plane A-A' is Figure 16A the cutting plane of the vertical cross-sectional view.

[0055] Figure 17A is a vertical cross-sectional view of a first exemplary structure after forming a contact via structure according to the first embodiment of the present disclosure.

[0056] Figure 17B is Figure 17A a top-down cross-sectional view of a first exemplary structure. The vertical plane A-A' is Figure 17A the cutting plane of the vertical cross-sectional view.

[0057] Figure 17C is the vertical cross-sectional view of the first exemplary structure along the Figure 17B vertical plane C-C'.

[0058] Figure 17D is the vertical cross-sectional view of the first exemplary structure along the Figure 17B vertical plane D-D'.

[0059] Figure 17E is the vertical cross-sectional view of the first exemplary structure along the Figure 17B vertical plane E-E'.

[0060] Figure 17F is the vertical cross-sectional view of the first exemplary structure along the Figure 17B vertical plane F-F'.

[0061] Figure 18A is the vertical cross-sectional view of an alternative configuration of the first exemplary structure after patterning the etch stop layer according to the first embodiment of the present disclosure.

[0062] Figure 18B is Figure 18A the top-down cross-sectional view of an alternative configuration of the first exemplary structure. The vertical plane A-A' is Figure 18A the cutting plane of the vertical cross-sectional view.

[0063] Figure 19A is the vertical cross-sectional view of an alternative configuration of the first exemplary structure after forming the contact via structure according to the first embodiment of the present disclosure.

[0064] Figure 19B is Figure 19A the top-down cross-sectional view of the first exemplary structure. The vertical plane A-A' is Figure 19A the cutting plane of the vertical cross-sectional view.

[0065] Figure 19C is the vertical cross-sectional view of the first exemplary structure along the Figure 19B vertical plane C-C'.

[0066] Figure 19D is the vertical cross-sectional view of the first exemplary structure along the Figure 19B vertical plane D-D'.

[0067] Figure 19E is the vertical cross-sectional view of the first exemplary structure along the Figure 19B vertical plane E-E'.

[0068] Figure 19F is the vertical cross-sectional view of the first exemplary structure along the Figure 19BVertical cross-sectional view of a first exemplary structure of the vertical plane F-F'.

[0069] Figure 20A Is a vertical cross-sectional view of a second exemplary structure after forming the lateral isolation trench and the access cavity according to the second embodiment of the present disclosure.

[0070] Figure 20B Is Figure 20A Top cross-sectional view of the second exemplary structure. The vertical plane A-A' is Figure 20A The cutting plane of the vertical cross-sectional view.

[0071] Figure 20C Is along Figure 20B Vertical cross-sectional view of the second exemplary structure of the vertical plane C-C'.

[0072] Figure 21A Is a vertical cross-sectional view of a second exemplary structure after forming the sacrificial lateral isolation trench filling structure according to the second embodiment of the present disclosure.

[0073] Figure 21B Is Figure 21A Top cross-sectional view of the second exemplary structure. The vertical plane A-A' is Figure 21A The cutting plane of the vertical cross-sectional view.

[0074] Figure 21C Is along Figure 21B Vertical cross-sectional view of the second exemplary structure of the vertical plane C-C'.

[0075] Figure 22A Is a vertical cross-sectional view of a second exemplary structure after forming the fin groove according to the second embodiment of the present disclosure.

[0076] Figure 22B Is Figure 22A Top cross-sectional view of the second exemplary structure. The vertical plane A-A' is Figure 22A The cutting plane of the vertical cross-sectional view.

[0077] Figure 22C Is along Figure 22B Vertical cross-sectional view of the second exemplary structure of the vertical plane C-C'.

[0078] Figure 22D Is along Figure 22B Vertical cross-sectional view of the second exemplary structure of the vertical plane D-D'.

[0079] Figure 23A Is a vertical cross-sectional view of a second exemplary structure after forming the fin-type insulating support structure according to the second embodiment of the present disclosure.

[0080] Figure 23B is Figure 23A a top cross-sectional view of a second exemplary structure of Figure 23A . The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0081] Figure 23C is the vertical cross-sectional view of the second exemplary structure along the vertical plane C-C' of Figure 23B .

[0082] Figure 23D is the vertical cross-sectional view of the second exemplary structure along the vertical plane D-D' of Figure 23B .

[0083] Figure 24A is the vertical cross-sectional view of the second exemplary structure after removing the sacrificial lateral isolation trench filling structure and forming a laterally extending cavity according to a second embodiment of the present disclosure.

[0084] Figure 24B is Figure 24A a top cross-sectional view of a second exemplary structure of Figure 24A . The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0085] Figure 24C is the vertical cross-sectional view of the second exemplary structure along the vertical plane C-C' of Figure 24B .

[0086] Figure 24D is the vertical cross-sectional view of the second exemplary structure along the vertical plane D-D' of Figure 24B .

[0087] Figure 24E is the vertical cross-sectional view of the second exemplary structure along the vertical plane E-E' of Figure 24B .

[0088] Figure 24F is the vertical cross-sectional view of the second exemplary structure along the vertical plane F-F' of Figure 24B .

[0089] Figure 24G is the horizontal cross-sectional view of the second exemplary structure along the horizontal plane G-G' of Figure 24A .

[0090] Figure 24H is the horizontal cross-sectional view of the second exemplary structure along the horizontal plane H-H' of Figure 24A .

[0091] Figure 24I is the horizontal cross-sectional view of the second exemplary structure along the horizontal plane I-I' of Figure 24A .

[0092] Figure 25A is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer according to a second embodiment of the present disclosure.

[0093] Figure 25B is Figure 25A a top cross-sectional view of a second exemplary structure. The vertical plane A-A' is Figure 25A the cutting plane of the vertical cross-sectional view.

[0094] Figure 25C is a vertical cross-sectional view of a second exemplary structure along the Figure 25B vertical plane C-C' of

[0095] Figure 25D is a vertical cross-sectional view of a second exemplary structure along the Figure 25B vertical plane D-D' of

[0096] Figure 25E is a vertical cross-sectional view of a second exemplary structure along the Figure 25B vertical plane E-E' of

[0097] Figure 25F is a vertical cross-sectional view of a second exemplary structure along the Figure 25B vertical plane F-F' of

[0098] Figure 25G is a horizontal cross-sectional view of a second exemplary structure along the Figure 25A horizontal plane G-G' of

[0099] Figure 25H is a horizontal cross-sectional view of a second exemplary structure along the Figure 25A horizontal plane H-H' of

[0100] Figure 25I is a horizontal cross-sectional view of a second exemplary structure along the Figure 25A horizontal plane I-I' of

[0101] Figure 26A is a vertical cross-sectional view of a second exemplary structure after forming a lateral isolation trench filling structure according to a second embodiment of the present disclosure.

[0102] Figure 26B is Figure 26A a top cross-sectional view of a second exemplary structure. The vertical plane A-A' is Figure 26A the cutting plane of the vertical cross-sectional view.

[0103] Figure 26C is a vertical cross-sectional view of a second exemplary structure along the Figure 26B vertical plane C-C' of

[0104] Figure 27A It is a vertical cross-sectional view of a second exemplary structure after forming a contact via structure according to a second embodiment of the present disclosure.

[0105] Figure 27B It is Figure 27A a top-down cross-sectional view of the second exemplary structure of. The vertical plane A-A' is Figure 27A the cutting plane of the vertical cross-sectional view of.

[0106] Figure 27C It is along Figure 27B a vertical cross-sectional view of the second exemplary structure along the vertical plane C-C' of.

[0107] Figure 27D It is along Figure 27B a vertical cross-sectional view of the second exemplary structure along the vertical plane D-D' of.

[0108] Figure 27E It is along Figure 27B a vertical cross-sectional view of the second exemplary structure along the vertical plane E-E' of.

[0109] Figure 28A It is a vertical cross-sectional view of a third exemplary structure after forming a lateral isolation trench according to a third embodiment of the present disclosure.

[0110] Figure 28B It is Figure 28A a top-down cross-sectional view of the third exemplary structure of. The vertical plane A-A' is Figure 28A the cutting plane of the vertical cross-sectional view of.

[0111] Figure 28C It is along Figure 28B a vertical cross-sectional view of the third exemplary structure along the vertical plane C-C' of.

[0112] Figure 29A It is a vertical cross-sectional view of a third exemplary structure after forming a sacrificial lateral isolation trench filling structure according to a third embodiment of the present disclosure.

[0113] Figure 29B It is Figure 29A a top-down cross-sectional view of the third exemplary structure of. The vertical plane A-A' is Figure 29A the cutting plane of the vertical cross-sectional view of.

[0114] Figure 29C It is along Figure 29B a vertical cross-sectional view of the third exemplary structure along the vertical plane C-C' of.

[0115] Figure 30AIs a vertical cross-sectional view of a third exemplary structure after forming fin grooves according to a third embodiment of the present disclosure.

[0116] Figure 30B Is Figure 30A A top cross-sectional view of the third exemplary structure of. The vertical plane A-A' is Figure 30A The cutting plane of the vertical cross-sectional view of.

[0117] Figure 30C Is along Figure 30B A vertical cross-sectional view of the third exemplary structure along the vertical plane C-C' of.

[0118] Figure 30D Is along Figure 30B A vertical cross-sectional view of the third exemplary structure along the vertical plane D-D' of.

[0119] Figure 30E Is along Figure 30B A vertical cross-sectional view of the third exemplary structure along the vertical plane E-E' of.

[0120] Figure 31A Is a vertical cross-sectional view of a third exemplary structure after forming a fin-type insulating support structure according to a third embodiment of the present disclosure.

[0121] Figure 31B Is Figure 31A A top cross-sectional view of the third exemplary structure of. The vertical plane A-A' is Figure 31A The cutting plane of the vertical cross-sectional view of.

[0122] Figure 31C Is along Figure 31B A vertical cross-sectional view of the third exemplary structure along the vertical plane C-C' of.

[0123] Figure 31D Is along Figure 31B A vertical cross-sectional view of the third exemplary structure along the vertical plane D-D' of.

[0124] Figure 31E Is along Figure 31B A vertical cross-sectional view of the third exemplary structure along the vertical plane E-E' of.

[0125] Figure 32A Is a vertical cross-sectional view of a third exemplary structure after removing a sacrificial lateral isolation trench filling structure and forming a laterally extending cavity according to a third embodiment of the present disclosure.

[0126] Figure 32B Is Figure 32A A top cross-sectional view of the third exemplary structure of. The vertical plane A-A' is Figure 32A The cutting plane of the vertical cross-sectional view of.

[0127] Figure 32C is along Figure 32B a vertical cross-sectional view of a third exemplary structure in the vertical plane C-C'.

[0128] Figure 32D is along Figure 32B a vertical cross-sectional view of a third exemplary structure in the vertical plane D-D'.

[0129] Figure 32E is along Figure 32B a vertical cross-sectional view of a third exemplary structure in the vertical plane E-E'.

[0130] Figure 32F is along Figure 32A a horizontal cross-sectional view of a third exemplary structure in the horizontal plane F-F'.

[0131] Figure 32G is along Figure 32A a horizontal cross-sectional view of a third exemplary structure in the horizontal plane G-G'.

[0132] Figure 32H is along Figure 32A a horizontal cross-sectional view of a third exemplary structure in the horizontal plane H-H'.

[0133] Figure 33A is a vertical cross-sectional view of a third exemplary structure after forming a conductive layer according to a third embodiment of the present disclosure.

[0134] Figure 33B is Figure 33A a top cross-sectional view of a third exemplary structure. The vertical plane A-A' is Figure 33A the cutting plane of the vertical cross-sectional view.

[0135] Figure 33C is along Figure 33B a vertical cross-sectional view of a third exemplary structure in the vertical plane C-C'.

[0136] Figure 33D is along Figure 33B a vertical cross-sectional view of a third exemplary structure in the vertical plane D-D'.

[0137] Figure 33E is along Figure 33B a vertical cross-sectional view of a third exemplary structure in the vertical plane E-E'.

[0138] Figure 33F is along Figure 33A a horizontal cross-sectional view of a third exemplary structure in the horizontal plane F-F'.

[0139] Figure 33G is a horizontal cross-sectional view of a third exemplary structure along a horizontal plane G-G' of Figure 33A .

[0140] Figure 33H is a horizontal cross-sectional view of a third exemplary structure along a horizontal plane H-H' of Figure 33A .

[0141] Figure 34A is a vertical cross-sectional view of a third exemplary structure after forming a lateral isolation trench filling structure according to a third embodiment of the present disclosure.

[0142] Figure 34B is Figure 34A a top-down cross-sectional view of a third exemplary structure of Figure 34A . The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0143] Figure 34C is a vertical cross-sectional view of a third exemplary structure along a vertical plane C-C' of Figure 34B .

[0144] Figure 35A is a vertical cross-sectional view of a third exemplary structure after forming a contact via structure according to a third embodiment of the present disclosure.

[0145] Figure 35B is Figure 35A a top-down cross-sectional view of a third exemplary structure of Figure 35A . The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0146] Figure 35C is a vertical cross-sectional view of a third exemplary structure along a vertical plane C-C' of Figure 35B .

[0147] Figure 35D is a vertical cross-sectional view of a third exemplary structure along a vertical plane D-D' of Figure 35B .

[0148] Figure 35E is a vertical cross-sectional view of a third exemplary structure along a vertical plane E-E' of Figure 35B . DETAILED DESCRIPTION

[0149] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device that includes composite dielectric isolation structures in a stepped region that provide support during replacement of a sacrificial material layer with a conductive layer. Various aspects of the three-dimensional memory device are now described in detail.

[0150] The accompanying drawings are not drawn to scale. In the case of illustrating a single instance of an element, multiple instances of the element may be replicated unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0151] Like reference numerals designate like or similar elements. Unless otherwise indicated, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise indicated, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or are not in direct contact with each other, the two elements are "separated" from each other or are "separated" from each other. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" located "on" the second element. As used herein, if there is an electrical conduction path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "work-in-progress" structure refers to an instantaneous structure in which the shape or composition of at least one component is subsequently modified.

[0152] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entirety of a structure below or above, or its extent may be less than the extent of the structure below or above. Further, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of a first continuous structure. For example, the layer may be located between the top surface and the bottom surface of the first continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the first continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0153] As used herein, if a second surface is located above or below a first surface and there is a vertical plane or a substantially vertical plane including the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that extends straight along a direction deviating from the vertical direction by less than 5 degrees. The vertical plane or the substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0154] As used herein, "memory tier" or "memory array tier" refers to the tier corresponding to the general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the top surface of the memory element array and a second horizontal plane including the bottom surface of the memory element array. As used herein, a "through-stack" element is an element that extends vertically through the memory tier.

[0155] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of electrical dopants, and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with electrical dopants. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material (i.e., provide a conductivity greater than 1.0×10 5 S / m) when formed as a crystalline material or when converted to a crystalline material through an annealing process (e.g., from an initial amorphous state). A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material having a concentration of electrical dopants (i.e., p-type dopants and / or n-type dopants) that provides a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material not doped with electrical dopants. Thus, a semiconductor material can be semi-conductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are made under standard conditions.

[0156] The various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be manufactured using the various embodiments described herein. The monolithic three-dimensional NAND strings are located in a monolithic three-dimensional NAND string array, and the monolithic three-dimensional NAND string array is located above a substrate. At least one memory cell in a first device tier of the three-dimensional NAND string array is located above another memory cell in a second device tier of the three-dimensional NAND string array.

[0157] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include one semiconductor chip (or "chip"), or multiple semiconductor chips that are fully bonded, for example, through flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of dies therein. Each die includes one or more planes. The same concurrent operations can be executed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be executed in each plane within the same memory die. In a memory die, each plane contains a certain number of memory blocks (or "blocks"), and these memory blocks are the smallest units that can be erased in a single erase operation. Each memory block contains a certain number of pages, and these pages are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0158] Reference Figure 1, illustrates an exemplary semiconductor die 1000 in accordance with embodiments of the present disclosure. The exemplary semiconductor die 1000 includes a plurality of three-dimensional memory array regions and a plurality of inter-array regions. The first exemplary semiconductor die 1000 may include a plurality of planes, each of which includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a corresponding contact region 200. Generally speaking, the semiconductor die 1000 may include a single plane or a plurality of planes. The total number of planes in the semiconductor die 1000 may be selected based on the performance requirements of the semiconductor die 1000. A pair of memory array regions 100 in a plane may be laterally spaced apart along a first horizontal direction hd1 (which may be the word line direction). For example, each pair of memory array regions 100 in a plane may include a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a contact region 200 along the first horizontal direction hd1. A second horizontal direction hd2 (which may be the bit line direction) may be perpendicular to the first horizontal direction hd1.

[0159] The exemplary semiconductor die 1000 to be fabricated may adopt various embodiments of the present disclosure to be described below. Figure 1 The exemplary semiconductor die 1000. Three exemplary structures are employed to provide an exemplary sequence of processing steps for forming Figure 1 the exemplary semiconductor die 1000.

[0160] Referring to Figure 2 , illustrates a first exemplary structure including a substrate 8 that includes a substrate semiconductor layer 9. The substrate 8 may be a single crystal silicon wafer, a silicon-on-insulator (SOI) substrate, or an insulating (e.g., glass or quartz) substrate. The substrate semiconductor layer 9 may be a single crystal semiconductor material layer, such as a single crystal silicon layer epitaxially grown on a silicon wafer or an SOI substrate, or a doped well in an upper portion of a silicon wafer or an SOI substrate. A semiconductor device 720 may be formed on the top surface of the substrate semiconductor layer 9. For example, the semiconductor device 720 may include field effect transistors, resistors, capacitors, diodes, and / or various other semiconductor devices known in the art. In one embodiment, the semiconductor device 720 may include peripheral (i.e., driver) circuitry for controlling the operation of a three-dimensional memory array to be formed thereabove subsequently. A metal interconnect structure embedded in an embedded dielectric material layer may be formed above the semiconductor device. The metal interconnect structure is referred to herein as a lower metal interconnect structure 780, and the dielectric material layer is referred to herein as a lower dielectric material layer 760. The lower metal interconnect structure 780 is electrically connected to various nodes of the semiconductor device 720 and may include metal line structures and metal via structures located at various levels of the lower dielectric material layer 760.

[0161] The semiconductor material layer 110 may be formed on the top surface of the underlying dielectric material layer 760. The semiconductor material layer 110 may be single-crystalline or polycrystalline and may be formed by layer transfer from a source substrate such as a single-crystalline silicon layer including a buried hydrogen implantation layer, or may be formed by deposition of a semiconductor material which may be a polycrystalline semiconductor material such as polysilicon.

[0162] An alternating stack of the insulating layer 32 and the sacrificial material layer 42 may be formed on the semiconductor material layer 110. As used herein, an alternating stack refers to a sequence of a plurality of instances of a first element and a plurality of instances of a second element, the sequence being arranged such that instances of the second element are located between each pair of vertically adjacent instances of the first element, and instances of the first element are located between each pair of vertically adjacent instances of the second element. An alternating stack refers to a sequence of a plurality of instances of a first material layer and a plurality of instances of a second material layer such that instances of the first material layer and the second material layer are interleaved.

[0163] The insulating layer 32 may be composed of a first material, and the sacrificial material layer 42 may be composed of a second material different from the first material. Each of the insulating layers 32 extends continuously over the entire region of the substrate 8 and may always have a uniform thickness. Each of the sacrificial material layers 42 includes a sacrificial dielectric material and extends continuously over the entire region of the substrate 8 and may always have a uniform thickness. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal nitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0164] The second material of the sacrificial material layer 42 is a dielectric material that is a sacrificial material that may be selectively removed relative to the first material of the insulating layer 32. As used herein, if a removal process removes the first material at a rate of at least twice the removal rate of the second material, the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The second material of the sacrificial material layer 42 may subsequently be replaced by conductive electrodes which may act as, for example, control gate electrodes of a vertical NAND device. In one embodiment, the sacrificial material layer 42 may be a material layer including silicon nitride.

[0165] Each insulating layer 32 may have a first thickness that may range from 15 nm to 60 nm, although smaller and larger thicknesses may also be employed. Each sacrificial material layer 42 may have a second thickness that may range from 15 nm to 60 nm, although smaller and larger thicknesses may also be employed. The total number of repetitions of a pair of insulating layer 32 and sacrificial material layer 42 in the alternating stack (32, 42) may range from 16 to 1024 (such as 64 to 512), although smaller and larger numbers may also be employed. The topmost layer among the insulating layers 32 is referred to herein as the top insulating layer 32T.

[0166] In an alternative embodiment, the semiconductor device 720, the underlying metal interconnect structure 780, and the underlying dielectric material layer 760 may be positioned beside the alternating stack (32, 42) on the substrate 8, rather than beneath the alternating stack (32, 42). In yet another alternative embodiment, the semiconductor device 720, the underlying metal interconnect structure 780, and the underlying dielectric material layer 760 may be omitted and not formed on the substrate 8. Instead, the semiconductor device 720 of the peripheral (i.e., driver) circuitry may be formed on a separate substrate and then bonded on top of the three-dimensional memory device. Optionally, in the case where the substrate 8 is later removed and the top source contact layer is formed on the exposed surface of the memory device, the semiconductor material layer 110 may also be omitted, or the semiconductor material layer may be modified to serve as part of a lateral source contact (e.g., a direct strip contact) that is subsequently formed beneath the alternating stack.

[0167] Reference Figures 3A to 3C , a stepped surface may be formed simultaneously within the inter-array region 200. A hard mask layer (not shown), such as a metal or dielectric mask material layer, may be formed on top of the alternating stack and patterned to form a plurality of rectangular openings. The area of the openings within the hard mask layer corresponds to the area where the stepped surface is to be formed subsequently. Each opening through the hard mask layer may be rectangular and may have a pair of sides parallel to the first horizontal direction hd1 and a pair of sides parallel to the second horizontal direction hd2. The rectangular openings through the hard mask layer may be arranged along the second horizontal direction hd2 and may or may not be alternately staggered along the first horizontal direction hd1.

[0168] A trimable mask layer (not shown) may be applied over the alternating stack. The trimable mask layer may include a trimable photoresist layer that may be controllably trimmed by a timed ashing process. The trimable mask layer may be patterned with an initial pattern such that the segment of each rectangular opening in the hard mask layer closest to the memory array region 100 is not masked by the trimable mask layer, while the remainder of each rectangular opening is covered by the trimable mask layer. For example, the trimable mask layer may have a rectangular shape (with straight edges parallel to the second horizontal direction hd2) such that the straight edges are located over the vertical steps of the corresponding stepped surface closest to one of the memory array regions 100.

[0169] A stepped surface may be formed within the rectangular openings in the hard mask layer by iteratively performing a set of layer patterning process steps. The set of layer patterning process steps includes: an anisotropic etching process that etches the unmasked portions of a pair of insulating layers 32 and a sacrificial material layer 42; and a mask trimming process in which the trimable mask layer is isotropically trimmed to provide shifted sidewalls shifted away from the nearest memory array region 100. A final anisotropic etching process may be performed after the last mask trimming process, and the trimable mask layer may be removed, for example, by ashing. The hard mask layer may be selectively removed from the material of the alternating stack (32, 42) by an isotropic etching process, such as a wet etching process. Alternatively, any other suitable process may be used to form the stepped surface.

[0170] A stepped cavity 69 may be formed within each region of the rectangular openings in the hard mask layer. Each stepped cavity 69 may include a steep wall region in which the tapered sidewalls of the alternating stack (32, 42) extend vertically from the bottommost layer of the alternating stack (32, 42) to the topmost layer of the alternating stack (32, 42). Each stepped cavity 69 has a corresponding stepped surface as the stepped bottom surface. Each stepped cavity has a pair of stepped sidewalls that extend laterally along the first horizontal direction hd1. Each stepped sidewall of the stepped cavity 69 abuts the stepped surface at the bottom edge and extends to the top surface of the topmost layer of the alternating stack (32, 42). The stepped surface is below each stepped cavity 69. Generally, the stepped surface 69 may be formed by patterning the alternating stack (32, 42) in each contact region 200, which is located between a corresponding first memory array region 100A and a second memory array region 100B.

[0171] Generally speaking, each stepped cavity 69 may have stepped surfaces, which include vertically extending surface segments interleaved with horizontally extending surface segments, and generally proceed along a first horizontal direction hd1 from the bottommost surface of the stepped surface (which may be the top surface segment of the semiconductor material layer 110) to the topmost surface of the alternating stack (32, 42). In addition, each stepped cavity 69 may include a pair of tapered sidewalls that are parallel to the first horizontal direction hd1, laterally spaced apart from each other along a second horizontal direction hd2, and have corresponding stepped bottom ends contiguous with the corresponding stepped perimeters of the stepped surfaces.

[0172] Reference Figure 4A and Figure 4B , a dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each stepped cavity. The dielectric fill material may be planarized to remove excess portions of the dielectric fill material above the horizontal plane including the topmost surface of the alternating stack (32, 42). Filling each remaining portion of the corresponding stepped cavity 69 with the dielectric fill material constitutes a re-entrant stepped dielectric material portion 65. Each re-entrant stepped dielectric material portion 65 is formed over the stepped surface of the alternating stack (32, 42).

[0173] Each re-entrant stepped dielectric material portion 65 fills the corresponding stepped cavity 69. In one embodiment, each re-entrant stepped dielectric material portion 65 has a first lateral extent LE1 along the second horizontal direction (e.g., bit line direction) hd2. In one embodiment, each re-entrant stepped dielectric material portion 65 has a first variable lateral extent along the first horizontal direction (e.g., word line direction) hd1, which decreases stepwise with the vertical distance from the horizontal plane including the bottommost surface of the alternating stack (32, 42). In one embodiment, the re-entrant stepped dielectric material portion 65 has a pair of tapered sidewalls extending along the first horizontal direction hd1.

[0174] Reference Figure 5A and Figure 5B, An optional photoresist layer (not shown) may be applied over the alternating stack (32, 42) and the recessed stepped dielectric material portion 65, and may be lithographically patterned to form an array of openings in the contact region 200. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the recessed stepped dielectric material portion 65 and / or through the alternating stack (32, 42) to form optional support openings. Each of the support openings may extend vertically at least from a horizontal plane including the top surface of the alternating stack (32, 42) to a horizontal plane including the bottom surface of the alternating stack (32, 42), and optionally into an upper portion of the semiconductor material layer 110. The photoresist layer may then be removed, for example, by ashing.

[0175] At least one dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) and / or doped silicate glass) may optionally be deposited in the support openings. The excess portion of the at least one dielectric fill material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T by a planarization process, which may employ a recess etching process. The remaining portion of the at least one dielectric fill material constitutes optional support pillar structures 20, which are subsequently used to provide structural support during replacement of the sacrificial material layer 42 with a conductive layer. Alternatively, Figure 5A and Figure 5B the steps illustrated in Figures 6A to 8B may be omitted, and the support pillar structures 20 may be omitted or may be formed during the same processing steps as the memory opening fill structure, as will be described with respect to

[0176] Referring to Figure 6A and Figure 6B , a photoresist layer (not shown) may be applied over the alternating stack (32, 42), and may be lithographically patterned to form an array of memory openings 49 in the memory region 100. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the alternating stack (32, 42) to form the memory openings 49. Each of the memory openings 49 may extend vertically at least from a horizontal plane including the top surface of the alternating stack (32, 42) to a horizontal plane including the bottom surface of the alternating stack (32, 42), and optionally into an upper portion of the semiconductor material layer 110. The photoresist layer may then be removed, for example, by ashing. In an alternative embodiment, the support openings described above in the contact region 200 may be formed simultaneously with the memory openings 49 in the memory region 100.

[0177] Figures 7A to 7F is a sequential vertical cross-sectional view of a region around a memory opening during formation of a memory opening fill structure according to a first embodiment of the present disclosure.

[0178] Reference Figure 7A illustrates Figure 6A and Figure 6B a memory opening 49 in an exemplary device structure of

[0179] and . The memory opening 49 extends through the alternating stack (32, 42) and optionally extends into the upper portion of the semiconductor material layer 110. The recess depth of the bottom surface of each memory opening 49 relative to the top surface of the semiconductor material layer 110 can range from 0 nm to 30 nm, but larger recess depths can also be employed. Optionally, the sacrificial material layer 42 can be partially laterally recessed, for example, by isotropic etching to form a laterally extending cavity (not shown).

[0180] Reference Figure 7B includes a stack of layers including a barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner layer 56 can be deposited in each memory opening 49. The stack of layers is referred to herein as the memory film 50.

[0181] The barrier dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer 52 can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. In one embodiment, the barrier dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., greater than the dielectric constant of silicon nitride). Additionally or alternatively, the barrier dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the barrier dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the barrier dielectric layer 52 can be formed by a conformal deposition method such as low-pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can range from 1 nm to 20 nm, but smaller and larger thicknesses can also be employed.

[0182] The memory material layer 54 can include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of the presence or absence of charge, the direction of ferroelectric polarization, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer 54 can include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metal material), which are patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed in laterally extending cavities that enter the sacrificial material layer 42. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 can have vertically coincident sidewalls, and the memory material layer 54 can be formed as a single continuous layer. Generally speaking, the memory material layer 54 can include a vertical stack of memory elements located at the level of the sacrificial material layer 42. For example, the vertical stack of memory elements can be embodied as an annular portion of the memory material layer 54 located at the level of the sacrificial material layer 42.

[0183] The optional dielectric liner 56 (if present) includes a dielectric liner material. In one embodiment, the dielectric liner 56 can include a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. Depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling can be performed by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. The dielectric liner 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, their alloys, and / or their combinations. In one embodiment, the dielectric liner 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly referred to as an ONO stack. In one embodiment, the dielectric liner 56 can include a carbon-free silicon oxide layer or a carbon-free silicon oxynitride layer. The thickness of the dielectric liner 56 can be in the range of 2 nm to 20 nm, but smaller or larger thicknesses can also be employed.

[0184] Optionally, a sacrificial capping material layer 601 can be formed over the memory film 50.

[0185] Reference Figure 7C, at least one anisotropic etching process is used to anisotropically etch the optional sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 sequentially. Multiple portions of the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 that are located above the top surface of the topmost insulating layer 32T can be removed by at least one anisotropic etching process. Additionally, the horizontal portions of the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form openings in their remaining portions. Each of the sacrificial capping material layer, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 can be etched by a corresponding anisotropic etching process using a corresponding etching chemical, which can be the same or possibly different for the various material layers.

[0186] Each remaining portion of the sacrificial capping material layer 601 (if used) can have a tubular configuration. The surface of the pedestal channel portion 11 (or the surface of the semiconductor material layer 110 in the case where the pedestal channel portion 11 is not used) can be physically exposed under the openings through the sacrificial capping material layer, dielectric liner layer 56, memory material layer 54, and dielectric metal oxide barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed such that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the pedestal channel portion 11 (or from the semiconductor material layer 110 in the case where the pedestal channel portion 11 is not used) by a certain recess distance. In one embodiment, the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 can have vertically coincident sidewalls. Subsequently, the sacrificial capping material layer 601 can be removed selectively with respect to the material of the dielectric liner layer 56. In the case where the sacrificial capping material layer 601 includes amorphous silicon, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to remove the sacrificial capping material layer. Alternatively, if the sacrificial capping material layer 601 contains a silicon material, the sacrificial capping material layer can be retained in the final device.

[0187] Reference Figure 7D, the semiconductor channel layer 60L can be directly deposited on the semiconductor surface of the pillar channel portion 11 (or directly deposited on the semiconductor material layer 110 if the pillar channel portion 11 is omitted), and can be directly deposited on the memory film 50. The semiconductor channel layer 60L includes semiconductor materials, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L can have doping of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer 110 and the pillar channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. The semiconductor channel layer 60L can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0188] Reference Figure 7E , the dielectric core layer can be deposited to fill any remaining portion of the memory cavity 49' within each memory opening 49. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating.

[0189] The horizontal portion of the dielectric core layer can be removed, for example, by a recess etching process, such that each remaining portion of the dielectric core layer is located within a corresponding memory opening 49 and has a corresponding top surface below the horizontal plane of the top surface including the top insulating layer 32T. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0190] Reference Figure 7F , a doped semiconductor material having doping of a second conductivity type can be deposited in each recessed area above the dielectric core 62. The deposited semiconductor material can have doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polycrystalline silicon.

[0191] Excess portions of the deposited semiconductor material doped with a second conductivity type and horizontal portions of the semiconductor channel layer 60L can be removed, for example, by chemical mechanical planarization (CMP) or recess etching processes, above a horizontal plane of the top surface including the top insulating layer 32T. Each remaining portion of the doped semiconductor material doped with a second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (which is doped with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0192] Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, an optional dielectric liner 56, a plurality of memory elements including a plurality of portions of the memory material layer 54, and an optional barrier dielectric layer 52. Each combination of the pedestal channel portion 11 (if present) within the memory opening 49, the memory stack structure 55, the dielectric core 62, and the drain region 63 is referred to herein as a memory opening fill structure 58.

[0193] In an alternative embodiment where the support opening is formed simultaneously with the memory opening 49, the support pillar structure 20 can be formed in the support opening simultaneously with the memory opening fill structure 58. In this alternative embodiment, the support pillar structure 20 has the same composition as the memory opening fill structure 58 but is not electrically connected to the subsequently formed bit line.

[0194] Reference Figure 8A and Figure 8B , illustrates a first exemplary structure after the memory opening fill structure 58 and the support pillar structure 20 are formed within the memory opening 49 and the support opening 19, respectively. Examples of the memory opening fill structure 58 can be formed within each memory opening 49. Examples of the support pillar structure 20 can be formed within each support opening. Other memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60 can also be used.

[0195] Reference Figures 9A to 9C , a contact level dielectric layer 80 can be formed over an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 and over the memory opening fill structure 58 and the support pillar structure 20. The contact level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact level dielectric layer 80 can include silicon oxide. The contact level dielectric layer 80 can have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be employed.

[0196] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and lithographically patterned to form elongated openings in the regions between clusters of the memory opening fill structures 58. Anisotropic etching may be employed to transfer the pattern in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), and the recessed stepped dielectric material portion 65 to form the lateral isolation trenches 79 that extend vertically at least from the top surface of the contact-level dielectric layer 80 to the top surface of the semiconductor material layer 110 and laterally across at least one memory array region 100 and at least a peripheral portion of the contact region 200.

[0197] In one embodiment, the lateral isolation trenches 79 may extend laterally along a first horizontal direction hd1 (which is the word line direction) and may be laterally spaced from each other along a second horizontal direction hd2 (which is the bit line direction) perpendicular to the first horizontal direction hd1. The memory opening fill structures 58 may be arranged in rows that extend along the first horizontal direction hd1. Each lateral isolation trench 79 may have a uniform width that is invariant along the longitudinal direction (i.e., along the first horizontal direction hd1). Multiple rows of memory opening fill structures may be located between an adjacent pair of lateral isolation trenches 79. In one embodiment, the lateral isolation trenches 79 may include source contact openings in which source contact via structures may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

[0198] According to one aspect of the present disclosure, the lateral isolation trench 79 includes a first type of lateral isolation trench 79A and a second type of lateral isolation trench 79B, and these second type of lateral isolation trenches are staggered with the first type of lateral isolation trench 79A along a second horizontal direction hd2. Each of the first type of lateral isolation trenches 79A continuously extends laterally along a first horizontal direction hd1 through the contact region 200, the first memory array region 100A, and the second memory array region 100B. Each of the second type of lateral isolation trenches 79B extends laterally through a corresponding one of the memory regions 100 (e.g., 100A or 100B), and partially extends into the peripheral portion of the contact region 200 without extending into the central portion of the contact region 200 or into the other one of the memory regions 100. In one embodiment, each pair of the second type of lateral isolation trenches 79B may be laterally spaced apart from each other by a certain gap along the first horizontal direction hd1, and this gap is located within the contact region 200. In one embodiment, each pair of the second type of lateral isolation trenches 79B may be aligned with each other along the second horizontal direction hd2. In this case, each longitudinal sidewall of the second type of lateral isolation trench 79B may be formed in a vertical plane parallel to the first horizontal direction hd1. The vertical plane may include the longitudinal sidewall of another second type of lateral isolation trench 79B within the corresponding pair of the second type of lateral isolation trenches 79B. In one embodiment, each pair of the second type of lateral isolation trenches 79B may be positioned in the middle between an adjacent pair of the first type of lateral isolation trenches 79A. In this case, the unit repeating structure including the first type of lateral isolation trench 79A and a pair of the second type of lateral isolation trenches 79B spaced apart from each other along the first horizontal direction hd1 may be uniformly periodically repeated along the second horizontal direction hd2.

[0199] The width of the lateral isolation trench 79 may be greater than the thickness of each sacrificial material layer 42. For example, the ratio of the width of the lateral isolation trench 79 along the second horizontal direction hd2 to the thickness of each sacrificial material layer 42 may be in the range of 2 to 30 (such as 4 to 15), but smaller or larger ratios may also be employed. According to one aspect of the present disclosure, the first type of lateral isolation trench 79A may be formed between adjacent pairs of the etched-back stepped dielectric material portions 65, and each pair of the second type of lateral isolation trenches 79B may cut through a corresponding one of the etched-back stepped dielectric material portions 65, as Figure 9B and Figure 9C shown.

[0200] The first type of lateral isolation trench 79A may be laterally staggered with the etched-back stepped dielectric material portions 65 along the second horizontal direction hd2. As Figure 9BAs shown, the cut length (CL1 or CL2) of each second-type lateral isolation trench 79B can be measured between an end wall of the remaining portion of the exposed etch-back stepped dielectric material portion 65 of the corresponding second-type lateral isolation trench 79B along the first horizontal direction hd1 and another end wall of the contact top insulating layer 32T in contact with the etch-back stepped dielectric material portion 65, which is parallel to the second horizontal direction hd2. The end walls of the second-type lateral isolation trenches 79 are parallel to the second horizontal direction hd2. The cut length (CL1 or CL2) of each second-type lateral isolation trench 79B can be in the range of 50% to 150% (such as 80% to 120%) of the lateral distance between adjacent pairs of first-type lateral isolation trenches 79A and second-type lateral isolation trenches 79B in the memory array region 100 along the second horizontal direction hd2.

[0201] Generally speaking, the lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 can be formed through the contact-level dielectric layer 80 and the alternating stack (32, 42). The alternating stack (32, 42) is divided by the first-type lateral isolation trenches 79A into a plurality of alternating stacks (32, 42) spaced laterally apart along the second horizontal direction hd2. A layer stack (32, 42, 80) is formed, and each layer stack in these layer stacks includes a corresponding patterned portion of the contact-level dielectric layer 80 and a corresponding alternating stack (32, 42), and is laterally spaced apart from each other by the lateral isolation trenches 79.

[0202] Reference Figure 10A and Figure 10B , a dielectric etch stop material different from the material of the sacrificial material layer 42 can be conformally deposited in the back trenches 79 and on the contact-level dielectric layer 80 to form an etch stop liner 78. The etch stop liner 78 can include silicon oxide, doped silicate glass, silicon carbonitride, silicon oxynitride, or a dielectric metal oxide material, which is resistant to the etch chemistry to be subsequently used to remove the sacrificial material layer 42. In one embodiment, the etch stop liner 78 includes silicon oxide. The etch stop liner 78 can be deposited by a conformal deposition process such as a chemical vapor deposition process. The thickness of the etch stop liner 78 can be in the range of 10 nm to 100 nm (such as 20 nm to 60 nm), but smaller and larger thicknesses can also be used.

[0203] Reference Figure 11A and Figure 11B, a photoresist layer 77 may be applied over the etch stop liner 78 and may be lithographically patterned into discrete portions of photoresist material 77 that cover end portions of the second type of lateral isolation trenches 79B that are in and / or near the contact region 200 without covering a plurality of portions of the second type of lateral isolation trenches 79B that are remote from the contact region 200 and without covering any of the first type of lateral isolation trenches 79A. In one embodiment, a plurality of portions of the second type of lateral isolation trenches 79B that are in the memory regions (100A, 100B) are not covered by the photoresist layer. An etch process may be performed to remove the portions of the etch stop liner 78 that are not covered by the photoresist layer 77. The etch process may include an isotropic etch process or an anisotropic etch process.

[0204] At Figure 10A and Figure 10B remaining portions of the etch stop liner 78 formed at the processing steps of include a plurality of etch stop liners 78 that cover the end portions of the second type of lateral isolation trenches 78. In one embodiment, each etch stop liner 78 may cover two end portions of a pair of the second type of lateral isolation trenches 79B that are in the contact region 200 and may extend laterally in a first horizontal direction hd1 across the contact region 200. Generally, the etch stop liner 78 may be formed at the end portions of the second type of lateral isolation trenches 79B that are in the contact region 200 such that the etch stop liner 78 is not present on a plurality of portions of the second type of lateral isolation trenches 79B that are remote from the contact region 200 and that are in the memory regions (100A, 100B) and is not present within the first type of lateral isolation trenches 79A.

[0205] Referring Figures 12A to 12D , the photoresist layer 77 may be removed, for example, by ashing. The etch stop liner 78 covers the entirety of each cut length (CL1 or CL2) of the end portion of each of the second type of lateral isolation trenches 79B. Accordingly, the back-etched stepped dielectric material portion 65 is not physically exposed to any cavity that is within the second type of lateral isolation trenches 79B.

[0206] Referring Figures 13A to 13H , an isotropic etch process may be performed to introduce an isotropic etchant for the material of the etch sacrificial material layer 42 into the first type of lateral isolation trenches 79A and into a plurality of pairs of the second type of lateral isolation trenches 79B. For example, if the sacrificial material layer 42 comprises silicon nitride, the isotropic etch process may include a wet etch process using hot phosphoric acid. Lateral extension cavities 43 are formed in the volumes from which portions of the etch sacrificial material layer 42 are removed by the isotropic etch process.

[0207] According to one aspect of the present disclosure, the isotropic etching process has an etching distance that is greater than half of the lateral distance between a first type of lateral isolation trench 79A and a pair of second type of lateral isolation trenches 79B closest to the first type of lateral isolation trench 79A. In one embodiment, the etching distance is less than the lateral distance between the first type of lateral isolation trench 79A and a pair of second type of lateral isolation trenches 79B closest to the first type of lateral isolation trench 79A. In one embodiment, the etching distance is less than the lateral dimension of the etch stop layer 78 along a first horizontal direction hd1.

[0208] After the isotropic etching process, a remaining portion of the sacrificial material layer 42 is present in each gap between multiple pairs of second type of lateral isolation trenches 79B, as Figure 13D and Figure 13E shown. The remaining portion of the sacrificial material layer 42 constitutes a vertical stack of dielectric material plates 42'. The vertical stack of dielectric material plates 42' can be formed under each etch-back stepped dielectric material portion 65. In one embodiment, the etch-back stepped dielectric material portion 65 can have a first lateral extent LE1 along a second horizontal direction hd2 ( Figure 13E shown in), and the dielectric material plates 42' in the vertical stack of dielectric material plates 42' can have a second lateral extent LE2 along the second horizontal direction hd2, which is less than the first lateral extent LE1.

[0209] In one embodiment, the plurality of dielectric material plates 42' within the vertical stack of dielectric material plates 42' can have a uniform width along the second horizontal direction hd2, which is less than the minimum lateral dimension of the etch-back stepped dielectric material portion 65 along the second horizontal direction hd2. In one embodiment, the dielectric material plates 42' within each vertical stack of dielectric material plates 42' can have lateral extents along the first horizontal direction hd1 that decrease with the vertical distance from the substrate 8. In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' can have a corresponding sidewall that is parallel to the second horizontal direction hd2 and contacts a corresponding vertical sidewall segment of the etch-back stepped dielectric material portion 65.

[0210] In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42 can include a concave sidewall segment 42C located at the same level as a corresponding laterally extending cavity 43. In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42 can include a first flat sidewall segment contacting the etch stop layer 78 and a second flat sidewall segment contacting another etch stop layer 78. A dielectric material plate region R42' can be formed between each pair of second type of lateral isolation trenches 79B that are laterally spaced apart from each other along the first horizontal direction hd1.

[0211] Reference Figures 14A to 14H , a backside barrier dielectric layer 44 can be optionally deposited in the laterally extending cavity 43 on the physically exposed surfaces of the recessed stepped dielectric material portion 65, the dielectric material plate 42', and the insulating layer 32 by a conformal deposition process, as Figure 14C shown. The backside barrier dielectric layer 44 comprises a dielectric material such as a dielectric metal oxide (such as alumina) and / or silicon oxide. The thickness of the backside barrier dielectric layer 44 can be in the range of 3 nm to 12 nm, although smaller and larger thicknesses can also be employed.

[0212] At least one conductive material can be deposited in the unfilled volume of the laterally extending cavity 43 by providing at least one reactant gas into the laterally extending cavity 43 via the lateral isolation trench 79. For example, the at least one conductive material can include a metal barrier layer and a metal fill material. The metal barrier layer comprises a conductive metal material that can act as a diffusion barrier layer and / or an adhesion promoting layer for the metal fill material to be deposited subsequently. The metal barrier layer can include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can be in the range of 2 nm to 8 nm (such as 3 nm to 6 nm), although smaller and larger thicknesses can also be employed. In one embodiment, the metal barrier layer can consist essentially of a conductive metal nitride such as TiN.

[0213] The metal fill material can be deposited over the metal barrier layer to form a metal fill material layer. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) can be employed to deposit the metal fill material layer. In one embodiment, the metal fill material layer can be a tungsten layer including residual levels of fluorine atoms as impurities. The metal fill material layer is spaced apart from the insulating layer 32 and the memory opening fill structure 58 by the metal barrier layer, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0214] A plurality of conductive layers 46 may be formed in the plurality of laterally extending cavities 43, and a continuous metal material layer may be formed on the sidewalls of each of the laterally isolated trenches 79 and on top of the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal fill material layer, and these portions are located between a vertically adjacent pair of dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer, and these continuous portions are located in the laterally isolated trenches 79 or above the contact-level dielectric layer 80.

[0215] By performing an etching process that etches at least one of the conductive materials of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each of the laterally isolated trenches 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the laterally extending cavities 43 constitutes a conductive layer 46. Each conductive layer 46 may be a conductive wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0216] The intermediate conductive layer 46 may act as a combination of a plurality of control gate electrodes located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device including a memory stack structure 55. In other words, the conductive layer 46 may be a word line that acts as a common control gate electrode for a plurality of vertical memory devices. At least one uppermost conductive layer 46 may include a drain-side select gate electrode. At least one lowermost conductive layer 46 may include a source-side select gate electrode.

[0217] Generally speaking, a plurality of portions of the sacrificial material layer 42 are replaced by a vertical stack of the conductive layers 46. In one embodiment, each vertical stack of the conductive layers 46 is formed between the nearest first-type laterally isolated trench 79A in the first-type laterally isolated trenches 79A and the nearest pair of second-type laterally isolated trenches 79B in the plurality of pairs of second-type laterally isolated trenches 79B, and does not laterally extend further along the second horizontal direction hd2 than the nearest first-type laterally isolated trench and the nearest pair of second-type laterally isolated trenches.

[0218] For each vertical stack of the insulating layer 32 that laterally extends between an adjacent pair of first-type laterally isolated trenches 79A in the contact region 200, a vertical stack of the first conductive layer 46 may be located on a first side of the vertical stack of the dielectric material plate 42' and may be staggered with the vertical stack of the insulating layer 32, and a vertical stack of the second conductive layer 46 may be located on a second side of the vertical stack of the dielectric material plate 42' and may be staggered with the vertical stack of the insulating layer 32.

[0219] The region extending between the laterally adjacent first type of lateral isolation trench 79A and the second type of lateral isolation trench 79B in the second horizontal direction includes memory blocks. The insulating layer 32 continuously extends in the second horizontal direction hd2 between the adjacent pair of first type of lateral isolation trenches 79A in the contact region 200. Accordingly, the insulating layer 32 continuously extends in the second horizontal direction hd2 between two adjacent memory blocks. In the space between the vertical stack of the dielectric material plate 42' and the corresponding first type of lateral isolation trench 79A, the conductive layer continuously extends in the first horizontal direction through the contact region 200 in each memory block between the memory regions (100A, 100B).

[0220] The second type of lateral isolation trench 79B extends through one of the memory regions 100A or 100B but does not extend all the way through the contact region 200. Instead, the alternating stack of the insulating layer 32 and the dielectric material plate 42' between a pair of second type of lateral isolation trenches 79B located in the contact region 200 electrically isolates the conductive layers 46 in adjacent memory blocks. The alternating stack of the insulating layer 32 and the dielectric material plate 42' prevents or reduces the lateral collapse of the insulating layer 32 into the lateral isolation trench 79 during the replacement of the sacrificial material layer 42 with the conductive layer 46 because the cavity 43 is not formed in the region of the dielectric material plate 42'. Accordingly, word line steps can be formed on opposite sides of the alternating stack of the insulating layer 32 and the dielectric material plate 42', thereby reducing the likelihood of the lateral collapse of the insulating layer 32 into the lateral isolation trench 79. The etch stop layer 78 prevents the formation of a continuous cavity 43 between two adjacent memory blocks. Accordingly, the conductive layer 46 is not shorted between two adjacent memory blocks.

[0221] Reference Figure 15A and Figure 15B and, an optional anisotropic etch process can be performed to remove the horizontal extension portion of the etch stop layer 78 from above the contact level dielectric layer 80 and from the bottom portion of the second type of lateral isolation trench 79B. In one embodiment, after the anisotropic etch process, each etch stop layer 78 can include only the vertical extension portion. Alternatively, the horizontal extension portion of the etch stop layer 78 can be retained and the optional anisotropic etch process can be omitted.

[0222] Reference Figure 16A and Figure 16B and, an ion implantation process can be optionally performed to implant dopants of the second conductivity type into the surface portion of the semiconductor material layer 110 located below the lateral isolation trench 79 to form optional source regions 61. Alternatively, a portion of the semiconductor material layer 110 can instead be replaced by a heavily doped semiconductor source strip that contacts the sidewalls of the vertical semiconductor channel 60.

[0223] The insulating material layer can be conformally deposited in the lateral isolation trenches 79 above the etch stop liner 78 and the contact level dielectric layer 80. An anisotropic etching process can be performed to remove the horizontally extending portions of the insulating material layer. Each remaining vertically extending portion of the insulating material layer constitutes an insulating spacer 74. The insulating spacer 74 includes a first insulating spacer 74A formed in the first type of lateral isolation trench 79A, and a second insulating spacer 74B formed in the second type of lateral isolation trench 79B and contacting a corresponding one of the etch stop liner 78.

[0224] Optionally, at least one conductive material can be deposited in the remaining unfilled volume of the lateral isolation trenches 79 to form an optional source contact via structure 76. The source contact via structure 76 can include a first source contact via structure 76A formed in the first lateral isolation trench 79A, and a second source contact via structure 76B formed in the second type of lateral isolation trench 79B.

[0225] Each adjacent combination of the insulating spacer 74 and the source contact via structure 76 constitutes a lateral isolation trench filling structure (74, 76) that fills the corresponding lateral isolation trench 79. The lateral isolation trench filling structure (74, 76) includes a first lateral isolation trench filling structure (74A, 76A) formed in the first lateral isolation trench 79A, and a second type of lateral isolation trench filling structure (74B, 76B) formed in the second type of lateral isolation trench 79B.

[0226] A composite dielectric isolation structure (65, 42', 74B, 78) can be formed between the vertical stacks of the first conductive layer 46 and the vertical stacks of the second conductive layer 46, which are located in adjacent memory blocks adjacent to the first lateral isolation trench filling structures (74A, 76A). Thus, the composite dielectric isolation structure (65, 42', 74B, 78) electrically isolates the vertical stacks of the first conductive layer 46 and the vertical stacks of the second conductive layer 46 located in adjacent memory blocks.

[0227] In one embodiment, the composite dielectric isolation structure (65, 42', 74B, 78) includes a recessed stepped dielectric material portion 65, a vertical stack of dielectric material plates 42', and a pair of second type lateral isolation trench fill structures (74B, 76B) laterally spaced along a first horizontal direction hd1. In one embodiment, the insulating layers 32 may be vertically spaced from each other and may be located above the substrate 8 between a first first type lateral isolation trench fill structure (74A, 76A) and a second first type lateral isolation trench fill structure (74A, 76A), the first first type lateral isolation trench fill structure and the second first type lateral isolation trench fill structure extending laterally along the first horizontal direction hd1 and being laterally spaced from each other along a second horizontal direction hd2.

[0228] In Figure 16B In one embodiment as shown, each of the second type lateral isolation trench fill structures (74B, 76B) has: a corresponding first region in the memory region 100 that has a first uniform width along the second horizontal direction hd2; and a corresponding second region in the contact region 200 that has a second uniform width and contacts a corresponding etch stop layer 78. In one embodiment, each of the second type lateral isolation trench fill structures (74B, 76B) includes a corresponding insulating liner 74B that includes a corresponding portion of insulating liner material and contacts the inner sidewalls of the first insulating layer 32 and the first conductive layer 46 of a first alternating stack (32, 46) and the second insulating layer 32 and the second conductive layer 46 of a second alternating stack (32, 46). In one embodiment, each of the first type lateral isolation trench fill structures (74A, 76A) includes a corresponding additional insulating liner 74A that includes a corresponding additional portion of insulating liner material. In one embodiment, all surfaces of the first alternating stack (32, 46) and the second alternating stack (32, 46) that contact the pair of second type lateral isolation trench fill structures (74B, 76B) contact corresponding surfaces of insulating liner material.

[0229] In Figure 14DIn one embodiment shown, at least one dielectric material plate 42' within the vertical stack of dielectric material plates 42' includes: first sidewall segments 42F that extend laterally along a first horizontal direction hd1 and contact one of the second type of lateral isolation trench fill structures (74B, 76B) that includes an etch stop liner 78; second sidewall segments 42S that extend laterally along a second horizontal direction hd2 and contact one of the second type of lateral isolation trench fill structures (74B, 76B) that includes an etch stop liner 78; first concave surface segments 42C that are located at the level of one of the first conductive layers 46 and contact the convex sidewall of a first structural element (44 or 46) selected from one of the first conductive layers 46 and a first barrier dielectric layer 44 that contacts one of the first conductive layers 46; and third sidewall segments 42T that extend laterally along the first horizontal direction hd1 and contact the flat sidewall of a second structural element (44 or 46).

[0230] Reference Figures 17A to 17F , a photoresist layer may be applied over the contact level dielectric layer 80 and may be lithographically patterned to form openings over the memory opening fill structure 58 and the region of the horizontally extending portions of the conductive layers 46 that are located below the stepped bottom surface of the etchback stepped dielectric material portion 65. An anisotropic etch process may be performed to form a drain contact via cavity over the drain region 63 of the memory opening fill structure 58 and a layer contact via cavity over the horizontally extending surface of the conductive layer 46 that is located below the etchback stepped dielectric material portion 65. At least one conductive material may be deposited in the drain contact via cavity to form a drain contact via structure 88 and may be deposited in the layer contact via cavity to form a layer contact via structure 86.

[0231] Reference Figure 18A and Figure 18B , by performing the processing steps described with reference to Figure 10A and Figure 10B 、 Figure 11A and Figure 11B as well as Figures 12A to 12D it is possible to obtain from Figures 9A to 9CThe first exemplary structure illustrated in Figure 11A and Figure 11B and Figures 12A to 12D is provided with an alternative configuration of the first exemplary structure, modified in that the etch stop layer 78 is replaced by a sacrificial etch stop layer 178, which can then be selectively removed with respect to the materials of the insulating layer 32 and the conductive layer 46. The sacrificial etch stop layer 178 comprises a material that can act as an etch stop material during subsequent isotropic etch steps of the isotropic etch sacrificial material layer 42. In one embodiment, the sacrificial etch stop layer 178 comprises a semiconductor material (such as polysilicon), a carbon-based material (such as amorphous carbon), or an organic material that can subsequently be removed by ashing. The sacrificial etch stop layer 178 can be deposited by a conformal or non-conformal deposition process. The thickness of the sacrificial etch stop layer 178 can range from 10 nm to 100 nm (such as 20 nm to 60 nm), but smaller and larger thicknesses can also be employed. The patterning processes described with reference to Figure 18A and Figure 18B can be performed to provide an alternative configuration of the first exemplary structure illustrated in

[0232] Reference Figures 19A to 19F , the processing steps described with reference to Figures 13A to 13H and Figures 14A to 14H can be performed. Subsequently, the sacrificial etch stop layer 178 can be selectively removed with respect to the insulating layer 32 and the conductive layer 46. The processing steps described with reference to Figure 15A and Figure 15B , Figure 16A and Figure 16B and Figures 17A to 17F can be performed to provide an alternative configuration of the first exemplary structure illustrated in Figures 19A to 19F

[0233] Reference Figures 1 to 19F ​, according to a first embodiment of the present disclosure, a three-dimensional memory device includes: insulating layers 32 that are vertically spaced apart from each other and extend continuously laterally between a first first-type laterally isolated trench fill structure (74A, 76A) and a second first-type laterally isolated trench fill structure (74A, 76A), the first first-type laterally isolated trench fill structure and the second first-type laterally isolated trench fill structure extending laterally along a first horizontal direction hd1 and being laterally spaced apart from each other along a second horizontal direction hd2; first conductive layers 46 that are vertically interleaved with the insulating layers 32 and contact the first first-type laterally isolated trench fill structure (74A, 76A); second conductive layers 46 that are vertically interleaved with the insulating layers 32 and contact the second first-type laterally isolated trench fill structure (74A, 76A); and a composite dielectric isolation structure {65, 42', 74B, optionally 78} that is located between the first conductive layers 46 and the second conductive layers 46 and includes an etched-back stepped dielectric material portion 65, a vertical stack of dielectric material plates 42', and a pair of second-type laterally isolated trench fill structures (74B, 76B) that are laterally spaced apart along the first horizontal direction hd1.

[0234] In one embodiment, the etched-back stepped dielectric material portion 65 has a first lateral extent LE1 along the second horizontal direction hd2; and each dielectric material plate 42' in the vertical stack of dielectric material plates 42' has a second lateral extent LE2 along the second horizontal direction hd2, the second lateral extent being less than the first lateral extent LE1.

[0235] In one embodiment, the dielectric material plates 42' within the vertical stack of dielectric material plates 42' have a lateral extent along the first horizontal direction hd1 that decreases with the vertical distance from the substrate 8.

[0236] In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' has a respective sidewall that is parallel to the second horizontal direction hd2 and contacts a respective vertical sidewall segment of the etched-back stepped dielectric material portion 65.

[0237] In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' includes a concave sidewall segment located at the same level as a respective conductive layer 46 selected from the first conductive layers 46 and the second conductive layers 46 and contacts a convex sidewall segment of a structural element (44 or 46) selected from the respective conductive layer 46 or a backside blocking dielectric layer 44 that contacts the respective conductive layer 46.

[0238] In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' further comprises: a first flat sidewall segment that contacts a flat sidewall segment of an etch stop layer 78 that contacts one of the pair of second-type lateral isolation trench fill structures (74B, 76B); and a second flat sidewall segment that contacts a flat sidewall segment of a structural element (44 or 46).

[0239] Alternatively, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' further comprises: a first flat sidewall segment that contacts a flat sidewall segment of one of the pair of second-type lateral isolation trench fill structures (74B, 76B); and a second flat sidewall segment that contacts a flat sidewall segment of a structural element (44 or 46).

[0240] In one embodiment, each of the second-type lateral isolation trench fill structures (74B, 76B) has a uniform width along a second horizontal direction hd2 and contacts a respective etch stop layer 78 having a lateral thickness less than half of the uniform width. In one embodiment, each of the second-type lateral isolation trench fill structures (74B, 76B) comprises a respective insulating liner 74B that comprises a respective portion of insulating liner material and contacts the inner sidewalls of the respective etch stop layer 78, the first insulating layer 32, the second insulating layer 32, the first conductive layer 46, and the second conductive layer 46; and each of the first-type lateral isolation trench fill structures (74A, 76A) comprises a respective additional insulating liner 74A that comprises a respective additional portion of insulating liner material, wherein all surfaces of the first alternating stack (32, 46) and the second alternating stack (32, 46) that contact the pair of second-type lateral isolation trench fill structures (74B, 76B) contact respective surfaces of insulating liner material.

[0241] In one embodiment, the etch-back stepped dielectric material portion 65 has a first variable lateral extent along a first horizontal direction hd1 that increases stepwise with the vertical distance from the substrate 8. In one embodiment, the etch-back stepped dielectric material portion 65 has a second variable lateral extent along a second horizontal direction hd2 that increases gradually along the second horizontal direction hd2 without any steps.

[0242] In one embodiment, the dielectric material plates 42' within the vertical stack of dielectric material plates 42' include: first sidewall segments that extend laterally along a first horizontal direction hd1 and contact one of the second type of laterally isolated trench fill structures (74B, 76B); second sidewall segments that extend laterally along a second horizontal direction hd2 and contact one of the second type of laterally isolated trench fill structures (74B, 76B); first concave surface segments that are located at the level of one of the first conductive layers 46 and contact the convex sidewalls of a first structural element (44 or 46), the first structural element being selected from one of the first conductive layers 46 and a first barrier dielectric layer that contacts one of the first conductive layers; and third sidewall segments that extend laterally along the first horizontal direction hd1 and contact the flat sidewalls of the first structural element (44 or 46).

[0243] In one embodiment, the plurality of dielectric material plates 42' within the vertical stack of dielectric material plates 42' have a uniform width along the second horizontal direction hd2, the uniform width being less than the minimum lateral dimension of the etch-back stepped dielectric material portion 65 along the second horizontal direction hd2.

[0244] Reference Figures 20A to 20C , the second exemplary structure according to the second embodiment of the present disclosure can be obtained from the first exemplary structure illustrated in Figures 9A to 9C by changing the pattern of the openings in the photoresist layer before performing the anisotropic etch process for forming the laterally isolated trenches 79. Specifically, in addition to the first type of laterally isolated trenches 79A and the second type of laterally isolated trenches 79B, access cavities 179 can also be formed. In one embodiment, a pair of access cavities 179 can be formed between each pair of second type of laterally isolated trenches 79B that are laterally spaced apart from each other along the first horizontal direction hd1. Each pair of access cavities 179 can be formed "in line" with a corresponding pair of second type of laterally isolated trenches 79B. In other words, the lateral extent of each pair of access cavities 179 along the second horizontal direction hd2 can be the same as the lateral extent of the corresponding pair of second type of laterally isolated trenches 79B along the second horizontal direction hd2.

[0245] In one embodiment, each access cavity 179 can be formed in the contact region 200 outside the region of the etch-back stepped dielectric material portion 65. In this case, the access cavities 179 do not penetrate any of the etch-back stepped dielectric material portions 65. The lateral extent of each access cavity 179 along the first horizontal direction hd1 can be less than the width of the gap between the nearest etch-back stepped dielectric material portion 65 and the nearest memory array region 100 along the first horizontal direction hd1.

[0246] Each second-type lateral isolation trench 79B may be formed entirely within the memory array region 100 (i.e., not extending into the contact region 200), or may extend through the memory array region 100 and laterally project into the peripheral portion of the contact region 200 such that the second-type lateral isolation trench 79B is laterally spaced from the nearest etch-back stepped dielectric material portion 65 by a corresponding access cavity 179.

[0247] A combination of a pair of second-type lateral isolation trenches 79B and a pair of access cavities 179 formed between an adjacent pair of first-type lateral isolation trenches 79A constitutes a trench group (79B, 179). The first-type lateral isolation trenches 79A and the trench group (79B, 179) are staggered along a second horizontal direction hd2. In this case, a unit repeating structure including the first-type lateral isolation trenches 79A, a pair of second-type lateral isolation trenches 79B, and a pair of access cavities 179 may be periodically repeated uniformly along the second horizontal direction hd2. Each of the first-type lateral isolation trenches 79A extends continuously laterally along a first horizontal direction hd1 through the contact region 200, the first memory array region 100A, and the second memory array region 100B. Each second-type lateral isolation trench 79B extends laterally through a corresponding one of the memory regions 100 and optionally extends into the peripheral portion of the contact region 200 without extending into the central portion of the contact region 200. In one embodiment, each pair of second-type lateral isolation trenches 79B may be laterally spaced apart from each other along the second horizontal direction hd2 by a gap located within the contact region 200 and including the etch-back stepped dielectric material portion 65 and a pair of access cavities 179. In one embodiment, each pair of second-type lateral isolation trenches 79B may be aligned with a corresponding pair of access cavities 179 along the second horizontal direction hd2. In this case, each longitudinal sidewall of the second-type lateral isolation trench 79B may be formed in a vertical plane parallel to the first horizontal direction hd1. The vertical plane may include the longitudinal sidewall of another second-type lateral isolation trench 79B within the corresponding pair of second-type lateral isolation trenches 79B and include the longitudinal sidewalls of the pair of access cavities 179. In one embodiment, each pair of second-type lateral isolation trenches 79B may be positioned in the middle between an adjacent pair of first-type lateral isolation trenches 79A.

[0248] The width of the lateral isolation trench 79 may be greater than the thickness of each sacrificial material layer 42. For example, the ratio of the width of the lateral isolation trench 79 along the second horizontal direction hd2 to the thickness of each sacrificial material layer 42 may range from 2 to 30 (such as 4 to 15), but smaller or larger ratios may also be employed. According to one aspect of the present disclosure, first-tier lateral isolation trenches 79A may be formed between adjacent pairs of etch-back stepped dielectric material portions 65, and each pair of second-type lateral isolation trenches 79B may be laterally located at the level of a respective one of the etch-back stepped dielectric material portions 65 along the first horizontal direction hd1.

[0249] Generally, the lateral isolation trench 79 extending laterally along the first horizontal direction hd1 may be formed through the contact-level dielectric layer 80 and the alternating stack (32, 42). The alternating stack (32, 42) is divided by the first-type lateral isolation trenches 79A into a plurality of alternating stacks (32, 42) that are laterally spaced apart along the second horizontal direction hd2. Layer stacks (32, 42, 80) are formed, each of these layer stacks including a respective patterned portion of the contact-level dielectric layer 80 and a respective alternating stack (32, 42), and being laterally spaced apart from each other by the lateral isolation trench 79. In one embodiment, each pair of second-type lateral isolation trenches 79B is laterally spaced apart from a respective one of the etch-back stepped dielectric material portions 65 by a respective pair of access cavities 179. Each pair of access cavities 179 is laterally spaced apart along the first horizontal direction hd1 by a respective one of the etch-back stepped dielectric material portions 65.

[0250] Reference Figures 21A to 21C , a sacrificial fill material may be deposited in the lateral isolation trench 79 and the access cavity 179, and then the sacrificial fill material may be selectively removed with respect to the materials of the insulating layer 32 and the sacrificial material layer 42. The sacrificial fill material may include, for example, a carbon-based material (such as amorphous carbon or diamond-like carbon) or a semiconductor material (such as amorphous silicon). Optionally, a thin sacrificial liner (not shown), such as a silicon oxide liner or a silicon nitride liner, may be deposited in the lateral isolation trench 79 and the access cavity 179 before depositing the sacrificial fill material. The excess portion of the sacrificial fill material may be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by performing a planarization process (such as a chemical mechanical planarization (CMP) process). Each portion of the sacrificial fill material that fills the first-type lateral isolation trench 79A constitutes a first-type sacrificial lateral isolation trench fill structure 75A, each portion of the sacrificial fill material that fills the second-type lateral isolation trench 79B constitutes a second-type sacrificial lateral isolation trench fill structure 75B, and each portion of the sacrificial fill material that fills the access cavity 179 constitutes a sacrificial access cavity fill structure (not shown).

[0251] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form an opening in the region above the access cavity 179 while covering the region of the lateral isolation trench 79. A selective etching process may be performed to remove the sacrificial access cavity fill structure from the access cavity 179. Voids are formed in the access cavity 179, and these voids include the empty volume from which the sacrificial access cavity fill structure has been removed. Subsequently, the photoresist layer may be removed, for example, by ashing. A first type of sacrificial lateral isolation trench fill structure 75A is present in the first type of lateral isolation trench 79A, and a second type of sacrificial lateral isolation trench fill structure 75B is present in the second type of lateral isolation trench 79B.

[0252] Reference Figures 22A to 22D , an isotropic etching process may be performed to laterally recess the sacrificial material layer 42 from around the access cavity 179. For example, if the sacrificial material layer 42 comprises silicon nitride, a wet etching process using hot phosphoric acid may be performed to laterally recess the sacrificial material layer 42 around each of the access cavities 179. The first type of sacrificial lateral isolation trench fill structure 75A and the second type of sacrificial lateral isolation trench fill structure 75B prevent the isotropic etchant of the isotropic etching process from entering the lateral isolation trench 79.

[0253] A recessed cavity is formed in the volume of the material from which the sacrificial material layer 42 has been removed. A vertical stack of recessed cavities may be formed around each access cavity 179. The recessed cavities project laterally outward from the respective access cavity 179 in the shape of laterally protruding fins and are thus referred to herein as fin grooves 143. Generally speaking, by laterally recessing the sacrificial material layer 42 isotropically, fin grooves 143 may be formed around each of the access cavities 179. Each adjacent combination of an access cavity 179 and the vertical stack of fin grooves 143 is referred to herein as a fin cavity (179, 143).

[0254] The etching distance of the isotropic etching process for forming the fin grooves 143 is less than the lateral pitch in the memory array region 100 between adjacent pairs of first-type lateral isolation trenches 79A and second-type lateral isolation trenches 79B along the second horizontal direction hd2. According to one aspect of the present disclosure, the etching distance of the isotropic etching process is greater than the lateral distance of any gap between the access cavity 179 and an adjacent second-type lateral isolation trench 79B, and greater than the lateral distance of any gap between the access cavity 179 and an adjacent re-entrant stepped dielectric material portion 65. The ratio of the etching distance of the isotropic etching process to the lateral pitch in the memory array region 100 between adjacent pairs of first-type lateral isolation trenches 79A and second-type lateral isolation trenches 79B along the second horizontal direction hd2 can be in the range of 0.1 to 0.7 (such as 0.15 to 0.4), but smaller or larger ratios can also be employed. Each of the fin grooves 143 can be laterally defined by a sidewall segment 145 of a corresponding sacrificial material layer 42.

[0255] Reference Figures 23A to 23D , a dielectric fill material can be deposited in the fin cavities (179, 143). The dielectric fill material can include, for example, silicon oxide, silicon carbonitride, silicon oxynitride, and / or dielectric metal oxides. In one embodiment, the dielectric fill material can include silicon oxide. The excess portion of the dielectric fill material can be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process (such as a recess etching process). Each remaining portion of the dielectric fill material filling the corresponding fin cavities (179, 143) constitutes a fin insulating support structure 176.

[0256] Generally, the fin insulating support structures 176 can be formed in the volumes of the fin grooves 143 and the access cavities 179. Each of the fin insulating support structures 176 includes a corresponding vertical stack of a corresponding vertically extending insulating core 176C and insulating fins 176F extending laterally outward from the corresponding vertically extending insulating core 176C. Each pair of second-type lateral isolation trenches 79B are laterally spaced apart from each other along the first horizontal direction hd1 by a corresponding set of two fin insulating support structures 176 and re-entrant stepped dielectric material portions 65. In one embodiment, each interface between a fin insulating support structure 176 and the sacrificial material layer 42 includes a corresponding convex sidewall segment of the insulating fin 176F of the fin insulating support structure 176 that contacts a corresponding concave sidewall segment of the sacrificial material layer 42. In one embodiment, each interface between a pair of fin insulating support structures 176 and the re-entrant stepped dielectric material portion 65 includes a corresponding flat sidewall segment of the insulating fins 176F of the pair of fin insulating support structures 176 that contacts a corresponding flat sidewall segment of the re-entrant stepped dielectric material portion 65.

[0257] Reference Figures 24A to 24I, the sacrificial lateral isolation trench fill structures (75A, 75B) can be selectively removed for the materials of the alternating stacks (32, 42) and the fin-type insulating support structure 176. A void is formed in the volume of the lateral isolation trench 79.

[0258] An isotropic etching process can be performed to introduce an isotropic etchant for etching the material of the sacrificial material layer 42 into the lateral isolation trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the isotropic etching process can include a wet etching process using hot phosphoric acid. A laterally extending cavity 43 is formed in the volume of the plurality of portions from which the sacrificial material layer 42 is removed by the isotropic etching process. Generally, the laterally extending cavity 43 can be formed by performing an isotropic etching process in which the isotropic etchant is supplied to the first type of lateral isolation trenches 79A and a plurality of pairs of the second type of lateral isolation trenches 79B.

[0259] According to one aspect of the present disclosure, the isotropic etching process has an etching distance that is greater than the lateral spacing between the first type of lateral isolation trench 79A and the nearest fin-type insulating support structure in the fin-type insulating support structure 176 along the second horizontal direction hd2. In one embodiment, the etching distance is less than the lateral distance between an adjacent pair of the first type of lateral isolation trench 79A and the second type of lateral isolation trench 79B. In one embodiment, the isotropic etching process has an etching distance that is greater than half of the lateral distance between the first type of lateral isolation trench 79A and the nearest pair of the second type of lateral isolation trenches 79B to the first type of lateral isolation trench 79A. In one embodiment, the etching distance is less than the lateral dimension of one of the fin-type insulating support structures 176 along the first horizontal direction hd1.

[0260] After the isotropic etching process, the remaining portions of the sacrificial material layer 42 are present between the plurality of pairs of fin-type insulating support structures 176 that are laterally spaced apart from each other along the first horizontal direction hd1. The remaining portions of the sacrificial material layer 42 constitute a vertical stack of dielectric material plates 42'. The vertical stack of dielectric material plates 42' can be formed under each of the etch-back stepped dielectric material portions 65. In Figure 24B and Figure 24H In one embodiment shown, the etch-back stepped dielectric material portion 65 can have a first lateral extent LE1 along the second horizontal direction hd2, and the dielectric material plates 42' in the vertical stack of dielectric material plates 42' can have a second lateral extent LE2 along the second horizontal direction hd2, and the second lateral extent is less than the first lateral extent LE1.

[0261] In one embodiment, a plurality of dielectric material plates 42' within a vertical stack of dielectric material plates 42' may have a uniform width along a second horizontal direction hd2, which uniform width is less than the minimum lateral dimension of the etch-back stepped dielectric material portion 65 along the second horizontal direction hd2. In one embodiment, the dielectric material plates 42' within each vertical stack of dielectric material plates 42' may have lateral extents along a first horizontal direction hd1, and these lateral extents decrease with the vertical distance from the substrate 8. In one embodiment, each dielectric material plate 42' within a vertical stack of dielectric material plates 42' may have a respective sidewall that is parallel to the second horizontal direction hd2 and contacts a respective vertical sidewall segment of the etch-back stepped dielectric material portion 65.

[0262] In Figure 24H In one embodiment as shown, one or more dielectric material plates 42' within a vertical stack of dielectric material plates 42' may include concave sidewall segments 42C located at the same level as the respective laterally extending cavities 43. A dielectric material plate region R42' may be formed between each pair of second type lateral isolation trenches 79B that are laterally spaced apart from each other along the first horizontal direction hd1.

[0263] In Figure 24H In one embodiment as shown, each interface between a pair of fin-type insulating support structures 176 and a vertical stack of dielectric material plates 42' includes a respective convex sidewall segment of the insulating fin 176F that contacts a respective concave sidewall segment 42C of the vertical stack of dielectric material plates 42'. In one embodiment, each interface between a pair of fin-type insulating support structures 176 and the etch-back stepped dielectric material portion 65 includes a respective flat sidewall segment of the insulating fin 176F that contacts a respective flat sidewall segment 65P of the etch-back stepped dielectric material portion 65.

[0264] Referring Figures 25A to 25I , a backside blocking dielectric layer 44 may optionally be deposited in the laterally extending cavities 43 on the physically exposed surfaces of the etch-back stepped dielectric material portion 65, the dielectric material plates 42', and the insulating layer 32 by a conformal deposition process. The backside blocking dielectric layer 44 comprises a dielectric material such as a dielectric metal oxide (e.g., alumina) and / or silicon oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 3 nm to 12 nm, although smaller and larger thicknesses may also be employed.

[0265] At least one conductive material can be deposited in the unfilled volume of the laterally extending cavity 43 by providing at least one reactant gas into the laterally extending cavity 43 via the lateral isolation trench 79. For example, the at least one conductive material can include a metal barrier layer and a metal fill material. The metal barrier layer includes a conductive metal material that can act as a diffusion barrier layer and / or an adhesion promoting layer for the metal fill material to be deposited subsequently. The metal barrier layer can include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can be in the range of 2 nm to 8 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses can also be employed. In one embodiment, the metal barrier layer can consist essentially of a conductive metal nitride such as TiN.

[0266] The metal fill material can be deposited on top of the metal barrier layer to form a metal fill material layer. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) can be used to deposit the metal fill material layer. In one embodiment, the metal fill material layer can be a tungsten layer including residual levels of fluorine atoms as impurities. The metal fill material layer is spaced apart from the insulating layer 32 and the memory opening fill structure 58 by the metal barrier layer, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0267] A plurality of conductive layers 46 can be formed in the plurality of laterally extending cavities 43, and a continuous metal material layer can be formed on the sidewalls of each lateral isolation trench 79 and on top of the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the metal barrier layer and a portion of the metal fill material layer that are located between a vertically adjacent pair of dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer that are located in the lateral isolation trench 79 or above the contact-level dielectric layer 80.

[0268] By performing an etching process that etches at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each of the laterally isolated trenches 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the laterally extending cavity 43 constitutes a conductive layer 46. Each conductive layer 46 can be a conductive wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0269] Each conductive layer 46 can act as a combination of a plurality of control gate electrodes located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device including the memory stack structure 55. In other words, each conductive layer 46 can be a word line that acts as a common control gate electrode for a plurality of vertical memory devices.

[0270] Generally speaking, a plurality of portions of the sacrificial material layer 42 are replaced by a vertical stack of the conductive layers 46. In one embodiment, each vertical stack of the conductive layers 46 is formed between the nearest first-type laterally isolated trench 79A and the nearest pair of second-type laterally isolated trenches 79B, and does not laterally extend further than the nearest first-type laterally isolated trench and the nearest pair of second-type laterally isolated trenches along the second horizontal direction hd2.

[0271] In one embodiment, the insulating layers 32 can be vertically spaced apart from each other and can continuously extend between a pair of first-type laterally isolated trenches 79A. For each vertical stack of the insulating layer 32 that laterally extends between an adjacent pair of first-type laterally isolated trenches 79A, a vertical stack of the first conductive layer 46 can be located on a first side of the vertical stack of the dielectric material plate 42' and can be staggered with the vertical stack of the insulating layer 32, and a vertical stack of the second conductive layer 46 can be located on a second side of the vertical stack of the dielectric material plate 42' and can be staggered with the vertical stack of the insulating layer 32.

[0272] Each fin-type insulating support structure 176 includes a corresponding vertically extending insulating core 176C that vertically extends through each layer within the first alternating stack (32, 46) and the second alternating stack (32, 46), and also includes a corresponding vertical stack of insulating fins 176F that laterally extend outward from the corresponding vertically extending insulating core 176C.

[0273] Reference Figures 26A to 26C can be performed with reference Figure 16A and Figure 16BThe described processing steps form a source region 61 below the lateral isolation trench 79 and fill the lateral isolation trench 79 with a lateral isolation trench fill structure (74, 76). The lateral isolation trench fill structure (74, 76) may include a first lateral isolation trench fill structure (74A, 76A) that fills the first lateral isolation trench 79A and a second type of lateral isolation trench fill structure (74B, 76B) that fills the second type of lateral isolation trench 79B.

[0274] The insulating layers 32 may be vertically spaced apart from each other and may be located over the substrate 8 between a first first type of lateral isolation trench fill structure (74A, 76A) and a second first type of lateral isolation trench fill structure (74A, 76A). The first and second first type of lateral isolation trench fill structures extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2. The first conductive layer 46 may be vertically interleaved with the insulating layers 32 and may contact the first first type of lateral isolation trench fill structure (74A, 76A). The second conductive layer 46 may be vertically interleaved with the insulating layers 32 and may contact the second first type of lateral isolation trench fill structure (74A, 76A).

[0275] A composite dielectric isolation structure {65, 42', 176, 74B} may be formed between the vertical stacks of the first conductive layer 46 and the second conductive layer 46 and may provide electrical isolation between these vertical stacks, which are located between an adjacent pair of first lateral isolation trench fill structures (74A, 76A). In one embodiment, the composite dielectric isolation structure includes an etch-back stepped dielectric material portion 65 having a first lateral extent LE1 along the second horizontal direction hd2 and a pair of fin-like insulating support structures 176, each fin-like insulating support structure including a respective vertically extending insulating core 176C that vertically extends through each layer within the first alternating stack (32, 46) and the second alternating stack (32, 46), and each fin-like insulating support structure further including a respective vertical stack of insulating fins 176F that extend laterally outward from the respective vertically extending insulating core 176C.

[0276] In one embodiment, the composite dielectric isolation structure further includes a pair of second-type lateral isolation trench fill structures (74B, 76B) that are laterally spaced apart along a first horizontal direction hd1. In one embodiment, each of the pair of second-type lateral isolation trench fill structures (74B, 76B) is in direct contact with a corresponding one of the pair of fin-type insulating support structures 176. In one embodiment, the etch-back stepped dielectric material portion 65 is laterally spaced apart from the pair of second-type lateral isolation trench fill structures (74B, 76B) by the pair of fin-type insulating support structures 176.

[0277] Reference Figures 27A to 27E , a photoresist layer may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form openings over the regions of the memory opening fill structure 58 and the horizontal extension portions of the conductive layer 46 that are located below the stepped bottom surface of the etch-back stepped dielectric material portion 65. An anisotropic etching process may be performed to form a drain contact via cavity over the drain region 63 of the memory opening fill structure 58 and a layer contact via cavity over the horizontal extension surface of the conductive layer 46 that is located below the etch-back stepped dielectric material portion 65. At least one conductive material may be deposited in the drain contact via cavity to form a drain contact via structure 88 and may be deposited in the layer contact via cavity to form a layer contact via structure 86.

[0278] Reference Figures 1 to 8B and Figures 20A to 27EAnd according to a second embodiment of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: insulating layers 32 that are vertically spaced apart from each other and extend continuously laterally between a first first-type laterally isolated trench fill structure (74A, 76A) and a second first-type laterally isolated trench fill structure (74A, 76A), the first first-type laterally isolated trench fill structure and the second first-type laterally isolated trench fill structure extending laterally along a first horizontal direction hd1 and being laterally spaced apart from each other along a second horizontal direction hd2; first conductive layers 46 that are vertically interleaved with the insulating layers 32 and contact the first first-type laterally isolated trench fill structure (74A, 76A); second conductive layers 46 that are vertically interleaved with the insulating layers 32 and contact the second first-type laterally isolated trench fill structure (74A, 76A); and a composite dielectric isolation structure {65, 42', 176, 74B}, the composite dielectric isolation structure being located between the first conductive layers 46 and the second conductive layers 46, wherein the composite dielectric isolation structure includes a re-entrant stepped dielectric material portion 65 and a pair of fin-type insulating support structures 176, each fin-type insulating support structure including a respective vertically extending insulating core 176C and a respective vertical stack of insulating fins 176F that extend laterally outward from the respective vertically extending insulating core 176C.

[0279] In one embodiment, the composite dielectric isolation structure {65, 42', 176, (74B, 76B)} further includes a pair of second-type laterally isolated trench fill structures (74B, 76B) that are laterally spaced apart along the first horizontal direction hd1. In one embodiment, each second-type laterally isolated trench fill structure (74B, 76B) of the pair of second-type laterally isolated trench fill structures (74B, 76B) is in direct contact with a respective one of the pair of fin-type insulating support structures 176. In one embodiment, the re-entrant stepped dielectric material portion 65 is laterally spaced apart from the pair of second-type laterally isolated trench fill structures (74B, 76B) by the pair of fin-type insulating support structures 176. In one embodiment, the vertically extending insulating core 176C extends vertically through each layer within the first alternating stack (32, 46) and the second alternating stack (32, 46).

[0280] In one embodiment, the etch-back stepped dielectric material portion 65 has a first lateral extent LE1 along the second horizontal direction hd2; and the composite dielectric isolation structure {65, 42', 176, 74B} further includes a vertical stack of dielectric material plates 42', each dielectric material plate having a second lateral extent LE2 along the second horizontal direction hd2, the second lateral extent being less than the first lateral extent LE1. In one embodiment, the dielectric material plates 42' within the vertical stack of dielectric material plates 42' have a lateral extent along the first horizontal direction hd1 that decreases with the vertical distance from the substrate 8. In one embodiment, each dielectric material plate 42' within the vertical stack of dielectric material plates 42' has a respective sidewall that is parallel to the second horizontal direction hd2 and contacts a respective vertical sidewall segment of the etch-back stepped dielectric material portion 65.

[0281] In one embodiment, each interface between a pair of fin-type insulating support structures 176 and the vertical stack of dielectric material plates 42' includes a respective convex sidewall segment of the insulating fin 176F that contacts a respective concave sidewall segment of the vertical stack of dielectric material plates 42'; and each interface between the pair of fin-type insulating support structures 176 and the etch-back stepped dielectric material portion 65 includes a respective flat sidewall segment of the insulating fin 176F that contacts a respective flat sidewall segment of the etch-back stepped dielectric material portion 65.

[0282] Reference Figures 28A to 28C , the third exemplary structure according to the third embodiment of the present disclosure can be obtained from the first exemplary structure illustrated in Figures 9A to 9C by changing the pattern of the openings in the photoresist layer before performing the anisotropic etching process for forming the lateral isolation trenches 79. Specifically, the patterns of each of the pair of second-type lateral isolation trenches 79B can be merged with each other by laterally extending the pair of second-type lateral isolation trenches 79B located between a respective adjacent pair of first-type lateral isolation trenches 79A through the contact region 200, thereby forming a second-type lateral isolation trench 79C that laterally extends through the first memory array region 100A, the contact region 200, and the second memory array region 100B.

[0283] Each of the lateral isolation trenches 79 extends laterally along a first horizontal direction hd1 through the alternating stack (32, 46). Each first type lateral isolation trench 79A is formed between a respective adjacent pair of re-entrant stepped dielectric material portions 65 and does not cut through any of the re-entrant stepped dielectric material portions 65. Each of the second type lateral isolation trenches 79C cuts through a respective one of the re-entrant stepped dielectric material portions 65 and divides the respective one of the re-entrant stepped dielectric material portions 65 into a respective pair of re-entrant stepped dielectric material portions 65 that are spaced apart from each other along a second horizontal direction hd2. The first type lateral isolation trenches 79A and the second type lateral isolation trenches 79C are staggered along the second horizontal direction hd2. The first type lateral isolation trenches 79A are laterally staggered along the second horizontal direction hd2 with multiple pairs of stepped dielectric material portions 65.

[0284] The width of the lateral isolation trenches 79 may be greater than the thickness of each sacrificial material layer 42. For example, the ratio of the width of the lateral isolation trenches 79 along the second horizontal direction hd2 to the thickness of each sacrificial material layer 42 may be in the range of 2 to 30 (such as 4 to 15), but smaller or larger ratios may also be employed. According to one aspect of the present disclosure, the first order lateral isolation trenches 79A may be formed between adjacent multiple pairs of re-entrant stepped dielectric material portions 65, and each pair of second type lateral isolation trenches 79C may cut through a respective one of the re-entrant stepped dielectric material portions 65.

[0285] Generally, the lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the contact level dielectric layer 80 and the alternating stack (32, 42). The alternating stack (32, 42) is divided by the lateral isolation trenches 79 into multiple alternating stacks (32, 42) that are laterally spaced apart along the second horizontal direction hd2. Layer stacks (32, 42, 80) are formed, each of these layer stacks including a respective patterned portion of the contact level dielectric layer 80 and a respective alternating stack (32, 42), and being laterally spaced apart from each other by the lateral isolation trenches 79.

[0286] A plurality of alternating stacks of the insulating layer 32 and the sacrificial material layer 42 may be formed over the semiconductor material layer 110. Each alternating stack of the insulating layer 32 and the sacrificial material layer 42 may be formed between a respective adjacent pair of a first type of lateral isolation trench 79A and a second type of lateral isolation trench 79C. Each of the recessed stepped dielectric material portions 65 has a respective first variable lateral extent along a first horizontal direction hd1, and the respective first variable lateral extent increases stepwise with the vertical distance from the horizontal plane including the bottom surface of the alternating stack (32, 42). Each of the recessed stepped dielectric material portions 65 has a respective second variable lateral extent along a second horizontal direction hd2, and the second variable lateral extent increases gradually without any steps with the vertical distance from the horizontal plane including the bottom surface of the alternating stack (32, 42).

[0287] Reference Figures 29A to 29C , a sacrificial fill material may be deposited in the lateral isolation trenches 79, and then the sacrificial fill material may be selectively removed with respect to the materials of the insulating layer 32 and the sacrificial material layer 42. The sacrificial fill material may include, for example, a carbon-based material (such as amorphous carbon or diamond-like carbon) or a semiconductor material (such as amorphous silicon). Optionally, a thin sacrificial liner (not shown), such as a silicon oxide liner or a silicon nitride liner, may be deposited in the lateral isolation trenches 79 before depositing the sacrificial fill material. The excess portion of the sacrificial fill material may be removed from above the horizontal plane including the top surface of the contact level dielectric layer 80 by performing a planarization process (such as a chemical mechanical planarization (CMP) process). A sacrificial lateral isolation trench fill structure 75 is formed in the lateral isolation trenches 79.

[0288] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and may be lithographically patterned to form openings in regions above multiple portions of the second type of lateral isolation trench 79C that are within the contact region 200, while covering all regions of the first type of lateral isolation trench 79A and regions of multiple portions of the second type of lateral isolation trench 79C that are within the memory array region 100. Optionally, regions of the second type of lateral isolation trench 79C that are in the peripheral portions of the contact region 200 near the memory array region 100 may be covered by the photoresist layer. An etching process may be performed to remove the sacrificial lateral isolation trench fill structure 75 in regions not covered by the patterned photoresist layer. Void spaces are formed in the volumes of the multiple portions from which the sacrificial lateral isolation trench fill structure 75 is removed. The void spaces are referred to herein as isolation cavities 279, and these isolation cavities include the empty volumes of the multiple portions from which the sacrificial lateral isolation trench fill structure 75 is removed. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0289] Generally, the entirety of each of the first lateral isolation trenches 79A and the first portion of the second type of lateral isolation trenches 79C that is outside the contact region 200 may be filled with a sacrificial trench fill material to provide a sacrificial lateral isolation trench fill structure 75. The second portion of the second type of lateral isolation trenches 79C that is in the contact region 200 is not filled with the sacrificial trench fill material to provide isolation cavities 279. In one embodiment, each of the isolation cavities 279 may have a lateral extent along the first horizontal direction hd1 that is greater than any of those in the etch-back stepped dielectric material portions 65. In this case, each of the etch-back stepped dielectric material portions 65 may have a longitudinal sidewall that is completely physically exposed to a corresponding one of the isolation cavities 279.

[0290] Reference Figures 30A to 30E , an optional first isotropic etch process may be performed to laterally recess the sacrificial material layer 42 from around the isolation cavities 279. For example, if the sacrificial material layer 42 comprises silicon nitride, a wet etch process using hot phosphoric acid may be performed to laterally recess the sacrificial material layer 42 around each of the isolation cavities 279. The sacrificial lateral isolation trench fill structure 75 prevents the isotropic etchant of the isotropic etch process from entering the portions of the lateral isolation trenches 79 that are filled with the sacrificial lateral isolation trench fill structure 75.

[0291] A recessed cavity is formed in the volume of the material from which the sacrificial material layer 42 is removed. A vertical stack of the recessed cavities may be formed around each of the isolation cavities 279. The recessed cavities project laterally outward from the corresponding isolation cavities 279 in the shape of laterally protruding fins and are thus referred to herein as fin grooves 143. Generally, the fin grooves 143 may be formed around each of the isolation cavities 279 by performing a first isotropic etch process that selectively etches a first portion of the sacrificial material layer 42 with respect to the insulating layer 32. The first isotropic etch process laterally recesses the sacrificial material layer 42 isotropically to form the fin grooves 143. Each adjacent combination of an isolation cavity 279 and the vertical stack of fin grooves 143 is referred to herein as a fin cavity (279, 143). Generally, the fin grooves 143 may be formed around the isolation cavities 279 by performing a first isotropic etch process that selectively etches a first portion of the sacrificial material layer 42 with respect to the insulating layer 32.

[0292] The etching distance of the isotropic etching process for forming the fin grooves 143 is less than the lateral spacing along the second horizontal direction hd2 between adjacent pairs of first type lateral isolation trenches 79A and second type lateral isolation trenches 79C. The ratio of the etching distance of the isotropic etching process to the lateral spacing along the second horizontal direction hd2 between adjacent pairs of first type lateral isolation trenches 79A and second type lateral isolation trenches 79C can be in the range of 0.1 to 0.7 (such as 0.15 to 0.4), but smaller or larger ratios can also be used. Each of the fin grooves 143 can be laterally defined by sidewall segments 145 of a corresponding sacrificial material layer 42. Alternatively, the formation of the fin grooves 143 can also be omitted.

[0293] Reference Figures 31A to 31E , a dielectric filling material can be deposited in the fin cavities (279, 143). If the fin grooves 143 are omitted, the dielectric filling material is only deposited in the isolation cavity 279. The dielectric filling material can include, for example, silicon oxide, silicon carbonitride, silicon oxynitride, and / or dielectric metal oxides. In one embodiment, the dielectric filling material can include silicon oxide. The excess portion of the dielectric filling material can be removed from above the horizontal plane of the top surface of the contact level dielectric layer 80 through a planarization process (such as a recess etching process). The filling of each remaining portion of the corresponding fin cavities (279, 143) with the dielectric filling material constitutes the fin insulating support structure 276. If the fin cavities 143 are omitted, each remaining portion of the dielectric filling material filling the corresponding isolation cavity 279 constitutes the insulating support structure 276.

[0294] Generally speaking, the fin insulating support structure 276 can be formed in the volumes of the fin grooves 143 and the isolation cavities 279. Each of the insulating support structures (e.g., the fin insulating support structure) 276 includes a corresponding vertical insulating wall portion 276W and a corresponding vertical stack of insulating fins 276F (optionally) extending laterally outward from the corresponding vertical insulating wall portion 276W. In one embodiment, each interface between the fin insulating support structure 276 and the sacrificial material layer 42 includes a corresponding convex sidewall segment of the insulating fin 276F of the fin insulating support structure 276 that contacts a corresponding concave sidewall segment of the sacrificial material layer 42, and also includes a corresponding flat sidewall segment of the insulating fin 276F that contacts a corresponding flat surface segment of the sacrificial material layer 42 parallel to the first horizontal direction hd1. In one embodiment, each interface between a pair of fin insulating support structures 276 and the re-entrant stepped dielectric material portion 65 includes a corresponding flat sidewall segment of the insulating fin 276F of the pair of fin insulating support structures 276 that contacts a corresponding flat sidewall segment (parallel to the second horizontal direction hd2) of the re-entrant stepped dielectric material portion 65.

[0295] In one embodiment, each fin-type insulating support structure 276 includes a vertical insulating wall portion 276W located between a pair of re-entrant stepped dielectric material portions 65, and optionally further includes a vertical stack of insulating fins 276F extending laterally outward from the vertical insulating wall portion 276W. In one embodiment, the vertical insulating wall portion 276W includes a first longitudinal sidewall and a second longitudinal sidewall, the first longitudinal sidewall extending laterally along a first horizontal direction hd1 and contacting a first re-entrant stepped dielectric material portion 65 of the pair of re-entrant stepped dielectric material portions 65, and the second longitudinal sidewall extending laterally along the first horizontal direction hd1 and contacting a second re-entrant stepped dielectric material portion 65 of the pair of re-entrant stepped dielectric material portions 65.

[0296] In one embodiment, within each fin-type insulating support structure 276, each vertical stack of insulating fins 276F has a variable lateral extent along the first horizontal direction hd1, and the variable lateral extent decreases with the vertical distance from the horizontal plane of the bottom surface including the alternating stack (32, 42). In one embodiment, within each fin-type insulating support structure 276, each vertical stack of insulating fins 276F has the same lateral extent along a second horizontal direction hd2, and the same lateral extent does not vary with the vertical distance from the horizontal plane of the bottom surface including the alternating stack (32, 42).

[0297] Reference Figures 32A to 32H , the sacrificial lateral isolation trench fill structure 75 can be selectively removed for the materials of the alternating stack (32, 42) and the fin-type insulating support structure 276. Void spaces are formed in the volume of the lateral isolation trench 79.

[0298] A second isotropic etching process can be performed to introduce an isotropic etchant for etching the material of the sacrificial material layer 42 into the void spaces (which are formed by removing the sacrificial lateral isolation trench fill structure 75) in the lateral isolation trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the second isotropic etching process can include a wet etching process using hot phosphoric acid. A laterally extending cavity 43 is formed in the volume from which multiple portions of the sacrificial material layer 42 are removed by the second isotropic etching process. Generally, the laterally extending cavity 43 can be formed by performing an isotropic etching process in which the isotropic etchant is provided to the first type of lateral isolation trench 79A and the second type of lateral isolation trench 79C.

[0299] According to one aspect of the present disclosure, the isotropic etching process has an etching distance that is greater than the lateral spacing along the second horizontal direction hd2 between the first type of lateral isolation trench 79A and the nearest fin insulation support structure in the fin insulation support structure 276. In one embodiment, the etching distance is less than the lateral distance between an adjacent pair of the first type of lateral isolation trench 79A and the second type of lateral isolation trench 79C. In one embodiment, the isotropic etching process has an etching distance that is greater than half of the lateral distance between an adjacent pair of the first type of lateral isolation trench 79A and the second type of lateral isolation trench 79C. In one embodiment, the etching distance is less than the lateral dimension of the fin insulation support structure 276 along the first horizontal direction hd1. In one embodiment, each interface between a pair of fin insulation support structures 276 and the re-entrant stepped dielectric material portion 65 includes a respective flat sidewall segment of the insulating fin 276F that contacts a respective flat sidewall segment of the re-entrant stepped dielectric material portion 65.

[0300] Reference Figures 33A to 33H , a backside barrier dielectric layer 44 can be optionally deposited in the laterally extended cavity 43 on the physically exposed surfaces of the re-entrant stepped dielectric material portion 65, the fin insulation support structure 276, and the insulating layer 32 by a conformal deposition process. The backside barrier dielectric layer 44 comprises a dielectric material such as a dielectric metal oxide (such as aluminum oxide) and / or silicon oxide. The thickness of the backside barrier dielectric layer 44 can be in the range of 3 nm to 12 nm, although smaller and larger thicknesses can also be employed.

[0301] At least one conductive material can be deposited in the unfilled volume of the laterally extended cavity 43 by providing at least one reactant gas into the laterally extended cavity 43 via the lateral isolation trench 79. For example, the at least one conductive material can include a metal barrier layer and a metal fill material as described above.

[0302] A plurality of conductive layers 46 can be formed in the plurality of laterally extended cavities 43, and a continuous metal material layer can be formed on the sidewalls of each lateral isolation trench 79 and above the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the metal barrier layer and a portion of the metal fill material layer that are located between a vertically adjacent pair of dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer that are located in the lateral isolation trench 79 or above the contact-level dielectric layer 80.

[0303] By performing an etching process that etches at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each of the lateral isolation trenches 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the laterally extending cavity 43 constitutes a conductive layer 46. Each conductive layer 46 can be a wire-like conductive structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0304] In one embodiment, each vertical stack of the conductive layers 46 is formed between the nearest first-type lateral isolation trench 79A and the nearest second-type lateral isolation trench 79C, and does not laterally extend further along the second horizontal direction hd2 than the nearest first-type lateral isolation trench and the nearest second-type lateral isolation trench.

[0305] In one embodiment, the insulating layers 32 can be vertically spaced apart from each other and can be located between a first-type lateral isolation trench 79A and a pair of second-type lateral isolation trenches 79C, which laterally extend along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2. A first alternating stack of the first insulating layer 32 and the first conductive layer 46 can be formed on one side of each fin-type insulating support structure 276, and a second alternating stack of the second insulating layer 32 and the second conductive layer 46 can be formed on the other side of each fin-type insulating support structure 276.

[0306] Each fin-type insulating support structure 276 includes a respective vertical insulating wall portion 276W that vertically extends through each layer within the first alternating stack (32, 46) and the second alternating stack (32, 46), and optionally further includes a respective vertical stack of insulating fins 276F that laterally extend outward from the respective vertical insulating wall portion 276W.

[0307] Reference Figures 34A to 34C , the processing steps described in reference Figure 16A and Figure 16B can be performed to form a source region 61 below the lateral isolation trench 79 and to fill the lateral isolation trench 79 with a lateral isolation trench filling structure (74, 76). The lateral isolation trench filling structure (74, 76) can include a first lateral isolation trench filling structure (74A, 76A) that fills the first lateral isolation trench 79A and a second lateral isolation trench filling structure (74B, 76B) that fills the second lateral isolation trench 79C.

[0308] The first alternating stack of the first insulating layer 32 and the second conductive layer 46 and the second alternating stack of the second insulating layer 32 and the second conductive layer 46 may be formed between a pair of adjacent first-type laterally isolated trench fill structures (74A, 76A). A composite dielectric isolation structure {65, 276, 74B} may be formed between the first alternating stack (32, 46) and the second alternating stack (32, 46). The composite dielectric isolation structure includes: a pair of re-entrant stepped dielectric material portions 65; an insulating support structure (e.g., a fin-type insulating support structure) 276, the insulating support structure including a vertical insulating wall portion 276W located between the pair of re-entrant stepped dielectric material portions 65, and optionally further including a vertical stack of insulating fins 276F extending laterally outward from the vertical insulating wall portion 276W; and a pair of second-type laterally isolated trench fill structures (74B, 76B), the pair of second-type laterally isolated trench fill structures being laterally spaced apart along a first horizontal direction hd1. In one embodiment, the vertical insulating wall portion 276W includes a first end wall in contact with one of the pair of second-type laterally isolated trench fill structures (74B, 76B), and a second end wall in contact with the other of the pair of second-type laterally isolated trench fill structures (74B, 76B).

[0309] Reference Figures 35A to 35E , a photoresist layer may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form openings over the memory opening fill structure 58 and the regions of the horizontal extensions of the conductive layer 46 that are located below the stepped bottom surfaces of the re-entrant stepped dielectric material portions 65. An anisotropic etching process may be performed to form a drain contact via cavity over the drain region 63 of the memory opening fill structure 58 and a layer contact via cavity over the horizontal extension surface of the conductive layer 46 that is located below the re-entrant stepped dielectric material portion 65. At least one conductive material may be deposited in the drain contact via cavity to form a drain contact via structure 88 and may be deposited in the layer contact via cavity to form a layer contact via structure 86.

[0310] Reference Figures 1 to 8B and Figures 28A to 35EAnd according to a third embodiment of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device including: a first alternating stack (32, 46) of a first insulating layer 32 and a first conductive layer 46 and a second alternating stack (32, 46) of a second insulating layer 32 and a second conductive layer 46, the first alternating stack and the second alternating stack being located on a substrate 8 between a pair of first-type lateral isolation trench filling structures (74A, 76A), the pair of first-type lateral isolation trench filling structures extending laterally along a first horizontal direction hd1 and being laterally spaced apart from each other along a second horizontal direction hd2; and a composite dielectric isolation structure, the composite dielectric isolation structure being located between the first alternating stack (32, 46) and the second alternating stack (32, 46) and including: a pair of re-entrant stepped dielectric material portions 65, an insulating support structure 276 including a vertical insulating wall portion 276W located between the pair of re-entrant stepped dielectric material portions 65, and a pair of second-type lateral isolation trench filling structures (74B, 76B) laterally spaced apart along the first horizontal direction hd1 by the insulating support structure 276.

[0311] In one embodiment, the vertical insulating wall portion 276W includes a first longitudinal sidewall and a second longitudinal sidewall, the first longitudinal sidewall extending laterally along the first horizontal direction hd1 and contacting a first re-entrant stepped dielectric material portion 65 of the pair of re-entrant stepped dielectric material portions 65, the second longitudinal sidewall extending laterally along the first horizontal direction hd1 and contacting a second re-entrant stepped dielectric material portion 65 of the pair of re-entrant stepped dielectric material portions 65. In one embodiment, the vertical insulating wall portion 276W includes: a first end wall contacting one of the pair of second-type lateral isolation trench filling structures (74B, 76B); and a second end wall contacting the other of the pair of second-type lateral isolation trench filling structures (74B, 76B).

[0312] In one embodiment, each of the pair of re-entrant stepped dielectric material portions 65 has a corresponding first variable lateral extent along the first horizontal direction hd1, the corresponding first variable lateral extent increasing stepwise with the vertical distance from a horizontal plane including the bottom surfaces of the first alternating stack (32, 46) and the second alternating stack (32, 46). In one embodiment, each of the pair of re-entrant stepped dielectric material portions 65 has a corresponding second variable lateral extent along the second horizontal direction hd2, the corresponding second variable lateral extent increasing gradually without any steps with the vertical distance from the horizontal plane.

[0313] In one embodiment, the insulating support structure 276 includes a fin-type insulating support structure that further includes a vertical stack of insulating fins 276F extending laterally outward from a vertical insulating wall portion 276W. Each vertical stack of insulating fins 276F has a variable lateral extent along a first horizontal direction hd1 that decreases with the vertical distance from a horizontal plane including the bottom surface of the first alternating stack (32, 46) and the second alternating stack (32, 46). In one embodiment, each vertical stack of insulating fins 276F has the same lateral extent along a second horizontal direction hd2, and the corresponding lateral extent does not vary with the vertical distance from the substrate 8.

[0314] In one embodiment, each of the insulating fins 276F includes: a corresponding convex sidewall surface segment that faces a corresponding concave sidewall surface segment of a corresponding one of the first conductive layer 46 and the second conductive layer 46; and a corresponding flat surface segment that is parallel to the first horizontal direction hd1 and contacts a corresponding one of the pair of second-type laterally isolated trench fill structures (74B, 76B).

[0315] The various embodiments described above can provide support structures, such as a vertical stack of dielectric material plates 42', a pair of fin-type insulating support structures 176, and / or an insulating support structure 276, between a pair of second-type laterally isolated trenches (79B or 79C) adjacent to each etch-back stepped dielectric material portion 65. During replacement of the sacrificial material layer 42 with the conductive layer 46, the support structures provide structural support to the insulating layer 32 and the etch-back stepped dielectric material portion 65. Pattern collapse during the formation of the laterally extending cavity 43 can be prevented or reduced.

[0316] Although the foregoing relates to specific embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the word "comprising" or "including" encompasses all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Where embodiments using specific structures and / or configurations are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such replacement is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art.

Claims

1. A three-dimensional memory device, comprising: An insulating layer that is vertically spaced apart from each other and extends continuously laterally between a first first-type laterally isolated trench fill structure and a second first-type laterally isolated trench fill structure, the first first-type laterally isolated trench fill structure and the second first-type laterally isolated trench fill structure extending laterally along a first horizontal direction and being laterally spaced apart from each other along a second horizontal direction; A first conductive layer that is vertically interleaved with the insulating layer and contacts the first first-type laterally isolated trench fill structure; A second conductive layer that is vertically interleaved with the insulating layer and contacts the second first-type laterally isolated trench fill structure; And A composite dielectric isolation structure that is located between the first conductive layer and the second conductive layer and includes a re-entrant stepped dielectric material portion, a vertical stack of dielectric material plates, and a pair of second-type laterally isolated trench fill structures that are laterally spaced apart along the first horizontal direction.

2. The three-dimensional memory device according to claim 1, wherein: The re-entrant stepped dielectric material portion has a first lateral extent along the second horizontal direction; and Each dielectric material plate in the vertical stack of dielectric material plates has a second lateral extent along the second horizontal direction, the second lateral extent being smaller than the first lateral extent.

3. The three-dimensional memory device according to claim 1, wherein the dielectric material plates in the vertical stack of dielectric material plates have a lateral extent along the first horizontal direction that decreases with the vertical distance from a horizontal plane including the bottom surface of the vertical stack.

4. The three-dimensional memory device according to claim 1, wherein each dielectric material plate in the vertical stack of dielectric material plates has a corresponding sidewall that is parallel to the second horizontal direction and contacts a corresponding vertical sidewall segment of the re-entrant stepped dielectric material portion.

5. The three-dimensional memory device according to claim 1, wherein each dielectric material plate in the vertical stack of dielectric material plates includes a concave sidewall segment located at the same level as a corresponding conductive layer selected from the first conductive layer and the second conductive layer and contacts a convex sidewall segment of a structural element selected from the corresponding conductive layer or a backside barrier dielectric layer that contacts the corresponding conductive layer.

6. The three-dimensional memory device according to claim 5, wherein each dielectric material plate in the vertical stack of dielectric material plates further includes: A first flat sidewall segment that contacts a flat sidewall segment of a first etch stop liner that contacts one of the pair of second-type laterally isolated trench fill structures; And A second flat sidewall segment that contacts a flat sidewall segment of the structural element.

7. The three-dimensional memory device according to claim 1, wherein each of the second-type lateral isolation trench filling structures in the second-type lateral isolation trench filling structure includes a corresponding insulating liner, and the insulating liner includes a corresponding portion of insulating liner material and contacts the inner sidewalls of the corresponding etch stop liner, the first insulating layer, the second insulating layer, the first conductive layer, and the second conductive layer.

8. The three-dimensional memory device according to claim 7, wherein each of the first-type lateral isolation trench filling structures in the first-type lateral isolation trench filling structure includes a corresponding additional insulating liner, and the corresponding additional insulating liner includes a corresponding additional portion of the insulating liner material.

9. The three-dimensional memory device according to claim 1, wherein the recessed stepped dielectric material portion has a first variable lateral extent along the first horizontal direction, and the first variable lateral extent increases step by step with the vertical distance from the horizontal plane including the bottommost surface of the vertical stack.

10. The three-dimensional memory device according to claim 9, wherein the recessed stepped dielectric material portion has a second variable lateral extent along the second horizontal direction, and the second variable lateral extent gradually increases along the second horizontal direction without any steps.

11. The three-dimensional memory device according to claim 1, wherein the dielectric material plates in the vertical stack of dielectric material plates include: a first sidewall segment that extends laterally along the first horizontal direction and contacts one of the second-type lateral isolation trench filling structures in the second-type lateral isolation trench filling structure; a second sidewall segment that extends laterally along the second horizontal direction and contacts the one second-type lateral isolation trench filling structure in the second-type lateral isolation trench filling structure; a first concave surface segment that is located at the level of one of the first conductive layers in the first conductive layer and contacts the convex sidewall of a first structural element, the first structural element being selected from one of the first conductive layers in the first conductive layer and a first barrier dielectric layer contacting the one first conductive layer in the first conductive layer; and a third sidewall segment that extends laterally along the first horizontal direction and contacts the flat sidewall of the first structural element.

12. The three-dimensional memory device according to claim 1, wherein the plurality of dielectric material plates in the vertical stack of dielectric material plates have a uniform width along the second horizontal direction, and the uniform width is less than the minimum lateral dimension of the recessed stepped dielectric material portion along the second horizontal direction.

13. The three-dimensional memory device according to claim 1, further comprising a first memory opening that extends through a first alternating stack of the first conductive layer vertically interleaved with the insulating layer; a second memory opening that extends through a second alternating stack of the second conductive layer vertically interleaved with the insulating layer; and A memory opening filling structure, the memory opening filling structure being located in the first memory opening and the second memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a memory film and a vertical semiconductor channel.

14. A method, comprising: Forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; Forming a lateral isolation trench through the alternating stack, wherein the lateral isolation trench includes a first type of lateral isolation trench that continuously extends laterally along a first horizontal direction through a contact region and a plurality of pairs of second type of lateral isolation trenches that are staggered with the first type of lateral isolation trench along a second horizontal direction, wherein each pair of the second type of lateral isolation trenches is laterally spaced apart from each other by a certain gap along the first horizontal direction, and the gap is located within the contact region; Forming an etch stop liner at an end portion of the second type of lateral isolation trench that is located within the contact region, such that the etch stop liner does not exist on a plurality of portions of the second type of lateral isolation trench that are away from the contact region and the etch stop liner does not exist within the first type of lateral isolation trench; And Replacing a plurality of portions of the sacrificial material layer with a conductive layer, wherein each vertical stack of the conductive layer is formed between the nearest first type of lateral isolation trench in the first type of lateral isolation trench and the nearest pair of the second type of lateral isolation trenches in the plurality of pairs of the second type of lateral isolation trenches, and does not laterally extend along the second horizontal direction farther than the nearest first type of lateral isolation trench and the nearest pair of the second type of lateral isolation trenches.

15. The method according to claim 14, further comprising: Forming a stepped cavity through the alternating stack; And Forming a re-entrant stepped dielectric material portion in the stepped cavity.

16. The method according to claim 15, wherein: The first type of lateral isolation trench is laterally staggered with the re-entrant stepped dielectric material portion along the second horizontal direction; and Each pair of the second type of lateral isolation trenches cuts through a corresponding one of the re-entrant stepped dielectric material portions in the re-entrant stepped dielectric material portion.

17. The method according to claim 16, further comprising performing an isotropic etching process after forming the etch stop liner, the isotropic etching process introducing an isotropic etchant for etching the material of the sacrificial material layer into the first type of lateral isolation trench and into the plurality of pairs of the second type of lateral isolation trenches to form a laterally extending cavity in a volume from which the plurality of portions of the sacrificial material layer are removed by the isotropic etching process.

18. The method according to claim 17, wherein after the isotropic etching process, a remaining portion of the sacrificial material layer exists in each gap between the plurality of pairs of the second type of lateral isolation trenches.

19. The method according to claim 18, wherein: The isotropic etching process has an etching distance that is greater than half of the lateral distance between a first-type lateral isolation trench among the first-type lateral isolation trenches and a pair of second-type lateral isolation trenches closest to the first-type lateral isolation trench among the multiple pairs of second-type lateral isolation trenches; the etching distance is less than the lateral dimension of an etching stop layer among the etching stop layers along the first horizontal direction; and The remaining portion of the sacrificial material layer forms a vertical stack of dielectric material plates.

20. The method according to claim 14, further comprising: forming memory openings through the alternating stack; and forming a memory opening fill structure in the memory openings, wherein each memory opening fill structure in the memory opening fill structure includes a memory film and a vertical semiconductor channel.

21. A three-dimensional memory device, comprising: Insulating layers that are vertically spaced apart from each other and extend continuously laterally between a first first-type lateral isolation trench fill structure and a second first-type lateral isolation trench fill structure, the first first-type lateral isolation trench fill structure and the second first-type lateral isolation trench fill structure extending laterally along a first horizontal direction and being laterally spaced apart from each other along a second horizontal direction; A first conductive layer that is vertically interleaved with the insulating layer and contacts the first first-type lateral isolation trench fill structure; A second conductive layer that is vertically interleaved with the insulating layer and contacts the second first-type lateral isolation trench fill structure; and A composite dielectric isolation structure located between the first conductive layer and the second conductive layer, wherein the composite dielectric isolation structure includes a re-entrant stepped dielectric material portion and a pair of fin-type insulating support structures, each fin-type insulating support structure including a corresponding vertically extending insulating core and a corresponding vertical stack of insulating fins extending laterally outward from the corresponding vertically extending insulating core.

22. The three-dimensional memory device according to claim 21, wherein the composite dielectric isolation structure further includes a pair of second-type lateral isolation trench fill structures that are laterally spaced apart along the first horizontal direction.

23. The three-dimensional memory device according to claim 22, wherein: Each second-type lateral isolation trench fill structure among the pair of second-type lateral isolation trench fill structures is in direct contact with a corresponding one of the pair of fin-type insulating support structures; The re-entrant stepped dielectric material portion is laterally spaced apart from the pair of second-type lateral isolation trench fill structures by the pair of fin-type insulating support structures; and The vertically extending insulating core extends vertically through each layer within the first alternating stack and the second alternating stack.

24. The three-dimensional memory device according to claim 21, further comprising a memory opening fill structure that includes a memory film and a vertical semiconductor channel.

25. The three-dimensional memory device according to claim 21, wherein: The etched-back stepped dielectric material portion has a first lateral extent along the second horizontal direction; and The composite dielectric isolation structure further includes a vertical stack of dielectric material plates, each dielectric material plate having a second lateral extent along the second horizontal direction, the second lateral extent being less than the first lateral extent.

26. The three-dimensional memory device according to claim 25, wherein the dielectric material plates in the vertical stack of dielectric material plates have a lateral extent along the first horizontal direction, the lateral extent decreasing with the vertical distance from the horizontal plane including the bottom surface of the insulating layer.

27. The three-dimensional memory device according to claim 25, wherein:[[]]END]] Each dielectric material plate in the vertical stack of dielectric material plates has a respective sidewall that is parallel to the second horizontal direction and contacts a respective vertical sidewall segment of the etched-back stepped dielectric material portion; Each interface between the pair of fin-type insulating support structures and the vertical stack of dielectric material plates includes a respective convex sidewall segment of the insulating fin that contacts a respective concave sidewall segment of the vertical stack of dielectric material plates; and Each interface between the pair of fin-type insulating support structures and the etched-back stepped dielectric material portion includes a respective flat sidewall segment of the insulating fin that contacts a respective flat sidewall segment of the etched-back stepped dielectric material portion.

28. A three-dimensional memory device, comprising: A first alternating stack of a first insulating layer and a first conductive layer and a second alternating stack of a second insulating layer and a second conductive layer, wherein the first alternating stack and the second alternating stack are located between a pair of first-type lateral isolation trench fill structures that extend laterally along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction; and A composite dielectric isolation structure that is located between the first alternating stack and the second alternating stack and includes: a pair of etched-back stepped dielectric material portions, an insulating support structure including a vertical insulating wall portion located between the pair of etched-back stepped dielectric material portions, and a pair of second-type lateral isolation trench fill structures that are laterally spaced apart along the first horizontal direction by the insulating support structure.

29. The three-dimensional memory device according to claim 28, wherein the vertical insulating wall portion includes: A first longitudinal sidewall that extends laterally along the first horizontal direction and contacts a first etched-back stepped dielectric material portion of the pair of etched-back stepped dielectric material portions; A second longitudinal sidewall that extends laterally along the first horizontal direction and contacts a second etched-back stepped dielectric material portion of the pair of etched-back stepped dielectric material portions; A first end wall that contacts one of the pair of second-type lateral isolation trench fill structures; and A second end wall that contacts the other of the pair of second-type lateral isolation trench fill structures.

30. The three-dimensional memory device according to claim 28, wherein each of the pair of re-entrant stepped dielectric material portions includes: a corresponding first variable lateral extent along the first horizontal direction, the corresponding first variable lateral extent increasing stepwise with a vertical distance from a horizontal plane including a bottom surface of the first alternating stack and the second alternating stack; and a corresponding second variable lateral extent along the second horizontal direction, the corresponding second variable lateral extent increasing gradually without any steps with the vertical distance from the horizontal plane.

31. The three-dimensional memory device according to claim 28, wherein: the insulating support structure includes a fin-type insulating support structure, and the fin-type insulating support structure further includes a vertical stack of insulating fins extending laterally outward from the vertical insulating wall portion; and each of the insulating fins includes: a corresponding convex sidewall surface segment facing a corresponding concave sidewall surface segment of a corresponding one of the first conductive layer and the second conductive layer; and a corresponding flat surface segment parallel to the first horizontal direction and contacting a corresponding one of the pair of second-type lateral isolation trench filling structures.

32. The three-dimensional memory device according to claim 31, wherein each of the insulating fins in the vertical stack of insulating fins includes: a variable lateral extent along the first horizontal direction, the variable lateral extent decreasing with a vertical distance from a horizontal plane including a bottom surface of the first alternating stack and the second alternating stack; and the same lateral extent along the second horizontal direction, the same lateral extent not varying with the vertical distance from the horizontal plane.

33. The three-dimensional memory device according to claim 28, further comprising a memory opening filling structure, the memory opening filling structure including a memory film and a vertical semiconductor channel.

34. A method, comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a cavity through the alternating stack; forming fin grooves around the cavity by isotropically laterally recessing the sacrificial material layer; forming a fin-type insulating support structure in a volume of the fin grooves and the cavity; forming lateral isolation trenches through the alternating stack, wherein the lateral isolation trenches include first-type lateral isolation trenches extending laterally through a contact region along a first horizontal direction and multiple pairs of second-type lateral isolation trenches staggered with the first-type lateral isolation trenches along a second horizontal direction, and wherein each pair of second-type lateral isolation trenches is laterally spaced apart from each other along the first horizontal direction by at least one of the fin-type insulating support structures in the fin-type insulating support structure; forming a laterally extending cavity by performing an isotropic etching process, the isotropic etching process isotropically recessing the sacrificial material layer by providing an isotropic etchant into the first-type lateral isolation trenches and the multiple pairs of second-type lateral isolation trenches; and Form a vertical stack of conductive layers in the laterally extending cavity.

35. The method according to claim 34, wherein: The cavity includes an access cavity formed before forming the laterally isolating trenches; and Each fin-type insulating support structure in the fin-type insulating support structures includes a corresponding vertical stack of a vertically extending insulating core and insulating fins extending laterally outward from the corresponding vertically extending insulating core.

36. The method according to claim 35, further comprising: Forming a stepped cavity through the alternating stack; And Forming a recessed stepped dielectric material portion in the stepped cavity, wherein: The first type of laterally isolating trenches are laterally staggered with the recessed stepped dielectric material portion along the second horizontal direction; and Each pair of the second type of laterally isolating trenches are laterally spaced apart from a corresponding one of the recessed stepped dielectric material portions in the recessed stepped dielectric material portion along the first horizontal direction.

37. The method according to claim 36, wherein: The access cavity includes multiple pairs of access cavities; Each pair of access cavities are laterally spaced apart from a corresponding one of the recessed stepped dielectric material portions in the recessed stepped dielectric material portion along the first horizontal direction; The remaining portion of the sacrificial material layer after the isotropic etching process includes a vertical stack of dielectric material plates; The isotropic etching process has an etching distance that is greater than half of the lateral distance between one of the first type of laterally isolating trenches and a pair of the second type of laterally isolating trenches that is closest to the one of the first type of laterally isolating trenches among the multiple pairs of the second type of laterally isolating trenches; and The etching distance is less than the lateral dimension of one of the fin-type insulating support structures along the first horizontal direction.

38. The method according to claim 34, further comprising filling the entirety of each of the first laterally isolating trenches and a first portion of the second type of laterally isolating trenches that is outside the contact region with a sacrificial trench filling material, wherein the cavity includes isolation cavities in multiple portions of the second type of laterally isolating trenches that are not filled with the sacrificial trench filling material.

39. The method according to claim 38, further comprising: Forming a stepped cavity through the alternating stack; Forming a recessed stepped dielectric material portion in the stepped cavity; And Removing the sacrificial trench filling material after forming the fin-type insulating support structures; Wherein: The first type of laterally isolating trenches are laterally staggered with the recessed stepped dielectric material portion along the second horizontal direction; Each of the second type of laterally isolating trenches cuts through a corresponding one of the recessed stepped dielectric material portions in the recessed stepped dielectric material portion and divides the corresponding one of the recessed stepped dielectric material portions in the recessed stepped dielectric material portion into a corresponding pair of recessed stepped dielectric material portions; Each isolation cavity in the isolation cavity has a lateral extent along the first horizontal direction that is larger than any of the re-entrant stepped dielectric material portions in the re-entrant stepped dielectric material portion; Before forming the lateral isolation trench, each of the re-entrant stepped dielectric material portions in the re-entrant stepped dielectric material portion has a first lateral extent along the second horizontal direction; and The first lateral extent is greater than the lateral extent of each fin-type insulating support structure in the fin-type insulating support structure along the second horizontal direction.

40. The method according to claim 34, further comprising: Forming a memory opening through the alternately stacked memory openings; And Forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a memory film and a vertical semiconductor channel.

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