Three-dimensional memory device with integrated contact and support structure and method of manufacturing same

Abstract

The invention discloses a memory device comprising: a first layer alternating stack of first insulating layers and conductive layers, the first layer alternating stack over a substrate; a second layer alternating stack of second insulating layers and second conductive layers, the second layer alternating stack overlying the first layer alternating stack; a memory stack structure extending vertically through the first layer alternating stack and the second layer alternating stack; and a first support and contact assembly extending vertically through the first layer alternating stack and the second layer alternating stack. The first support and contact assembly includes: a first contact via structure contacting an annular top surface of the conductive layer; a first dielectric pillar structure, the first dielectric pillar structure underlying the reference level conductive layer; and a first layer of dielectric spacer, the first layer of dielectric spacer laterally surrounding the first contact via structure.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 356,825, filed on July 21, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE WITH INTEGRATED CONTACT AND SUPPORT STRUCTURE AND METHOD OF MAKING THE SAME", and for all purposes, the entire content of this application is hereby incorporated by reference, which application claims the priority of U.S. Provisional Application No. 63 / 484,619, filed on February 13, 2023. Technical Field Background Art

[0003] Three - dimensional vertical NAND strings with one bit per cell are disclosed in the article by T. Endoh et al., entitled "Novel Ultra - High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", IEDM Proc. (2001) 33 - 36. Summary of the Invention

[0004] According to one aspect of the present disclosure, a memory device is provided, the memory device including: a first layer of a first insulating layer and a first conductive layer alternately stacked, the first layer alternately stacked being located above a substrate; a second layer of a second insulating layer and a second conductive layer alternately stacked, the second layer alternately stacked being overlaid on the first layer alternately stacked; memory openings extending vertically through the first layer alternately stacked and the second layer alternately stacked; memory opening filling structures located in the memory openings, wherein each of the memory opening filling structures includes a corresponding vertical stack of memory elements; and a first support and contact assembly extending vertically through the first layer alternately stacked and the second layer alternately stacked, and including: a first contact via structure contacting a circular top surface of a first reference conductive layer and having a top surface above a horizontal plane including a topmost surface of the second layer alternately stacked, the first reference conductive layer being one of the first conductive layers of the first layer alternately stacked; a first dielectric pillar structure having at least one first laterally protruding fin portion protruding outward at each level of a first subset of the first conductive layers underlying the first reference conductive layer; and a first layer of dielectric spacers laterally surrounding the first contact via structure, not in direct contact with the first dielectric pillar structure, and extending vertically through each of the first conductive layers within a second subset of the first conductive layers overlying the first reference conductive layer.

[0005] According to another aspect of the present disclosure, a memory device includes: a first layer of a first insulating layer and a first conductive layer alternately stacked, the first layer being alternately stacked above a substrate; a second layer of a second insulating layer and a second conductive layer alternately stacked, the second layer being alternately stacked over the first layer; memory openings vertically extending through the first layer and the second layer; memory opening filling structures located in the memory openings, each of the memory opening filling structures including a respective vertical semiconductor channel and a vertical stack of memory elements; a first support and contact assembly vertically extending through the first layer and the second layer and including: a first contact via structure contacting a ring-shaped top surface of a first reference conductive layer, the first reference conductive layer being one of the first conductive layers of the first layer; and a first dielectric pillar structure underlying the first contact via structure, wherein there is no air gap in the first dielectric pillar structure; and a second support and contact assembly vertically extending through the first layer and the second layer and including: a second contact via structure contacting a ring-shaped top surface of a second reference conductive layer, the second reference conductive layer being one of the second conductive layers of the second layer; and a second dielectric pillar structure underlying the second contact via structure, wherein an air gap is included in the second dielectric pillar structure.

[0006] According to another aspect of the present disclosure, a method of forming a memory device includes: forming a first layer of a first insulating layer and a first sacrificial material layer alternately stacked above a substrate; forming first layer via cavities in the first layer; vertically extending a central region of the first layer via cavities into an upper portion of the substrate without vertically extending a peripheral region of the first layer via cavities; partially filling the first layer via cavities with a first dielectric layer stack and a first sacrificial via filling material; forming a second layer of a second insulating layer and a second sacrificial material layer alternately stacked above the first layer; forming second layer via cavities through each of the second sacrificial material layers of the second layer; partially filling the second layer via cavities with a second dielectric layer stack and a second sacrificial via filling material; replacing the first sacrificial material layers and the second sacrificial material layers with a first conductive layer and a second conductive layer, respectively; forming contact via cavities by removing the second sacrificial via filling material portion and the first sacrificial via filling material portion; physically exposing a ring-shaped top surface section of a reference level conductive layer, the reference level conductive layer being one of the conductive layers, by removing a ring-shaped portion of the first dielectric layer stack; and forming a first contact via structure in the contact via cavities. Description of the Drawings

[0007] Figure 1A is a vertical cross - sectional view of an exemplary structure after forming a combination of a substrate dielectric liner and a sacrificial substrate pad structure according to an embodiment of the present disclosure.

[0008] Figure 1B is Figure 1A a top - view of an exemplary structure of. The hinged vertical plane A - A’ is Figure 1A the plane of the vertical cross - sectional view of.

[0009] Figure 2A is a vertical cross - sectional view of an exemplary structure after forming an alternating stack of a first insulating layer and a first layer of a sacrificial material layer, a first memory opening, and a first support opening according to an embodiment of the present disclosure.

[0010] Figure 2B is Figure 2A a partial perspective top - view of an exemplary structure of. The hinged vertical plane A - A’ is Figure 2A the plane of the vertical cross - sectional view of.

[0011] Figure 3 is a vertical cross - sectional view of an exemplary structure after forming a first sacrificial opening filling structure and an interlayer insulating layer according to an embodiment of the present disclosure.

[0012] Figure 4A is a vertical cross - sectional view of an exemplary structure after forming a first patterned hard mask layer and a first layer of contact via cavities according to an embodiment of the present disclosure.

[0013] Figure 4B is Figure 4A a partial perspective top - view of an exemplary structure of. The hinged vertical plane A - A’ is Figure 4A the plane of the vertical cross - sectional view of.

[0014] Figure 5 is a vertical cross - sectional view of an exemplary structure after forming a first sacrificial spacer material layer according to an embodiment of the present disclosure.

[0015] Figure 6 is a vertical cross - sectional view of an exemplary structure after forming a first patterned photoresist layer and performing a first anisotropic etching process that vertically extends the central portion of the first layer of contact via cavities according to an embodiment of the present disclosure.

[0016] Figure 7 is a vertical cross - sectional view of an exemplary structure after removing the remaining portions of the first sacrificial spacer material layer and the first patterned hard mask layer and removing the sacrificial substrate pad structure according to an embodiment of the present disclosure.

[0017] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a first continuous dielectric liner in accordance with an embodiment of the present disclosure.

[0018] Figure 9 is a vertical cross-sectional view of an exemplary structure after forming a first continuous dielectric material layer in accordance with an embodiment of the present disclosure.

[0019] Figure 10 is a vertical cross-sectional view of an exemplary structure after forming a first dielectric fill material layer in accordance with an embodiment of the present disclosure.

[0020] Figure 11 is a vertical cross-sectional view of an exemplary structure after depositing and vertically recessing a first sacrificial via fill material in accordance with an embodiment of the present disclosure.

[0021] Figure 12 is a vertical cross-sectional view of an exemplary structure after forming a first via cavity fill structure in a process in accordance with an embodiment of the present disclosure.

[0022] Figure 13 is a vertical cross-sectional view of an exemplary structure after forming an alternating stack of a second insulating layer and a second sacrificial material layer in accordance with an embodiment of the present disclosure.

[0023] Figure 14 is a vertical cross-sectional view of an exemplary structure after forming a second layer of memory openings and a second layer of support openings in accordance with an embodiment of the present disclosure.

[0024] Figure 15 is a vertical cross-sectional view of an exemplary structure after forming interlayer memory openings and interlayer support openings in accordance with an embodiment of the present disclosure.

[0025] Figure 16A is a vertical cross-sectional view of an exemplary structure after forming a memory opening fill structure and a support pillar structure in accordance with an embodiment of the present disclosure.

[0026] Figure 16B is Figure 16A a partial perspective top view of an exemplary structure. The hinged vertical plane A-A’ is Figure 16A the plane of the vertical cross-sectional view of

[0027] Figure 17A is a vertical cross-sectional view of an exemplary structure after forming a first contact level dielectric layer, a second patterned hard mask layer, and a second layer of contact via cavities in accordance with an embodiment of the present disclosure.

[0028] Figure 17B is Figure 17A a partial perspective top view of an exemplary structure. The hinged vertical plane A-A’ isFigure 17A The plane of the vertical cross-section.

[0029] Figure 18 Is a vertical cross-section of an exemplary structure after forming a second sacrificial spacer material layer according to an embodiment of the present disclosure.

[0030] Figure 19 Is a vertical cross-section of an exemplary structure after forming a second patterned photoresist layer and after performing a second anisotropic etching process that vertically extends the central portion of the first subset of via cavities in the second layer according to an embodiment of the present disclosure.

[0031] Figure 20 Is a vertical cross-section of an exemplary structure after removing the remaining portions of the second sacrificial spacer material layer and the second patterned hard mask layer, removing the first subset of the first sacrificial via fill material portions, and forming a second continuous dielectric liner according to an embodiment of the present disclosure.

[0032] Figure 21 Is a vertical cross-section of an exemplary structure after forming a second continuous dielectric material layer according to an embodiment of the present disclosure.

[0033] Figure 22 Is a vertical cross-section of an exemplary structure after forming a second dielectric fill material layer according to an embodiment of the present disclosure.

[0034] Figure 23 Is a vertical cross-section of an exemplary structure after forming a third patterned photoresist layer and after performing a third anisotropic etching process that vertically extends the central portion of the second subset of via cavities in the third layer according to an embodiment of the present disclosure.

[0035] Figure 24 Is a vertical cross-section of an exemplary structure after depositing and vertically recessing a second sacrificial via fill material according to an embodiment of the present disclosure.

[0036] Figure 25 Is a vertical cross-section of an exemplary structure after forming a second via cavity fill structure in a forming process according to an embodiment of the present disclosure.

[0037] Figure 26A Is a vertical cross-section of an exemplary structure after forming a second contact level dielectric layer and a backside trench according to an embodiment of the present disclosure.

[0038] Figure 26B Is Figure 26A A partial perspective top view of an exemplary structure. The articulated vertical plane A-A’ is Figure 26A The plane of the vertical cross-section.

[0039] Figure 27 is a vertical cross-sectional view of an exemplary structure after replacing a sacrificial material layer with a conductive layer according to an embodiment of the present disclosure.

[0040] Figure 28 is a vertical cross-sectional view of an exemplary structure after forming a backside trench fill structure according to an embodiment of the present disclosure.

[0041] Figure 29A is a vertical cross-sectional view of an exemplary structure after forming a third contact level dielectric layer and a connection via cavity according to an embodiment of the present disclosure.

[0042] Figure 29B is Figure 29A a partial perspective top view of an exemplary structure. The hinged vertical plane A-A’ is Figure 29A the plane of the vertical cross-sectional view of

[0043] Figure 30 is a vertical cross-sectional view of an exemplary structure after removing a second subset of a second sacrificial via fill material portion and a first sacrificial via fill material portion according to an embodiment of the present disclosure.

[0044] Figure 31 is a vertical cross-sectional view of an exemplary structure after performing a first anisotropic etching process to remove horizontal extensions of a second dielectric fill material layer and a first dielectric fill material layer according to an embodiment of the present disclosure.

[0045] Figure 32 is a vertical cross-sectional view of an exemplary structure after performing an isotropic etching process to isotropically recess remaining portions of a second dielectric fill material layer and a first dielectric fill material layer according to an embodiment of the present disclosure.

[0046] Figure 33 is a vertical cross-sectional view of an exemplary structure after performing a second anisotropic etching process to remove horizontal extensions of a second dielectric material layer and a first dielectric material layer according to an embodiment of the present disclosure.

[0047] Figure 34 is a vertical cross-sectional view of an exemplary structure after performing an etching process to remove horizontal extensions of a second dielectric liner and a first dielectric liner according to an embodiment of the present disclosure.

[0048] Figure 35A is a vertical cross-sectional view of an exemplary structure after forming a contact via structure on a physically exposed annular surface of a conductive layer according to an embodiment of the present disclosure.

[0049] Figure 35B is Figure 35A a partial perspective top view of an exemplary structure. The hinged vertical plane A-A’ isFigure 35A The plane of a vertical cross-section.

[0050] Figure 36 、 Figure 37 and Figure 38 are vertical cross-sections of exemplary structures according to alternative embodiments of the present disclosure. Detailed Description

[0051] As discussed above, the present disclosure relates to three-dimensional memory devices including integrated contact and support structures and methods of manufacturing the same, aspects of which are described below.

[0052] The figures are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is illustrated, unless explicitly described or otherwise clearly indicated as not being repeated. Ordinal numbers such as "first", "second", and "third" are used only to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0053] Like reference numerals denote like or similar elements. Unless otherwise specified, elements with the same reference numeral are assumed to have the same constitution and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, an element "on" a second element may be outside or inside the surface of the second element. As used herein, an element is "directly on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical path between the element and the second element consisting of at least one conductive material. As used herein, a "prototype" structure or a "structure in process" is a transient structure that is subsequently modified in terms of the shape or constitution of at least one of its components.

[0054] As used herein, a "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a smaller extent than the underlying or overlying structure. Additionally, a layer can be a region of a continuous structure that is uniform or non-uniform and has a thickness less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, above it, and / or below it.

[0055] Generally speaking, a semiconductor die or semiconductor package can include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (usually one or two). Although there are some limitations, the same concurrent operations can be performed on each plane. Each plane contains a plurality of blocks, which are the smallest units that can be erased by a single erase operation. Each block contains a plurality of pages, which are the smallest units that can be programmed, i.e., the smallest units on which a read operation can be performed.

[0056] Reference Figure 1A and Figure 1B , illustrates an exemplary structure according to an embodiment of the present disclosure, the exemplary structure including a substrate 9 that includes a semiconductor material layer at least in its upper portion. The semiconductor material layer can include a single-crystalline semiconductor material layer or a polycrystalline semiconductor material layer. Below the semiconductor material layer, the substrate 9 can include or not include additional layers (such as a dielectric material layer embedding a metal interconnect structure) and / or semiconductor devices (such as peripheral circuits for controlling the operation of a three-dimensional memory array to be formed subsequently). In one embodiment, the substrate 9 can include a commercially available semiconductor wafer, such as a single-crystalline silicon wafer. The semiconductor material layer can include the upper portion of the silicon wafer, doped wells in the silicon wafer, an epitaxial silicon layer on the silicon wafer, etc.

[0057] An array of substrate recesses 1 can be formed in an upper portion of the substrate in the contact region 300. The contact region 300 can include a first contact region 301 and a second contact region 302, in the first contact region, a first contact via structure for providing an electrical connection to the first conductive layer is subsequently formed, and in the second contact region, a second contact via structure for providing an electrical connection to the second conductive layer is subsequently formed. The memory array region 100 can be arranged adjacent to the contact region. In one embodiment, the substrate recesses 1 can be arranged as rows extending laterally along a first horizontal direction (e.g., the word line direction) hd1, which is perpendicular to the boundary between the memory array region 100 and the contact region 300. The rows of substrate recesses 1 can be laterally spaced apart from each other along a second horizontal direction (e.g., the bit line direction) hd2, which can be perpendicular to the first horizontal direction hd1 and parallel to the boundary between the memory array region 100 and the contact region 300.

[0058] The depth of the substrate recesses 1 can be in the range of 50 nm to 500 nm, and the lateral dimension (such as the diameter) of the recesses can be in the range of 200 nm to 2000 nm, but smaller and larger dimensions can also be used for the depth and the lateral dimension. A substrate dielectric liner layer including a dielectric material (such as silicon oxide) can be deposited in the substrate recesses 1, and a sacrificial fill material (which is also referred to as a sacrificial substrate fill material or a substrate pad fill material) can be deposited in the remaining volume of the substrate recesses. The sacrificial fill material can include a carbon material (e.g., amorphous carbon or diamond-like carbon) or a metal (e.g., tungsten). The excess portions of the sacrificial fill material and the substrate dielectric liner layer can be removed from above a horizontal plane including the top surface of the substrate 9 by performing a planarization process such as a chemical mechanical planarization process. Each remaining portion of the sacrificial fill material constitutes a sacrificial substrate pad 5. Each remaining portion of the substrate dielectric liner layer constitutes a substrate dielectric pad 3. Each adjacent combination of the substrate dielectric pad 3 and the sacrificial substrate pad 5 fills a corresponding substrate recess 1.

[0059] Reference Figure 2A and Figure 2B, a first insulating layer 132 and a first layer of a first sacrificial material layer 142 can be alternately stacked above the substrate 9. The first insulating layer 132 includes an insulating material such as undoped silicate glass or doped silicate glass, and the first sacrificial material layer 142 includes a sacrificial material such as silicon nitride or silicon germanium alloy. The first layer of the alternating stack (132, 142) can include multiple repetitions of a unit layer stack that includes the first insulating layer 132 and the first sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first layer of the alternating stack (132, 142) can be, for example, in the range of 8 to 1024 (such as 32 to 256), but fewer and more repetitions can also be employed. Each first insulating layer in the first insulating layer 132 can have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses can also be used. Each first sacrificial material layer in the first sacrificial material layer 142 can have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses can also be used.

[0060] An etch mask layer (not shown) can be formed above the first layer of the alternating stack (132, 142), and the etch mask layer can be lithographically patterned to form various openings therein. An anisotropic etching process can be performed to transfer the pattern of the openings in the etch mask layer through the first layer of the alternating stack (132, 142). First layer openings (149, 119) can be formed through the first layer of the alternating stack (132, 142). The first layer openings (149, 119) can include a first layer memory opening 149 that vertically extends through each layer within the first layer of the alternating stack (132, 142) in the memory array region 100; and can also include a first layer support opening 119 that is formed through the first layer of the alternating stack (132, 142) in the contact region 300 and is subsequently used to form a support pillar structure in the contact region. In one embodiment, the first layer memory openings 149 can be formed in rows that horizontally extend along a first horizontal direction hd1. The rows of the first layer memory openings 149 can be horizontally spaced apart along a second horizontal direction hd1 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first layer memory openings 149 can be formed as a periodic two-dimensional array (such as a hexagonal periodic two-dimensional array). Subsequently, the etch mask layer can be removed.

[0061] Reference Figure 3, optionally, a pedestal channel portion 11 may be formed at the bottom of each opening in the first layer openings (149, 119). The pedestal channel portion 11 may include a semiconductor material that can be deposited by a selective semiconductor material deposition process that grows the semiconductor material from the physically exposed surface of the substrate 9. A selective semiconductor deposition process (such as, selective epitaxy process) may be employed to form the pedestal channel portion 11. The pedestal channel portion 11 may include single-crystalline silicon that is epitaxially aligned with the single-crystalline semiconductor material in the substrate 9, or may include polycrystalline semiconductor material (e.g., polysilicon). In one embodiment, the top surface of the pedestal channel portion 11 may be formed below the interface between the bottommost first insulating layer 132 and the bottommost first sacrificial material layer 142.

[0062] A first layer of sacrificial fill material may be deposited in the remaining unfilled volume of the first layer openings (149, 119). The excess portion of the first layer of sacrificial fill material may be removed by performing a planarization process above the horizontal plane including the top surface of the topmost first insulating layer 132. Each remaining portion of the first layer of sacrificial fill material constitutes a first layer of sacrificial opening fill structure (148, 118). The first layer of sacrificial opening fill structure (148, 118) includes a first layer of sacrificial memory opening fill structure 148 formed in the first layer memory opening 149, and a first layer of sacrificial support opening fill structure 118 formed in the first layer support opening 119. The first layer of sacrificial fill material may include amorphous carbon, diamond-like carbon, semiconductor material, organosilicate glass, polymer material, or any other material that can be subsequently selectively removed with respect to the materials of the first layer of alternating stack (132, 142) and the pedestal channel portion 11.

[0063] An insulating layer may be optionally formed above the first layer of alternating stack (132, 142). This insulating layer (if formed) is referred to herein as the interlayer insulating layer 180. The interlayer insulating layer 180 may have the same material composition and a substantially same thickness range as the first insulating layer 132.

[0064] Reference Figure 4A and Figure 4B, a first patterned hard mask layer 171 may be formed over the interlayer insulating layer 180 by depositing and patterning a hard mask material. The first patterned hard mask layer 171 includes a material that can act as an etch mask material during subsequent anisotropic etching processes. In one embodiment, the first patterned hard mask layer 171 may include a semiconductor material (such as amorphous silicon) and may have a thickness in the range of 50 nm to 500 nm, although smaller and larger thicknesses may be employed. The hard mask material may be patterned by applying a photoresist material over the hard mask material and lithographically patterning the photoresist material, and transferring the pattern in the photoresist material through the hard mask material. In one embodiment, the pattern of the openings in the first patterned hard mask layer 171 may be the same as the pattern of the substrate recesses 1 (in which the substrate dielectric liner 3 and the sacrificial substrate pad 5 are present), or may be modified according to the pattern of the substrate recesses 1 such that each opening in the first patterned hard mask layer 171 has at least partial overlap with the pattern of the corresponding substrate recess 1. In some embodiments, each opening in the first patterned hard mask layer 171 may have a perimeter that, in a top view, is located over or outside the perimeter of the corresponding underlying substrate recess 1.

[0065] The first via cavities 181 are formed through respective subsets of the layers within the first layer alternating stack (132, 142). Each of the first via cavities 181 in the first via cavities 181 may extend vertically through the interlayer dielectric layer 170 and through respective subsets of the first sacrificial material layer 142 and the first insulating layer 132 such that the top surface of the selected first insulating layer 132 is physically exposed at the bottom of each of the first via cavities 181. In one embodiment, the first via cavities 181 may have different depths from each other, and each first insulating layer 132 may be physically exposed to a corresponding overlying first via cavity 181.

[0066] The first via cavities 181 having different depths may be formed using multiple masked anisotropic etching processes. In an illustrative example, the openings in the first patterned hard mask layer 171 may have the pattern of all of the first via cavities 181 that will subsequently be formed. An anisotropic etching process may be performed to transfer the pattern of the openings in the first patterned hard mask layer 171 through the interlayer insulating layer 180.

[0067] Subsequently, multiple iterations of a combination of a corresponding masking process and a corresponding anisotropic etching process can be performed to etch through corresponding subsets of the first sacrificial material layer 142 and corresponding subsets of the first insulating layer 132. Each masking process forms a corresponding patterned photoresist layer (not shown) that masks corresponding subsets of the openings in the first patterned hard mask layer 171 and does not mask corresponding complementary subsets of these openings. Each anisotropic etching process etches a corresponding number of the first sacrificial material layer 142 and a corresponding number of insulating layers 32 under each opening in the first patterned hard mask layer 171 that is not masked by the corresponding patterned photoresist layer. In one embodiment, the number of etched first sacrificial material layer 142 and etched first insulating layer 132 under the unmasked openings in the first patterned hard mask layer 171 can be a non-negative integer power of 2, i.e., 1, 2, 4, 8, 16, 32, 64, etc. By using combinations of various mask patterns for the patterned photoresist layer, the total depth of the first via cavity 181 can be varied to enable physical exposure of the top surface of the first insulating layer 132 at each level. Subsequently, the first patterned hard mask layer 171 can be removed.

[0068] The first via cavity 181 can include a first type of the first via cavity 181A formed in the first contact region 301 and a second type of the first via cavity 181B formed in the second contact region 302. In one embodiment, the first type of the first via cavity 181A has various depths such that each of the first insulating layer 132 and the interlayer insulating layer 180 has a top surface section physically exposed to the corresponding overlying first type of the first via cavity 181A. In one embodiment, each of the second type of the first via cavity 181B can extend through each layer within the first alternating stack (132, 142) except the bottommost first insulating layer 132. In this case, each of the second type of the first via cavity 181B can vertically extend through each first sacrificial material layer 142 in the first alternating stack (132, 142). The lateral dimension (such as diameter) of the first via cavity 181 can be in the range of 200 nm to 3,000 nm, but smaller and larger lateral dimensions can also be employed.

[0069] Reference Figure 5, a first sacrificial spacer material layer 173L may be deposited above the first patterned hard mask layer 171 and in the peripheral portion of the first layer via cavity 181. The first sacrificial spacer material layer 173L includes a material that can subsequently be used as an etch mask material for the materials of the first layer alternating stack (132, 142). In one embodiment, the first sacrificial spacer material layer 173L includes a semiconductor material such as polysilicon or amorphous silicon. The thickness of the first sacrificial spacer material layer 173L may be in the range of 50 nm to 1,000 nm, but smaller and larger thicknesses may also be employed. A void 181' may be formed in each volume of the first layer via cavity 181 that is not filled with the first sacrificial spacer material layer 173L.

[0070] Reference Figure 6 , a first patterned photoresist layer 177 may be formed above the first sacrificial spacer material layer 173L. Generally, the first patterned photoresist layer 177 may have an opening in the region of the first layer via cavity 181. For example, in a plan view (such as a top view), the opening in the first patterned photoresist layer 177 may be located at or within the periphery of a corresponding one of the first layer cavities 181.

[0071] A first anisotropic etching process may be performed to vertically extend the central portion of the first layer contact via cavity 181, which is laterally surrounded by the vertical extension portion of the first sacrificial spacer material layer 173L. The first anisotropic etching process may include a first anisotropic etching step of etching the material of the first sacrificial spacer material layer 173L. The portion of the first sacrificial spacer material layer 173L that is not masked by the first patterned photoresist layer 177 is uniformly vertically recessed. Each portion of the first sacrificial spacer material layer 173L underlying the corresponding void 181' is etched through, and the top surface section of the corresponding underlying first insulating layer 132 (or interlayer insulating layer 180) is physically exposed under the corresponding void 181'. The tubular portion of the first sacrificial spacer material layer 173L remains in the peripheral region of each first layer via cavity 181, while the central portion of the first sacrificial spacer material layer 173L in each first layer via cavity 181 is etched through during the first anisotropic etching step of the first anisotropic etching process. Each tubular portion of the first sacrificial spacer material layer 173L remaining in the corresponding first layer cavity 181 constitutes the first sacrificial spacer 173.

[0072] The first anisotropic etching process may include a second anisotropic etching step that selectively etches the materials of the first insulating layer 132 and the first sacrificial material layer 142 with respect to the materials of the first sacrificial spacer 173 and the sacrificial substrate pad 5. The second anisotropic etching step of the first anisotropic etching process etches the portion of the first layer alternating stack (132, 142) that is underlying the first layer via cavity 181 and is not covered by the tubular portion of the first sacrificial spacer material layer 173L (i.e., the first sacrificial spacer 173). Each central region of the first layer via cavity 181 may vertically extend into a corresponding sacrificial substrate pad 5 that fills a corresponding substrate recess, while the peripheral region of the first layer via cavity 181 occupied by the first sacrificial spacer 173 does not vertically extend.

[0073] Reference Figure 7 , the first patterned photoresist layer 177, the first sacrificial spacer material layer 173L, the first sacrificial spacer 173, the first patterned hard mask layer 171, and the sacrificial substrate pad 5 may be subsequently removed. For example, the first patterned photoresist layer 177 may be removed by performing an ashing process. In the case where the first sacrificial spacer material layer 173L, the first sacrificial spacer 173, the first patterned hard mask layer 171, and the sacrificial substrate pad 5 include a semiconductor material (such as, polysilicon or amorphous silicon), a wet etching process using tetramethylammonium hydroxide ( T MAH) or trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) may be performed to remove the first sacrificial spacer material layer 173L, the first sacrificial spacer 173, the first patterned hard mask layer 171, and the sacrificial substrate pad 5. If the sacrificial substrate pad 5 includes carbon, these sacrificial substrate pads may be removed by ashing. A stepped cavity having a wider upper portion and a narrower lower portion may be formed.

[0074] After the above removal steps, the first layer via cavity 181 vertically extends through the entire first layer alternating stack (132, 142) and is referred to as the first through-layer cavity 183. The first through-layer cavity 183 extends into the upper portion of the substrate 9. Each first through-layer cavity in the first through-layer cavity 183 includes the entire volume of a corresponding one of the first layer via cavities 181 formed at the processing steps as in Figure 4A and Figure 4B . The first through-layer cavity 183 further includes voids formed by the second anisotropic etching process and by removing the first sacrificial spacer 173 and the sacrificial substrate pad 5. The first through-layer cavity 183 may include a first type of through-layer cavity 183A formed in the first contact region 301 and a second type of through-layer cavity 183B formed in the second contact region 302.

[0075] Reference Figure 8, a selective isotropic etching process can be performed to laterally recess the first sacrificial material layer 142 selectively with respect to the material of the first insulating layer 132. For example, if the first sacrificial material layer 142 includes silicon nitride, a wet etching process using hot phosphoric acid can be performed to laterally recess the first sacrificial material layer 142. Generally, the sidewalls of the first sacrificial material layer 142 can be laterally recessed around the first via cavity 183 with respect to the sidewalls of the first insulating layer 132. Each first via cavity in the first via cavity 183 can include a corresponding set of lateral protrusions (i.e., lateral recesses 142R are formed at each level of the first sacrificial material layer 142) at each level of the first sacrificial material layer 142. A first continuous dielectric liner layer 122L can be deposited conformally in the first via cavity 183 (including in the lateral recesses 142R). The first continuous dielectric liner layer 122L includes a dielectric material (such as silicon oxide) and can have a thickness in the range of 3 nm to 10 nm, but smaller and larger thicknesses can also be used. Alternatively, the silicon oxide first continuous dielectric liner layer 122L can be formed by radical oxidation of the exposed silicon nitride sacrificial material layer 142 (e.g., in-situ steam generation (ISSG)).

[0076] Reference Figure 9 , a first continuous dielectric material layer 124L can be conformally deposited to fill the remaining volume of the lateral recesses 142R in the first sacrificial material layer 142 around the first via cavity 183. The first continuous dielectric material layer 124L includes a dielectric material different from the material of the first continuous dielectric liner layer 122L, such as silicon nitride or silicon carbonitride. The thickness of the first continuous dielectric material layer 124L can be in the range of 30 nm to 300 nm, but smaller or larger thicknesses can also be used. Each remaining volume of the first via cavity 183 includes a narrower lower portion 183L below the bottommost first insulating layer 132 and a wider upper portion 183U above the bottommost first insulating layer 132.

[0077] Reference Figure 10 , a first dielectric fill material layer 126L can be deposited to fill the narrower lower portions 183L of each first via cavity in the first via cavity 183 without completely filling the wider upper portions 183U of each first via cavity in the first via cavity 183. The first dielectric fill material layer 126L includes a dielectric fill material, such as silicon oxide.

[0078] Reference Figure 11, a first sacrificial via fill material may be deposited in the remaining unfilled volume (e.g., upper portion 183U) of the first via cavity 183. The first sacrificial via fill material includes a fill material different from the material of the first dielectric fill material layer 126L. In one embodiment, the first sacrificial via fill material may include a semiconductor material, such as polysilicon or amorphous silicon, or may include a carbon-based material, such as amorphous carbon or diamond-like carbon. The first sacrificial via fill material may be vertically recessed by CMP such that the remaining portions of the first sacrificial via fill material have a top surface substantially at a horizontal plane including the topmost surface of the first continuous dielectric material layer 124L. Each remaining portion of the first sacrificial via fill material is referred to herein as a first sacrificial via fill material portion 128.

[0079] The horizontal extension of the first dielectric fill material layer 126L may be removed from above the horizontal plane including the topmost surface of the first continuous dielectric material layer 124L, for example, by performing a recess etch-back process. The continuous dielectric material layer 124L may act as an etch stop during the recess etch-back process. Each remaining portion of the first dielectric fill material layer 126L located within a respective one of the first via cavities 183 is referred to herein as a first dielectric fill material portion 126.

[0080] Reference Figure 12 , the horizontal extensions of the first continuous dielectric material layer 124L and the first continuous dielectric liner layer 122L above the horizontal plane including the top surface of the interlayer insulating layer 180 may be removed, for example, by performing a series of etch-back processes. Optionally, the sections of the first dielectric fill material portion 126 and the first sacrificial via fill material portion 128 protruding above the horizontal plane including the top surface of the interlayer insulating layer 180 may be removed, for example, by performing a trimming planarization process (such as a chemical mechanical polishing (CMP) process). Each remaining portion of the first continuous dielectric liner layer 122L constitutes a first dielectric liner 122. Each remaining portion of the first continuous dielectric material layer 124L constitutes a first dielectric material layer 124.

[0081] The set of all material portions filling the first via cavity 183 constitutes the first via cavity fill structure 130 in the process, i.e., the fill structure in the process of filling the corresponding via cavity. The first via cavity fill structure 130 in each process includes a substrate dielectric liner 3, a first dielectric liner 122, a first dielectric material layer 124, a first dielectric fill material portion 126, and a first sacrificial via fill material portion 128. In one embodiment, the top surfaces of the first dielectric liner 122, the first dielectric material layer 124, the first dielectric fill material portion 126, and the first sacrificial via fill material portion 128 may be formed in a horizontal plane including the top surface of the interlayer dielectric layer 180. Each adjacent set of the first dielectric liner 122, the first dielectric material layer 124, and the first dielectric fill material portion 126 is herein referred to as the first dielectric layer stack (122, 124, 126).

[0082] Reference Figure 13 , a second alternating stack of a second insulating layer 232 and a second sacrificial material layer 242 may be formed over the substrate 9. The second insulating layer 232 includes an insulating material such as undoped silicate glass or doped silicate glass, and the second sacrificial material layer 242 includes a sacrificial material such as silicon nitride or silicon germanium alloy. The second alternating stack (232, 242) may include multiple repetitions of a unit layer stack including the second insulating layer 232 and the second sacrificial material layer 242. The total number of repetitions of the unit layer stack within the second alternating stack (232, 242) may be, for example, in the range of 8 to 1024 (such as 32 to 256), but fewer and more repetitions may also be employed. Each second insulating layer in the second insulating layer 232 may have a thickness in the range of 20 nm to 200 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. Each second sacrificial material layer in the second sacrificial material layer 242 may have a thickness in the range of 20 nm to 200 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be employed.

[0083] Reference Figure 14, an etch mask layer 187 (such as a photoresist layer) can be formed above the second layer alternating stack (232, 242), and the etch mask layer can be lithographically patterned to form various openings therein. An anisotropic etching process can be performed to transfer the pattern of the openings in the etch mask layer 187 through the second layer alternating stack (232, 242). Second layer openings (249, 219) can be formed through the second layer alternating stack (232, 242). The second layer openings (249, 219) can include second layer memory openings 249 that vertically extend through each layer within the second layer alternating stack (232, 242) in the memory array region 200; and can also include second layer support openings 219 that are formed through the second layer alternating stack (232, 242) in the contact region 300 and are subsequently used to form support pillar structures in the contact region. Each of the second layer memory openings 249 can be formed on top of a corresponding one of the first layer sacrificial memory opening fill structures 148. Each of the second layer support openings 219 can be formed on top of a corresponding one of the first layer sacrificial support opening fill structures 118.

[0084] Reference Figure 15 , the first layer sacrificial opening fill structures (148, 118) can subsequently be selectively removed from below the second layer sacrificial openings (249, 219) for the materials of the base channel portion 11, the first layer alternating stack (132, 142), and the second layer alternating stack (232, 242). For example, if the first layer sacrificial opening fill structures (148, 118) include carbon-based materials, an ashing process can be performed to remove the first layer sacrificial opening fill structures (148, 248). If the etch mask layer 187 includes a photoresist layer, during the ashing process, the photoresist layer will be removed together with the first layer sacrificial opening fill structures (148, 118). Each volume adjacent to the volumes of the first layer memory opening 149 and the second layer memory opening 249 is referred to herein as an interlayer memory opening 49, which is also referred to as a memory opening. Each volume adjacent to the volumes of the first layer support opening 119 and the second layer support opening 219 is referred to herein as an interlayer support opening 19, which is also referred to as a support opening. The base channel portion 11 can be disposed at the bottom of each of the interlayer memory openings 49 and the interlayer support openings 19.

[0085] Reference Figure 16A and Figure 16B, a series of processing steps can be performed to form a memory opening fill structure 58 within each interlayer memory opening 49 and within each interlayer support opening 19. For example, a memory film 50 can be formed within each of the memory opening 49 and the support opening 19. The memory film 50 can include any memory material that can store information by charge trapping, change in resistivity, change in ferroelectric polarization direction (e.g., in a ferroelectric material), or any other material in which information can be stored. For example, each memory film 50 can include a layer stack that includes a blocking dielectric layer 52, a charge storage material layer 54, and a tunneling dielectric layer 56. In one embodiment, the memory film 50 can be formed by depositing material layers and / or material portions and, for example, removing excess portions of the material layers and / or material portions from the exterior and bottom of the memory opening 49 and the support opening 19 by performing an anisotropic etching process (e.g., a sidewall spacer etching process). In one embodiment, the blocking dielectric layer 52 can include a silicon oxide or aluminum oxide layer. The charge storage material layer 54 can include a silicon nitride layer. The tunneling dielectric layer 56 can include a silicon oxide layer or an "ONO" stack of a silicon oxide / silicon nitride / silicon oxide layer.

[0086] A vertical semiconductor channel 60 can be formed within each of the memory opening 49 and the support opening 19 by conformally depositing a doped semiconductor channel material of a first conductivity type (e.g., amorphous silicon or polycrystalline silicon). The semiconductor channel material can be doped with the same conductivity type as the horizontal semiconductor channel (not explicitly shown) located in the substrate 9. A dielectric fill material can be deposited in the remaining volume of the memory opening 49 and the support opening 19, and the dielectric fill material can be vertically recessed to form a dielectric core 62. A semiconductor material doped with a second conductivity type (e.g., amorphous silicon or polycrystalline silicon) can be deposited over each dielectric core 62 at the top of each vertical semiconductor channel 60 to form a drain region 63 within each of the memory opening 49 and the support opening 19. The second conductivity type is opposite to the first conductivity type. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each memory stack structure 55 includes a corresponding vertical stack of memory elements. For example, each vertical stack of memory elements can include portions of the charge storage layer 54 located at the level of the sacrificial material layers (142, 242), which are subsequently replaced by conductive layers.

[0087] Typically, a memory opening fill structure 58 is formed in a memory opening 49, and a support pillar structure 20 is formed in a support opening 19. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical stack of memory elements (e.g., portions of memory membranes 50), a drain region 63, and an optional dielectric core 62. A drain select level dielectric isolation structure (not shown) may be formed through the uppermost collection of the second sacrificial material layer 242.

[0088] Reference Figure 17A and Figure 17B , an insulating layer may optionally be formed over the second layer alternating stack (232, 242). The insulating layer (if formed) is referred to herein as a first contact level dielectric layer 280. A second patterned hard mask layer 271 may be formed over the first contact level dielectric layer 280 by depositing and patterning a hard mask material. The second patterned hard mask layer 271 includes a material that can act as an etch mask material during subsequent anisotropic etch processes. In one embodiment, the second patterned hard mask layer 271 may include a semiconductor material (such as amorphous silicon) and may have a thickness in the range of 50 nm to 500 nm, although smaller and larger thicknesses may be employed. The hard mask layer 271 may be patterned by applying a photoresist material over the hard mask layer 271 and lithographically patterning the photoresist material, and transferring the pattern in the photoresist material through the hard mask layer 271. In one embodiment, the pattern of the openings in the second patterned hard mask layer 271 may be the same as the pattern of a first via cavity fill structure 130 in the process, and the pattern of the first via cavity fill structure in the process is the same as the pattern of the first layer via cavity 181.

[0089] Second layer via cavities 281 are formed through corresponding subsets of the layers within the second layer alternating stack (232, 242). Each second layer via cavity in the second layer via cavities 281 may vertically extend through the contact level dielectric layer 280 and through corresponding subsets of the second sacrificial material layer 242 and the second insulating layer 232 such that the top surface of a selected second insulating layer 232 is physically exposed at the bottom of each second layer via cavity 281. In one embodiment, the second layer via cavities 281 may have different depths from each other, and each second insulating layer 232 may be physically exposed to a corresponding overlying second layer via cavity 281.

[0090] The second via cavities 281 with different depths can be formed by using multiple masked anisotropic etching processes. In an illustrative example, the openings in the second patterned hard mask layer 271 can have the pattern of all the second via cavities 281 to be formed subsequently. An anisotropic etching process can be performed to transfer the pattern of the openings in the second patterned hard mask layer 271 through the first contact level dielectric layer 280.

[0091] Subsequently, multiple iterations of a combination of a corresponding masking process and a corresponding anisotropic etching process can be performed to etch through corresponding subsets of the second sacrificial material layer 242 and corresponding subsets of the second insulating layer 232. Each masking process forms a corresponding patterned photoresist layer (not shown) that masks a corresponding subset of the openings in the second patterned hard mask layer 271 and does not mask the corresponding complementary subsets of these openings. Each anisotropic etching process etches a corresponding number of the second sacrificial material layer 242 and a corresponding number of the insulating layer 32 under each opening in the second patterned hard mask layer 271 that is not masked by the corresponding patterned photoresist layer. In one embodiment, the number of the etched second sacrificial material layer 242 and the etched second insulating layer 232 under the unmasked openings in the second patterned hard mask layer 271 can be a non - negative integer power of 2, i.e., 1, 2, 4, 8, 16, 32, 64, etc. By using combinations of various mask patterns for the patterned photoresist layer, the total depth of the second via cavities 281 can vary so as to physically expose the top surface of the second insulating layer 232 at each level. Subsequently, the second patterned hard mask layer 271 can be removed.

[0092] The second via cavities 281 can include a first type of second via cavity 281A formed in the first contact region 301 and a second type of second via cavity 281B formed in the second contact region 302. In one embodiment, the second type of second via cavity 281B has various depths such that each second insulating layer in the second insulating layer 232 has a top surface section that is physically exposed to the corresponding overlying second type of second via cavity 281A. In one embodiment, each of the first type of second via cavity 281A can extend through each layer in the second alternating stack (232, 242) except the bottom - most second insulating layer 232. In this case, each of the first type of second via cavity 281A can vertically extend through each second sacrificial material layer 242 in the second alternating stack (232, 242). The lateral dimension (such as diameter) of the second via cavities 281 can be in the range of 200 nm to 3,000 nm, but smaller and larger lateral dimensions can also be employed.

[0093] Reference Figure 18, a second sacrificial spacer material layer 273L can be deposited above the second patterned hard mask layer 271 and in the peripheral portion of the second layer vias cavity 281. The second sacrificial spacer material layer 273L includes a material that can subsequently be used as an etch mask material for the materials of the second layer alternating stack (232, 242). In one embodiment, the second sacrificial spacer material layer 273L includes a semiconductor material, such as polysilicon or amorphous silicon. The thickness of the second sacrificial spacer material layer 273L can be in the range of 50 nm to 1,000 nm, but smaller and larger thicknesses can also be employed. A void 281' can be formed in each volume of the second layer vias cavity 281 that is not filled with the second sacrificial spacer material layer 273L.

[0094] Reference Figure 19 , a second patterned photoresist layer 277 can be formed above the second sacrificial spacer material layer 273L. Generally speaking, the second patterned photoresist layer 277 can have openings in the regions of the second type of second layer vias cavity 281B. For example, in a plan view (such as a top view), the openings in the second patterned photoresist layer 277 can be located at or within the periphery of a corresponding one of the second type of second layer cavities 281B in the second contact region 302.

[0095] A second anisotropic etching process can be performed to vertically extend the central portion of the second type of second layer contact vias cavity 281B, which is laterally surrounded by the vertical extension portion of the second sacrificial spacer material layer 273L. The second anisotropic etching process can include a first anisotropic etching step of etching the material of the second sacrificial spacer material layer 273L. The portions of the second sacrificial spacer material layer 273L that are not masked by the second patterned photoresist layer 277 are uniformly vertically recessed. Each portion of the second sacrificial spacer material layer 273L underlying the corresponding void 281' is etched through, and the top surface section of the corresponding underlying second insulating layer 232 (or the first contact level dielectric layer 280) is physically exposed under the corresponding void 281'. The tubular portions of the second sacrificial spacer material layer 273L are retained in the peripheral regions of each second type of second layer vias cavity 281, while the central portion of the second sacrificial spacer material layer 273L in each second type of second layer vias cavity 281 is etched through during the second anisotropic etching step of the second anisotropic etching process. Each tubular portion of the second sacrificial spacer material layer 273L retained in the corresponding second type of second layer cavity 281 constitutes the second sacrificial spacer 273.

[0096] The second anisotropic etching process may include a second anisotropic etching step that selectively etches the materials of the second insulating layer 232 and the second sacrificial material layer 242 with respect to the materials of the second sacrificial spacer 273 and the first sacrificial via fill material portion 128. The second anisotropic etching step of the second anisotropic etching process etches the underlying portion of the second layer alternating stack (232, 242) that is below the second type of second layer via cavity 281B and not covered by the tubular portion (i.e., the second sacrificial spacer 273) of the second sacrificial spacer material layer 273L. Each central region of the second type of second layer via cavity 281 may vertically extend into the upper portion of the corresponding underlying first sacrificial via fill material portion 128, while the peripheral region of the second type of second layer via cavity 281B occupied by the second sacrificial spacer 273 does not vertically extend.

[0097] Reference Figure 20 , the second patterned photoresist layer 277, the second sacrificial spacer material layer 273L, the second sacrificial spacer 273, and the second patterned hard mask layer 271, as well as a subset of the first sacrificial via fill material portion 128 in the second region 302, may be subsequently removed. For example, the second patterned photoresist layer 277 may be removed by performing an ashing process. In the case where the first subset of the second sacrificial spacer material layer 273L, the second sacrificial spacer 273, the second patterned hard mask layer 271, and the first sacrificial via fill material portion 128 in the second contact region 302 includes a semiconductor material (such as polysilicon or amorphous silicon), a wet etching process using TMAH or TMY may be performed to remove the second sacrificial spacer material layer 273L, the second sacrificial spacer 273, and the second patterned hard mask layer 271, as well as the first subset of the first sacrificial via fill material portion 128 that is not covered by the bottommost second insulating layer 232 and is located in the second contact region 302.

[0098] Subsequently, a selective isotropic etching process may be performed to laterally recess the second sacrificial material layer 242 selectively with respect to the materials of the second insulating layer 232 and the first dielectric fill material portion 126. For example, if the second sacrificial material layer 242 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to laterally recess the second sacrificial material layer 242. Generally, the sidewalls of the second sacrificial material layer 242 may be laterally recessed around the second layer via cavity 281 with respect to the sidewalls of the second insulating layer 232, and the second layer via cavity is now referred to as the second through-layer cavity 283. Each second through-layer cavity in the second through-layer cavity 283 includes as in Figure 17A and Figure 17Bthe entire volume of a respective one of the second via cavities 281 formed at the processing step. The second through-layer cavity 283 further includes voids formed by a second anisotropic etching process and by removing a first subset of the second sacrificial spacer 273 and the first sacrificial via fill material portion 128. Finally, the second through-layer cavity 283 further includes a lateral recess 242R formed at the level of the sacrificial material layer 242. The second through-layer cavity 283 may include a first type of through-layer cavity 283A formed in the first contact region 301 and a second type of through-layer cavity 283B formed in the second contact region 302. Each second through-layer cavity in the second through-layer cavity 283 may include a corresponding set of lateral protrusions corresponding to the lateral recesses 242R located at each level of the second sacrificial material layer 242. A second continuous dielectric liner layer 222L may be deposited conformally in the second through-layer cavity 283. The second continuous dielectric liner layer 222L includes a dielectric material (such as, silicon oxide), and may have a thickness in the range of 3 nm to 20 nm, but smaller and larger thicknesses may also be employed. Alternatively, the silicon oxide second continuous dielectric liner layer 222L may be formed by radical oxidation of the exposed silicon nitride second sacrificial material layer 242 (e.g., in-situ steam generation (ISSG)).

[0099] Reference Figure 21 , a second continuous dielectric material layer 224L may be conformally deposited to fill the remaining volume of the lateral recesses in the second sacrificial material layer 242 surrounding the second through-layer cavity 283. The second continuous dielectric material layer 224L includes a dielectric material, such as silicon nitride or silicon carbonitride. The thickness of the second continuous dielectric material layer 224L may be in the range of 30 nm to 300 nm, but smaller or larger thicknesses may also be employed. The second through-layer cavity 283 includes a narrower lower portion 283L located in the first alternating stack (232, 242) and a wider upper portion 283U located in the second alternating stack (132, 142).

[0100] Reference Figure 22 , a second dielectric fill material layer 226L may be deposited to fill the narrower lower portion 283L of each second through-layer cavity in the second through-layer cavity 283, without completely filling the wider upper portion 283U of each second through-layer cavity in the second through-layer cavity 283. The second dielectric fill material layer 226L includes a dielectric fill material, such as silicon oxide.

[0101] Reference Figure 23, a third patterned photoresist layer 279 may be formed over the second dielectric fill material layer 226L. Generally, the third patterned photoresist layer 279 may have openings in regions of the second via-through cavity 283A of the first type. For example, in a plan view (such as a top view), the openings in the third patterned photoresist layer 279 may be located at or within the vertically extending inner sidewalls of the second dielectric fill material layer that is within a respective one of the second via-through cavities 283A of the first type in the first contact region 301.

[0102] A third anisotropic etching process may be performed to vertically extend the voids located at the central portions of the second layer contact via cavities 281A of the first type, which are now the central portions of the second via-through cavities 283A of the first type. The third anisotropic etching process etches through the horizontally extending unmasked portions of the second dielectric fill material layer 226, the underlying portion of the bottommost second insulating layer 232, and the interlayer insulating layer 180. The top surfaces of each of the first sacrificial via fill material portions 128 underlying the second via-through cavities 283A of the first type may be physically exposed. Subsequently, the third patterned photoresist layer 279 may be removed, for example, by ashing.

[0103] Reference Figure 24 , a second sacrificial via fill material may be deposited in the remaining unfilled volume of the second via-through cavity 283. The second sacrificial via fill material includes a fill material different from the material of the second dielectric fill material layer 226L. In one embodiment, the second sacrificial via fill material may include a semiconductor material such as polysilicon or amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon. The second sacrificial via fill material may be vertically recessed (e.g., by CMP) such that the remaining portions of the second sacrificial via fill material have top surfaces in or near a horizontal plane including the topmost surface of the second continuous dielectric material layer 224L. Each of the remaining portions of the second sacrificial via fill material is referred to herein as a second sacrificial via fill material portion 228.

[0104] The horizontal extension of the second dielectric fill material layer 226L can be removed, for example, by performing a recess etching process above the horizontal plane including the top surface of the second continuous dielectric material layer 224L. Each remaining portion of the second dielectric fill material layer 226L located within a respective one of the second via-level cavities 283 is referred to herein as a second dielectric fill material portion 226. An optional air gap 129 free of any solid-phase material can be formed within the narrower lower portion 283L of each of the second via-level cavities 283. The top of the air gap 129 is encapsulated by the bottom portion of a respective one of the second dielectric fill material portions 226. The bottom and sides of the air gap 129 are encapsulated by a respective one of the first dielectric fill material portions 126. However, there is no air gap 129 in the first contact region 301.

[0105] Reference Figure 25 , the horizontal extensions of the second continuous dielectric material layer 224L and the second continuous dielectric liner layer 222L located above the horizontal plane including the top surface of the first contact-level dielectric layer 280 can be removed, for example, by performing at least one etching process. Optionally, the segments of the second dielectric fill material portions 226 and the second sacrificial via fill material portions 228 protruding above the horizontal plane including the top surface of the first contact-level dielectric layer 280 can be removed, for example, by performing a trimming planarization process (such as a chemical mechanical polishing process). Each remaining portion of the second continuous dielectric liner layer 222L constitutes a second dielectric liner 222. Each remaining portion of the second continuous dielectric material layer 224L constitutes a second dielectric material layer 224.

[0106] The set of all material portions filling the second via-level cavities 283 constitutes the second via cavity fill structure 230 in the process, i.e., the fill structure in the process filling the respective via cavities. Each second via cavity fill structure 230 in the process includes a second dielectric liner 222, a second dielectric material layer 224, second dielectric fill material portions 226, and second sacrificial via fill material portions 228. In one embodiment, the top surfaces of the second dielectric liner 222, the second dielectric material layer 224, the second dielectric fill material portions 226, and the second sacrificial via fill material portions 228 can be formed in the horizontal plane including the top surface of the first contact-level dielectric layer 280. Each adjacent set of the second dielectric liner 222, the second dielectric material layer 224, and the second dielectric fill material portions 226 is referred to herein as a second dielectric layer stack (222, 224, 226).

[0107] Reference Figure 26A and Figure 26B, a second contact-level dielectric layer 282 can be deposited over the first contact-level dielectric layer 280. The second contact-level dielectric layer 280 can include a dielectric material, such as undoped silicate glass or doped silicate glass, and can have a thickness in the range of 100 nm to 1000 nm, although smaller and larger thicknesses can also be employed.

[0108] A photoresist layer (not shown) can be applied over the second contact-level dielectric layer 282, and the photoresist layer can be lithographically patterned to form openings in a region extending across the memory array region 100 and the contact region 300. The openings in the photoresist layer can extend laterally along a first horizontal direction hd1 between each adjacent cluster of the memory opening fill structures 58. A backside trench 79 can be formed by transferring the pattern in the photoresist layer through the contact-level dielectric layers (280, 282), the second alternating stack (232, 242), and the first alternating stack (132, 142) and into the substrate 9. Portions of the contact-level dielectric layers (280, 282), the second alternating stack (232, 242), and the first alternating stack (132, 142) underlying the openings in the photoresist layer can be removed to form the backside trench 79. In one embodiment, the backside trench 79 can be formed between clusters of the memory opening fill structures 58. The clusters of the memory opening fill structures 58 can be laterally spaced apart by the backside trench 79 along a second horizontal direction hd2.

[0109] Reference Figure 27 , an etchant that selectively etches the materials of the first and second sacrificial material layers (142, 242) relative to the materials of the first and second insulating layers (132, 232) and the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, by using an isotropic etching process. A first backside recess is formed in the volume from which the first sacrificial material layer 142 is removed. A second backside recess is formed in the volume from which the second sacrificial material layer 242 is removed.

[0110] The isotropic etching process can be a wet etching process that employs a wet etching solution, or can be a vapor-phase (dry) etching process in which the etchant is introduced into the backside trench 79 in a gaseous phase. For example, if the first and second sacrificial material layers (142, 242) include silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide and silicon.

[0111] Each of the first dorsal recess and the second dorsal recess may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first dorsal recess and the second dorsal recess may be greater than the height of the corresponding dorsal recess. A plurality of first dorsal recesses may be formed in the volume of material from which the first sacrificial material layer 142 is removed. A plurality of second dorsal recesses may be formed in the volume of material from which the second sacrificial material layer 242 is removed. Each of the first dorsal recess and the second dorsal recess may extend substantially parallel to the top surface of the substrate 9. The dorsal recesses may be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the overlying insulating layer (132 or 232). In one embodiment, each of the first dorsal recess and the second dorsal recess may always have a uniform height.

[0112] Optionally, a dorsal barrier dielectric layer (not shown) may be deposited in the dorsal recesses and dorsal trenches 79 and over the contact level dielectric layer 280. The dorsal barrier dielectric may include a dielectric metal oxide material such as alumina. At least one conductive material may be conformally deposited in the plurality of dorsal recesses, on the sidewalls of the dorsal trenches 79, and over the contact level dielectric layer 280. The at least one conductive material may include at least one metal material, i.e., a conductive material including at least one metal element.

[0113] A plurality of conductive layers 146 may be formed in the plurality of first dorsal recesses, a plurality of second conductive layers 246 may be formed in the plurality of second dorsal recesses, and a continuous metal material layer (not shown) may be formed on the sidewalls of each dorsal trench 79 and over the contact level dielectric layer 280. Thus, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with a first conductive material layer and a second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the dorsal barrier dielectric layer and the conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the dorsal barrier dielectric layer and the second conductive layer 246. A dorsal cavity exists in the portion of each dorsal trench 79 that is not filled with the continuous metal material layer.

[0114] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy (such as a metal silicide), an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and / or ruthenium. In one embodiment, the metal material can include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the backside recess can be a combination of a titanium nitride layer and a tungsten fill material. In one embodiment, the metal material can be deposited by chemical vapor deposition or atomic layer deposition.

[0115] The deposited metal material of the continuous metal material layer can be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the contact-level dielectric layers (280, 282). Each remaining portion of the deposited metal material in the first backside recess constitutes the conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes the second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure (e.g., a word line or a select gate electrode).

[0116] Each memory opening fill structure in the memory opening fill structure 58 (which includes the corresponding memory stack structure 55) includes a vertical stack of memory elements at each level of the conductive layers (146, 246). A subset of the intermediate conductive layers (146, 246) can include word lines for the memory elements. At least one uppermost conductive layer 246 can include a drain-side select gate electrode. At least one lowermost conductive layer 146 can include a source-side select gate electrode.

[0117] Reference Figure 28 , a layer of insulating spacer material can be conformally deposited in the backside trenches 79 and above the contact-level dielectric layers (280, 282). An anisotropic etching process can be performed to remove the horizontal extensions of the insulating spacer material layer. Each remaining vertical extension of the insulating spacer material layer constitutes the insulating spacer 74.

[0118] At least one conductive material (such as at least one metallic material) can be deposited in the unfilled volume of the dorsal trench 79. A planarization process such as a chemical mechanical polishing process and / or a recess etching process can be performed to remove the excess of the at least one conductive material above a horizontal plane including the top surface of the second contact level dielectric layer 282. In some embodiments, an upper portion of the second contact level dielectric layer 282 can be removed in parallel during the planarization process. Each remaining portion of the at least one conductive material laterally surrounded by the respective insulating spacer 74 constitutes a dorsal contact via structure 76.

[0119] Reference Figure 29A and Figure 29B , a third contact level dielectric layer 284 can be formed above the second contact level dielectric layer 282. A photoresist layer (not shown) can be applied above the contact level dielectric layers (280, 282, 284), and an opening can be formed above the region of the second via cavity fill structure 230 in the process. An anisotropic etching process can be performed to etch through the unmasked portions of the contact level dielectric layers (280, 282, 284) to form connection via cavities 81 through the contact level dielectric layers (280, 282, 284). The top surface of the second via cavity fill structure 230 in the process can be physically exposed at the bottom of the connection via cavity 81. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0120] Reference Figure 30 , subsequently, a second subset of the first sacrificial via fill material portion 128 and the second sacrificial via fill material portion 228 present in the first contact region 301 of the exemplary structure illustrated in Figure 29A and Figure 29B can be selectively removed for the materials of the contact level dielectric layers (280, 282, 284) and the second dielectric fill material portion 226. For example, if the second sacrificial via fill material portion 228 and the second subset of the first sacrificial via fill material portion 128 include a semiconductor material such as amorphous silicon, a wet etching process using TMY or TMAH can be used to remove the second subset of the first sacrificial via fill material portion 128 and the second sacrificial via fill material portion 228.

[0121] The contact via cavity 85 is formed in the volume from which the first subset of the first sacrificial via fill material portion 128 and the second sacrificial via fill material portion 228 have been removed. The first subset of the contact via cavity 85 that is located in the first contact region 301 is referred to as the first contact via cavity 85A. The second subset of the contact via cavity 85 that is located in the second contact region 302 is referred to as the second contact via cavity 85B. Each first contact via cavity in the first contact via cavity 85A can be laterally surrounded by a corresponding first dielectric fill material portion 126 and a corresponding second dielectric fill material portion 226. Each second contact via cavity in the second contact via cavity 85B can be laterally surrounded by a corresponding second dielectric fill material portion 226.

[0122] Reference Figure 31 , a first anisotropic etching process can be performed to vertically recess the physical exposure level surfaces of the first dielectric fill material portion 126 and the second dielectric fill material portion 226. The third contact level dielectric layer 284 can be vertically recessed in parallel during the anisotropic etching process. The annular top surface of the first dielectric material layer 124 can be physically exposed under each first contact via cavity 85A. The annular top surface of the second dielectric material layer 224 can be physically exposed under each second contact via cavity 85B. Each remaining portion of the first dielectric fill material portion 126 that underlies a corresponding first contact via cavity 85A is referred to herein as a pillar fill dielectric material portion 326. Each remaining portion of the second dielectric fill material portion 226 that underlies all corresponding second contact via cavities 85B is referred to herein as an internal dielectric fill material portion 426. Each internal dielectric fill material portion 426 can vertically extend through a subset of the first conductive layer 146 and at least one second conductive layer 246, including the bottommost second conductive layer 246.

[0123] Reference Figure 32, an isotropic etching process can be performed to isotropically recess the physically exposed surfaces of the first dielectric fill material portion 126 and the second dielectric fill material portion 226. During the isotropic etching process, the physically exposed surfaces of the contact level dielectric material layers (280, 282, 284) can be recessed in parallel. In one embodiment, the first dielectric fill material portion 126 and the second dielectric fill material portion 226 can include a silicate glass material (such as doped silicate glass or organosilicate glass) having a high etching rate, and the contact level dielectric material layers (280, 282, 284) can include a silicate glass material (such as undoped silicate glass) having a low etching rate. In this case, the etching rate of the contact level dielectric material layers (280, 282, 284) can be lower than the etching rates of the first dielectric fill material portion 126 and the second dielectric fill material portion 226. The duration of the isotropic etching process is selected such that the tubular portions of each of the first dielectric fill material portion 126 and the second dielectric fill material portion 226 remain around the respective contact via cavity 85 after the isotropic etching process. Each remaining tubular portion of the first dielectric fill material portion 126 around the bottom portion of the respective first contact via cavity 85A is referred to herein as a first tubular dielectric material portion 127. Each remaining tubular portion of the second dielectric fill material portion 226 around the contact via cavity 85 is referred to herein as a second tubular dielectric material portion 227.

[0124] Each second dielectric material layer laterally surrounding a respective one of the first contact via cavities 85A in the second dielectric material layer 224 can have an annular bottom portion having a physically exposed annular top surface, a physically exposed annular bottom surface, and a physically exposed cylindrical sidewall. Each second tubular dielectric material portion 227 can contact the inner cylindrical sidewall of the respective second dielectric material layer 224. Each first tubular dielectric material portion 227 located around a respective one of the first contact via cavities 85A can contact the inner cylindrical sidewall of the respective first dielectric material layer 124.

[0125] Reference Figure 33, a second anisotropic etching process can be performed to remove the unmasked horizontally extending portions of the second dielectric material layer 224 and the first dielectric material layer 124. Alternatively, an isotropic etching process can be used instead. Each remaining portion of the first dielectric material layer 124 located below the corresponding first contact via cavity 85A is referred to herein as a pillar dielectric material layer 324. Each remaining portion of the second dielectric material layer 224 located below the corresponding second contact via cavity 85B is referred to herein as an internal dielectric material layer 424. Each internal dielectric material layer 424 can be laterally surrounded by a corresponding portion of the first dielectric fill material 126 underlying the second contact via cavity 85B and can laterally surround a corresponding internal dielectric material portion 426.

[0126] In one embodiment, the bottom portions of the first dielectric material layer 124 and the second dielectric material layer 224 can be laterally recessed outwardly relative to the inner sidewalls of the corresponding overlying first dielectric fill material portions 126 or relative to the inner sidewalls of the corresponding overlying second dielectric fill material portions 226. In such a case, an annular recess can be formed below the first dielectric fill material portion 126 and below the second dielectric fill material portion 226, and the annular recess can subsequently be filled with a laterally protruding annular portion of the corresponding contact via structure.

[0127] Reference Figure 34 , an etching process can be performed to remove the physically exposed portions of the first dielectric liner 122, the second dielectric liner 222, and an optional backside barrier dielectric layer (if present). An anisotropic etching process and / or an isotropic etching process can be performed. Each first conductive layer in the first conductive layer 146 can have a corresponding annular top surface physically exposed to the corresponding first contact via cavity 85A. Each second conductive layer in the second conductive layer 246 can have a corresponding annular top surface physically exposed to the corresponding second contact via cavity 85B.

[0128] In one embodiment, each first dielectric liner 122 around the first contact via cavity 85A can be divided into two discrete portions by an etching process. In such a case, each remaining portion of the first dielectric liner 122 underlying the corresponding first contact via cavity 85A is referred to herein as a pillar dielectric liner 322. In one embodiment, each second dielectric liner 222 around the second contact via cavity 85B can be divided into two discrete portions by an etching process. In such a case, each remaining portion of the second dielectric liner 222 underlying the corresponding second contact via cavity 85B is referred to herein as an internal dielectric liner 422.

[0129] Each adjacent combination of the substrate dielectric liner 3 (which may be optional) underlying the corresponding first contact via cavity 85A, the pillar dielectric liner 322, the pillar dielectric material layer 324, and the pillar fill dielectric material portion 326 constitutes a first dielectric pillar structure 320. Each adjacent combination of the substrate dielectric liner 3 (which may be optional) underlying the corresponding second contact via cavity 85B, the first dielectric liner 122, the first dielectric material layer 124, the first dielectric fill material portion 126, the internal dielectric liner 422, the internal dielectric material layer 424, the internal dielectric fill material portion 426, and the optional air gap 129 constitutes a second dielectric pillar structure 420.

[0130] Each adjacent combination of the first dielectric liner 122, the first dielectric material layer 124, and the first tubular dielectric material portion 127 around the first contact via cavity 85A constitutes a first layer dielectric spacer (122, 124, 127). Each adjacent combination of the second dielectric liner 222, the second dielectric material layer 224, and the second tubular dielectric material portion 227 around the contact via cavity 85 constitutes a second layer dielectric spacer (222, 224, 227).

[0131] At least one of the first dielectric pillar structures 320 may include at least one first laterally protruding fin portion 320F that protrudes outward at each level of a corresponding first subset of the first conductive layer 146. In one embodiment, the first layer dielectric spacer (122, 124, 127) includes at least one first laterally protruding fin portion 150F that protrudes outward at each level of a second subset of the first conductive layer 146. The second layer dielectric spacer (222, 224, 227) includes at least one first laterally protruding fin portion 250F that protrudes outward at each level of the second conductive layer 246. At least one of the second dielectric pillar structures 420 may include a first laterally protruding fin portion 420FF that protrudes outward at each level of the first conductive layer 246, and at least one second laterally protruding fin portion 420SF that protrudes outward at each level of a corresponding first subset of the second conductive layer 146.

[0132] In one embodiment, each first layer dielectric spacer (122, 124, 127) does not directly contact the corresponding underlying first dielectric pillar structure 320 and may vertically extend through each first conductive layer 146 within a corresponding second subset of the first conductive layer 146. In one embodiment, each second layer dielectric spacer (222, 224, 227) around the corresponding first contact via cavity 85A does not directly contact the corresponding underlying first layer dielectric spacer (122, 124, 127) and may vertically extend through each second conductive layer 246. In one embodiment, each second layer dielectric spacer (222, 224, 227) around the corresponding second contact via cavity 85B does not directly contact the corresponding underlying second dielectric pillar structure 420 and may vertically extend through each second conductive layer 246 within a corresponding second subset of the second conductive layer 246.

[0133] Reference Figure 35A and Figure 35B , at least one conductive material may be deposited in each of the first contact via cavity 85A and the second contact via cavity 85B. The at least one conductive material may include a metal barrier liner and a metal fill material. The metal barrier liner may include a conductive metal barrier material such as TiN, TaN, WN, MoN, TiC, TaC, and / or WC. The metal fill material may include a metal or an intermetallic alloy such as Ti, Ta, W, Mo, Co, Ru, W, Cu, etc. The excess portion of the at least one conductive material may be removed from above a horizontal plane including the top surface of the third contact level dielectric layer 284 by performing a planarization process. The planarization process may employ a chemical mechanical polishing process or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding first contact via cavity 85A constitutes a first contact via structure 86A. Each remaining portion of the at least one conductive material filling the corresponding second contact via cavity 85B constitutes a second contact via structure 86B. The first contact via structure 86A and the second contact via structure 86B are collectively referred to herein as the contact via structure 86.

[0134] Each adjacent combination of the first dielectric pillar structure 320, the first layer dielectric spacer (122, 124, 127), the second layer dielectric spacer (222, 224, 227), and the first contact via structure 86A constitutes a first support and contact assembly 380 located in the first contact region 301. Each adjacent combination of the second dielectric pillar structure 420, the second layer dielectric spacer (222, 224, 227) (which may be referred to as a dielectric spacer or an additional dielectric spacer), and the second contact via structure 86B constitutes a second support and contact assembly 480 in the second contact region 302. Each support and contact assembly in the support and contact assemblies (380, 480) provides electrical contact with the corresponding conductive layer (146, 246).

[0135] Figure 36 Illustrates an alternative exemplary structure according to an alternative embodiment of the present disclosure. In the alternative embodiment, Figure 33 and Figure 34 The etching steps shown etch through the first dielectric liner 122, the first dielectric material layer 124, and the exposed first insulating material layer 132 to expose the first backside barrier dielectric layer 144 located above the corresponding first conductive layer 146, as shown in the inset of Figure 36 . These etching steps also etch through the second dielectric liner 222, the second dielectric material layer 224, and the exposed second insulating material layer 232 to expose the second backside barrier dielectric layer (not shown for clarity) located above the corresponding second conductive layer 246.

[0136] Referring to Figure 37 , the portion of the first backside barrier dielectric layer exposed in the contact via cavity 85 can be removed by an etching process to expose the surface of the underlying conductive layer (146, 246). If the backside barrier dielectric layer includes alumina, the etching process can include a hot phosphoric acid etching process.

[0137] Referring to Figure 38 , as described above with respect to Figure 35A and Figure 35B , a contact via structure 86 is formed in the contact via cavity 85. If the etching process of Figure 33 does not provide sufficient space between the conductive layer (146, 246) and the contact via structure 86, then the process of the alternative embodiment of Figures 36 to 38 is advantageous.

[0138] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a memory device includes: a first layer of a first insulating layer 132 and a first conductive layer 146, which are alternately stacked (132, 146) and located above a substrate 9; a second layer of a second insulating layer 232 and a second conductive layer 246, which are alternately stacked (232, 246) and overlie the first layer of the alternately stacked (132, 146); a memory opening 49 that vertically extends through the first layer of the alternately stacked (132, 146) and the second layer of the alternately stacked (232, 246); memory opening filling structures 58 that are located in the memory opening 49, wherein each of the memory opening filling structures in the memory opening filling structures 58 includes a vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., a portion of a memory film 50); and a first support and contact assembly 380 that vertically extends through the first layer of the alternately stacked (132, 146) and the second layer of the alternately stacked (232, 246). The first support and contact assembly 380 includes: a first contact via structure 86A that contacts a circular top surface of a first reference conductive layer 146 and has a top surface above a horizontal plane including a top surface of the second layer of the alternately stacked (232, 246), and the first reference conductive layer is one of the first conductive layers 146 in the first layer of the alternately stacked (132, 146); a first dielectric pillar structure 320 that has at least one first laterally protruding fin portion 320F protruding outward at each level of a first subset of underlying layers of the first conductive layer 146 underlying the first reference conductive layer 146; and a first layer of dielectric spacers (122, 124, 127) that laterally surrounds the first contact via structure 86A, does not directly contact the first dielectric pillar structure 320, and vertically extends through each of the first conductive layers 146 within a second subset of the first conductive layer 146 overlying the first reference conductive layer 146.

[0139] As used herein, a "reference" layer refers to a layer selected as a reference among a plurality of layers having similar characteristics. Thus, for each first contact via structure 86A in an exemplary structure, there is a first conductive layer 146 that directly contacts the first contact via structure 86A. The first conductive layer 146 that directly contacts the first contact via structure 86A becomes the reference first conductive layer 146 for the first contact via structure 86A. Similarly, the second conductive layer 246 that directly contacts the second contact via structure 86B becomes the reference second conductive layer 246 for the second contact via structure 86B.

[0140] In one embodiment, the memory device further includes a second dielectric spacer (222, 224, 227) that laterally surrounds the first contact via structure 86A and contacts each of the second conductive layers in the second conductive layer 246. In one embodiment, the second dielectric spacer (222, 224, 227) does not directly contact the first dielectric spacer (122, 124, 127).

[0141] In one embodiment, the first dielectric spacer (122, 124, 127) includes at least one first laterally protruding fin portion 150F that protrudes outward at each level of a second subset of the first conductive layer 146. The second dielectric spacer (222, 224, 227) includes at least one first laterally protruding fin portion 250F that protrudes outward at each level of the second conductive layer 246.

[0142] In one embodiment, the second dielectric spacer (222, 224, 227) includes an annular bottom surface that contacts the top surface of the bottommost second insulating layer 232 of the second insulating layer 232. In one embodiment, the topmost surface of the first dielectric spacer (122, 124, 127) contacts the bottom surface of the bottommost second insulating layer 232 of the second insulating layer 232.

[0143] In one embodiment, the first dielectric column structure 320 includes: a column dielectric liner 322 that vertically extends through each of the first conductive layers 146 within a first subset of the first conductive layer 146; and a column dielectric material layer 324 that is laterally surrounded by the column dielectric liner 322 and includes a vertically extending portion that vertically extends from the first contact via structure 86A into a portion of the substrate 9 underlying the first alternating stack (132, 146). In one embodiment, the first dielectric column structure 320 further includes a column dielectric filler material portion 326 that is laterally surrounded by the column dielectric material layer 324.

[0144] In one embodiment, the first dielectric spacer (122, 124, 127) includes: a first dielectric liner 122 that contacts each of the first conductive layers 146 within a second subset of the first conductive layer 146; and a first dielectric material layer 124 that is laterally surrounded by the first dielectric liner 122 and includes a vertically extending portion that extends through each of the first conductive layers 146 within the second subset of the first conductive layer 146.

[0145] In one embodiment, the first layer of dielectric spacers (122, 124, 127) further includes a first tubular dielectric material portion 127 that laterally surrounds the first dielectric material layer 124 and contacts a section of the cylindrical sidewall of the first contact via structure 86A. In one embodiment, the first tubular dielectric material portion 127 contacts within the annular top surface of the laterally protruding annular portion of the first contact via structure 86A that fills the annular recess underlying the first tubular dielectric material portion 127.

[0146] In one embodiment, the memory device further includes a second support and contact assembly 480 that vertically extends through the first layer of alternating stacks (132, 146) and the second layer of alternating stacks (232, 246). The second support and contact assembly 480 includes: a second contact via structure 86B that contacts the annular top surface of the second reference conductive layer 246 and has a top surface in a horizontal plane that includes the topmost surface of the second layer of alternating stacks (232, 246), the second reference conductive layer being one of the second conductive layers 246 in the second layer of alternating stacks (232, 246); and a second dielectric pillar structure 420 that underlies and contacts the second contact via structure 86B and extends into the substrate 9.

[0147] In one embodiment, the second dielectric pillar structure 420 includes second laterally protruding fin portions 420FF that protrude outwardly at each level of the first conductive layer 146. In one embodiment, the second dielectric pillar structure 420 further includes at least one additional laterally protruding fin portion 420SF that protrudes outwardly at each level of a first subset of the second conductive layers 246 that underlie the second reference conductive layer 246.

[0148] In one embodiment, the second dielectric pillar structure 420 includes: a first dielectric liner 122 that vertically extends through each layer within the first layer alternating stack (132, 146); a first dielectric material layer 124 that is laterally surrounded by the first dielectric liner 122 and includes a vertically extending portion and a laterally extending annular portion, the vertically extending portion vertically extending through each layer within the first layer alternating stack (132, 146), the laterally extending annular portions including portions of the fin-like portion 420FF and laterally protruding outward from the vertically extending portion at each level of the first conductive layer 146; a first dielectric fill material portion 126 that is laterally surrounded by the first dielectric liner 122; an additional dielectric liner 422 (i.e., an internal dielectric liner 422) that vertically extends from the bottom surface of the second contact via structure 86B into a volume located within the first dielectric fill material portion 126 and has a bottom surface below a horizontal plane including the topmost surface of the first layer alternating stack (132, 146).

[0149] In one embodiment, the first support and contact assembly 380 has no air gap 129 in the first dielectric pillar structure 320, while the second support and contact assembly 480 includes an air gap 129 in the second dielectric pillar structure 420.

[0150] Various embodiments of the present disclosure can be used to provide a three-dimensional memory device including support and contact assemblies (380, 480). Each of the support and contact assemblies (380, 480) includes a corresponding contact via structure 86 and a corresponding dielectric pillar structure (320 or 420) that provide structural support throughout the manufacturing process and after forming the contact via structure 86. The dielectric pillar structures (320, 420) are formed below the corresponding contact via structures 86. Thus, the sides of the corresponding contact via structures 86 do not contact the sidewalls of the dielectric pillar structures (320, 420) that are vertically spaced apart from the contact via structures 86, or the sidewalls of the support pillar structure 20 that are laterally spaced apart from the contact via structures 86. This lack of sidewall contact prevents or reduces undesired asymmetrically shaped contact via structures 86, which in turn reduces defects and open circuits. Additionally, the combined dielectric pillar structures (320, 420) and support pillar structure 20 have a high density, which prevents or reduces pattern collapse during replacement of the sacrificial material layer with a conductive layer.

[0151] Although specific preferred embodiments have been mentioned previously, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including". In the case where embodiments employing a particular structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A memory device, the memory device comprising: A first insulating layer and a first layer of a first conductive layer stacked alternately, the first layer of alternating stack being located above a substrate; A second insulating layer and a second layer of a second conductive layer stacked alternately, the second layer of alternating stack being overlaid on the first layer of alternating stack; A memory opening, the memory opening extending vertically through the first layer of alternating stack and the second layer of alternating stack; A memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical semiconductor channel and a vertical stack of memory elements; And A first support and contact assembly, the first support and contact assembly extending vertically through the first layer of alternating stack and the second layer of alternating stack, and comprising: A first contact via structure, the first contact via structure contacting a circular top surface of a first reference conductive layer and having a top surface above a horizontal plane including the topmost surface of the second layer of alternating stack, the first reference conductive layer being one of the first conductive layers in the first layer of alternating stack; A first dielectric pillar structure, the first dielectric pillar structure having at least one first laterally protruding fin portion protruding outwardly at each level of a first subset of the first conductive layer underlying the first reference conductive layer; and A first layer of dielectric spacers, the first layer of dielectric spacers laterally surrounding the first contact via structure, not in direct contact with the first dielectric pillar structure, and extending vertically through each first conductive layer in a second subset of the first conductive layer overlying the first reference conductive layer.

2. The memory device according to claim 1, the memory device further comprising a second layer of dielectric spacers, the second layer of dielectric spacers laterally surrounding the first contact via structure and contacting each second conductive layer in the second conductive layer.

3. The memory device according to claim 2, wherein: The second layer of dielectric spacers is not in direct contact with the first layer of dielectric spacers; and The second layer of dielectric spacers includes an annular bottom surface contacting a top surface of the bottommost second insulating layer in the second insulating layer.

4. The memory device according to claim 2, wherein: The first layer of dielectric spacers includes at least one first laterally protruding fin portion protruding outwardly at each level of the second subset of the first conductive layer; and The second layer of dielectric spacers includes at least one first laterally protruding fin portion protruding outwardly at each level of the second conductive layer.

5. The memory device according to claim 1, wherein a topmost surface of the first layer of dielectric spacers contacts a bottom surface of the bottommost second insulating layer in the second insulating layer.

6. The memory device according to claim 1, wherein the first dielectric pillar structure includes: A pillar dielectric liner, the pillar dielectric liner extending vertically through each first conductive layer in the first subset of the first conductive layer; And A columnar dielectric material layer, the columnar dielectric material layer being laterally surrounded by the columnar dielectric liner and including a vertically extending portion that vertically extends from the first contact via structure into a portion of the substrate underlying the first layer of alternating stacks; and A first dielectric fill material portion, the first dielectric fill material portion being laterally surrounded by the columnar dielectric material layer.

7. The memory device according to claim 6, wherein the first layer of dielectric spacers includes: A first dielectric liner that contacts each of the first conductive layers within the second subset of the first conductive layer; and A first dielectric material layer, the first dielectric material layer being laterally surrounded by the first dielectric liner and including a vertically extending portion that extends through each of the first conductive layers within the second subset of the first conductive layer; and A first tubular dielectric material portion that laterally surrounds the first dielectric material layer and contacts a section of the cylindrical sidewall of the first contact via structure.

8. The memory device according to claim 7, wherein the first tubular dielectric material portion contacts within the annular top surface of the laterally protruding annular portion of the first contact via structure.

9. The memory device according to claim 1, the memory device further comprising a second support and contact assembly that vertically extends through the first layer of alternating stacks and the second layer of alternating stacks, and includes: A second contact via structure that contacts the annular top surface of a second reference conductive layer and has a top surface within the horizontal plane including the topmost surface of the second layer of alternating stacks, the second reference conductive layer being one of the second conductive layers within the second layer of alternating stacks; and A second dielectric column structure that underlies and contacts the second contact via structure and extends into the substrate.

10. The memory device according to claim 9, wherein: The first dielectric column structure has no air gap, while the second dielectric column structure includes an air gap; The second dielectric column structure includes: a second laterally protruding fin portion that protrudes outwardly at each level of the first conductive layer; and At least one additional laterally protruding fin portion that protrudes outwardly at each level of a first subset of the second conductive layer underlying the second reference conductive layer.

11. The memory device according to claim 9, wherein the second dielectric column structure includes: A first dielectric liner that vertically extends through each layer within the first layer of alternating stacks; A first dielectric material layer, the first dielectric material layer being laterally surrounded by the first dielectric liner and including a vertically extending portion and a laterally extending annular portion, the vertically extending portion vertically extends through each layer within the first layer of alternating stacks, the laterally extending annular portion laterally protrudes outwardly from the vertically extending portion at each level of the first conductive layer; A first dielectric fill material portion, the first dielectric fill material portion being laterally surrounded by the first dielectric liner; An additional dielectric liner, the additional dielectric liner vertically extending from a bottom surface of the second contact via structure into a volume within the first dielectric fill material portion and having a bottom surface below a horizontal plane including a topmost surface of the first layer of alternating stacks.

12. A memory device, the memory device comprising: A first layer of alternating stacks of a first insulating layer and a first conductive layer, the first layer of alternating stacks being located above a substrate; A second layer of alternating stacks of a second insulating layer and a second conductive layer, the second layer of alternating stacks being overlying the first layer of alternating stacks; A memory opening, the memory opening vertically extending through the first layer of alternating stacks and the second layer of alternating stacks; A memory opening fill structure, the memory opening fill structure being located in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical semiconductor channel and a vertical stack of memory elements; A first support and contact assembly, the first support and contact assembly vertically extending through the first layer of alternating stacks and the second layer of alternating stacks and including: A first contact via structure, the first contact via structure contacting an annular top surface of a first reference conductive layer, the first reference conductive layer being one of the first conductive layers in the first layer of alternating stacks; and A first dielectric pillar structure, the first dielectric pillar structure underlying the first contact via structure, wherein there is no air gap in the first dielectric pillar structure; and A second support and contact assembly, the second support and contact assembly vertically extending through the first layer of alternating stacks and the second layer of alternating stacks and including: A second contact via structure, the second contact via structure contacting an annular top surface of a second reference conductive layer, the second reference conductive layer being one of the second conductive layers in the second layer of alternating stacks; and A second dielectric pillar structure, the second dielectric pillar structure underlying the second contact via structure, wherein an air gap is included in the second dielectric pillar structure.

13. The memory device according to claim 12, wherein: The first dielectric pillar structure has at least one first laterally protruding fin portion protruding outwardly at each level of a first subset of the first conductive layer underlying the first reference conductive layer; And The second dielectric pillar structure has at least one second laterally protruding fin portion protruding outwardly at each level of a first subset of the second conductive layer underlying the second reference conductive layer.

14. The memory device according to claim 12, wherein: The first support and contact assembly further includes a first layer dielectric spacer and a second layer dielectric spacer, the first layer dielectric spacer and the second layer dielectric spacer laterally surrounding the first contact via structure at corresponding levels of the first conductive layer and the second conductive layer; The first layer of dielectric spacers includes at least one first laterally protruding fin portion protruding outwardly at each level of a second subset of the first conductive layer that overlies the reference first conductive layer; and The second layer of dielectric spacers includes at least one first laterally protruding fin portion protruding outwardly at each level of the second conductive layer.

15. A method of forming a memory device, the method comprising: Forming a first alternating stack of a first insulating layer and a first sacrificial material layer over a substrate; Forming first layer vias cavities in the first alternating stack; Vertically extending a central region of the first layer vias cavities into an upper portion of the substrate without vertically extending a peripheral region of the first layer vias cavities; Partially filling the first layer vias cavities with a first dielectric layer stack and a first sacrificial via fill material; Forming a second alternating stack of a second insulating layer and a second sacrificial material layer over the first alternating stack; Forming second layer vias cavities through each of the second sacrificial material layers of the second alternating stack; Partially filling the second layer vias cavities with a second dielectric layer stack and a second sacrificial via fill material; Replacing the first sacrificial material layer and the second sacrificial material layer with a conductive layer and a second conductive layer, respectively; Forming contact vias cavities by removing the second sacrificial via fill material portion and the first sacrificial via fill material portion; Physically exposing an annular top surface section of a reference level conductive layer, which is one of the conductive layers, by removing an annular portion of the first dielectric layer stack; And Forming a first contact via structure in the contact vias cavities.

16. The method according to claim 15, the method further comprising: Forming a first sacrificial spacer material layer in the first layer vias cavities; And Anisotropically etching the first sacrificial spacer material layer by performing a first anisotropic etching process, wherein a tubular portion of the first sacrificial spacer material layer remains in the peripheral region of the first layer vias cavities, and a central portion of the first sacrificial spacer material layer is etched through by the anisotropic etching process, and the anisotropic etching process etches a portion of the first alternating stack underlying the first layer vias cavities and not covered by the tubular portion of the first sacrificial spacer material layer.

17. The method according to claim 16, the method further comprising: Removing the tubular portion of the first sacrificial spacer material layer after the anisotropic etching process; And Laterally recessing sidewalls of the first sacrificial material layer around the first layer vias cavities relative to sidewalls of the first insulating layer before forming the first dielectric layer stack and the first sacrificial via fill material portion.

18. The method according to claim 15, wherein a remaining portion of the first dielectric layer stack after removing the annular portion of the first dielectric layer stack includes: A first dielectric pillar structure underlying the contact vias cavities; And A first dielectric spacer that laterally surrounds the first contact via structure and does not directly contact the first dielectric pillar structure.

19. The method according to claim 15, the method further comprising: Forming additional first via cavities through each first sacrificial material layer in the first alternating stack; Vertically extending a central region of the additional first via cavities into the substrate without vertically extending a peripheral region of the additional first via cavities; Partially filling the additional first via cavities with an additional first dielectric layer stack and an additional first sacrificial via fill material; Forming additional second via cavities in the second alternating stack; Vertically extending a central region of the additional second via cavities into the additional first sacrificial via fill material without vertically extending a peripheral region of the additional second via cavities; Partially filling the additional second via cavities with an additional second dielectric layer stack and an additional second sacrificial via fill material; Forming additional contact via cavities by removing the additional second sacrificial via fill material portion and the additional first sacrificial via fill material portion; Physically exposing an annular top surface section of a second reference conductive layer, which is one of the second conductive layers in the second conductive layer, by removing an annular portion of the additional second dielectric layer stack; And Forming a second contact via structure in the additional contact via cavities.

20. The method according to claim 19, the method further comprising selectively removing the additional first sacrificial via fill material portion for the additional first dielectric layer stack after vertically extending the central region of the additional second via cavities, wherein the additional second dielectric layer stack is deposited in a cavity formed by removing the additional first sacrificial via fill material portion.

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