3D NAND hybrid word line contact and through array via region

Abstract

Systems, apparatuses, and methods may provide techniques to arrange a word line access structure of a memory device. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a plurality of word lines through a plurality of stacks of non-volatile memory structures. A plurality of through array vias pass through the plurality of stacks, wherein the plurality of through array vias and the plurality of word lines are mixed in a shared word line access structure region. Additionally or alternatively, multi-level through-vias are formed through a plurality of stacks of non-volatile memory structures of a memory device based on word line contact patterning, based on which the memory device is fabricated. And depositing a metal thin film to fill the through holes so as to form word line contacts.

Description

Technical Field

[0001] Embodiments generally relate to memory structures. More particularly, embodiments relate to the layout of word line contacts and through array vias used in 3D NAND memory structures. Background Art

[0002] NAND-type flash memory (“NAND memory”) can be organized into multiple cells, where each cell contains one or more data bits and can be accessed through an array of bit lines (columns) and word lines (rows). As the number of levels or word lines (WLs) increases in each generation of 3D NAND, the number of WL contacts also increases, requiring more wiring paths to connect the word line contacts to the corresponding string driver complementary metal oxide semiconductor (CMOS) devices. Brief Description of the Drawings

[0003] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and the appended claims, and by referring to the following drawings, in which:

[0004] Figure 1 is a block diagram of an example of an existing multi-stack non-volatile memory device;

[0005] Figure 2 shows an example side view of a memory die according to an embodiment;

[0006] Figure 3 is a block diagram of an example existing memory device having a sequential stepped structure;

[0007] Figure 4 is a block diagram of another example existing memory device having a parallel stepped structure;

[0008] Figures 5A - 5B is a comparison of an existing word line contact formation ( Figure 5A ) with an example word line contact formation according to an embodiment ( Figure 5B ) in a cross-sectional view;

[0009] Figure 6 is a cross-sectional view of a multi-level word line contact patterning according to an embodiment;

[0010] Figures 7A - 7B is a comparison of an existing word line contact formation ( Figure 7A ) with an example word line contact formation according to an embodiment ( Figure 7B ) in a top view and a cross-sectional view;

[0011] Figure 8 is a flowchart of an example of another method of forming a memory device according to an embodiment;

[0012] Figure 9 is an illustration of an example of a semiconductor packaging device according to an embodiment; and

[0013] Figure 10 is a block diagram of an example of a performance-enhanced computing system according to an embodiment. Detailed Description

[0014] As described above, a NAND-type flash memory (“NAND memory”) can be organized into multiple cells, where each cell contains one or more data bits and can be accessed through an array of bit lines (columns) and word lines (rows). A 3D NAND memory has vertical channels (column shape) and horizontal WLs (plate shape) in the cell array. Each word line (WL) is connected to a WL driver through a WL contact. As the number of levels or word lines (WLs) increases in each generation of 3D NAND, the number of word line contacts also increases, and more wiring paths are needed to connect the word line contacts to the corresponding string driver complementary metal oxide semiconductor (CMOS) devices.

[0015] Some existing WL contact formation methods generally include step (SC) formation, oxide gap filling and chemical mechanical polishing (CMP), WL contact patterning and metal filling, and additional chemical mechanical polishing (CMP). This is a long process involving many process steps. Therefore, in 3D NAND memory manufacturing, the production cost of WL contact formation is very high. For this problem, there is no known good solution. Existing 3D NAND products generally have a common WL contact formation method, namely the step process. Unfortunately, because the number of steps and processing time increase with the increase in the number of levels, the production cost of this step also continues to expand.

[0016] Some existing WL contact formation methods generally include placing WL contacts on a pre-formed step. Each WL is usually only connected to a designated WL and kept at a sufficient distance from other WLs to avoid short circuits. However, due to process variations (e.g., etch bias, interlayer coverage error, cumulative process error during trimming / etching, etc.), in the existing step (SC) process, the WL contacts may be too close to other WLs, resulting in dielectric breakdown of the insulator between them. Therefore, in the existing step (SC) process, such a short circuit between the WL contacts and WLs will have a negative impact on yield loss.

[0017] Unfortunately, in the existing stepped (SC) process, word line (WL) contacts and through-array vias (TAVs) are typically located in different regions. The WL contacts are formed in the SC, and the TAVs will be formed outside the SC. Those WL contacts and TAVs should be connected through a metal layer above the array. As the number of WLs increases, the metal wiring may become more crowded and the challenge also increases. In the existing stepped (SC) process, this is one of the limitations of the placement of WL contacts and TAVs in WL connections, with lower layout flexibility and making die scaling more challenging.

[0018] Unfortunately, in the existing stepped process, increasing the space between WL contacts typically increases the die size, thereby reducing the likelihood of a short circuit occurring between the WL contacts and the WLs. Additionally, in the existing stepped process, any attempt to randomly distribute WL contacts will occupy a large area, thereby significantly increasing the die size.

[0019] As will be described in more detail below, the systems, devices, and methods described herein can provide techniques for arranging the word line access structure of a memory device. In some examples, the memory device includes a memory array and a memory block coupled to the memory array. The memory block includes multiple word lines passing through multiple stacks of a non-volatile memory structure. Multiple through-array vias pass through the multiple stacks, wherein the multiple through-array vias and the multiple word lines are mixed in a shared word line access structure region. Additionally or alternatively, based on word line contact patterning, multi-level vias are formed through multiple stacks of the non-volatile memory structure of the memory device, and then the memory device is fabricated based on this. A metal thin film is deposited and the vias are filled to form word line contacts.

[0020] Some embodiments described herein provide a word line contact structure that is significantly different from existing solutions. For example, as will be described in more detail below, some embodiments described herein provide a WL contact structure with a direct contact from the top of the array to each word line without a stepped structure. Thus, each via can directly land on each word line without forming a stepped structure.

[0021] Advantageously, some embodiments described herein provide cost effectiveness due to fewer process steps required. This structure does not result in production losses due to short circuits between WL contacts and WLs during the process formation. Additionally, some embodiments described herein provide complete WL contact layout flexibility, where the WL contact positions can be defined by mask layout (e.g., rather than by a stepped formation process as in existing processes).

[0022] Figure 1FIG. 0 is a block diagram of an example of a conventional multi-stack non-volatile memory device 100. As shown, the memory device 100 is a multi-stack non-volatile memory device that includes a thin film stack 101 (e.g., which may be formed as one or more multi-stack memory architectures, multi-layer memory architectures, etc., or combinations thereof).

[0023] In some embodiments, the thin film stack 101 may include an array of memory cells 102 having conductive access lines (e.g., word lines 110 and bit lines 112). For example, the memory cells 102 may include materials capable of being in two or more stable states to store logical values.

[0024] In the example shown, a stepped structure 120 is utilized. However, as will be described in more detail below, in some embodiments described herein, such stepped structure 120 may be dispensed with.

[0025] Examples of multi-stack or multi-layer memory architectures include multi-stack memories and 3D NAND memories. Different memory technologies use different terms. For example, in some memory devices, a stack typically refers to a stack of one layer of memory cells that can be individually addressed. In contrast, 3D NAND memory devices are generally considered to include NAND arrays that include many layers rather than stacks. In 3D NAND, a stack may refer to a subset of memory cell layers (e.g., a stack of two X layers effectively provides a 2X layer NAND device). The term "stack" will be used in this disclosure to describe layers, levels, or similar portions of three-dimensional memories.

[0026] The memory device 100 may include non-volatile memory and / or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the data state stored in the medium. In one embodiment, the memory structure is a block-addressable storage device, such as those based on NAND technology. The storage device may also include next-generation non-volatile devices.

[0027] As will be described in more detail below, the systems, devices, and methods of some embodiments herein provide techniques for arranging the word line access structure of a memory device.

[0028] Figure 2 A simplified example side view of a memory die 200 according to an embodiment of the present disclosure is shown. According to one embodiment, the memory die 200 includes a 3D flash memory architecture and utilizes word line bridges to share the word line access structure between two tiles of a memory array.

[0029] According to one embodiment, the memory die 200 includes a memory array 202 and peripheral circuitry 204. According to one embodiment, the memory array 202 includes memory cells 205 and 206 that are accessed (e.g., read / written) using the peripheral circuitry 204. According to one embodiment, the peripheral circuitry 204 is fabricated in the memory die 200 at least partially under the memory array 202, e.g., using under-array CMOS fabrication techniques.

[0030] According to one embodiment, the memory array 202 is divided into a first tile 208 and a second tile 210. Although two tiles are shown and described, according to one embodiment, the memory array 202 can be divided into dozens or hundreds of tiles to facilitate access and operation of the memory array 202. According to one embodiment, the first tile 208 includes a memory block 212 that includes the memory cells 205 and a word-line access structure 218. According to one embodiment, the word-line access structure 218 includes a through-array via 220 and a word-line contact 222. According to one embodiment, the through-array via 220 connects the word line of the memory cell 205 to the peripheral circuitry 204 under the memory array 202. According to one embodiment, the word-line contact 222 connects the word line of the memory cell 205 to a metal contact for connection to an upper metal level. For illustrative purposes, the word-line access structure 218 is shown disproportionately large compared to the memory cell 205. In reality, according to one embodiment, the memory cell 205 can occupy a much larger area in the memory array than the word-line access structure 218.

[0031] According to one embodiment, the second tile 210 includes a memory block 224 that includes the memory cells 206 and a word-line access structure 226. According to one embodiment, the word-line access structure 226 includes a through-array via 228 and a word-line contact 230. According to one embodiment, the through-array via 228 passes through the memory block 224 to couple the upper metal level to the peripheral circuitry 204. According to one embodiment, the word-line contact 230 provides a platform and / or structure such that a metal contact connects the word line of the memory cell 206 to the upper metal level located at or above the top of the memory array 202.

[0032] According to one embodiment, the peripheral circuitry 204 includes a word-line driver 234 and a bit-line driver 236 for driving the word lines and bit lines of the memory array 202.

[0033] Figure 3It is a block diagram of an example existing memory device 300 having a continuous stepped structure. As shown, the existing memory device 30 typically has one or more stepped wells for each memory block. Additionally, word line contacts typically fall on each stack (e.g., all three stacks in some embodiments). Further, the stepped wells and the through-array vias (TAVs) are placed in continuous positions.

[0034] As shown, the existing memory device 300 includes a memory array 302 and a memory block 304 coupled to the memory array 302. Each memory block (e.g., memory block 304 and memory block 324) is typically limited to a total of two stepped wells per memory block (e.g., stepped wells 310 / 312 of memory block 304 and stepped wells 320 / 322 of memory block 324).

[0035] A plurality of metal routings 334 individually connect a plurality of word line contacts 332 to a plurality of string driver contacts 330. As shown, individual stepped wells typically have word line contacts 332 falling on each stack (e.g., all three stacks in some embodiments). Further, the stepped wells and the through-array vias (e.g., TAV 306) are placed in continuous positions (e.g., where the stepped wells are interspersed between each pair of sequential TAVs).

[0036] Figure 4 It is a block diagram of another example existing memory device 400 having a parallel stepped structure. As shown, the existing memory device 400 differs from the existing memory device 300 in several aspects. The existing memory device 400 typically includes more than two stepped wells (e.g., three stepped wells in the shown example). Additionally, the plurality of stepped wells have word line contacts falling on only one stack (e.g., one stepped well per stack). Further, the stepped wells and the through-array vias (TAVs) are placed side by side in parallel positions.

[0037] As shown, the existing memory device 400 typically includes a memory array 402 and a memory block 404 coupled to the memory array 402.

[0038] The existing memory block typically includes a first through-array via region 406 and a first stepped region 408. The first stepped region 408 is coupled to a plurality of stacks (e.g., Figure 1 stack 0, stack 1, etc.) of, and is positioned adjacent to the first through-array via region 406.

[0039] The first stepped region 408 includes a first stepped well 410 and a second stepped well 412 positioned continuously with the first stepped well 410. In some embodiments, the first stepped region 408 includes a third stepped well 414 positioned continuously with the first stepped well 410 and the second stepped well 412.

[0040] The first stepped well 410 is typically only coupled to the first of the plurality of stacked groups (e.g., Figure 1 stacked group 0). In such examples, the second stepped well 412 is only coupled to the second of the plurality of stacked groups (e.g., Figure 1 stacked group 1). The second stepped well 412 is different from the first stepped well 410, and the second of the plurality of stacked groups (e.g., Figure 1 stacked group 1) is different from the first of the plurality of stacked groups (e.g., Figure 1 stacked group 0).

[0041] An existing memory device 400 typically includes a second memory block 424 coupled to a memory array 402. The second memory block 424 includes a second through-array via region 426 and a second stepped region 428. In such examples, the second stepped region 428 is coupled to the plurality of stacked groups (e.g., Figure 1 stacked group 0, stacked group 1, etc.), and is positioned adjacent to the second through-array via region 426.

[0042] The first stepped region 408 and the second stepped region 428, and the first through-array via region 406 and the second through-array via region 426 can form a sandwich structure. Such a sandwich structure positions the first stepped region 408 and the second stepped region 428 outside the sandwich, and positions the first through-array via region 406 and the second through-array via region 426 adjacent to each other inside the sandwich.

[0043] Similarly, the first stepped region 408 and the second stepped region 428, and the first through-array via region 406 and the second through-array via region 426 can extend parallel to each other and perpendicular to the memory array 402.

[0044] The first through-array via region 406 typically includes a plurality of string driver contacts 430, and the first stepped region 408 includes a plurality of word line contacts 432. In such examples, a plurality of metal routings 434 individually connect the plurality of word line contacts 432 to the plurality of string driver contacts 430. As shown, the plurality of metal routings 434 extend parallel to the memory array 402.

[0045] Figures 5A - 5B is a cross-sectional view comparing the existing word line contact formation ( Figure 5A ) of a multi-stacked group non-volatile memory structure 500 with the example word line contact formation ( Figure 5B ) of an example multi-stacked group non-volatile memory structure 550 according to an embodiment.

[0046] Refer to Figure 5A, in the existing process, a thin film stack of the multi-stack non-volatile memory structure 500 is formed by depositing multiple oxide / polysilicon (OPOP) thin layers and so on. According to the WL contact formation process, the OPOP layer will be removed, and the top of the polysilicon layer of each word line (WL) will be exposed (b). This formation process generally includes multiple OPOP layer etching and resist trimming sequences (for example, the step formation process). Then, the step area will be filled with oxide and planarized by CMP (c). Next, word line (WL) contact patterning (d) and metal filling (e) are performed.

[0047] Referring to FIG. 5b, according to an embodiment, a thin film stack 552 of an exemplary multi-stack non-volatile memory structure 550 is formed in a similar manner by depositing multiple oxide / polysilicon (OPOP) thin layers and so on. Conversely, the exemplary process disclosed herein for the exemplary multi-stack non-volatile memory structure 550 does not have a step formation operation (b), nor an oxide filling operation or a CMP operation (c). Through holes 554 having a diameter of approximately 300 to 2000 nm will be formed in the OPOP layer, and each hole will terminate at each polysilicon word line. Then, a metal thin film 556 will be deposited to fill the through holes 554, and then CMP will be performed to remove the residual metal. Compared with the existing step process, removing the oxide filling and CMP processes helps to reduce the cost of the embodiments described herein.

[0048] Additional details regarding various embodiments of the exemplary multi-stack non-volatile memory structure 550 are described below with respect to Figure 6 and 7B discussed.

[0049] Figure 6 is a cross-sectional view of a multi-level word line contact patterning for an exemplary multi-stack non-volatile memory structure 650 according to an embodiment. As shown, a multi-mask patterning process can be performed to form multi-level through holes 654. For example, in each mask stage of the multi-mask patterning process, the multi-mask pattern can cover different parts of the word line cavity 655.

[0050] In some embodiments, the multi-mask patterning process further includes forming a first process resist, a second process resist, a third process resist, etc. For example, such a first process resist can include forming a first process resist 660 to cover the first half of the word line cavity, where the first process resist has a first pattern that only covers every other word line cavity; etching the first uncovered half of the word line cavity; and removing the first process resist.

[0051] Additionally or alternatively, such a second process resist 662 may include forming a second process resist to cover a second half of the word line cavity, wherein the second process resist has a second pattern that covers only every third word line cavity; etching the second uncovered half of the word line cavity; and removing the second process resist.

[0052] Additionally or alternatively, such a third process resist 664 may include forming a third process resist to cover a third half of the word line cavity, wherein the third process resist has a third pattern that covers only every third word line cavity; etching the third uncovered half of the word line cavity; and removing the third process resist.

[0053] In operation, in the WL contact patterning step (e.g., see Figure 5B step (d)), in some embodiments, multiple masks are introduced to process multi-level vias. Figure 6 An example of forming WL0 - WL7 contacts is shown. First, a hard mask is deposited on top of the OPOP layer, and then circular patterns are etched in the hard mask, for example, using photolithography and reactive ion etching (RIE). Each circular pattern on the hard mask will become a corresponding WL contact. Then, a 1-layer process resist will cover half of the WL contact, and the other half of the WL contact will be processed by 1-layer etching. For example, this 1-layer etching can be performed by etch termination detection or precise time control etching under highly selective conditions. Then, the resist is removed by dry or wet processing. Similarly, 2-layer and 4-layer processes can be employed. In the example shown, after a multi-mask patterning process (e.g., 1-layer, 2-layer, 4-layer, etc.), 8 WL contacts (WL0 - WL7) are formed. Generally, N (N = 1, 2, 3,...) masks are required to form 2N or fewer WL contacts. For example, to form 100 WL contacts for 100 WL layers, this photolithography and etching process can be repeated 7 times.

[0054] Additional details regarding various embodiments of the example multi-stack non-volatile memory structure 650 are discussed below with respect to Figure 7B discussed.

[0055] Figures 7A - 7B is a top view and cross-section comparing the formation of existing word line contacts of an existing multi-stack non-volatile memory structure 700 ( Figure 7A ) with the formation of example word line contacts of an example multi-stack non-volatile memory structure 750 according to an embodiment ( Figure 7B ).

[0056] Refer to Figure 7B, in some embodiments, the memory block 752 includes multiple word line contacts 756 that pass through multiple stacks of the exemplary multi-stack non-volatile memory structure 750. Additionally or alternatively, multiple through-array vias 770 pass through the multiple stacks, where the multiple through-array vias 770 and the multiple word lines 756 are mixed in a shared word line access structure region 780.

[0057] In some examples, the multiple through-array vias 770 and the multiple word lines 756 are mixed such that a first word line among the multiple word lines 756 is located between a first through-array via among the through-array vias 770 and a second through-array via among the through-array vias 770 in the shared word line access structure region 780.

[0058] Additionally or alternatively, the multiple through-array vias 770 and the multiple word lines 756 are mixed such that a first row among the multiple word lines 756 is located between a first row among the through-array vias 770 and a second row among the through-array vias 770 in the shared word line access structure region 780.

[0059] In some embodiments, the multiple word lines 756 pass through the multiple stacks in a variable-depth pattern (e.g., a V-shaped depth pattern, etc., as shown herein), while the multiple through-array vias 770 pass through the multiple stacks at a common depth.

[0060] In operation, a sidewall process is performed on the word line (WL) contact holes. After hole reactive ion etching (RIE), Si oxide (or the like) will be deposited on the bottom and sidewalls of the holes, and then the bottom oxide will be removed by a subsequent RIE (e.g., in a penetration step). Then, metal for the word line contacts is filled. The Si oxide sidewalls will act as an insulating material between the WL contacts and other WLs and are generally not affected by variations in the oxide thickness. Therefore, as long as the thickness of the oxide film is sufficient to prevent WL-WL short circuits and sufficient to control oxide thickness fluctuations, this structure can be immune to WL-WL short circuits.

[0061] Conversely, referring to Figure 7A , a typical ladder-based layout of an existing multi-stack non-volatile memory structure 700 is shown. As shown, the WL contacts are formed in the ladder region, and the TAVs are physically separated from the WL contacts in a separate region. The separation of the WL contacts and the TAVs generally makes the metal wiring between them challenging. Since the embodiments described herein may not form a ladder structure, the WL contacts can be placed anywhere in the WL connection region, as Figure 7B shown.

[0062] Figure 8is a flowchart of an example of a method 800 for forming a memory device according to an embodiment. The method 800 can generally be implemented to form a memory device, such as the memory device 550( Figure 5B ) that has been discussed, the memory device 650( Figure 6 ), and the memory device 750( Figure 7B ).

[0063] The illustrated processing block 802 is for depositing a hard mask on a plurality of stacks of a non-volatile memory structure. For example, depositing such a hard mask can be performed before forming multi-level vias, as will be described in more detail below.

[0064] The illustrated processing block 804 is for engraving a word line cavity in the hard mask. For example, a word line cavity can be engraved in the hard mask to correspond to a position for forming a desired word line contact.

[0065] The illustrated processing block 806 is for performing a multi-mask patterning process to form multi-level vias. For example, the multi-mask pattern can cover different portions of the word line cavity at each mask stage of the multi-mask patterning process. In some examples, the multi-mask patterning process further includes performing the multi-mask patterning process for an iteration number determined by the number of word lines to be accessed. For example, additional process resist formation and etching will be repeated until all word lines are reached. Generally, forming 2N or fewer WL contacts requires N (N = 1, 2, 3,...) masks. For example, to form 100 WL contacts for 100 WL layers, this lithography and etching process can be repeated 7 times.

[0066] In some embodiments, the multi-mask patterning process further includes forming a first process resist, a second process resist, and a third process resist, etc. For example, such a first process resist can include forming a first process resist to cover a first half of the word line cavity, where the first process resist has a first pattern that covers only every other word line cavity; etching the first uncovered half of the word line cavity; and removing the first process resist.

[0067] Additionally or alternatively, such a second process resist can include forming a second process resist to cover a second half of the word line cavity, where the second process resist has a second pattern that covers only every third word line cavity; etching the second uncovered half of the word line cavity; and removing the second process resist.

[0068] Additionally or alternatively, such a third process resist can include forming a third process resist to cover a third half of the word line cavity, where the third process resist has a third pattern that covers only every third word line cavity; etching the third uncovered half of the word line cavity; and removing the third process resist.

[0069] The processing block 808 shown is used to deposit an insulating liner in the multi-level vias. For example, depositing such an insulating liner in the multi-level vias can be performed before depositing a metal thin film to fill the vias.

[0070] The processing block 810 shown is used to remove the bottom portion of the insulating liner.

[0071] The processing block 812 shown is used to deposit a metal thin film to fill the vias, thereby forming word line contacts.

[0072] The processing block 814 shown is used to remove the residual metal thin film of the deposited metal thin film.

[0073] The processing block 816 shown is used to form a plurality of through-array vias passing through the plurality of stacks. For example, the plurality of through-array vias and the word line contacts can be mixed in the shared word line access structure region.

[0074] For example, the plurality of through-array vias and the word line contacts are mixed such that the first word line of the word line contacts is located between the first through-array via and the second through-array via in the through-array vias in the shared word line access structure region.

[0075] Additionally or alternatively, the plurality of through-array vias and the word line contacts are mixed such that the first row in the word line contacts is located between the first row and the second row in the through-array vias in the shared word line access structure region.

[0076] Additional details regarding various embodiments of method 800 are discussed below with regard to Figure 9 and 10 discussed.

[0077] Figure 9 A semiconductor device 900 (e.g., a chip, die, and / or package) is shown. The device 900 shown includes one or more substrates 902 (e.g., silicon, sapphire, gallium arsenide) and logic 904 (e.g., a transistor array and other integrated circuit / IC components) coupled to the substrate 902. In an embodiment, the logic 904 implements one or more aspects of the memory device 550 ( Figure 5B ), the memory device 650 ( Figure 6 ), the memory device 750 ( Figure 7B ) that have been discussed.

[0078] In one example, the logic 904 includes transistor channel regions positioned (e.g., embedded) within the substrate 902. Thus, the interface between the logic 904 and the substrate 902 may not be a abrupt junction. The logic 904 can also be considered to include an epitaxial layer grown on the initial wafer of the substrate 902.

[0079] Now turning toFigure 10 , a performance-enhanced computing system 1040 is shown. In the illustrated example, a solid-state drive (SSD) 1042 includes a device controller device 1044 coupled to a NAND 1046. The illustrated NAND 1046 includes a memory device 1048 having a set of multi-level NVM cells and logic 1052 (e.g., transistor arrays and other integrated circuit / IC components, coupled to one or more substrates containing silicon, sapphire, and / or gallium arsenide), and a chip controller device 1050 including logic 1054. The logic 1054 may include one or more of configurable or fixed-function hardware.

[0080] The illustrated system 1040 also includes a system-on-chip (SoC) 1056 having a host processor 1058 (e.g., a central processing unit / CPU) and an input / output (I / O) module 1060. The host processor 1058 may include an integrated memory controller 1062 (IMC) that communicates with system memory 1064 (e.g., a RAM dual in-line memory module / DIMM). The illustrated I / O module 1060 is coupled to the SSD 1042 and other system components, such as a network controller 1066.

[0081] In some embodiments, the NAND 1046 implements one or more aspects of the memory devices 550 ( Figure 5B ), memory devices 650 ( Figure 6 ), memory devices 750 ( Figure 7B ) that have been discussed. For example, the NAND 1046 may be implemented as a multi-stack non-volatile memory structure that includes multiple stacks coupled to a device controller device 1044 (e.g., a memory controller).

[0082] Additional notes and examples:

[0083] Example 1 includes a memory device that includes a memory array and a memory block coupled to the memory array. The memory block includes multiple word lines that pass through multiple stacks of a non-volatile memory structure; and multiple through-array vias that pass through the multiple stacks, where the multiple through-array vias and the multiple word lines are mixed in a shared word line access structure region.

[0084] Example 2 includes the memory device according to Example 1, where the multiple through-array vias and the multiple word lines are mixed such that a first word line among the multiple word lines is located between a first through-array via among the through-array vias and a second through-array via among the through-array vias in the shared word line access structure region.

[0085] Example 3 includes the memory device according to Example 1, wherein the plurality of through-array vias and the plurality of word lines are mixed such that a first row of the plurality of word lines is located between a first row of the through-array vias and a second row of the through-array vias in the shared word line access structure region.

[0086] Example 4 includes the memory device according to any one of Examples 1 to 3, wherein the plurality of word lines pass through the plurality of stacks in a variable depth pattern, while the plurality of through-array vias pass through the plurality of stacks at a common depth.

[0087] Example 5 includes the memory device according to any one of Examples 1 to 4, wherein the shared word line access structure region does not include a 3D NAND ladder structure.

[0088] Example 6 includes the memory device according to any one of Examples 1 to 5, wherein the memory device includes 3D NAND.

[0089] Example 7 includes a system, which includes:

[0090] a memory controller; and

[0091] a multi-stack non-volatile memory structure coupled to the memory controller, the multi-stack non-volatile memory structure including a plurality of stacks, the multi-stack non-volatile memory structure including:

[0092] a plurality of word line contacts passing through the plurality of stacks; and

[0093] a plurality of through-array vias passing through the plurality of stacks, wherein the plurality of through-array vias and the plurality of word line contacts are mixed in a shared word line access structure region.

[0094] Example 8 includes the system according to Example 7, wherein the plurality of through-array vias and the plurality of word line contacts are mixed such that a first word line contact of the plurality of word line contacts is located between a first through-array via of the through-array vias and a second through-array via of the through-array vias in the shared word line access structure region.

[0095] Example 9 includes the system according to Example 7, wherein the plurality of through-array vias and the plurality of word line contacts are mixed such that a first row of the plurality of word line contacts is located between a first row of the through-array vias and a second row of the through-array vias in the shared word line access structure region.

[0096] Example 10 includes the system according to any one of Examples 7 to 9, wherein the plurality of word line contacts pass through the plurality of stacks in a variable depth pattern, while the plurality of through-array vias pass through the plurality of stacks at a common depth.

[0097] Example 11 includes the system according to any one of Examples 7 to 10, wherein the shared word line access structure region does not include a 3D NAND ladder structure.

[0098] Example 12 includes the system according to any one of Examples 7 to 11, wherein the multi-stack non-volatile memory structure includes 3D NAND.

[0099] Example 13 includes a method, which includes: forming multi-level vias through multiple stacks of a non-volatile memory structure of a memory device based on word line contact patterning; and depositing a metal film to fill the vias, thereby forming word line contacts.

[0100] Example 14 includes the method according to Example 13, which further includes: depositing an insulating liner in the multi-level vias before depositing the metal film.

[0101] Example 15 includes the method according to Example 14, which further includes: removing a bottom portion of the insulating liner.

[0102] Example 16 includes the method according to any one of Examples 13 to 15, which further includes: depositing a hard mask on multiple stacks of the non-volatile memory structure before forming the multi-level vias; engraving word line cavities in the hard mask, where the word line cavities correspond to positions for forming the word line contacts; and performing a multi-mask patterning process to form the multi-level vias, wherein the multi-mask patterns cover different portions of the word line cavities in each mask stage of the multi-mask patterning process.

[0103] Example 17 includes the method according to Example 16, wherein the multi-mask patterning process further includes performing the multi-mask patterning process for an iteration number determined by the number of word lines to be accessed, and the multi-mask patterning process further includes: forming a first process resist to cover a first half of the word line cavities, wherein the first process resist has a first pattern that covers only every other word line cavity; etching a first uncovered half of the word line cavities; removing the first process resist; forming a second process resist to cover a second half of the word line cavities, wherein the second process resist has a second pattern that covers only every other pair of word line cavities; etching a second uncovered half of the word line cavities; removing the second process resist; forming a third process resist to cover a third half of the word line cavities, wherein the third process resist has a third pattern that covers only every third word line cavity; etching a third uncovered half of the word line cavities; and removing the third process resist.

[0104] Example 18 includes the method according to any one of Examples 13 to 17, further comprising: forming a plurality of through-array vias through the plurality of stacked groups, wherein the plurality of through-array vias and the word line contacts are mixed in a shared word line access structure region.

[0105] Example 19 includes the method according to Example 18, wherein the plurality of through-array vias and the word line contacts are mixed such that a first word line among the word line contacts is located between a first through-array via among the through-array vias and a second through-array via among the through-array vias in the shared word line access structure region.

[0106] Example 20 includes the method according to Example 18, wherein the plurality of through-array vias and the word line contacts are mixed such that a first row among the word line contacts is located between a first row among the through-array vias and a second row among the through-array vias in the shared word line access structure region.

[0107] Example 21 includes an apparatus comprising means for performing the method according to any one of Examples 13 to 20.

[0108] Example 22 includes a machine-readable storage device comprising machine-readable instructions that, when executed, implement the method according to any one of the preceding claims or realize the apparatus according to any one of the preceding claims.

[0109] The embodiments are suitable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-chip (SoC), SSD / NAND controller ASICs, and the like. Additionally, in some of the figures, signal conductor lines are represented by lines. Some of the figures may be different to indicate more component signal paths, may have digital labels to indicate the number of component signal paths, and / or may have arrows at one or more ends to indicate the primary information flow direction. However, this should not be construed as limiting. Instead, such added details may be used in conjunction with one or more exemplary embodiments to more easily understand the circuitry. Any represented signal line, whether or not it has additional information, may actually include one or more signals that may propagate in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, fiber optic lines, and / or single-ended lines.

[0110] Unless otherwise specifically stated, it should be understood that terms such as "processing", "operating", "calculating", "determining", etc. refer to actions and / or processes in which a computer or a computing system or similar electronic computing device manipulates and / or transforms data represented as physical quantities (e.g., electrons) in the registers and / or memories of the computing system into other data represented as physical quantities in a similar manner in the memories, registers, or other such information storage devices, transmission, or display devices of the computing system. The embodiments are not limited thereto.

[0111] Example dimensions / models / values / ranges may have been given, but the embodiments are not limited thereto. As manufacturing technologies (such as lithography) mature over time, it is expected that devices of smaller dimensions can be manufactured. Additionally, for the sake of simplicity of illustration and discussion, and in order not to obscure certain aspects of the embodiments, well-known power / ground connections of IC chips and other components may or may not be shown in the figures. Further, the arrangements may be shown in block diagram form to avoid obscuring the embodiments, and also in view of the fact that details regarding the implementation of such block diagram arrangements highly depend on the platform within which this embodiment is implemented, i.e., these details should be entirely within the knowledge of those skilled in the art. In cases where specific details (such as circuits) are set forth to describe example embodiments, those skilled in the art should appreciate that the embodiments can be practiced without these specific details or with variations of these specific details. Accordingly, this specification should be regarded as illustrative rather than restrictive.

[0112] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between related components, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, the terms "first", "second", etc. are used herein merely for convenience of discussion and have no particular temporal or chronological significance unless otherwise indicated.

[0113] As used in this application and the claims, a list of items joined by the term "one or more of" can be any combination of the listed terms. For example, the phrase "one or more of A, B, or C" can mean: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0114] Based on the above description, those skilled in the art will appreciate that the broad techniques in the embodiments can be implemented in various forms. Thus, although the embodiments have been described in conjunction with specific examples, the true scope of the embodiments should not be limited thereby, as those skilled in the art will be able to understand other modifications after studying the drawings, the specification, and the appended claims.

Claims

1. A memory device, comprising: A memory array; And A memory block coupled to the memory array, the memory block comprising: Multiple word lines passing through multiple stacks of a non-volatile memory structure; And Multiple through-array vias passing through the multiple stacks, wherein the multiple through-array vias and the multiple word lines are mixed in a shared word line access structure region.

2. The memory device according to claim 1, wherein the multiple through-array vias and the multiple word lines are mixed such that a first word line among the multiple word lines is located between a first through-array via among the through-array vias and a second through-array via among the through-array vias in the shared word line access structure region.

3. The memory device according to claim 1, wherein the multiple through-array vias and the multiple word lines are mixed such that a first row among the multiple word lines is located between a first row among the through-array vias and a second row among the through-array vias in the shared word line access structure region.

4. The memory device according to claim 1, wherein the multiple word lines pass through the multiple stacks in a variable-depth pattern, while the multiple through-array vias pass through the multiple stacks at a common depth.

5. The memory device according to claim 1, wherein the shared word line access structure region does not contain a 3D NAND ladder structure.

6. The memory device according to claim 1, wherein the memory device includes 3D NAND.

7. A system, comprising: A memory controller; And A multi-stack non-volatile memory structure coupled to the memory controller, the multi-stack non-volatile memory structure including multiple stacks, the multi-stack non-volatile memory structure comprising: Multiple word line contacts passing through the multiple stacks; And Multiple through-array vias passing through the multiple stacks, wherein the multiple through-array vias and the multiple word line contacts are mixed in a shared word line access structure region.

8. The system according to claim 7, wherein the multiple through-array vias and the multiple word line contacts are mixed such that a first word line contact among the multiple word line contacts is located between a first through-array via among the through-array vias and a second through-array via among the through-array vias in the shared word line access structure region.

9. The system according to claim 7, wherein the multiple through-array vias and the multiple word line contacts are mixed such that a first row among the multiple word line contacts is located between a first row among the through-array vias and a second row among the through-array vias in the shared word line access structure region.

10. The system according to claim 7, wherein the multiple word line contacts pass through the multiple stacks in a variable-depth pattern, while the multiple through-array vias pass through the multiple stacks at a common depth.

11. The system according to claim 7, wherein the shared word line access structure region does not contain a 3D NAND ladder structure.

12. The system according to claim 7, wherein the multi-stack non-volatile memory structure includes 3D NAND.

13. A method, comprising: Forming a plurality of multi-level vias through a plurality of stacks of a non-volatile memory structure of a memory device based on word line contact patterning; And Depositing a metal thin film to fill the vias, thereby forming word line contacts.

14. The method according to claim 13, further comprising: Depositing an insulating liner in the multi-level vias before depositing the metal thin film.

15. The method according to claim 14, further comprising: Removing a bottom portion of the insulating liner.

16. The method according to claim 13, further comprising: Depositing a hard mask on the plurality of stacks of the non-volatile memory structure before forming the multi-level vias; Etching word line cavities in the hard mask, the word line cavities corresponding to positions for forming the word line contacts; And Performing a multi-mask patterning process to form the multi-level vias, wherein the multi-mask patterns cover different portions of the word line cavities at each mask stage of the multi-mask patterning process.

17. The method according to claim 16, wherein the multi-mask patterning process further comprises performing the multi-mask patterning process for an iteration number determined by the number of word lines to be accessed, and the multi-mask patterning process further comprises: Forming a first process resist to cover a first half of the word line cavities, wherein the first process resist has a first pattern that covers only every other word line cavity; Etching a first uncovered half of the word line cavities; Removing the first process resist; Forming a second process resist to cover a second half of the word line cavities, wherein the second process resist has a second pattern that covers only every other pair of word line cavities; Etching a second uncovered half of the word line cavities; Removing the second process resist; Forming a third process resist to cover a third half of the word line cavities, wherein the third process resist has a third pattern that covers only every third word line cavity; Etching a third uncovered half of the word line cavities; And Removing the third process resist.

18. The method according to claim 13, further comprising: Forming a plurality of through-array vias through the plurality of stacks, wherein the plurality of through-array vias and the word line contacts are mixed in a shared word line access structure region.

19. The method according to claim 18, wherein the plurality of through-array vias and the word line contacts are mixed such that a first word line among the word line contacts is located between a first through-array via and a second through-array via among the through-array vias in the shared word line access structure region.

20. The method according to claim 18, wherein the plurality of through-array vias and the word line contacts are mixed such that a first row among the word line contacts is located between a first row and a second row among the through-array vias in the shared word line access structure region.

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