Low-voltage band-gap reference starting circuit

Abstract

The invention discloses a low-voltage band-gap reference starting circuit which is characterized in that the negative end of an operational amplifier is connected to the ground through a bipolar transistor Q1, and the positive end of the operational amplifier is connected to the ground after being connected in series with a bipolar transistor Q2 through an R1; the negative end of the operational amplifier is connected to the ground through the R3, and the positive end of the operational amplifier is connected to the ground through the R2; source electrodes of the PMOS transistors M1, M2 and M3 are connected to power supply voltage; grid electrodes of the M1, the M2 and the M3 are connected to the output end of the operational amplifier; an R6 is connected between the negative end of the operational amplifier and the drain electrode of the M1; a R7 is connected between the positive end of the operational amplifier and the drain electrode of the M2; the drain electrode of the M3 is grounded through the R4; the grid electrode of the NMOS tube M4 is connected with the drain electrode of the M1, the drain electrode of the NMOS tube M4 is connected with the grid electrode of the NMOS tube M5, the drain electrode of the NMOS tube M5 is connected with the grid electrode of the M1, and the source electrodes of the NMOS tube M4 and the NMOS tube M5 are connected to the ground; and the drain electrode of the M4 is connected with the power supply voltage through the R5. According to the invention, the circuit can work normally at any process pin.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a low-voltage bandgap reference startup circuit. Background Art

[0002] In the design of low-voltage analog circuits, a bandgap reference that can generate a voltage at a low power supply is usually required. And the operation of the bandgap reference often requires a suitable startup circuit to ensure that the circuit operates in a normal state.

[0003] A conventional low-voltage bandgap reference structure specifically includes an operational amplifier for clamping, two bipolar junction transistors (BJTs), a resistor R1 (ΔVBE / R1) for generating a current proportional to absolute temperature (PTAT), two identical resistors R2 and R3 (VBE / R2) for generating a negative temperature current, and three current mirrors M1, M2, and M3. Here, PMOS transistors are selected as the current mirrors. Finally, a temperature-independent voltage VBG is generated across resistor R4 by combining the zero-temperature-drift currents of positive and negative temperatures.

[0004] A startup circuit is added to the above conventional low-voltage bandgap reference structure to obtain a low-voltage bandgap reference with a startup circuit. Among them, the gate of NMOS transistor M4 is connected to the negative terminal of the operational amplifier, and the drain of NMOS transistor M5 is connected to the output terminal of the operational amplifier. If this startup circuit is not added, at the moment of power-on, if the input of the operational amplifier is a low voltage, the output of the operational amplifier is a high voltage. At this time, PMOS transistors M1 and M2 cannot be started because their gates are at a high voltage, and the entire circuit cannot work. After adding the startup circuit, if the above situation occurs, the output of the operational amplifier is a low voltage. At this time, the gate of NMOS transistor M4 is at a low voltage, and the NMOS transistor is not conducting. The drain of the NMOS transistor follows the power supply voltage VDD through resistor R5 and is at a high voltage, that is, the gate of NMOS transistor M5 is at a high voltage, and M5 conducts. Then, it will pull down the voltage at the output terminal of the operational amplifier through M5, thereby enabling PMOS transistors M1 and M2 to conduct, and the input of the operational amplifier is also correspondingly raised. At this time, M4 conducts and M5 turns off, and the operational amplifier establishes a loop, making the entire circuit operate in a steady state.

[0005] However, the problem with this startup circuit is that the turn-on voltage VTH of M4 varies with the process corner and is not fixed. When VTH is very large and greater than the VBE voltage at the negative terminal of the operational amplifier, it may cause M4 to fail to turn on, and subsequently M5 does not pull down the gate voltage of M1 completely, causing the operational amplifier to operate in the wrong metastable state. Therefore, to solve the above problems, a new low-voltage bandgap reference startup circuit is urgently needed. Summary of the Invention

[0006] The object of the present invention is to provide a low-voltage bandgap reference startup circuit in view of the deficiencies of the prior art.

[0007] The object of the present invention is achieved by the following technical solutions: A low-voltage bandgap reference startup circuit includes: an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a current proportional to the absolute temperature, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2, and M3, a zero temperature drift resistor R4, two NMOS transistors M4 and M5, and three resistors R5, R6, and R7 for increasing the voltage; wherein, the bases and collectors of Q1 and Q2 are connected, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is grounded; one end of R2 is grounded and the other end is connected to the positive terminal of the operational amplifier; the sources of M1, M2, and M3 are connected together and connected to the power supply voltage VDD; the gates of M1, M2, and M3 are connected together and connected to the output terminal of the operational amplifier; the drain of M1 is connected to one end of R6, the other end of R6 is connected to the negative terminal of the operational amplifier; the drain of M2 is connected to one end of R7, the other end of R7 is connected to the positive terminal of the operational amplifier; the drain of M3 is connected to one end of R4, the other end of R4 is grounded, and a voltage VBG independent of temperature is generated at the end of R4 far from the ground; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, the drain of M5 is connected to the gate of M1, the sources of M4 and M5 are connected together and connected to the ground; one end of R5 is connected to the drain of M4 and the other end is connected to VDD.

[0008] Further, the bipolar transistors Q1 and Q2 are of the same type, both being PNP transistors or NPN transistors.

[0009] Further, when the bipolar transistors Q1 and Q2 are both PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base and collector of Q1 are connected and then grounded, the emitter of Q2 is connected to one end of the resistor R1, and the base and collector of Q2 are connected and then grounded.

[0010] Further, when both the bipolar transistors Q1 and Q2 are NPN transistors, the base of Q1 is connected to the collector and then connected to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base of Q2 is connected to the collector and connected to one end of the resistor R1, and the emitter of Q2 is grounded.

[0011] Further, the resistance value of the resistor R6 satisfies the following conditions:

[0012] wherein, represents the voltage between the base and the emitter of the PMOS transistor M1, represents the source-drain current of the PMOS transistor M1, represents the resistance value of the resistor R6, represents the threshold voltage of the NMOS transistor M4.

[0013] Further, the resistance value of the resistor R7 is greater than the resistance value of the resistor R6.

[0014] Further, the resistor R5 can also be replaced by n series-connected PMOS inverse ratio transistors. The drain of the previous PMOS inverse ratio transistor is connected to the source of the next PMOS inverse ratio transistor. The source of the first PMOS inverse ratio transistor is connected to the power supply voltage VDD, and the drain of the last PMOS inverse ratio transistor is connected to the drain of the NMOS transistor M4; the gates of the n PMOS inverse ratio transistors are connected together and connected to one end of a resistor r, and the other end of the resistor r is connected to the ground.

[0015] Further, the width-to-length ratio W / L of the PMOS inverse ratio transistor is less than 1.

[0016] The beneficial effects of the present invention are as follows: By using two NMOS transistors M4 and M5, the present invention can simplify the circuit wiring structure, effectively saving area and cost; by adding a resistor R6 between the negative terminal of the operational amplifier and the drain of the PMOS transistor M1, by changing the resistance value of the resistor R6, the voltage of the gate of the NMOS transistor M4 can be raised, enabling the circuit to work properly at any process corner; at the same time, by adding a resistor R7 between the positive terminal of the operational amplifier and the drain of the PMOS transistor M2, and the resistance value of R7 is greater than the resistance value of R6, it effectively ensures that the negative feedback is always greater than the positive feedback; the present invention solves the problem that the threshold voltage of the MOS transistor is large at some process corners, resulting in the startup circuit not working properly, and at the same time, the overall loop is still negative feedback, without bringing new problems, enabling the circuit to work properly. Description of the Drawings

[0017] Figure 1 is a circuit diagram of an existing low-voltage bandgap reference structure with a startup circuit added; Figure 2 It is a circuit diagram of the low-voltage bandgap reference startup circuit of the present invention; Figure 3 It is another circuit diagram of the low-voltage bandgap reference startup circuit of the present invention. Specific Embodiments

[0018] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0019] The terms used in the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0020] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0021] The present invention will be described in detail below with reference to the drawings. Without conflict, the features in the following embodiments and implementation manners may be combined with each other.

[0022] Figure 1 It is a circuit diagram of an existing low-voltage bandgap reference structure with a startup circuit added. As Figure 1As shown, the circuit includes a low-voltage bandgap reference structure and a start-up circuit. The low-voltage bandgap reference structure includes an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a PTAT current, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2, and M3, and a zero-temperature-drift resistor R4, and finally generates a temperature-independent voltage VBG; the start-up circuit includes two NMOS transistors M4 and M5 and a resistor R5. Among them, in the low-voltage bandgap reference structure, when the two bipolar transistors Q1 and Q2 are PNP transistors, the negative terminal of the operational amplifier is connected to the emitter of the PNP transistor Q1, and the collector of the PNP transistor Q1 is connected to the base and then grounded; one end of the resistor R3 is grounded, and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the PNP transistor Q2, and the collector of the PNP transistor Q2 is connected to the base and then grounded; one end of the resistor R2 is grounded, and the other end is connected to the positive terminal of the operational amplifier; the sources of the three PMOS transistors M1, M2, and M3 are connected together and connected to the power supply voltage VDD; the gates of the three PMOS transistors M1, M2, and M3 are connected together and connected to the output terminal of the operational amplifier; the drain of the PMOS transistor M1 is connected to the negative terminal of the operational amplifier, the drain of the PMOS transistor M2 is connected to the positive terminal of the operational amplifier, the drain of the PMOS transistor M3 is connected to one end of the zero-temperature-drift resistor R4, and the other end of the zero-temperature-drift resistor R4 is grounded; a temperature-independent voltage VBG is generated at the end of the zero-temperature-drift resistor R4 away from the ground. In the start-up circuit, the gate of the NMOS transistor M4 is connected to the negative terminal of the operational amplifier, the drain of the NMOS transistor M4 is connected to the gate of the NMOS transistor M5, the drain of the NMOS transistor M5 is connected to the output terminal of the operational amplifier, the sources of the NMOS transistors M4 and M5 are connected together and connected to the ground; one end of the resistor R5 is connected to the drain of the NMOS transistor M4, and the other end is connected to the power supply voltage VDD.

[0023] It should be understood that the two bipolar transistors Q1 and Q2 can also be NPN transistors. At this time, the collector of the NPN transistor Q1 is connected to the base and then connected to the negative terminal of the operational amplifier, and the emitter of the NPN transistor Q1 is grounded; the collector of the NPN transistor Q2 is connected to the base and then connected to one end of the resistor R1, and the emitter of the NPN transistor Q2 is grounded.

[0024] In the embodiment of the present invention, for Figure 1Improve the circuit shown, and make the circuit work properly at any process corner by increasing the voltage of the gate of NMOS transistor M4, so as to obtain the low-voltage bandgap reference startup circuit of the present invention. The low-voltage bandgap reference startup circuit of the present invention is as shown in Figure 2 shown, and specifically includes an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a PTAT current, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2 and M3, a zero-temperature-drift resistor R4, two NMOS transistors M4 and M5, and three resistors R5, R6 and R7 for increasing the voltage. Among them, the bases and collectors of Q1 and Q2 are connected, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is grounded; one end of R2 is grounded and the other end is connected to the positive terminal of the operational amplifier; the sources of M1, M2 and M3 are connected together and connected to the power supply voltage VDD; the gates of M1, M2 and M3 are connected together and connected to the output terminal of the operational amplifier; the drain of M1 is connected to one end of R6, the other end of R6 is connected to the negative terminal of the operational amplifier; the drain of M2 is connected to one end of R7, the other end of R7 is connected to the positive terminal of the operational amplifier; the drain of M3 is connected to one end of R4, the other end of R4 is grounded, and a temperature-independent voltage VBG is generated at the end of R4 far from the ground; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, the drain of M5 is connected to the gate of M1, the sources of M4 and M5 are connected together and connected to the ground; one end of R5 is connected to the drain of M4 and the other end is connected to VDD. In this circuit, the two NMOS transistors are used for pulling down, and its wiring structure is simple, saving area and cost. If they are replaced with PMOS transistors, the circuit will be complicated, with more transistors and higher cost. Therefore, in the startup circuit, using two NMOS transistors can make the circuit wiring structure simple, effectively saving area and cost; it also solves the problem that the threshold voltage of the MOS transistor is large at some process corners, resulting in the startup circuit not working properly. At the same time, the overall loop is still negative feedback, without bringing new problems, enabling the circuit to work properly.

[0025] Further, the two bipolar transistors Q1 and Q2 are of the same type, both PNP transistors or NPN transistors. When the two bipolar transistors Q1 and Q2 are PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base and collector of Q1 are connected and then grounded, the emitter of Q2 is connected to one end of the resistor R1, and the base and collector of Q2 are connected and then grounded, as shown in Figure 2As shown. When the two bipolar transistors Q1 and Q2 are NPN transistors, the base of Q1 is connected to the collector and then to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base of Q2 is connected to the collector and then to one end of the resistor R1, and the emitter of Q2 is grounded.

[0026] Furthermore, the resistance value of the resistor R6 satisfies the following conditions:

[0027] Wherein, represents the voltage between the base and emitter of the PMOS transistor M1, represents the source-drain current of the PMOS transistor M1, represents the resistance value of the resistor R6, represents the threshold voltage of the NMOS transistor M4. Through the resistor R6, the gate of the NMOS transistor M4 is raised by a voltage of R6*IDS1. As long as the resistance value of R6 is changed so that the resistance value of the resistor R6 satisfies the above formula, the circuit can work normally. In addition, a resistor R7 with a resistance value greater than R6 needs to be added to the positive terminal path of the operational amplifier to ensure that the loop negative feedback is always greater than the positive feedback, so as to ensure that the circuit works in a normal loop.

[0028] Furthermore, the resistance value of the resistor R7 is greater than the resistance value of the resistor R6. As Figure 2 shown, by adding a resistor R6 between the negative terminal of the operational amplifier and the drain of the PMOS transistor M1, and adding a resistor R7 between the positive terminal of the operational amplifier and the drain of the PMOS transistor M2 at the same time, it is necessary to ensure that the resistance value of R7 is greater than the resistance value of R6, because after adding R6, the feedback coefficient of the negative feedback will decrease. Therefore, it is necessary to increase R7 with a larger resistance value than R6 to make the decrease in the feedback coefficient of the positive feedback more than that of the negative feedback, ensuring that the negative feedback is always greater than the positive feedback.

[0029] Since the startup circuit is an auxiliary circuit and should not bring a large power consumption, and after the NMOS transistor M4 is turned on, because the overdrive voltage of M4 can be almost ignored, so , wherein represents the source-drain current of the NMOS transistor M4, represents the power supply voltage, represents the resistance value of the resistor R5. If a small source-drain current of the NMOS transistor M4 is required, then R5 needs a very large resistance value and a very large area. Therefore, in some other embodiments, such as Figure 3As shown, n PMOS inverse ratio transistors connected in series are used to replace the resistor R5. These n PMOS inverse ratio transistors all adopt inverse ratio to increase the equivalent impedance of the NMOS transistor. The gates of the n PMOS inverse ratio transistors connected in series are connected to the ground through a small resistor to ensure better conduction, and the area required for the n PMOS inverse ratio transistors to generate the same impedance as the resistor R5 is greatly reduced, thus saving area.

[0030] Specifically, as Figure 3 shown, the source of the first PMOS inverse ratio transistor is connected to the power supply voltage VDD, the drain of the first PMOS inverse ratio transistor is connected to the source of the second PMOS inverse ratio transistor, the drain of the second PMOS inverse ratio transistor is connected to the source of the third PMOS inverse ratio transistor, and so on. The drain of the previous PMOS inverse ratio transistor is connected to the source of the next PMOS inverse ratio transistor. The drain of the last PMOS inverse ratio transistor is connected to the drain of the NMOS transistor M4. The gates of the n PMOS inverse ratio transistors are connected together and connected to one end of a small resistor r, and the other end of the small resistor r is connected to the ground.

[0031] Furthermore, the aspect ratio W / L of the PMOS inverse ratio transistor is less than 1.

[0032] In summary, the present invention can make the circuit wiring structure simple, effectively saving area and cost by using two NMOS transistors M4 and M5; the present invention adds a resistor R6 between the negative terminal of the operational amplifier and the drain of the PMOS transistor M1. By changing the resistance value of the resistor R6, the voltage of the gate of the NMOS transistor M4 can be raised, enabling the circuit to work properly on any process pin; at the same time, a resistor R7 is added between the positive terminal of the operational amplifier and the drain of the PMOS transistor M2, and the resistance value of R7 is greater than that of R6, effectively ensuring that the negative feedback is always greater than the positive feedback; the present invention solves the problem that the threshold voltage of the MOS transistor is large at some process pins, resulting in the startup circuit not working properly. At the same time, the overall loop is still negative feedback, without bringing new problems, enabling the circuit to work properly.

[0033] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0034] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A low-voltage bandgap reference startup circuit, characterized in that Comprising: An operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a current proportional to the absolute temperature, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2 and M3, a zero temperature drift resistor R4, two NMOS transistors M4 and M5, and three resistors R5, R6 and R7 for boosting the voltage; wherein, the bases and collectors of Q1 and Q2 are connected, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is grounded; one end of R2 is grounded and the other end is connected to the positive terminal of the operational amplifier; the sources of M1, M2 and M3 are connected together and connected to the power supply voltage VDD; the gates of M1, M2 and M3 are connected together and connected to the output terminal of the operational amplifier; the drain of M1 is connected to one end of R6, the other end of R6 is connected to the negative terminal of the operational amplifier; the drain of M2 is connected to one end of R7, the other end of R7 is connected to the positive terminal of the operational amplifier; the drain of M3 is connected to one end of R4, the other end of R4 is grounded, and a voltage VBG independent of temperature is generated at the end of R4 far from the ground; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, the drain of M5 is connected to the gate of M1, the sources of M4 and M5 are connected together and connected to the ground; one end of R5 is connected to the drain of M4 and the other end is connected to VDD.

2. The low-voltage bandgap reference startup circuit according to claim 1, wherein The bipolar transistors Q1 and Q2 are of the same type, both being PNP transistors or NPN transistors.

3. The low-voltage bandgap reference startup circuit according to claim 2, characterized in that When the bipolar transistors Q1 and Q2 are both PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base and collector of Q1 are connected and then grounded, the emitter of Q2 is connected to one end of the resistor R1, and the base and collector of Q2 are connected and then grounded.

4. The low-voltage bandgap reference start-up circuit according to claim 2, characterized in that When the bipolar transistors Q1 and Q2 are both NPN transistors, the base and collector of Q1 are connected and then connected to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base and collector of Q2 are connected and connected to one end of the resistor R1, and the emitter of Q2 is grounded.

5. The low-voltage bandgap reference startup circuit according to claim 1, wherein The resistance value of the resistor R6 satisfies the following conditions: ； Among them, represents the voltage between the base and the emitter of PMOS transistor M1, represents the source-drain current of PMOS transistor M1, represents the resistance value of resistor R6, represents the threshold voltage of NMOS transistor M4.

6. The low-voltage bandgap reference startup circuit according to claim 1, characterized in that, The resistance value of the resistor R7 is greater than that of the resistor R6.

7. The low-voltage bandgap reference startup circuit according to claim 1, wherein The resistor R5 can also be replaced by n series-connected PMOS inverse ratio transistors, the drain of the previous PMOS inverse ratio transistor is connected to the source of the next PMOS inverse ratio transistor, wherein the source of the first PMOS inverse ratio transistor is connected to the power supply voltage VDD, and the drain of the last PMOS inverse ratio transistor is connected to the drain of the NMOS transistor M4; the gates of the n PMOS inverse ratio transistors are connected together and connected to one end of a resistor r, and the other end of the resistor r is connected to the ground.

8. The low-voltage bandgap reference startup circuit according to claim 7, characterized in that, The width-to-length ratio W / L of the PMOS inverse ratio transistor is less than 1.

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