Processor with decoupled vector processing units based on data path splitting

Abstract

The application relates to a processor based on a decoupled vector processing unit split by a data path, comprising a pointer taking unit, a decoding unit, a vector processing unit, a scalar processing unit, a memory access scheduling unit and a storage unit. In the processor, a separate path execution state management subunit is arranged in each data path of the vector processing unit, a more accurate scheduling reference is provided for the microinstruction splitting processing of the main scheduler, the difficulty of microinstruction tracking and management is reduced, the register reading request path is optimized, and the timing risk is reduced; and the architecture manages the sequence of scalar and vector memory access requests through a unified memory access scheduling unit, the management difficulty of memory consistency is reduced, and the reliability of the processor system is enhanced.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of processor technology, and particularly relates to a processor based on a decoupled vector processing unit split by a data path. BACKGROUND

[0002] A processor is the core of calculation and control of an information processing system. A modern processor instruction set architecture (ISA) can be divided into complex instruction set (CISC) and reduced instruction set (RISC). The former has instructions that read data from memory to registers, calculate, and then write the calculation results back to memory. The instruction set is relatively complex but powerful. The latter can only access memory through dedicated memory access instructions. The operation of a single instruction is simple, but the memory access efficiency may be reduced. The reduced instruction set has developed to the fifth generation (RISC-V), and a vector extension instruction set has been introduced, so that the processor can support vector processing. Vector processing technology effectively reduces the number of instruction fetching and instruction emission by processing multiple data with one instruction, thereby improving the parallelism of data processing, and has been widely used in high-performance processors.

[0003] In related technologies, there are mainly two designs of vector processing units in a processor: a tightly coupled architecture and a decoupled architecture. The tightly coupled vector architecture mixes traditional scalar processing units and vector processing units together, and they share the decoding, scheduling, and execution pipeline. Although it saves part of the hardware overhead, it leads to high design complexity and also limits the upper limit of the working frequency of the processor. The decoupled vector architecture separates the design of the scalar processing unit and the vector processing unit. When the decoding module identifies a vector instruction, it sends it to the vector processing unit, which is responsible for the execution of the vector instruction independently. In addition, by further splitting the large-width vector data processing into multiple independent small-width data processing paths, the timing bottleneck of the vector data path design can be effectively reduced, and the decoupled vector architecture has gradually become the mainstream of the vector architecture in high-performance processors.

[0004] Generally, in the pipeline of a processor based on a decoupled vector architecture, instructions are sent from a fetch unit to a decoding unit. When the decoding unit identifies that the instruction is a vector instruction, it sends it to the vector processing unit in the back end. The vector processing unit includes a main scheduler, a data path unit, a cross-path unit, a memory access unit, and an execution state management unit. Among them:

[0005] The main scheduler is responsible for splitting the instruction into microinstructions according to the data path bandwidth, and each microinstruction is responsible for the calculation of a part of data in the vector;

[0006] The data path unit is divided into several small-bandwidth data paths, each of which includes a path scheduler, a path register stack, a path execution unit, and a path register write-back state table;

[0007] The path scheduler queries the path register write-back state table to determine whether all the required registers are ready for reading, and then sends a register reading request to the path register stack and transmits the read data to the path execution unit for microinstruction execution. After the microinstruction execution is completed, the corresponding entry in the path register write-back state table is cleared, and the execution state management unit is notified.

[0008] Each path can only receive microinstructions for reading and writing the path register stack, and there is no direct data interaction between all the paths, thereby reducing the timing risk within the path and between the paths. If there is an instruction that needs to read and write across data paths, the cross-path unit is responsible for sending register reading and writing requests to the corresponding paths and performing the corresponding instruction execution.

[0009] The memory unit is responsible for the execution of vector memory instructions, which splits the memory instruction into several memory requests and sends them to the storage unit for memory reading and writing, and sends register reading / writing requests to the corresponding paths as needed. After the memory request execution is completed, the execution state management unit is notified. When all microinstructions and memory requests of a vector instruction are executed, the execution state management unit notifies the back-end scalar processing unit, which is responsible for the sequential submission of all instructions.

[0010] However, in the architecture of the above-mentioned vector processing unit, the splitting of microinstructions makes it difficult to manage and track the execution state of microinstructions, because the execution information of microinstructions is only visible within the path, so that the main scheduler cannot timely perceive the change of the execution state of microinstructions, and thus it is difficult to accurately schedule instructions. Secondly, because the cross-path unit and the memory unit both have register reading requests to the data path, the timing between them will affect each other, further increasing the timing risk. Moreover, because the vector memory instruction and the scalar memory instruction independently access the storage unit, it is difficult to manage memory consistency.

[0011] Therefore, it is necessary to optimize the architecture of the vector processing unit to solve the above technical problems. SUMMARY

[0012] The present application provides a processor based on a decoupled vector processing unit with data path splitting, aiming to solve the timing and memory consistency management problems of the existing processor for microinstruction splitting.

[0013] To solve the above technical problems, the application provides a processor of decoupled vector processing unit based on data path splitting, which comprises a fetch unit, a decoding unit, a vector processing unit, a scalar processing unit, a memory access scheduling unit and a storage unit, wherein:

[0014] The fetch unit is used to fetch instructions from the processor memory and send them to the decoding unit.

[0015] The decoding unit is used to analyze the instructions and identify scalar instructions and / or vector instructions from the instructions, wherein the vector instructions are sent to the vector processing unit when the vector instructions are identified, and the scalar instructions are sent to the scalar processing unit when the scalar instructions are identified.

[0016] The vector processing unit is used to execute the vector instructions, and generate a vector memory access request for requesting access to the storage unit according to the vector memory access instruction when the vector instruction is a vector memory access instruction.

[0017] The scalar processing unit is used to execute the scalar instructions, and generate a scalar memory access request for requesting access to the storage unit according to the scalar memory access instruction when the scalar instruction is a scalar memory access instruction.

[0018] The memory access scheduling unit is used to send the vector memory access request and / or the scalar memory access request to the storage unit according to a preset scheduling mode.

[0019] The storage unit is used to perform memory access according to the vector memory access request and / or the scalar memory access request, and return corresponding memory access response information to the vector processing unit and / or the scalar processing unit.

[0020] Furthermore, the vector processing unit comprises a main scheduler, a plurality of path register write-back state tables, a data path unit and an execution state management unit, and the data path unit comprises a path register stack, wherein:

[0021] The main scheduler is used to determine whether the vector instruction belongs to an arithmetic instruction or a vector storage instruction, and if so, split the vector instruction into a plurality of micro-instructions with the same number as the number of path register write-back state tables according to the data path bandwidth of the data path unit.

[0022] Each entry in each of the path register write-back state tables is used to record the write-back state of the path register required by a micro-instruction, and the entry of the write-back state is available or working state.

[0023] The data path unit comprises a plurality of data paths, each of the data paths comprises an independent path scheduler, a path register stack and a path execution unit, and one of the data paths corresponds to one of the path register write-back state tables, wherein:

[0024] The path scheduler is configured to listen to the write-back state recorded in the path register write-back state table, and send a corresponding register read request to the path register stack according to the micro instruction when a path register in the path register stack is available;

[0025] The path execution unit is configured to execute the micro instruction according to the path register data read from the path register stack according to the register read request;

[0026] The execution state management unit comprises a plurality of path execution state management sub-units, and one of the path execution state management sub-units corresponds to one of the data paths, and the path execution state management sub-unit is configured to monitor the execution state of the micro instruction.

[0027] Further, the vector processing unit further comprises a memory access unit, and the memory access unit is configured to:

[0028] receive the vector instruction from the main scheduler, receive the path register data read by the path execution unit if the vector instruction is a vector storage instruction, and split the vector memory access instruction into a plurality of memory access sub-requests;

[0029] send the memory access sub-requests to the memory access scheduling unit as the vector memory access requests, and obtain the memory access response information corresponding to the vector memory access requests from the memory access scheduling unit;

[0030] send first confirmation information to the execution state management unit after all the memory access sub-requests are executed.

[0031] Further, the vector processing unit further comprises a cross-path unit, and the cross-path unit is configured to:

[0032] receive the micro instruction split by the main scheduler and the path register data read by the data path unit, execute the micro instruction according to the path register data, and write the execution result of the micro instruction back to the path register stack of the corresponding data path unit.

[0033] Further, the path execution unit is further configured to:

[0034] After the execution of the microinstruction is completed, the entry of the write-back status of the path register write-back status table is updated, and second confirmation information is sent to the corresponding path execution status management subunit.

[0035] Furthermore, the execution status management unit is further configured to:

[0036] After receiving the first confirmation information issued by the memory access unit and all the path execution status management subunits receiving the second confirmation information issued by their corresponding path execution units, a notification signal indicating that the execution of the vector instruction is completed is sent to the scalar processing unit.

[0037] Furthermore, the memory access unit is further configured to:

[0038] receiving the vector instruction from the main scheduler, and if the vector instruction is a vector load instruction, splitting the vector memory access instruction into a plurality of memory access sub-requests;

[0039] sending the memory access sub-request as the vector memory access request to the memory access scheduling unit, obtaining the memory access response information corresponding to the vector memory access request from the memory access scheduling unit, and simultaneously issuing a corresponding register write request to the path register file according to the memory access response information, wherein the register write request is used to write the data corresponding to the vector memory access request into the path register file;

[0040] After all the memory access sub-requests are executed, first confirmation information is sent to the execution status management unit.

[0041] Furthermore, the execution status management unit is further configured to:

[0042] After receiving the first confirmation information sent by the memory access unit and completing the execution of all the register write requests, a notification signal of completing the execution of the vector instruction is sent to the scalar processing unit.

[0043] Furthermore, the preset scheduling method is:

[0044] sending the vector memory access request and / or the scalar memory access request to the storage unit in sequence according to the order of the scalar instructions and / or the vector instructions parsed from the instruction by the decoding unit; or

[0045] The vector memory access request and / or the scalar memory access request are sent to the storage unit in disorder according to a preset priority.

[0046] The processor based on the decoupled vector memory access unit has the advantages that: the processor is provided, each data path of the vector processing unit is equipped with a separate path execution state management subunit, the microinstruction splitting processing of the main dispatcher is provided with more accurate scheduling reference, the difficulty of microinstruction tracking and management is reduced, the register read request path is optimized, and the timing risk is reduced; and the architecture manages the sequence of the scalar and vector memory request through the unified memory scheduling unit, the management difficulty of the memory consistency is reduced, and the reliability of the processor system is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 is a structural schematic diagram of a processor based on a decoupled vector processing unit of data path splitting provided by an embodiment of the present application;

[0048] Figure 2 is a structural schematic diagram of a vector processing unit in the processor based on the decoupled vector processing unit of data path splitting provided by an embodiment of the present application;

[0049] Figure 3 is a scheduling flowchart of the vector processing unit executing a vector instruction provided by an embodiment of the present application;

[0050] Figure 4 is a scheduling flowchart of the vector processing unit executing a cross-path vector instruction provided by an embodiment of the present application;

[0051] Figure 5 is a memory instruction execution flowchart provided by an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0053] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a processor based on a decoupled vector processing unit of data path splitting provided by an embodiment of the present application, the processor 100 includes a fetch unit 101, a decoding unit 102, a vector processing unit 103, a scalar processing unit 104, a memory scheduling unit 105 and a storage unit 106, wherein:

[0054] The fetch unit 101 is used to fetch instructions from the processor memory and send them to the decoding unit 102;

[0055] The decoding unit 102 is configured to parse the instruction and identify a scalar instruction and / or a vector instruction from the instruction, wherein: when the vector instruction is identified, the vector instruction is sent to the vector processing unit 103; and when the scalar instruction is identified, the scalar instruction is sent to the scalar processing unit 104.

[0056] The vector processing unit 103 is configured to execute the vector instruction, and when the vector instruction is a vector memory access instruction, generate a vector memory access request for requesting to access the storage unit 106 according to the vector memory access instruction.

[0057] The scalar processing unit 104 is configured to execute the scalar instruction, and when the scalar instruction is a scalar memory access instruction, generate a scalar memory access request for requesting to access the storage unit 106 according to the scalar memory access instruction.

[0058] The memory access scheduling unit 105 is configured to send the vector memory access request and / or the scalar memory access request to the storage unit 106 according to a preset scheduling mode.

[0059] The storage unit 106 is configured to perform memory access according to the vector memory access request and / or the scalar memory access request, and return corresponding memory access response information to the vector processing unit 103 and / or the scalar processing unit 104.

[0060] Based on the above processor 100, the embodiment of the present application achieves the design goal of decoupling architecture, that is, the vector instruction and the ordinary scalar instruction are shunted in the decoding stage, and the instructions are executed by the vector processing unit 103 and the scalar processing unit 104 respectively, which simplifies the pipeline design. At the same time, the processor 100 of the embodiment of the present application unifies the management of vector and scalar memory access requests through the memory access scheduling unit 105, which conforms to the design principle of the storage hierarchy and is beneficial to guarantee the cache consistency.

[0061] Further, in the embodiment of the present application, the microinstruction splitting processing of the vector instruction is executed by the vector processing unit 103, and specifically, please refer to Figure 2 , Figure 2 FIG. 1 is a structural schematic diagram of a vector processing unit 103 in a processor 100 based on a decoupling vector processing unit 103 according to an embodiment of the present application, the vector processing unit 103 comprises a main scheduler 1031, a plurality of path register write-back state tables 1032, a data path unit 1033, and an execution state management unit 1034, the data path unit 1033 comprises a path register stack, wherein:

[0062] The main scheduler 1031 is used for judging whether the vector instruction belongs to an arithmetic instruction or a vector storage instruction, and if yes, splitting the vector read instruction into a plurality of micro-instructions according to the data path bandwidth of the data path unit 1033, and the number of the micro-instruction is same as that of the path register write back state table 1032;

[0063] Each entry in the path register write back state table 1032 is used for recording the write back state of the path register required by a micro-instruction, and the entry of the write back state is available or working state;

[0064] The data path unit 1033 comprises a plurality of data paths, each of the data paths comprises an independent path scheduler 10331, a path register stack 10332 and a path execution unit 10333, and one of the data paths corresponds to one of the path register write back state tables 1032, wherein:

[0065] The path scheduler 10331 is used for listening to the write back state recorded by the path register write back state table 1032, and sending a corresponding register read request to the path register stack 10332 according to the micro-instruction when the path register in the path register stack 10332 is available;

[0066] The path execution unit 10333 is used for executing the micro-instruction according to the path register data read from the path register stack 10332 by the register read request;

[0067] The execution state management unit 1034 comprises a plurality of path execution state management sub-units 10341, and one of the path execution state management sub-units 10341 corresponds to one of the data paths, and the path execution state management sub-unit 10341 is used for monitoring the execution state of the micro-instruction.

[0068] The arithmetic instructions described in the embodiment of the present application include a first type of which the read / write of the path register can be completed in the data path, and a second type of which the read / write of the path register stack needs to be performed across the data paths; the vector storage instruction described in the embodiment of the present application is used for writing the data read from the data path into a storage unit 106. In the embodiment of the present application, the main scheduler 1031 performs micro-instruction splitting mainly aiming at the read / write instructions of the path register in the data path, and these instructions will be split into register read requests by the main scheduler 1031 and sent to the data path unit 1033 to generate the register read requests. The micro-instruction corresponding to the first type of arithmetic instruction is executed by the path execution unit 10333 in a single data path.

[0069] In the above structure, by decoupling the data path, separating the path register write-back state table 1032 from the data path, and directly setting as the subordinate structure of the main scheduler 1031, more accurate scheduling reference can be provided for the main scheduler 1031; and based on the path register write-back state table 1032, the main scheduler 1031 can quickly query the path register state to automatically adjust the splitting strategy according to the data path bandwidth, so as to fully utilize the hardware resources. That is, as shown in the scheduling flow diagram of the vector instruction, through the design of decoupling the data path, when the vector read instruction is executed: Figure 3

[0070] S201, first, the main scheduler 1031 executes the query of the path register write-back state table 1032 and the splitting of the micro instruction;

[0071] S202, the main scheduler 1031 issues the micro instruction to the path scheduler 10331 to generate a register read request, and sends the data read from the path register stack 10332 to the path execution unit 10333;

[0072] S203, the path execution unit 10333 executes the micro instruction;

[0073] S204, the execution state management subunit 10341 monitors the execution state of the micro instruction, and at the same time, the path execution unit 10333 clears or updates the related entries of the path register write-back state table 1032.

[0074] In the embodiment of the present application, by decoupling the data path, all read requests for the path register are uniformly set to be issued by the main scheduler, which reduces the read request path from the cross-path unit and the memory access unit to the path register stack, and reduces the timing risk compared with the existing architecture.

[0075] Further, the vector processing unit 103 further includes a memory access unit 1035, which is configured to:

[0076] receive the vector instruction from the main scheduler 1031, if the vector instruction is a vector storage instruction, receive the path register data read by the path execution unit 10333, and split the vector memory instruction into a plurality of memory sub-requests;

[0077] send the memory sub-requests to the memory scheduling unit 105 as the vector memory request, and obtain the memory response information corresponding to the vector memory request from the memory scheduling unit 105;

[0078] after all the memory sub-requests are executed, send first confirmation information to the execution state management unit 1034. ​

[0079] Further, the vector processing unit 103 further comprises a cross lane unit 1036, which is configured to:

[0080] receive the microinstruction split by the main scheduler 1031 and the lane register data read by the data lane unit 1033, and execute the microinstruction according to the lane register data, and write the execution result of the microinstruction back to the lane register stack 10332 of the corresponding data lane unit 1033.

[0081] The cross lane unit 1036 is a next level structure of the main scheduler 1031, and acts according to whether the microinstruction type split by the main scheduler 1031 needs to perform cross-data-lane vector register reading. The design of the cross lane unit 1036 allows different data lanes to directly read and write the vector registers of the other party, avoiding the round trip transmission of data between the lane register stack 10332 and another lane register stack 10332, thereby reducing the additional access overhead when different microinstructions are executed. That is, as shown in the scheduling flow diagram of the cross-lane vector instruction, the execution involving the cross-lane unit 1036 is different from that shown in the execution flow diagram. Figure 4 Figure 3

[0082] S301, while the main scheduler 1031 executes microinstruction splitting, the corresponding microinstruction is sent to the cross lane unit 1036:

[0083] S302, the lane scheduler 10331 generates a cross-lane register read request;

[0084] S303, the lane register stack 10332 reads data from the corresponding lane register according to the register read request;

[0085] S304, the cross lane unit 1036 executes the microinstruction, and sends the data read in S303 to the corresponding lane execution unit 10333 of the other lane.

[0086] In the embodiment of the application, the microinstruction executed by the cross lane unit 1036 mainly corresponds to the second type of arithmetic instruction described in the above embodiment for cross-lane reading / writing of the lane register stack.

[0087] Specifically, the lane execution unit 10333 is further configured to:

[0088] After the execution of the microinstruction is completed, the entry of the write-back state of the lane register write-back state table 1032 is updated, and second confirmation information is sent to the corresponding lane execution state management subunit 10341.

[0089] ​​The execution state management unit 1034 is further configured to:

[0090] After receiving the first confirmation information sent by the memory access unit 1035 and the second confirmation information sent by the corresponding path execution unit 10333 received by all the path execution state management sub-units 10341, the notification signal of the completion of the vector instruction execution is sent to the scalar processing unit 104.

[0091] The path execution unit 10333 directly executes micro-instructions. In the normal pipeline process, after executing a micro-instruction, the path execution unit 10333 updates the related entry of the path register write-back state table 1032, and changes the current used vector register state from the working state to the available state, thereby quickly providing the basis for the reference of the main scheduler 1031.

[0092] In the decoupled processor 100, when the vector processing unit 103 completes the execution of all the vector instructions, the notification signal needs to be transmitted to the scalar processing unit 104. In the embodiment of the present application, the execution state management unit 1034 which uniformly manages all the data paths is used to realize this process. In the embodiment of the present application, the first confirmation information is mainly used to judge the execution state of the vector memory instruction (and the corresponding memory sub-request), and the second confirmation information is mainly used to judge the execution state of the micro-instruction. The notification signal needs to be sent to the scalar execution unit 104 after the vector execution unit 103 completely executes all the parts (memory sub-requests and micro-instructions) of the vector instruction.

[0093] Different from the splitting process of the vector instruction related to the read / write of the path register stack by the main scheduler 1031 in the above embodiment, for the processing mode of the vector load instruction related to the loading of data from the storage unit to the vector register stack data storage, the memory access unit 1035 is further configured to:

[0094] receive the vector instruction from the main scheduler 1031, if the vector instruction is a vector load instruction, split the vector memory instruction into a plurality of memory sub-requests;

[0095] send the memory sub-requests to the memory access scheduling unit 105 as the vector memory requests, and obtain the memory response information corresponding to the vector memory requests from the memory access scheduling unit 105, and according to the memory response information, send the corresponding register write request to the path register stack 10332, the register write request is used to write the data corresponding to the vector memory request into the path register stack 10332;

[0096] after the execution of all the memory sub-requests is completed, send the first confirmation information to the execution state management unit 1034.

[0097] Different from steps S201-S204, the vector load instruction of loading data from the storage unit to the vector register stack does not need the main scheduler 1031 to split the microinstruction, but directly makes the memory access request to the storage unit 106 by the memory access unit 1035.

[0098] The execution state management unit 1034 is further configured to:

[0099] After receiving the first confirmation information sent by the memory access unit 1035 and all the register write requests are executed, the scalar processing unit 104 is sent a notification signal of the execution completion of the vector instruction.

[0100] Similarly, for the execution of the vector load instruction related to the loading of data from the storage unit to the vector register stack, the microinstruction splitting by the main scheduler 1031 is not needed in the execution process, and thus the execution state of the memory sub-request and the execution state of the corresponding register write request are used to determine whether the vector processing unit 103 executes all the vector instructions.

[0101] In the embodiment of the present application, the operation of sending the vector memory request and / or the scalar memory request to the storage unit 106 is performed by the memory scheduling unit 105 arranged at the next stage of the scalar processing unit 104 and the vector processing unit 103, and the preset scheduling mode is:

[0102] According to the order of the scalar instruction and / or the vector instruction parsed from the instruction by the decoding unit 102, the vector memory request and / or the scalar memory request is sent to the storage unit 106 in order; or,

[0103] According to the preset priority, the vector memory request and / or the scalar memory request is sent to the storage unit 106 out of order.

[0104] Through the above design, the memory scheduling unit 105 in the embodiment of the present application determines how the vector and scalar memory requests compete for the storage resources, so as to determine the characteristics of the processor 100 according to different hardware use environments. Figure 5 The memory instruction execution flow diagram is shown in the figure:

[0105] S401, after the decoding unit 102 obtains the instruction, the vector memory instruction and the scalar memory instruction are judged, and the instruction is sent to the vector or scalar processing unit according to the judgment result;

[0106] S402, the vector processing unit 103 and the scalar processing unit 104 correspondingly execute the vector instruction and generate the vector and scalar memory request;

[0107] S403, the memory access scheduling unit 105 determines the sending order of the vector and scalar memory access requests according to a preset scheduling mode, and sends the memory access requests to the storage unit 106 according to the order;

[0108] S404, the storage unit 106 reads relevant data according to the vector and scalar memory access requests.

[0109] Among them, the sequentially executed mode is suitable for the use environment dominated by scalar operation and sensitive to delay (such as real-time control, low-power device); the out-of-order execution mode is suitable for the use environment with high proportion of vector operation and sensitive to throughput (such as AI, scientific calculation). During implementation, it can be set according to actual needs.

[0110] The processor implemented based on the decoupled vector memory access unit has the beneficial effects that: in the processor, a separate path execution state management subunit is arranged in each data path of the vector processing unit, which provides more accurate scheduling reference for the microinstruction splitting processing of the main scheduler, reduces the difficulty of microinstruction tracking and management, optimizes the register read request path, and reduces the timing risk; and the architecture manages the order of scalar and vector memory access requests through a unified memory access scheduling unit, reduces the management difficulty of memory consistency, and enhances the reliability of the processor system.

[0111] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to complete, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments of the method. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0112] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0113] The embodiments of the present application are described above with reference to the accompanying drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, but not restrictive, and the person of ordinary skill in the art can make many equivalent changes in form without departing from the purpose of the present application and the scope of protection of the claims, and all the changes are within the protection of the present application.

Claims

1. A processor based on a decoupled vector processing unit split based on data paths, characterized in that, The processor comprises a fetch unit, a decode unit, a vector processing unit, a scalar processing unit, a memory access scheduling unit and a storage unit, wherein: The fetch unit is configured to fetch instructions from a processor memory and send the instructions to the decode unit; The decode unit is configured to analyze the instructions and identify scalar instructions and / or vector instructions from the instructions, wherein: when the vector instructions are identified, the vector instructions are sent to the vector processing unit; and when the scalar instructions are identified, the scalar instructions are sent to the scalar processing unit; The vector processing unit is configured to execute the vector instructions and, when the vector instructions are vector memory access instructions, generate vector memory access requests for requesting access to the storage unit according to the vector memory access instructions; The scalar processing unit is configured to execute the scalar instructions and, when the scalar instructions are scalar memory access instructions, generate scalar memory access requests for requesting access to the storage unit according to the scalar memory access instructions; The memory access scheduling unit is configured to send the vector memory access requests and / or the scalar memory access requests to the storage unit according to a preset scheduling mode; The storage unit is configured to perform memory access according to the vector memory access requests and / or the scalar memory access requests and return corresponding memory access response information to the vector processing unit and / or the scalar processing unit; The vector processing unit comprises a main scheduler, a plurality of lane register write-back state tables, a data lane unit and an execution state management unit, and the data lane unit comprises a lane register stack, wherein: The main scheduler is configured to determine whether the vector instructions belong to arithmetic instructions or vector storage instructions, and if so, split the vector instructions into a plurality of micro-instructions according to a data lane bandwidth of the data lane unit, the number of the micro-instructions being the same as the number of the lane register write-back state tables; Each entry in each of the lane register write-back state tables is configured to record a write-back state of a lane register required by a micro-instruction, and the write-back state entry is available or working; The data lane unit comprises a plurality of data lanes, each of the data lanes comprises an independent lane scheduler, a lane register stack and a lane execution unit, and one of the data lanes corresponds to one of the lane register write-back state tables, wherein: The lane scheduler is configured to listen to the write-back state recorded by the lane register write-back state table, and when a lane register in the lane register stack is available, send a corresponding register read request to the lane register stack according to the micro-instruction; The lane execution unit is configured to execute the micro-instruction according to the lane register data read from the lane register stack according to the register read request; The execution state management unit comprises a plurality of lane execution state management sub-units, and one of the lane execution state management sub-units corresponds to one of the data lanes, and the lane execution state management sub-unit is configured to monitor the execution state of the micro-instruction.

2. The decoupled vector processing unit based on data lane partitioning processor of claim 1, wherein, The vector processing unit further comprises a memory unit, and the memory unit is configured to: receiving the vector instruction from the main scheduler, if the vector instruction is a vector store instruction, receiving the lane register data read by the lane execution unit, and splitting the vector memory instruction into a plurality of memory sub-requests; sending the memory sub-requests to the memory scheduling unit as the vector memory requests, and obtaining the memory response information corresponding to the vector memory requests from the memory scheduling unit; after all the memory sub-requests are executed, sending first confirmation information to the execution state management unit.

3. The decoupled vector processing unit based on data lane partitioning processor of claim 1, wherein, The vector processing unit further comprises a cross-lane unit, configured to: receive the micro-instructions split by the main scheduler and the lane register data read by the data lane unit, and execute the micro-instructions according to the lane register data, and write the execution results of the micro-instructions back to the lane register stack of the corresponding data lane unit.

4. The decoupled vector processing unit based on data lane partitioning processor of claim 2, wherein, The lane execution unit is further configured to: after the execution of the micro-instructions is completed, update the entry of the write-back state of the lane register write-back state table, and send second confirmation information to the corresponding lane execution state management sub-unit.

5. The decoupled vector processing unit based on data lane partitioning processor of claim 4, wherein, The execution state management unit is further configured to: after receiving the first confirmation information sent by the memory unit and the second confirmation information sent by all the lane execution state management sub-units, send a notification signal of the completion of the execution of the vector instruction to the scalar processing unit.

6. The data path split based decoupled vector processing unit processor of claim 2, wherein, The memory unit is further configured to: receive the vector instruction from the main scheduler, if the vector instruction is a vector load instruction, split the vector memory instruction into a plurality of memory sub-requests; send the memory sub-requests to the memory scheduling unit as the vector memory requests, and obtain the memory response information corresponding to the vector memory requests from the memory scheduling unit, and simultaneously send corresponding register write requests to the lane register stack according to the memory response information, the register write requests being used to write data corresponding to the vector memory requests into the lane register stack; after all the memory sub-requests are executed, send first confirmation information to the execution state management unit.

7. The decoupled vector processing unit based on data lane partitioning processor of claim 6, wherein, The execution state management unit is further configured to: after receiving the first confirmation information sent by the memory unit and the second confirmation information sent by all the lane execution state management sub-units, send a notification signal of the completion of the execution of the vector instruction to the scalar processing unit.

8. The data path split based decoupled vector processing unit processor of claim 1, wherein, The preset scheduling mode is: sending the vector memory requests and / or the scalar memory requests to the storage unit in sequence according to the order of the scalar instructions and / or the vector instructions parsed from the instructions by the decoding unit; or sending the vector memory requests and / or the scalar memory requests to the storage unit out of order according to a preset priority.

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