A method and system for evaluating computer hardware performance based on simulation model

Abstract

The present invention provides a method and system for evaluating computer hardware performance based on a simulation model, and relates to the technical field of computer performance evaluation. The present invention constructs hardware component models such as processors, memory, and I / O by parsing a system structure description file, and performs semantic analysis on the instruction stream or parallel computing graph of the application to be evaluated to form a task load model. The model is input into an event-driven scheduling module, and simulation is performed on the hardware component model to generate a task-resource mapping and record task latency, communication volume, and power consumption. The average response latency, data bandwidth, and unit energy consumption are calculated based on the simulation data, and an evaluation report is output for comparison with the performance baseline. The present invention can realize multi-dimensional performance prediction for real loads and can be used for architecture optimization and solution selection.

Description

Technical Field

[0001] The present invention relates to the technical field of computer performance evaluation, and in particular to a method and system for evaluating computer hardware performance based on a simulation model. Background Art

[0002] With the rapid evolution of computer architecture, the complexity of processors, memory, GPUs, and I / O subsystems continues to increase. Traditional hardware performance evaluation methods rely on real-world measurements, obtaining performance metrics by running standard performance testing software (such as SPEC and PassMark). While intuitive, these methods are limited in adaptability and repeatability, making it difficult to conduct rapid comparative analysis in the early stages of a design or across multiple hardware configurations.

[0003] In recent years, with advancements in virtualization technology, system simulation, and modeling capabilities, researchers have increasingly favored using software-based simulations to predict hardware performance. This is particularly true during the design phase of system-on-chip (SoC) and high-performance server architectures, where simulation analysis based on hardware behavior models has become a trend. Furthermore, AI-assisted performance modeling methods are emerging to improve evaluation accuracy and inference speed.

[0004] Current simulation models face several challenges in hardware performance evaluation: First, they lack a high-fidelity performance mapping mechanism for general computing tasks, resulting in significant discrepancies between model predictions and actual operational values. Second, the evaluation dimensions are relatively single, often overlooking the coordinated constraints of multiple metrics (such as latency, bandwidth, and power consumption). Third, they lack a dynamic input task load-driven mechanism, making it difficult to reflect the hardware's response behavior under real-world workloads. Therefore, a simulation performance evaluation method that comprehensively considers load characteristics, hardware model accuracy, and multi-metric output is urgently needed. Summary of the Invention

[0005] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide a method and system for evaluating computer hardware performance based on a simulation model, which realizes multi-index simulation evaluation of hardware performance for real task loads and improves the accuracy and interpretability of performance prediction.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A method for evaluating computer hardware performance based on a simulation model, comprising:

[0008] Based on the system structure description file of the target computer system, build the hardware component model of each computing hardware unit;

[0009] Based on the instruction stream or parallel computation graph of the application to be evaluated, the task operation sequence, resource call behavior, and data dependency are extracted to form a task load model.

[0010] Input the task load model into the scheduling module, and use the scheduling module to start the task scheduling process under the event-driven mechanism to control the simulation execution of each task in the corresponding hardware component model, dynamically generate the resource mapping relationship between the task and the hardware component model, and record the task execution delay, data communication overhead and power consumption indicators;

[0011] Determine the resource mapping relationship, task execution delay, data communication overhead and power consumption indicators as simulation data;

[0012] Based on the simulation data, a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption is constructed, and the multi-index performance evaluation result is horizontally compared with the preset performance baseline to obtain a performance evaluation report.

[0013] Preferably, it also includes:

[0014] The performance evaluation report is used as feedback input to iteratively optimize key parameters of the hardware component model; the key parameters include: processing delay parameters, communication bandwidth parameters, power consumption model parameters and resource capacity parameters.

[0015] Preferably, based on the system structure description file of the target computer system, a hardware component model of each computing hardware unit is constructed, including:

[0016] Reading a system structure description file of the target computer system; the system structure description file includes processor structure, memory hierarchy, interconnection topology and I / O interface configuration parameters;

[0017] Parsing the system structure description file to extract structural parameters and operating characteristic parameters of each computing hardware unit; the structural parameters and operating characteristic parameters include main frequency, cache capacity, bus width, access delay and power consumption model coefficient;

[0018] Establishing corresponding hardware component models according to the extracted parameters; the hardware component models include a processor model, a memory model, an I / O model and an interconnection structure model;

[0019] The constructed hardware component models are stored in a model library of the simulation platform in a modular form.

[0020] Preferably, based on the instruction stream or parallel computation graph of the application to be evaluated, the task operation sequence, resource call behavior, and data dependency are extracted to form a task load model, including:

[0021] Obtaining an instruction stream or parallel computation graph of the application to be evaluated; the instruction stream is a sequence of instructions generated by the application after compilation or during execution; the parallel computation graph represents the control and data dependencies between multiple tasks;

[0022] Performing semantic parsing on the instruction stream or parallel computing graph to extract task operation types therein; the task operation types include arithmetic operations, logical judgments, memory access operations, and communication instructions;

[0023] Analyze the calling relationship between the instruction stream or parallel computing graph and hardware resources to determine the calling path and occupied cycles of each task on the processor, memory, cache and I / O resources, and generate a description of the resource calling behavior;

[0024] Build a data dependency graph between tasks based on the preset read and write order to represent the execution constraints of tasks before and after;

[0025] The task operation type, the resource call behavior description, and the before and after execution constraints are encapsulated into structured data to form a task load model.

[0026] Preferably, the calling relationship between the instructions or nodes and the hardware resources is analyzed to determine the calling path and occupied cycles of each task on the processor, memory, cache and I / O resources, and generate a description of the resource calling behavior, including:

[0027] Parsing the task nodes in the instruction stream or parallel computation graph and identifying the resource usage fields involved in each instruction or task node; the resource usage fields include register read and write, memory access, and I / O operations;

[0028] Establishing a call mapping path between task operations and target resources based on the resource usage field and the hierarchical structure of the hardware component model; the call path includes the access sequence of the processor pipeline, caches at various levels, main memory channels, and I / O subsystems;

[0029] estimating the occupancy period of each task on the resource call path by combining the processing delay parameter and bandwidth parameter preset in the hardware component model;

[0030] The resource call path and corresponding occupation period of each task are encapsulated into structured description information to form a resource call behavior description.

[0031] Preferably, a data dependency graph between tasks is constructed based on a preset read and write order to represent the execution constraints before and after the tasks, including:

[0032] Extracting data access operations involved in the task operation sequence; the data access operations include read operations and write operations in each task, and identifying the shared variables and data objects involved;

[0033] Analyze the access relationship between different tasks to the same data object according to the preset read and write order rules, and identify data access dependencies such as read-after-write, write-after-read, or write-after-write.

[0034] Establishing directed dependency edges between tasks based on the data access dependency to represent the forward and backward execution constraint relationship between tasks;

[0035] All the directed dependency edges are constructed into a data dependency graph; the data dependency graph is a directed acyclic graph, which is used to represent the executable sequence and parallel scope of tasks while maintaining data consistency.

[0036] Preferably, the task load model is input into a scheduling module, and the scheduling module is used to start a task scheduling process under an event-driven mechanism to control each task to simulate execution in the corresponding hardware component model, dynamically generate a resource mapping relationship between the task and the hardware component model, and simultaneously record task execution delay, data communication overhead and power consumption indicators, including:

[0037] Instantiate the event-driven scheduling module in the simulation platform;

[0038] The scheduling module loads and registers the hardware component model from the model library of the simulation platform on demand;

[0039] Create a global simulation clock and initialize the event queue to provide a unified time base and event management structure for task scheduling;

[0040] Writing the task load model into the ready task list of the event queue and setting an initial scheduling event according to the data dependency graph;

[0041] When the initial scheduling event is triggered, the scheduling module selects the currently executable task according to the preset scheduling strategy and queries the real-time resource occupancy status of each hardware component model;

[0042] Binding the selected currently executable task to the available hardware component model instance, generating and dynamically updating a resource mapping relationship between the task and the hardware component model;

[0043] During the task simulation execution, the scheduling module is used to periodically send monitoring events, and the task execution delay, data communication overhead and power consumption indicators are collected and recorded according to the global simulation clock;

[0044] When all tasks are completed or the simulation termination conditions are reached, the final resource mapping relationship and the accumulated task execution delay, data communication overhead and power consumption indicators are output.

[0045] Preferably, a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption is constructed based on the simulation data, and the multi-index performance evaluation result is horizontally compared with a preset performance baseline to obtain a performance evaluation report, including:

[0046] Formatting the simulation data, extracting single-task execution delay, data communication volume, and power consumption records, and aggregating them by task number;

[0047] Calculate the average response delay, total data transmission bandwidth, and unit task energy consumption respectively; where average response delay = sum of all task execution delays / number of tasks; total data transmission bandwidth = sum of all task data communication volume / simulation duration; unit task energy consumption = sum of all task power consumption / number of tasks;

[0048] Determining the average response delay, the total data transmission bandwidth, and the unit task energy consumption as a multi-index performance evaluation result;

[0049] Retrieving a baseline indicator set corresponding to the current task load type from a database of preset performance baselines, and performing item-by-item difference calculations between the multi-indicator performance evaluation result and the baseline indicator set to obtain horizontal comparison data;

[0050] According to the preset report template, the multi-index performance evaluation results and the horizontal comparison data are used to generate a performance evaluation report, and output it to the user interface.

[0051] A computer hardware performance evaluation system based on a simulation model, comprising:

[0052] A hardware modeling unit, used to construct a hardware component model of each computing hardware unit based on a system structure description file of a target computer system;

[0053] The task modeling unit is used to extract the task operation sequence, resource call behavior and data dependency based on the instruction stream or parallel computing graph of the application to be evaluated to form a task load model;

[0054] a simulation scheduling unit, configured to input the task load model into a scheduling module, and utilize the scheduling module to initiate a task scheduling process under an event-driven mechanism to control each task to be simulated and executed in the corresponding hardware component model, dynamically generate a resource mapping relationship between the task and the hardware component model, and simultaneously record task execution latency, data communication overhead, and power consumption indicators;

[0055] A simulation data generating unit, configured to determine the resource mapping relationship, task execution delay, data communication overhead, and power consumption index as simulation data;

[0056] The performance evaluation unit is used to construct a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption based on the simulation data, and compare the multi-index performance evaluation result with a preset performance baseline to obtain a performance evaluation report.

[0057] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0058] The present invention overcomes the defects of the existing technology in the evaluation means of insufficient accuracy, lack of dynamics and multi-dimensional performance coverage. By constructing a hardware component model that strictly corresponds to the target system structure, and combining it with the task load model of the application to be evaluated, task scheduling simulation is realized under an event-driven mechanism, which can accurately restore the scheduling behavior and running load of tasks on different resources. The resource mapping relationship, execution delay, communication overhead and power consumption indicators collected on this basis are uniformly defined as simulation data, which supports the construction of multi-index performance evaluation results under a unified evaluation system, and is horizontally compared with the preset performance baseline, realizing the quantification and visualization of the performance differences of different computing architectures under real load conditions, and significantly improving the engineering adaptability and decision-making guidance value of the evaluation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A flow chart of a method provided by an embodiment of the present invention;

[0061] Figure 2 A schematic diagram of the system structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0063] The purpose of the present invention is to provide a computer hardware performance evaluation method and system based on a simulation model, which can realize multi-index simulation evaluation of hardware performance for real task loads and improve the accuracy and interpretability of performance prediction.

[0064] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0065] Figure 1 A flow chart of the method provided in the embodiment of the present invention is shown in FIG. Figure 1 As shown, the present invention provides a method for evaluating computer hardware performance based on a simulation model, comprising:

[0066] Step 100: Building a hardware component model of each computing hardware unit based on the system structure description file of the target computer system;

[0067] Step 200: Based on the instruction stream or parallel computation graph of the application to be evaluated, extract the task operation sequence, resource call behavior, and data dependency to form a task load model;

[0068] Step 300: Input the task load model into the scheduling module, and use the scheduling module to start the task scheduling process under the event-driven mechanism to control the simulation execution of each task in the corresponding hardware component model, dynamically generate the resource mapping relationship between the task and the hardware component model, and simultaneously record the task execution delay, data communication overhead and power consumption indicators;

[0069] Step 400: Determine the resource mapping relationship, task execution delay, data communication overhead and power consumption index as simulation data;

[0070] Step 500: Construct a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption based on the simulation data, and compare the multi-index performance evaluation result with the preset performance baseline to obtain a performance evaluation report.

[0071] Preferably, it also includes:

[0072] The performance evaluation report is used as feedback input to iteratively optimize key parameters of the hardware component model; the key parameters include: processing delay parameters, communication bandwidth parameters, power consumption model parameters and resource capacity parameters.

[0073] Specifically, in this embodiment, the performance evaluation report is used as feedback input to iteratively optimize the key parameters of the hardware component model. Specifically, this embodiment first analyzes the multi-index performance evaluation results generated in the performance evaluation report, calculates the difference between each performance indicator and the preset performance baseline, and obtains an error vector. Subsequently, an optimization objective function is constructed with the error vector as input, and an optimization algorithm suitable for multi-parameter nonlinear problems is used to solve it, such as a numerical optimization method based on a gradient adjustment strategy or an evolutionary algorithm based on a search strategy. Through the optimization process, key parameter values ​​for updating the hardware component model are obtained, including parameters such as processing delay, communication bandwidth, power consumption model, and resource capacity. In this embodiment, the updated parameters are written into the corresponding hardware component model and reloaded into the simulation platform, and the simulation process is rerun under the same task load model conditions to generate a new performance evaluation report. The optimization process is continuously iterated with error vector convergence as the criterion, and ultimately a hardware component model with high evaluation accuracy and universal adaptability under the current load is obtained.

[0074] Preferably, based on the system structure description file of the target computer system, a hardware component model of each computing hardware unit is constructed, including:

[0075] Reading a system structure description file of the target computer system; the system structure description file includes processor structure, memory hierarchy, interconnection topology and I / O interface configuration parameters;

[0076] Parsing the system structure description file to extract structural parameters and operating characteristic parameters of each computing hardware unit; the structural parameters and operating characteristic parameters include main frequency, cache capacity, bus width, access delay and power consumption model coefficient;

[0077] Establishing corresponding hardware component models according to the extracted parameters; the hardware component models include a processor model, a memory model, an I / O model and an interconnection structure model;

[0078] The constructed hardware component models are stored in a model library of the simulation platform in a modular form.

[0079] Specifically, in this embodiment, the target computer system's system architecture description file is first read. This file can originate from an actual system configuration list, a system architecture diagram, or hardware resource description information generated by automated tools. The system architecture description file contains the structural configuration data of multiple hardware components, including the processor structure, memory hierarchy, interconnection topology, and the number and bandwidth configuration of I / O interfaces, providing a complete data foundation for the subsequent modeling process.

[0080] Next, the system structure description file is parsed to extract the structural parameters and operating characteristic parameters of each computing hardware unit. In this embodiment, the extracted parameters include the processor's main frequency, cache capacity, bus width, access latency of different levels of storage, and the power consumption model coefficients of each hardware module under typical load. These parameters can be confirmed through static configuration files, chip description documents, or experimental data tables, and converted into structured inputs through a parsing script for invocation by the model construction module.

[0081] After parameter extraction is completed, corresponding hardware component models are established based on the types and configuration requirements of different computing hardware units. This embodiment constructs a processor model, a memory model, an I / O model, and an interconnection structure model, each of which encapsulates its structure and performance parameters in a modular form. The established hardware component models are uniformly stored in the model library of the simulation platform. The model library supports model version management, on-demand loading, and parameterized instantiation, which is used for simulation scheduling and performance evaluation process calls of subsequent task loads.

[0082] Preferably, based on the instruction stream or parallel computation graph of the application to be evaluated, the task operation sequence, resource call behavior, and data dependency are extracted to form a task load model, including:

[0083] Obtaining an instruction stream or parallel computation graph of the application to be evaluated; the instruction stream is a sequence of instructions generated by the application after compilation or during execution; the parallel computation graph represents the control and data dependencies between multiple tasks;

[0084] Performing semantic parsing on the instruction stream or parallel computing graph to extract task operation types therein; the task operation types include arithmetic operations, logical judgments, memory access operations, and communication instructions;

[0085] Analyze the calling relationship between the instruction stream or parallel computing graph and hardware resources to determine the calling path and occupied cycles of each task on the processor, memory, cache and I / O resources, and generate a description of the resource calling behavior;

[0086] Build a data dependency graph between tasks based on the preset read and write order to represent the execution constraints of tasks before and after;

[0087] The task operation type, the resource call behavior description, and the before and after execution constraints are encapsulated into structured data to form a task load model.

[0088] In this embodiment, the instruction stream or parallel computation graph of the application to be evaluated is first obtained. The instruction stream can be extracted from the target application by a static compilation tool or a runtime analyzer, reflecting the instruction sequence during its specific execution process. The parallel computation graph represents the control relationship and data dependency structure between various computing tasks. It is often generated by a program modeling tool, a data flow analysis module, or a task scheduler, and is used to reflect the possible concurrent execution modes between tasks. These two types of input serve as the basic data sources for task load modeling.

[0089] Subsequently, the instruction stream or parallel computing graph is semantically parsed to extract the task operation types contained therein, including arithmetic operations, logical judgments, memory accesses, and communication interactions. This embodiment uses a structured syntax tree or instruction classification table to identify and classify task operations, and combines the distribution structure of various hardware resources in the system to further analyze the calling relationship between task instructions and processors, memory, cache, and I / O resources. On this basis, combined with the task granularity, instruction complexity, and the delay and bandwidth parameters in the preset resource model, the access path and occupancy cycle of each task operation to the corresponding resources are calculated to generate a corresponding resource calling behavior description.

[0090] Finally, based on the extracted instruction access sequence, a data dependency graph is constructed between tasks, identifying the forward and backward execution constraints caused by data read and write conflicts between tasks. This dependency represents task scheduling restrictions using directed edges, forming a structured task scheduling graph. This embodiment encapsulates task operation types, resource call behavior descriptions, and forward and backward execution constraints into structured data to form a complete task load model. This model serves as input to the simulation scheduling module for subsequent mapping scheduling and performance evaluation simulation in the hardware component model.

[0091] Preferably, the calling relationship between the instructions or nodes and the hardware resources is analyzed to determine the calling path and occupied cycles of each task on the processor, memory, cache and I / O resources, and generate a description of the resource calling behavior, including:

[0092] Parsing the task nodes in the instruction stream or parallel computation graph and identifying the resource usage fields involved in each instruction or task node; the resource usage fields include register read and write, memory access, and I / O operations;

[0093] Establishing a call mapping path between task operations and target resources based on the resource usage field and the hierarchical structure of the hardware component model; the call path includes the access sequence of the processor pipeline, caches at various levels, main memory channels, and I / O subsystems;

[0094] estimating the occupancy period of each task on the resource call path by combining the processing delay parameter and bandwidth parameter preset in the hardware component model;

[0095] The resource call path and corresponding occupation period of each task are encapsulated into structured description information to form a resource call behavior description.

[0096] In this embodiment, to analyze the call relationship between each task and hardware resources in the application to be evaluated, each task node in the instruction stream or parallel computation graph is first parsed. Specifically, the system traverses each instruction or each task node and extracts field information related to resource access. The resource usage fields include register read and write operations, various memory address access instructions, and I / O calls related to peripheral interaction. This parsing process can be implemented based on instruction format templates or static analysis tools to extract structured resource usage data, laying the foundation for subsequent call path derivation.

[0097] After completing the extraction of resource usage fields, the hierarchical structure of the hardware component model is further combined to establish a mapping path for the resource access process involved in each task operation. This embodiment identifies the access sequence of the processor pipeline, the first-level cache, the second-level cache, the main memory interface channel, and the peripheral I / O module in sequence according to the processor architecture and memory architecture, forming a complete call path from the task to the target resource. For each resource access operation, the system also marks the starting node (such as the computing core) and the end node (such as the target memory block or I / O port) in the path, and retains the logical access order and data flow information in the path.

[0098] After establishing the call path, the system estimates the access time of tasks along the call path, combining the processing delay and bandwidth parameters of each resource module in the pre-built hardware component model. The system then comprehensively calculates the occupied cycles of each instruction on each resource node based on factors such as the type of instruction and the bandwidth limitations and concurrency conflicts on the mapped path. Ultimately, the resource call path and occupied cycles corresponding to each task operation are integrated into a structured data description, forming a resource call behavior description that serves as a key component of the task load model and is used for subsequent scheduling and simulation modeling.

[0099] Preferably, a data dependency graph between tasks is constructed based on a preset read and write order to represent the execution constraints before and after the tasks, including:

[0100] Extracting data access operations involved in the task operation sequence; the data access operations include read operations and write operations in each task, and identifying the shared variables and data objects involved;

[0101] Analyze the access relationship between different tasks to the same data object according to the preset read and write order rules, and identify data access dependencies such as read-after-write, write-after-read, or write-after-write.

[0102] Establishing directed dependency edges between tasks based on the data access dependency to represent the forward and backward execution constraint relationship between tasks;

[0103] All the directed dependency edges are constructed into a data dependency graph; the data dependency graph is a directed acyclic graph, which is used to represent the executable sequence and parallel scope of tasks while maintaining data consistency.

[0104] In this embodiment, to construct a data dependency graph between tasks, the system first scans the extracted task operation sequences to identify the data access operations involved in each task, including read and write operations. Using semantic parsing and variable mapping mechanisms, the system identifies the shared variables or data objects involved in these operations, such as global variables, shared memory blocks, or I / O buffers. This process can be performed based on an abstract syntax tree or intermediate representation (IR), ensuring that the relationship between data objects and operations is accurately established.

[0105] The system then matches data access pairs across all tasks according to pre-set read-write order rules to analyze whether data access dependencies exist. These dependencies typically include read-after-write (RAW), write-after-read (WAR), and write-after-write (WAW). The system traverses accesses to the same data object between task pairs. When it detects that the preceding task writes to the object and the succeeding task reads or writes to the same object, it determines that an execution order constraint exists. The system generates directed edges for these dependencies, identifying the scheduling order required for data consistency.

[0106] After analyzing the access relationships of all task pairs, the system organizes the identified directed dependency edges by task number into a data dependency graph. This graph is a directed acyclic graph (DAG), where each node represents a specific task and each edge represents the forward and backward execution constraints formed by data dependencies. This graph structure allows the system to clearly define the executable order and parallel execution range between tasks while maintaining data consistency, providing structured support for subsequent scheduling modules to initialize scheduling events and perform dependency checks.

[0107] Preferably, the task load model is input into a scheduling module, and the scheduling module is used to start a task scheduling process under an event-driven mechanism to control each task to simulate execution in the corresponding hardware component model, dynamically generate a resource mapping relationship between the task and the hardware component model, and simultaneously record task execution delay, data communication overhead and power consumption indicators, including:

[0108] Instantiate the event-driven scheduling module in the simulation platform;

[0109] The scheduling module loads and registers the hardware component model from the model library of the simulation platform on demand;

[0110] Create a global simulation clock and initialize the event queue to provide a unified time base and event management structure for task scheduling;

[0111] Writing the task load model into the ready task list of the event queue and setting an initial scheduling event according to the data dependency graph;

[0112] When the initial scheduling event is triggered, the scheduling module selects the currently executable task according to the preset scheduling strategy and queries the real-time resource occupancy status of each hardware component model;

[0113] Binding the selected currently executable task to the available hardware component model instance, generating and dynamically updating a resource mapping relationship between the task and the hardware component model;

[0114] During the task simulation execution, the scheduling module is used to periodically send monitoring events, and the task execution delay, data communication overhead and power consumption indicators are collected and recorded according to the global simulation clock;

[0115] When all tasks are completed or the simulation termination conditions are reached, the final resource mapping relationship and the accumulated task execution delay, data communication overhead and power consumption indicators are output.

[0116] In this embodiment, the simulation platform first instantiates the event-driven scheduling module and loads hardware component model instances such as processor models, memory models, I / O models, and interconnection structure models from the model library on demand through an interface. Subsequently, the platform creates a global simulation clock and initializes the event queue, pushing basic events such as system startup events and resource status update events into the queue, and establishes a unified time base and event management structure based on this. After initialization is completed, the system writes the constructed task load model into the ready task list of the event queue and generates a corresponding dependency detection event for each task based on the aforementioned data dependency graph to ensure that the subsequent scheduling process can correctly identify the executable status of the task.

[0117] When the first dependency detection events in the ready queue are triggered, the scheduling module uses a preset scheduling strategy (e.g., based on priority or resource minimization) to select the currently executable task. The scheduling module queries the resource usage status of each hardware component model in real time, determines the availability of processor cores, cache levels, memory channels, and I / O interfaces, and binds the selected task to a hardware component model instance that meets the resource constraints. After binding, the scheduling module immediately updates the resource mapping table between the task and the hardware component model, generates the corresponding task start event and expected completion event, and writes them back to the event queue, achieving a closed-loop drive for task scheduling and execution.

[0118] During task simulation execution, the scheduling module periodically triggers monitoring events based on the global simulation clock's advance. It reads the status registers or counters of each hardware component model, collecting and accumulating task execution latency, data communication volume, and energy consumption statistics. If the monitoring event detects that all tasks have completed, or the simulation reaches a preset termination condition, the scheduling module stops advancing the clock and freezes the event queue. At this point, the system outputs the final resource mapping relationship, along with the accumulated task execution latency, total data communication overhead, and power consumption metrics, as complete simulation data results, providing input for subsequent multi-metric performance evaluation.

[0119] Preferably, a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption is constructed based on the simulation data, and the multi-index performance evaluation result is horizontally compared with a preset performance baseline to obtain a performance evaluation report, including:

[0120] Formatting the simulation data, extracting single-task execution delay, data communication volume, and power consumption records, and aggregating them by task number;

[0121] Calculate the average response delay, total data transmission bandwidth, and unit task energy consumption respectively; where average response delay = sum of all task execution delays / number of tasks; total data transmission bandwidth = sum of all task data communication volume / simulation duration; unit task energy consumption = sum of all task power consumption / number of tasks;

[0122] Determining the average response delay, the total data transmission bandwidth, and the unit task energy consumption as a multi-index performance evaluation result;

[0123] Retrieving a baseline indicator set corresponding to the current task load type from a database of preset performance baselines, and performing item-by-item difference calculations between the multi-indicator performance evaluation result and the baseline indicator set to obtain horizontal comparison data;

[0124] According to the preset report template, the multi-index performance evaluation results and the horizontal comparison data are used to generate a performance evaluation report, and output it to the user interface.

[0125] In this embodiment, after the simulation is complete, the resulting simulation data is first formatted. The system reads the raw records of task execution latency, data communication volume, and power consumption according to the task number. Data generated by the same task in different time slices is aggregated into a unified data table, and invalid or duplicate sampling points are removed to obtain a structured set of single-task metrics. This set is stored as a four-tuple of "task number - execution latency - communication volume - power consumption", providing a clear data dimension for subsequent statistical operations.

[0126] The system then uses aggregation functions in the statistics module to calculate global performance metrics: First, the execution latency of all tasks is summed and divided by the number of tasks to obtain the average response latency; second, the data communication volume of all tasks is summed and divided by the simulation duration to obtain the total data transmission bandwidth; and third, the power consumption of all tasks is summed and divided by the number of tasks to obtain the energy consumption per task. These three calculation results are encapsulated as a triplet of "average response latency, total data transmission bandwidth, and energy consumption per task," forming the multi-metric performance evaluation result. This is then written into the performance results table along with the task number and simulation configuration.

[0127] After generating the multi-metric performance evaluation results, the system connects to a pre-set performance baseline database, retrieves the baseline metric set corresponding to the current task load type, and calculates the difference values ​​item by item along the same dimension to obtain horizontal comparison data. Finally, the system populates the multi-metric performance evaluation results and horizontal comparison data into a report structure according to a pre-set report template, automatically generating a performance evaluation report that includes a performance radar chart, a difference bar chart, and a metric summary table. This report is then presented through the user interface or exported as a PDF file, allowing developers and hardware designers to quickly compare the performance differences between different architectures or parameter configurations.

[0128] Corresponding to the above method, such as Figure 2 As shown, this embodiment also provides a computer hardware performance evaluation system based on a simulation model, including:

[0129] A hardware modeling unit, used to construct a hardware component model of each computing hardware unit based on a system structure description file of a target computer system;

[0130] The task modeling unit is used to extract the task operation sequence, resource call behavior and data dependency based on the instruction stream or parallel computing graph of the application to be evaluated to form a task load model;

[0131] a simulation scheduling unit, configured to input the task load model into a scheduling module, and utilize the scheduling module to initiate a task scheduling process under an event-driven mechanism to control each task to be simulated and executed in the corresponding hardware component model, dynamically generate a resource mapping relationship between the task and the hardware component model, and simultaneously record task execution latency, data communication overhead, and power consumption indicators;

[0132] A simulation data generating unit, configured to determine the resource mapping relationship, task execution delay, data communication overhead, and power consumption index as simulation data;

[0133] The performance evaluation unit is used to construct a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption based on the simulation data, and compare the multi-index performance evaluation result with a preset performance baseline to obtain a performance evaluation report.

[0134] The beneficial effects of the present invention are as follows:

[0135] (1) The present invention implements a high-fidelity simulation environment that corresponds one-to-one with the actual hardware structure by parsing the target computer system description file into modular hardware component models such as processor model, memory model, I / O model and interconnection structure model. Compared with traditional evaluation methods that rely on benchmark scores, the present invention can accurately reflect the latency, bandwidth and power consumption characteristics of different hardware units in the early design stage, thereby significantly improving the accuracy of performance prediction and shortening the hardware prototype verification cycle.

[0136] (2) The present invention converts the instruction stream or parallel computation graph of the application to be evaluated into a task load model, and simulates the dynamic interaction between tasks and hardware resources within an event-driven scheduling framework. It generates task-resource mapping relationships in real time and simultaneously records execution latency, communication overhead, and power consumption indicators. This breaks through the limitations of existing technologies that have a single evaluation dimension and lack runtime data association, and realizes multi-dimensional performance acquisition that is load-related and resource-traceable.

[0137] (3) By calculating the average response delay, total data transmission bandwidth and unit task energy consumption of the simulation data and comparing them horizontally with the preset performance baseline, the performance evaluation report output by the present invention can intuitively display the advantages and bottlenecks of each hardware configuration under real load in the form of quantitative differences; the report, combined with visual charts, provides chip designers and system integrators with a basis for quick decision-making, reducing the manpower and experimental costs of comparing multiple solutions.

[0138] (4) This invention further introduces a closed-loop feedback mechanism for performance evaluation results, using an optimization algorithm to iteratively adjust key parameters such as processing delay, communication bandwidth, power consumption model, and resource capacity, continuously revising the accuracy of the hardware component model. This self-learning iterative process enables the simulation environment to continuously adapt to hardware evolution and load changes, improving the versatility and sustainable application value of the method and laying the foundation for subsequent automated hardware design space exploration.

[0139] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0140] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A method for evaluating computer hardware performance based on a simulation model, characterized in that: include: S1. Based on the system structure description file of the target computer system, build the hardware component model of each computing hardware unit; S2. Based on the instruction stream or parallel computation graph of the application to be evaluated, extract the task operation sequence, resource call behavior, and data dependency to form a task load model; S3. Input the task load model into the scheduling module, and use the scheduling module to start the task scheduling process under the event-driven mechanism to control the simulation execution of each task in the corresponding hardware component model, dynamically generate the resource mapping relationship between the task and the hardware component model, and record the task execution delay, data communication overhead and power consumption indicators; S4, determining the resource mapping relationship, task execution delay, data communication overhead and power consumption index as simulation data; S5. Construct a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption based on the simulation data, and compare the multi-index performance evaluation result with a preset performance baseline to obtain a performance evaluation report; Step S2 includes: Obtaining an instruction stream or parallel computation graph of the application to be evaluated; the instruction stream is a sequence of instructions generated by the application after compilation or during execution; the parallel computation graph represents the control and data dependencies between multiple tasks; Performing semantic parsing on the instruction stream or parallel computing graph to extract task operation types therein; the task operation types include arithmetic operations, logical judgments, memory access operations, and communication instructions; Analyze the calling relationship between the instruction stream or parallel computing graph and hardware resources to determine the calling path and occupied cycles of each task on the processor, memory, cache and I / O resources, and generate a description of the resource calling behavior; Build a data dependency graph between tasks based on the preset read and write order to represent the execution constraints of tasks before and after; Encapsulating the task operation type, the resource call behavior description, and the pre- and post-execution constraints into structured data to form a task load model; Step S3 includes: Instantiate the event-driven scheduling module in the simulation platform; The scheduling module loads and registers the hardware component model from the model library of the simulation platform on demand; Create a global simulation clock and initialize the event queue to provide a unified time base and event management structure for task scheduling; Writing the task load model into the ready task list of the event queue and setting an initial scheduling event according to the data dependency graph; When the initial scheduling event is triggered, the scheduling module selects the currently executable task according to the preset scheduling strategy and queries the real-time resource occupancy status of each hardware component model; Binding the selected currently executable task to an available hardware component model instance, generating and dynamically updating a resource mapping relationship between the task and the hardware component model; During the task simulation execution, the scheduling module is used to periodically send monitoring events, and the task execution delay, data communication overhead and power consumption indicators are collected and recorded according to the global simulation clock; When all tasks are completed or the simulation termination conditions are reached, the final resource mapping relationship and the accumulated task execution delay, data communication overhead and power consumption indicators are output.

2. The method for evaluating computer hardware performance based on a simulation model according to claim 1, wherein: Also includes: Iteratively optimizing key parameters of the hardware component model using the performance evaluation report as feedback input; The key parameters include: processing delay parameters, communication bandwidth parameters, power consumption model parameters and resource capacity parameters.

3. The method for evaluating computer hardware performance based on a simulation model according to claim 1, wherein: Step S1 includes: Reading a system structure description file of the target computer system; the system structure description file includes processor structure, memory hierarchy, interconnection topology and I / O interface configuration parameters; Parsing the system structure description file to extract structural parameters and operating characteristic parameters of each computing hardware unit; the structural parameters and operating characteristic parameters include main frequency, cache capacity, bus width, access delay and power consumption model coefficient; Establishing corresponding hardware component models according to the extracted parameters; the hardware component models include a processor model, a memory model, an I / O model and an interconnection structure model; The constructed hardware component models are stored in a model library of the simulation platform in a modular form.

4. The method for evaluating computer hardware performance based on a simulation model according to claim 1, wherein: Analyze the call relationship between the instruction stream or parallel computation graph and hardware resources to determine the call path and occupied cycles of each task on the processor, memory, cache, and I / O resources, and generate a description of resource call behavior, including: Parsing the task nodes in the instruction stream or parallel computation graph and identifying the resource usage fields involved in each instruction or task node; the resource usage fields include register read and write, memory access, and I / O operations; Establishing a call mapping path between task operations and target resources based on the resource usage field and the hierarchical structure of the hardware component model; the call path includes the access sequence of the processor pipeline, caches at various levels, main memory channels, and I / O subsystems; estimating the occupancy period of each task on the resource call path by combining the processing delay parameter and bandwidth parameter preset in the hardware component model; The resource call path and corresponding occupation period of each task are encapsulated into structured description information to form a resource call behavior description.

5. The method for evaluating computer hardware performance based on a simulation model according to claim 1, wherein: Build a data dependency graph between tasks based on the preset read and write order to represent the execution constraints before and after the tasks, including: Extracting data access operations involved in the task operation sequence; the data access operations include read operations and write operations in each task, and identifying the shared variables and data objects involved; Analyze the access relationship between different tasks to the same data object according to the preset read and write order rules, and identify data access dependencies such as read-after-write, write-after-read, or write-after-write. Establishing directed dependency edges between tasks based on the data access dependency to represent the forward and backward execution constraint relationship between tasks; All the directed dependency edges are constructed into a data dependency graph; the data dependency graph is a directed acyclic graph, which is used to represent the executable sequence and parallel scope of tasks while maintaining data consistency.

6. The method for evaluating computer hardware performance based on a simulation model according to claim 1, wherein: Step S5 includes: Formatting the simulation data, extracting single-task execution delay, data communication volume, and power consumption records, and aggregating them by task number; Calculate the average response delay, total data transmission bandwidth, and unit task energy consumption respectively; where average response delay = sum of all task execution delays / number of tasks; total data transmission bandwidth = sum of all task data communication volume / simulation duration; unit task energy consumption = sum of all task power consumption / number of tasks; Determining the average response delay, the total data transmission bandwidth, and the unit task energy consumption as a multi-index performance evaluation result; Retrieving a baseline indicator set corresponding to the current task load type from a database of preset performance baselines, and performing item-by-item difference calculations between the multi-indicator performance evaluation result and the baseline indicator set to obtain horizontal comparison data; According to the preset report template, the multi-index performance evaluation results and the horizontal comparison data are used to generate a performance evaluation report, and output it to the user interface.

7. A computer hardware performance evaluation system based on a simulation model, characterized in that: For implementing the method for evaluating computer hardware performance based on a simulation model according to any one of claims 1 to 6, the system for evaluating computer hardware performance based on a simulation model comprises: A hardware modeling unit, used to construct a hardware component model of each computing hardware unit based on a system structure description file of a target computer system; The task modeling unit is used to extract the task operation sequence, resource call behavior and data dependency based on the instruction stream or parallel computing graph of the application to be evaluated to form a task load model; a simulation scheduling unit, configured to input the task load model into a scheduling module, and utilize the scheduling module to initiate a task scheduling process under an event-driven mechanism to control each task to be simulated and executed in the corresponding hardware component model, dynamically generate a resource mapping relationship between the task and the hardware component model, and simultaneously record task execution latency, data communication overhead, and power consumption indicators; A simulation data generating unit, configured to determine the resource mapping relationship, task execution delay, data communication overhead, and power consumption index as simulation data; The performance evaluation unit is used to construct a multi-index performance evaluation result including average response delay, total data transmission bandwidth, and unit task energy consumption based on the simulation data, and compare the multi-index performance evaluation result with a preset performance baseline to obtain a performance evaluation report.

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