Data processing methods, devices, interface circuits, and chips

Abstract

This disclosure belongs to the field of equipment inspection technology, and provides a data processing method, device, interface circuit, and chip. The method includes: a NOR flash memory chip interface circuit receiving instruction information sent by an MCU; synchronizing each instruction information through an N-level flip-flop sampling method; filtering out glitches in the instruction information by comparing the values ​​of different levels of flip-flops; and after decoding the instruction information, determining the type and data operation time of the eFlash IP using configuration information in the IP mode register, and performing data processing based on this type and data operation time. This disclosure improves the anti-interference and compatibility of the NOR flash memory chip.

Description

Technical Field

[0001] This disclosure belongs to the field of storage technology, and in particular relates to a data processing method, apparatus, interface circuit and chip. Background Technology

[0002] Flash memory chips, as a core component of data storage, offer advantages such as long data retention time, low power consumption, and fast read / write speeds, playing a crucial role in various electronic devices. Currently, the mainstream flash memory chips are divided into two main categories: NOR flash memory and NAND flash memory. NOR flash memory is widely used in the boot memory of embedded systems.

[0003] When a flash memory chip interacts with a microcontroller unit (MCU) for data reading and writing, the MCU typically controls the flash memory chip to perform various operations by inputting instructions. Specifically, the MCU sends instruction information to the flash memory chip, the interface circuitry in the flash memory chip receives this instruction information, decodes it, and sends it to the embedded flash IP (eFlash IP) within the flash memory chip. The eFlash IP then performs the data processing operations such as reading and writing. The eFlash IP is an embedded IP core or module that implements the functionality of an external flash memory.

[0004] In practical applications, eFlash IP and interface circuits are susceptible to glitches during signal transmission due to noise coupling, power supply ripple, and electromagnetic interference. These glitches not only affect data integrity but can also cause system malfunctions. Existing technologies typically employ filtering circuits to reduce signal noise, but their effectiveness is limited when dealing with high-frequency signals and complex interference environments. Furthermore, eFlash IPs come in various types, each with different interface standards, communication protocols, and timing requirements. Consequently, the same interface circuit for a flash memory chip cannot be compatible with different types of eFlash IPs.

[0005] Therefore, how to simultaneously improve the anti-interference and compatibility of flash memory chips is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned issues, this disclosure provides a data processing method, apparatus, interface circuit, and chip, the purpose of which is to improve the anti-interference and compatibility of flash memory chips.

[0007] To achieve the above objectives, this disclosure mainly provides the following technical solutions:

[0008] In a first aspect, this disclosure provides a data processing method applied to an interface circuit for a NOR flash memory chip, comprising:

[0009] Receive instruction information sent by the microcontroller unit, the instruction information including an enable signal, and an address and data corresponding to the enable signal;

[0010] The enable signal, address, and data are synchronized using an N-level flip-flop sampling method, where N is an integer greater than or equal to 3;

[0011] By comparing whether the values ​​of different levels of triggers are equal, glitches in the enable signal, address, and data are filtered out to obtain the filtered enable signal, address, and data.

[0012] Based on the filtered enable signal, address, and data, decoding is performed using a combination of state machine and indicator bit signals to generate corresponding IP operation signals, IP addresses, and IP data.

[0013] Based on the IP operation signal, the type and operation time of the embedded flash IP are determined in the configuration information of the IP mode register, which is used to store relevant information of the embedded flash IP.

[0014] By utilizing the type of the embedded flash memory IP and the IP operation time, the IP operation signal, IP address, and IP data are respectively input to each input port of the embedded flash memory IP, enabling the embedded flash memory IP to perform data processing operations.

[0015] Secondly, this disclosure provides a data processing apparatus applied to an NOR flash memory chip interface circuit, the apparatus comprising:

[0016] The receiving unit is used to receive instruction information sent by the microcontroller unit. The instruction information includes an enable signal, as well as an address and data corresponding to the enable signal.

[0017] The synchronization unit is used to synchronize the enable signal, address, and data through N-level flip-flop sampling, where N is an integer greater than or equal to 3;

[0018] The filtering unit is used to filter out glitches in the enable signal, address, and data by comparing whether the values ​​of different level flip-flops are equal, so as to obtain the filtered enable signal, address, and data.

[0019] The decoding unit is used to decode the filtered enable signal, address, and data by combining a state machine and indicator bit signals, and generate corresponding IP operation signals, IP addresses, and IP data respectively.

[0020] The determining unit is used to determine the type and operation time of the embedded flash IP based on the IP operation signal and the configuration information of the IP mode register, wherein the IP mode register is used to store relevant information of the embedded flash IP.

[0021] By utilizing the type of the embedded flash memory IP and the IP operation time, the IP operation signal, IP address, and IP data are respectively input to each input port of the embedded flash memory IP, enabling the embedded flash memory IP to perform data processing operations.

[0022] On the other hand, this disclosure also provides a NOR flash memory chip interface circuit, characterized in that the interface circuit is used to perform the method of the first aspect.

[0023] On the other hand, this disclosure also provides a NOR flash memory chip, characterized in that the flash memory chip includes an interface circuit and an embedded flash memory IP, the interface circuit being used to perform the method of the first aspect.

[0024] On the other hand, this disclosure also provides a storage medium for storing a computer program, wherein the computer program, when running, controls the device where the storage medium is located to execute the method described in the first aspect.

[0025] On the other hand, this disclosure also provides an electronic device, the device including at least one processor, and at least one memory and bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the method as described in the first aspect above.

[0026] Compared with the prior art, this disclosure has the following advantages:

[0027] This disclosure presents an NOR flash memory chip interface circuit that receives instruction information sent by an MCU. It synchronizes each instruction message using an N-stage flip-flop sampling method, comparing the values ​​of different stages of the flip-flops one by one to filter out glitches in the instruction information. After decoding the instruction information, it uses the configuration information in the IP mode register to determine the type and data operation time of the eFlash IP, and performs data processing based on this type and data operation time. This interface circuit not only filters out glitches in the signal but also supports different types of eFlash IP, thus improving the anti-interference and compatibility of the flash memory chip.

[0028] Other features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a NOR flash memory chip interface circuit according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown;

[0032] Figure 3 A glitch-free write cycle timing diagram is shown;

[0033] Figure 4 A timing diagram of a write cycle with glitches is shown;

[0034] Figure 5 A write cycle timing diagram for glitch filtering according to an embodiment of the present disclosure is shown;

[0035] Figure 6 A timing diagram of a handshake feedback type IP programming operation according to an embodiment of the present disclosure is shown;

[0036] Figure 7 A timing diagram of operation programming for a time-controlled stationary IP according to an embodiment of the present disclosure is shown;

[0037] Figure 8 A schematic diagram of a burr removal process according to an embodiment of the present disclosure is shown;

[0038] Figure 9 A schematic diagram of the structure of a data processing apparatus according to an embodiment of the present disclosure is shown. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0040] Existing flash memory chips are insufficient to meet the memory requirements of modern application systems such as rail transit and train control systems. The requirements are specifically reflected in two aspects: firstly, the need for interference-resistant signal communication, and secondly, the need for compatibility with multiple types of eFlashIP.

[0041] Regarding interference immunity, in existing electronic application systems, flash memory chips often need to work in conjunction with MCUs, static random-access memory (SRAM), etc. Their signal communication is susceptible to glitches caused by noise coupling, power supply ripple, and electromagnetic interference. Existing technologies often use traditional filtering circuits to reduce signal noise. However, this method has limited filtering effectiveness in high-frequency signals and complex interference environments, and may introduce additional delays, increasing unnecessary overhead. Modern application systems require flash memory chips to have strong anti-glitch interference capabilities to ensure fast and stable signal communication.

[0042] Regarding the need for compatibility with multiple types of eFlash IP, modern application systems typically require support for various eFlash IP types to meet different application scenarios and performance requirements. Different types of eFlash IP include handshake-feedback eFlash IP and time-controlled constant-state eFlash IP. Handshake-feedback eFlash IP has a signal interface indicating internal busy status, allowing for handshake feedback of signals from the interface circuit. The IP control circuit of the flash memory chip can monitor this signal to determine whether the current operation (e.g., write, erase) has been completed. Time-controlled constant-state eFlash IP, on the other hand, lacks a status indication interface, requiring the IP control circuit of the flash memory chip to periodically calculate whether the current operation is complete. Furthermore, the timing requirements for the interface circuit inputs differ between the two types of eFlash IP. Therefore, the difficulty in supporting multiple types of eFlash IP poses challenges to the design and integration of application systems, limiting their flexibility and scalability, and hindering the extended development of complex systems.

[0043] Therefore, modern application systems urgently need a flash memory chip that is compatible with multiple eFlash IPs and accurately filters out glitches and interference. Based on this, embodiments of this disclosure provide a NOR flash memory chip interface circuit. This interface circuit is a sequential logic circuit that can connect asynchronous MCUs and eFlash IPs. Figure 1As shown, the NOR flash memory chip interface circuit in this embodiment receives instruction information from the MCU. The instruction information specifically includes enable signals such as chip select enable, output enable, and write enable, along with corresponding addresses and data. After synchronization processing, the occurrence and propagation of metastability are reduced. The stabilized instruction information then undergoes glitching to eliminate the impact of high and low level glitches on signal logic. Instruction decoding is then performed using a combination of a state machine and indicator bit signals for rapid processing. IP control is then performed according to the configuration information of the IP mode register to ensure compatibility with different types of eFlash IP. Finally, explicit IP operation signals such as write and erase, along with their addresses and data, are sent to the flash memory storage unit. It should be noted that the MCU's address and control signals for reading the flash memory chip also undergo similar synchronization and glitching processing before being sent to the interface circuit. The interface circuit then retrieves the specific data from the flash memory storage unit to complete the flash memory chip reading process.

[0044] Accordingly, this disclosure provides a data processing method applied to an NOR flash memory chip interface circuit, such as... Figure 2 As shown, the data processing method of this disclosure includes:

[0045] 101. Receive instruction information sent by the microcontroller unit. The instruction information includes an enable signal, as well as the address and data corresponding to the enable signal.

[0046] The instruction information is used to instruct the flash memory chip to execute corresponding instruction operations. Enable signals include operations such as read, write, sector erase, full erase, erase pause, erase resume, and bypass write.

[0047] In this step, the interface circuit receives instruction information sent by the MCU, causing the interface circuit to perform corresponding data operations. For example, if the instruction information indicates writing data to the flash memory chip, the instruction information includes write enable, as well as the corresponding address and data. It should be noted that if the instruction information indicates reading data from the flash memory chip, the instruction information only includes read enable and the corresponding read address; the address itself is not included in the instruction information.

[0048] 102. Synchronize the enable signal, address, and data using an N-level flip-flop sampling method.

[0049] Where N is an integer greater than or equal to 3.

[0050] Since the clocks of the MCU and the interface circuit are usually out of sync, in this embodiment of the disclosure, the enable signal, address, and data are synchronized by sampling through N-level flip-flops to eliminate the metastability of external asynchronous signals.

[0051] 103. By comparing whether the values ​​of different levels of flip-flops are equal, glitches in the enable signal, address, and data are filtered out to obtain the filtered enable signal, address, and data.

[0052] Here, "different-level flip-flops" refers to flip-flops of different levels other than the first-level flip-flop. For example, when N=4, different-level flip-flops refer to the second-level and third-level flip-flops, or the third-level and fourth-level flip-flops, or the second-level and fourth-level flip-flops, or the second-level, third-level, and fourth-level flip-flops. The filtered enable signal, address, and data are the stable enable signal, address, and data after filtering out glitches and interference.

[0053] Because flash memory chips need to receive instruction information from the MCU in a timely manner, they typically need to record the instruction information in each cycle using register latching. The following explanation uses the write cycle as an example. The write cycle timing without glitches is as follows: Figure 3 As shown, this disclosure latches addresses Addr to Addr_vld on the falling edge of the enable signal Enable, continuously updates data Data_vld while Enable is low, and stops updating and latches data on the rising edge of the enable signal.

[0054] However, glitches or interference in the enable signal may affect the specific information latched, such as... Figure 4 As shown, the Enable signal may experience glitches due to external electromagnetic interference, causing fluctuations in both address and data. This can lead to latching incorrect addresses or data. Specifically, if a glitch occurs when the Enable signal is low, both address and data will glitch at the time of the glitch. Since the address is latched when the Enable signal falls, it will latch again when the glitch occurs and is on its falling edge, causing Addr_vld to latch the incorrect address glitch addr.

[0055] This embodiment of the disclosure can filter out glitches in the enable signal, address, and data by comparing whether the values ​​of the Nth and (N-1)th stage flip-flops are equal, thus obtaining the filtered enable signal, address, and data. For example, when N=4, it can first determine whether the values ​​of the 4th stage flip-flop and the 3rd stage flip-flop are equal. If they are not equal, it indicates that the enable signal is unstable, and the enable signal is discarded. The next cycle's enable signal is then received for further judgment. If they are equal, it indicates that the enable signal is stable. Then, when a specific edge of the enable signal arrives, the stability of the corresponding data is determined by comparing whether the values ​​of the 4th stage address flip-flop and the 3rd stage flip-flop are equal, and the stability of the corresponding address is determined by comparing whether the values ​​of the 4th stage data flip-flop and the 3rd stage flip-flop are equal. This embodiment of the disclosure can ensure that the signal has been stable for at least 3 clock cycles through the above comparison and judgment, thereby latching accurate address and data. Specific edges include, for example, falling edges and rising edges. The stable enable signal is the filtered enable signal, and the latched address and data are the filtered address and data.

[0056] This embodiment effectively filters out glitches during signal transmission with minimal timing overhead. The write cycle timing after glitches filtering is shown in Figure 5. After a certain delay, high-level glitches are filtered out, resulting in a stable enable signal Enable_rg. Based on the stable enable signal Enable_rg, accurate addresses and data can be latched. This embodiment avoids communication errors caused by signal glitches by latching accurate addresses Addr_vld and Data_vld, ensuring the accuracy of data transmission.

[0057] 104. Based on the filtered enable signal, address, and data, decode using a combination of state machine and indicator bit signals to generate corresponding IP operation signals, IP addresses, and IP data.

[0058] The state machine is the main part of the decoding circuit in the flash memory chip, and instruction recognition is achieved by controlling state transitions through the state machine. Indicator bit signals are used to indicate certain special states, such as erase pause state indicator, bypass write mode indicator, user information query indicator, etc. The indicator bit signals record the different special states of the decoding circuit, and together with the state machine, they control the decoding process to achieve the processing of complex instructions. In this embodiment, the IP operation signal, IP address, and IP data are the operation signal, address, and data input to the input port of the eFlash IP, respectively. The operation signal is used to indicate the specific operation to be performed by the eFlash IP, such as write or erase.

[0059] In one feasible approach, the specific methods for generating IP operation signals, IP addresses, and IP data are as follows:

[0060] Step 1: Based on the filtered enable signal, perform state transitions of the state machine according to the filtered address and data.

[0061] Step 2: Using the indicator bit signal, after the last instruction cycle of the instruction information is identified, generate the corresponding IP operation signal, IP address, and IP data respectively.

[0062] Since the MCU sends multi-cycle instructions, the corresponding address and data need to be sent within several consecutive cycles. Each time the decoding circuit receives a stable instruction from the MCU, the state machine jumps according to the specific address and data of the instruction. After fully recognizing an instruction, it generates an operation indication signal indicating that instruction and sends the operation indication signal to the eFlash IP. The operation indication signal includes the IP operation signal, IP address, and IP data. In this embodiment, the specific timing of sending the operation indication signal is determined by the IP mode register and can be adjusted according to different types of IP.

[0063] 105. Based on the IP operation signal, determine the type and operation time of the eFlash IP in the configuration information of the IP mode register.

[0064] The IP mode register stores relevant information about the eFlash IP. When the eFlash IP is of time-controlled fixed-state type, the IP operation time is the time it takes for the eFlash IP to perform the corresponding operation. When the eFlash IP is of handshake feedback type, the IP operation time is the timeout period for the eFlash IP to perform the corresponding operation.

[0065] In addition to a state machine, the decoding circuit also includes an IP control circuit. The IP control circuit in this embodiment is a configurable control circuit, which can be flexibly configured and adjusted in the IP mode register according to the interface protocols and timing requirements of different eFlash IPs. Through flexible configuration and adjustment, this embodiment can be compatible with various types of eFlash IPs, thereby reducing the complexity and cost of system integration. Specifically, this embodiment can configure a series of IP mode registers to output timing signals for different types of eFlash IPs, thereby controlling the operation of different eFlash IPs.

[0066] For example, the IP mode register in this embodiment is shown in Table 1. The ip_mode register represents the working type of the eFlash IP, i.e., the type of eFlash IP. ip_mode=0 indicates handshake feedback type, and ip_mode=1 indicates time-controlled stationary type. The ip_pg_time register represents the write operation time of the eFlash IP. This time has different meanings in different types of eFlash IP. In the time-controlled stationary type eFlash IP, this time is the time required for the eFlash IP to perform this operation. After this number of clock cycles, the eFlash IP completes the operation, the interface circuit removes the write operation signal and the corresponding address and data from the eFlash IP input port, the decoder state machine jumps back to the initial state, and allows the reception of new write operation signals and corresponding address and data sent by the MCU. In the handshake feedback type eFlash IP, this time is the timeout protection time of the interface circuit. The interface circuit will continuously monitor the output port of the eFlash IP within this number of clock cycles, waiting to receive the feedback signal that the eFlash IP operation is completed. Only after successfully receiving the feedback signal is the operation considered complete. If no feedback signal is received within the predetermined time (IP write timeout time), it indicates that the IP operation has timed out, and the decoder state machine jumps back to the initial state. ip_se_time and ip_ce_time represent the sector erase time and the whole-chip erase time of the eFlash IP, respectively. Their meanings in different types of eFlash IP are similar to ip_pg_time, and will not be repeated here.

[0067]

[0068] Table 1 IP Mode Register

[0069] In this step, the value in the ip_mode register is obtained to determine the type of eFlash IP. Based on the generated IP operation signal and the type of eFlash IP, the IP operation time is determined in the IP mode register. For example, if ip_mode=0 and the IP operation signal is the IP whole-chip erase operation signal, the value in the ip_ce_time register will be obtained. This value is the timeout time for the IP whole-chip erase operation.

[0070] After determining the type of eFlash IP and the corresponding IP operation time, the type of eFlash IP and the IP operation time can be used to input IP operation signals, IP addresses, and IP data to each input port of the eFlash IP, so that the eFlash IP can perform data processing operations.

[0071] 106. If the eFlash IP is of the handshake feedback type, then after inputting the IP operation signal, IP address and IP data to each input port of the eFlash IP respectively, monitor the feedback signal of the output port of the eFlash IP during the IP operation time.

[0072] The feedback signal is used to instruct the eFlash IP to complete the data processing operation.

[0073] When the IP control circuit of this embodiment determines that the eFlash IP is a handshake feedback type, it will input IP operation signals, IP addresses, and IP data to each input port of the eFlash IP, and then monitor the output port feedback signals of the eFlash IP during the IP operation time.

[0074] For example, such as Figure 6 As shown, after the decoding circuit parses a write instruction to the eFlash IP, it sets the write operation enable signal of the eFlash IP and inputs the corresponding IP write operation signal Prog, as well as the corresponding ip addr and ip data, to each input port of the eFlash IP. Upon receiving the IP write operation signals Prog, ip addr, and ip data, the eFlash IP begins writing data and sets the busy indicator bit to indicate that the eFlash IP is performing a write operation. After the eFlash IP completes the operation, it resets the busy indicator bit. Upon receiving the feedback signal that the busy indicator bit has been reset, the IP control circuit immediately removes the IP write operation signals Prog, ip addr, and ip data from the input port of the eFlash IP, preparing to receive the next new IP operation signal, along with the corresponding IP address and IP data.

[0075] It should be noted that if no feedback signal is received within the IP operation time, the state machine will jump back to the initial state and cancel the IP operation signals, IP addresses, and IP data on each input port in order to receive the next instruction information.

[0076] 107. If the eFlash IP is of time-controlled fixed-state type, when IP operation signals, IP addresses, and IP data are input to each input port of the eFlash IP, a timer is started, and after the timer counts to reach the IP operation time, the input of IP operation signals, IP addresses, and IP data stops, so that data processing operations can be performed through the eFlash IP.

[0077] Since the time-controlled stationary type eFlash IP does not have a busy indicator bit to indicate the internal working state, the embodiments of this disclosure use the IP operation time for timing so as to control the corresponding operation of the eFlash IP according to the IP operation time.

[0078] For example, such as Figure 7 As shown, the IP control circuit inputs the IP write operation signal Prog, along with the corresponding ip addr and ip data, to each input port of the eFlash IP, while simultaneously starting an internal timer. When the counter reaches the predetermined value stored in the ip_pg_time register, the IP control circuit cancels the IP write operation signals Prog, ip addr, and ip data to indicate that the write operation is complete and is ready to receive new IP operation signals, along with the corresponding IP address and IP data.

[0079] The interface circuit of this disclosure embodiment, in both configuration modes (handshake feedback type and time-controlled stationary type), can stably input operation enable and corresponding address, data, and other information while the eFlash IP is working. This disclosure embodiment ensures the integrity and effectiveness of the write and erase processes and terminates the operation based on signal feedback or internal timing, avoiding the potential for interface circuit failure due to internal errors in the eFlash IP. Furthermore, this disclosure embodiment provides strong support for the development of high-performance embedded systems by controlling the operation of different types of eFlash IPs.

[0080] To illustrate the data processing method proposed in this disclosure in more detail, the following provides a detailed explanation of the process for filtering signal glitches using the interface circuit, such as... Figure 8 As shown, the specific steps are as follows:

[0081] The interface circuit receives external input signals, such as instruction information sent by the MCU. This instruction information includes an enable signal, address, and data. The interface circuit first synchronizes the enable signal, address, and data using N-level flip-flops. Then, it checks the stability of each instruction message. Specifically, it compares the values ​​of the Nth-level and (N-1th-level) flip-flops for the enable signal to determine its stability. If unstable, it checks the stability of the next enable signal. If stable, it detects the falling edge of the enable signal. When the falling edge arrives, it compares the values ​​of the Nth-level and (N-1th-level) flip-flops for the address to determine their stability. If not, it checks the stability of the next address signal until a stable address is found and latches it. If the values ​​are equal, it latches the address directly and then detects the rising edge of the enable signal. When the rising edge arrives, it latches stable data. The specific judgment process is similar to the address execution steps and will not be elaborated here.

[0082] In one feasible approach, the steps for filtering signal glitches are as follows:

[0083] Determine if the values ​​of the enable signal stage 3 flip-flops and stage 2 flip-flops are equal; if they are not equal, discard the enable signal; if they are equal, when the falling edge of the enable signal arrives, determine if the values ​​of the address stage 3 flip-flops and stage 2 flip-flops are equal; if they are equal, latch the address, and when the rising edge of the enable signal arrives, filter out data glitches by comparing the values ​​of the data stage 3 flip-flops and stage 2 flip-flops; if they are not equal, discard the address.

[0084] The interface circuit in this embodiment effectively ensures the stability and accuracy of instruction information through edge-latch glitches, enhancing the anti-glitch interference capability of the NOR flash memory chip. Furthermore, since this embodiment only latches the corresponding address and data at the edge of the enable signal, it greatly reduces the stringent requirements on signal timing and pulse width. In addition, compared to using multiple flip-flops, this embodiment, with only three flip-flops, can reduce the probability of metastability without affecting system performance (synchronizing too many flip-flops will degrade system performance).

[0085] Based on the above method, this disclosure provides a data processing apparatus for improving the anti-interference and compatibility of flash memory chips. The embodiments of this apparatus correspond to the foregoing method embodiments. For ease of reading, this embodiment will not repeat the details of the foregoing method embodiments one by one, but it should be understood that the apparatus in this embodiment can implement all the contents of the foregoing method embodiments. Specifically, as follows... Figure 9 As shown, the device, applied to an interface circuit for NOR flash memory chips, includes:

[0086] The receiving unit 31 is used to receive instruction information sent by the microcontroller unit. The instruction information includes an enable signal and an address and data corresponding to the enable signal.

[0087] Synchronization unit 32 is used to synchronize the enable signal, address, and data through N-level flip-flop sampling, where N is an integer greater than or equal to 3;

[0088] Filtering unit 33 is used to filter out glitches in the enable signal, address, and data by comparing whether the values ​​of different level triggers are equal, so as to obtain the filtered enable signal, address, and data.

[0089] Decoding unit 34 is used to decode the filtered enable signal, address and data by combining state machine and indicator bit signal to generate corresponding IP operation signal, IP address and IP data respectively.

[0090] The determining unit 35 is used to determine the type and operation time of the embedded flash IP based on the IP operation signal in the configuration information of the IP mode register, wherein the IP mode register is used to store relevant information of the embedded flash IP.

[0091] Output unit 36 ​​is used to input the IP operation signal, IP address and IP data to each input port of the embedded flash memory IP according to the type of the embedded flash memory IP and the IP operation time, so that the embedded flash memory IP can perform data processing operations.

[0092] Furthermore, the output unit includes:

[0093] The monitoring module is used to monitor the feedback signal of the output port of the embedded flash IP during the IP operation time after inputting the IP operation signal, IP address and IP data to each input port of the embedded flash IP, if the type of the embedded flash IP is handshake feedback type. The feedback signal is used to instruct the embedded flash IP to complete the data processing operation.

[0094] The counting module is used to start a timer when the IP operation signal, IP address, and IP data are input to each input port of the embedded flash IP if the embedded flash IP is of time-controlled fixed-state type, and to stop inputting the IP operation signal, IP address, and IP data after the timer count reaches the IP operation time, so as to realize data processing operation through the embedded flash IP.

[0095] Furthermore, the monitoring module is specifically used for:

[0096] If the feedback signal is not received within the IP operation time, the state machine jumps back to the initial state.

[0097] Furthermore, the monitoring module is also specifically used for:

[0098] Cancel the IP operation signals, IP addresses, and IP data on each input port in order to receive the next instruction information.

[0099] Furthermore, the filtering unit includes:

[0100] The judgment module is used to determine whether the values ​​of the Nth stage flip-flop and the (N-1)th stage flip-flop of the enable signal are equal;

[0101] A filtering module is used to filter out glitches in the address and the data when the specific edge of the enable signal arrives if the judgment module determines that they are equal, so as to obtain the filtered enable signal, address, and data.

[0102] The discard module is used to discard the enable signal if the judgment module determines that they are not equal.

[0103] Furthermore, the filtering module is specifically used for:

[0104] When the falling edge of the enable signal arrives, determine whether the values ​​of the Nth level flip-flop and the (N-1)th level flip-flop are equal;

[0105] If they are equal, the address is latched, and when the rising edge of the enable signal arrives, glitches in the data are filtered out by comparing the values ​​of the Nth stage flip-flop and the (N-1)th stage flip-flop.

[0106] If they are not equal, the address is discarded.

[0107] Furthermore, N equals 3.

[0108] Furthermore, the decoding unit includes:

[0109] Based on the filtered enable signal, the state machine performs state transitions according to the filtered address and data.

[0110] Using the indicator bit signal, after the last instruction cycle of the instruction information is identified, the corresponding IP operation signal, IP address, and IP data are generated respectively;

[0111] Furthermore, the IP operation time is the number of clock cycles.

[0112] Furthermore, the enable signal is used to indicate one of the following: data reading, writing, sector erasure, full erasure, erasure pause, erasure resume, and bypass writing.

[0113] Furthermore, this disclosure also provides an NOR flash memory chip interface circuit, characterized in that the interface circuit is used to perform the above-described... Figure 2 The method described in [the document / article].

[0114] Furthermore, this disclosure also provides a NOR flash memory chip, characterized in that the flash memory chip includes an interface circuit and an embedded flash memory IP, the interface circuit being used to perform the above-described... Figure 2 The method described in [the document / article].

[0115] Furthermore, this disclosure also provides a processor for running a program, wherein the program executes the above-described... Figure 2 The method described in [the document / article].

[0116] Furthermore, this disclosure also provides a storage medium for storing a computer program, wherein the computer program, when running, controls the device where the storage medium is located to execute the above-described... Figure 2 The method described in [the document / article].

[0117] Furthermore, this disclosure provides an electronic device, which includes at least one processor, at least one memory connected to the processor, and a bus; wherein the processor and the memory communicate with each other via the bus; the processor is used to call program instructions in the memory to execute the above-described data processing method. The device described herein may be a server, PC, PAD, mobile phone, etc.

[0118] Furthermore, this disclosure also provides a computer program product that, when executed on a data processing device, is adapted to execute a program that initializes the inspection method steps of the network device as described above.

[0119] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A data processing method, characterized in that, The method, applied to an interface circuit for NOR flash memory chips, includes: Receive instruction information sent by the microcontroller unit, the instruction information including an enable signal, and an address and data corresponding to the enable signal; The enable signal, address, and data are synchronized using an N-level flip-flop sampling method, where N is an integer greater than or equal to 3; By comparing whether the values ​​of different trigger levels are equal, glitches in the enable signal, address, and data are filtered out, resulting in the filtered enable signal, address, and data, including... Determine whether the values ​​of the Nth stage flip-flop and the (N-1)th stage flip-flop of the enable signal are equal; If they are equal, then when a specific edge of the enable signal arrives, glitches in the address and the data are filtered out to obtain a filtered enable signal, address, and data; this includes determining whether the values ​​of the Nth level flip-flop and the (N-1)th level flip-flop of the address are equal when the falling edge of the enable signal arrives; if they are equal, the address is latched, and when the rising edge of the enable signal arrives, glitches in the data are filtered out by comparing the values ​​of the Nth level flip-flop and the (N-1)th level flip-flop; if they are not equal, the address is discarded. If they are not equal, then discard the enable signal; Based on the filtered enable signal, address, and data, decoding is performed using a combination of state machine and indicator bit signals to generate corresponding IP operation signals, IP addresses, and IP data. The indicator bit signals are used to indicate special states, including erase pause state indicator bit, bypass write mode indicator bit, and user information query indicator bit. The indicator bit signals record the different special states of the decoding circuit. Embedded flash IPs include handshake feedback type and time-controlled stationary type; Based on the IP operation signal, the type and operation time of the embedded flash IP are determined in the configuration information of the IP mode register. The IP mode register is used to store relevant information of the embedded flash IP, including: when the type of the embedded flash IP is time-controlled fixed state, the IP operation time is the time for the embedded flash IP to perform the corresponding operation; when the type of the embedded flash IP is handshake feedback type, the IP operation time is the timeout time for the embedded flash IP to perform the corresponding operation. By utilizing the type of the embedded flash memory IP and the IP operation time, the IP operation signal, IP address, and IP data are respectively input to each input port of the embedded flash memory IP, enabling the embedded flash memory IP to perform data processing operations.

2. The method according to claim 1, characterized in that, Using the type of the embedded flash memory IP and the IP operation time, the IP operation signal, IP address, and IP data are respectively input to each input port of the embedded flash memory IP, enabling the embedded flash memory IP to perform data processing operations, including: If the embedded flash IP is of the handshake feedback type, then after inputting the IP operation signal, IP address and IP data to each input port of the embedded flash IP respectively, the feedback signal of the output port of the embedded flash IP is monitored during the IP operation time. The feedback signal is used to instruct the embedded flash IP to complete the data processing operation. or, If the embedded flash IP is of the time-controlled fixed-state type, then when the IP operation signal, IP address and IP data are input to each input port of the embedded flash IP respectively, a timer is started, and after the timer count reaches the IP operation time, the input of the IP operation signal, IP address and IP data is stopped, so as to realize data processing operation through the embedded flash IP.

3. The method according to claim 1, characterized in that, N equals 3.

4. The method according to claim 1, characterized in that, Based on the filtered enable signal, address, and data, decoding is performed using a combination of state machine and indicator bit signals to generate corresponding IP operation signals, IP addresses, and IP data, including: Based on the filtered enable signal, the state machine performs state transitions according to the filtered address and data. Using the indicator bit signal, after the last instruction cycle of the instruction information is identified, the corresponding IP operation signal, IP address, and IP data are generated respectively; After monitoring the feedback signal of the output port of the embedded flash IP, the method further includes: If the feedback signal is not received within the IP operation time, the state machine jumps back to the initial state.

5. The method according to claim 4, characterized in that, After the state machine jumps back to the initial state, the method further includes: Cancel the IP operation signals, IP addresses, and IP data on each input port in order to receive the next instruction information.

6. The method according to claim 1, characterized in that, The IP operation time is the number of clock cycles.

7. The method according to claim 1, characterized in that, The enable signal is used to indicate one of the following: data reading, writing, sector erasure, full erasure, erasure pause, erasure resume, and bypass writing.

8. A data processing apparatus, characterized in that, The device, used in NOR flash memory chip interface circuits, comprises: The receiving unit is used to receive instruction information sent by the microcontroller unit. The instruction information includes an enable signal, as well as an address and data corresponding to the enable signal. The synchronization unit is used to synchronize the enable signal, address, and data through N-level flip-flop sampling, where N is an integer greater than or equal to 3; A filtering unit is used to filter out glitches in the enable signal, address, and data by comparing whether the values ​​of different flip-flops are equal, thereby obtaining the filtered enable signal, address, and data. The filtering unit includes: The judgment module is used to determine whether the values ​​of the Nth stage flip-flop and the (N-1)th stage flip-flop of the enable signal are equal; A filtering module is used to filter out glitches in the address and data when a specific edge of the enable signal arrives, if the judgment module determines that they are equal, to obtain a filtered enable signal, address, and data; including, when the falling edge of the enable signal arrives, determining whether the values ​​of the Nth level flip-flop and the (N-1)th level flip-flop of the address are equal; if they are equal, latching the address, and when the rising edge of the enable signal arrives, filtering out glitches in the data by comparing the values ​​of the Nth level flip-flop and the (N-1)th level flip-flop of the data; if they are not equal, discarding the address; A discard module is used to discard the enable signal if the judgment module determines that they are not equal. The decoding unit is used to decode the filtered enable signal, address, and data by combining a state machine and indicator bit signals to generate corresponding IP operation signals, IP addresses, and IP data respectively. The indicator bit signals are used to indicate special states, including erase pause state indicator bit, bypass write mode indicator bit, and user information query indicator bit. The indicator bit signals record the different special states of the decoding circuit. Embedded flash IPs include handshake feedback type and time-controlled stationary type; The determining unit is used to determine the type and IP operation time of the embedded flash IP based on the IP operation signal and the configuration information of the IP mode register. The IP mode register is used to store relevant information of the embedded flash IP, including: when the type of the embedded flash IP is time-controlled fixed state type, the IP operation time is the time for the embedded flash IP to perform the corresponding operation; when the type of the embedded flash IP is handshake feedback type, the IP operation time is the timeout time for the embedded flash IP to perform the corresponding operation. The output unit is used to input the IP operation signal, IP address, and IP data to each input port of the embedded flash memory IP according to the type of the embedded flash memory IP and the IP operation time, so that the embedded flash memory IP can perform data processing operations.

9. The apparatus according to claim 8, characterized in that, The output unit includes: The monitoring module is used to monitor the feedback signal of the output port of the embedded flash IP during the IP operation time after inputting the IP operation signal, IP address and IP data to each input port of the embedded flash IP, if the type of the embedded flash IP is handshake feedback type. The feedback signal is used to instruct the embedded flash IP to complete the data processing operation. The counting module is used to start a timer when the IP operation signal, IP address, and IP data are input to each input port of the embedded flash IP if the embedded flash IP is of time-controlled fixed-state type, and to stop inputting the IP operation signal, IP address, and IP data after the timer count reaches the IP operation time, so as to realize data processing operation through the embedded flash IP.

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