Modeling method and device for structure simulation model of chip advanced packaging

Abstract

The invention discloses a modeling method and device for a structure simulation model of chip advanced packaging. The modeling method of the structure simulation model of the chip advanced package comprises the following steps: obtaining package structure description data; according to component placement parameters in the packaging structure description data, component space layout parameters are determined, and based on component description parameters in the packaging structure description data, assembly block template protocol processing is carried out to obtain an assembly block protocol template; according to the assembly block specification template, performing grid layout on the assembly block specification template to obtain a to-be-divided assembly block template, and performing grid division on the to-be-divided assembly block template to obtain to-be-spliced assembly blocks; and arranging the to-be-spliced assembly blocks according to the component space arrangement parameters to obtain a discretized packaging structure simulation model. According to the technical scheme provided by the embodiment of the invention, the labor cost of advanced packaging structure simulation can be reduced, and the processing effect of a large-scale packaging structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of advanced chip packaging design, and particularly to a method and device for modeling a structural simulation model of advanced chip packaging. Background Art

[0002] In the technological evolution of silicon-based semiconductors, the number of transistors doubles every 18 - 24 months, doubling the chip performance or halving the cost. This law is called "Moore's Law". The continuation of Moore's Law requires raising the threshold of new technology research and development, lengthening the research and development cycle, and the process technology iteration also takes longer time, and its cost will also increase significantly. In order to further improve chip performance and reduce costs, achieving heterogeneous integration of the system through the use of advanced packaging technology has become one of the key technologies for industry manufacturers. However, at the same time, advanced packaging has brought the complexity of the packaging structure and also brought more challenges in terms of potential failure mechanisms and modes of chip packaging. As an important part of advanced packaging design, the structural simulation analysis of chip packaging has received more and more attention from researchers.

[0003] The structural simulation analysis process is divided into geometric modeling, preprocessing, simulation solution, and postprocessing stages: In the geometric modeling stage, a geometric model to be analyzed is established; in the preprocessing stage, the geometric model is discretized and relevant structural simulation data is set to generate a simulation model; in the solution stage, simulation parameters are set and simulation calculations are performed to obtain simulation results; in the postprocessing stage, visual analysis of the simulation results is carried out and the analysis results are fed back to the packaging design.

[0004] Currently, major EDA (Electronic Design Automation) providers support the structural analysis of advanced chip packaging by providing general tools. Engineers first use CAD (Computer Aided Design) software for the geometric modeling of the packaging, and then import the modeling results into CAE (Computer Aided Engineering) preprocessing software for mesh division. These discrete and general processing tools, although comprehensive in function, lack close cooperation with each other, and at the same time do not provide customized support and optimization for the structural analysis of advanced packaging, resulting in a large amount of manual work required in the geometric modeling and preprocessing stages of the existing structural simulation analysis of advanced packaging, and there are often situations where the processing of large-scale packaging structures crashes. Summary of the Invention

[0005] The present invention provides a method and device for modeling a structural simulation model of advanced chip packaging to solve the problems of high labor cost and poor processing effect of large-scale packaging structures existing in the existing structural simulation of advanced packaging.

[0006] According to one aspect of the present invention, there is provided a method for modeling a structural simulation model of an advanced chip package, including:

[0007] Obtaining package structure description data;

[0008] Determining component spatial layout parameters according to the component placement parameters in the package structure description data, and performing assembly block template specification processing based on the component description parameters in the package structure description data to obtain an assembly block specification template;

[0009] Performing grid layout on the assembly block specification template according to the assembly block specification template to obtain an assembly block template to be divided, and performing grid division on the assembly block template to be divided to obtain an assembly block to be spliced;

[0010] Laying out the assembly block to be spliced according to the component spatial layout parameters to obtain a discretized package structure simulation model.

[0011] According to another aspect of the present invention, there is provided a simulation modeling device for a chip package structure, including:

[0012] A data acquisition module for obtaining package structure description data;

[0013] An assembly block specification template determination module for determining component spatial layout parameters according to the component placement parameters in the package structure description data, and performing assembly block template specification processing based on the component description parameters in the package structure description data to obtain an assembly block specification template;

[0014] A grid layout and division module for performing grid layout on the assembly block specification template according to the assembly block specification template to obtain an assembly block template to be divided, and performing grid division on the assembly block template to be divided to obtain an assembly block to be spliced;

[0015] An assembly block layout module for laying out the assembly block to be spliced according to the component spatial layout parameters to obtain a discretized package structure simulation model.

[0016] According to another aspect of the present invention, there is provided an electronic device, the electronic device includes:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for modeling a structural simulation model of an advanced chip package according to any embodiment of the present invention.

[0020] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the modeling method of the structure simulation model of the chip advanced packaging according to any embodiment of the present invention when executed.

[0021] The technical solution of the embodiment of the present invention obtains the package structure description data, determines the component spatial layout parameters according to the component placement parameters in the package structure description data, performs the assembly block template specification process based on the component description parameters in the package structure description data to obtain the assembly block specification template, then performs grid layout on the assembly block specification template to obtain the assembly block template to be divided, and performs grid division on the assembly block template to be divided to obtain the assembly block to be spliced. Further, according to the component spatial layout parameters, the assembly block to be spliced is laid out to obtain a discretized package structure simulation model. In this solution, based on the package structure description data, the spatial layout of components can be automatically determined, and the assembly block templates corresponding to the components can be specified to reduce the number of templates and improve the subsequent processing efficiency, effectively avoiding system crashes during the processing of large-scale package structures. Moreover, the processes of grid layout, grid division of the templates, and finally splicing the assembly blocks based on the spatial layout of the components do not require manual intervention, solving the problems of high labor cost and poor processing effect of large-scale package structures in the existing advanced packaging structure simulation, and being able to reduce the labor cost of advanced packaging structure simulation and improve the processing effect of large-scale package structures.

[0022] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a flowchart of a modeling method for a structure simulation model of chip advanced packaging provided in Embodiment 1 of the present invention;

[0025] Figure 2 It is a flowchart of a modeling method for a structure simulation model of chip advanced packaging provided in Embodiment 2 of the present invention;

[0026] Figure 3It is a functional module diagram of a modeling tool for a structural simulation model of advanced chip packaging provided in Embodiment 3 of the present invention;

[0027] Figure 4 It is a schematic diagram of a singular template and a trivial template in a bump array component provided in Embodiment 3 of the present invention;

[0028] Figure 5 It is a schematic diagram of the position where a buffer to be adjusted is added provided in Embodiment 3 of the present invention;

[0029] Figure 6 It is a schematic diagram of the cross-section position in the vertical direction provided in Embodiment 3 of the present invention;

[0030] Figure 7 It is a logical schematic diagram of a homotopy mapping provided in Embodiment 3 of the present invention;

[0031] Figure 8 It is a structural schematic diagram of a modeling device for a structural simulation model of advanced chip packaging provided in Embodiment 4 of the present invention;

[0032] Figure 9 It shows a structural schematic diagram of an electronic device that can be used to implement the embodiments of the present invention. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0035] Embodiment 1

[0036] Figure 1The following is a flowchart of a modeling method for a structural simulation model of an advanced chip packaging. This embodiment is applicable to the case of automatic modeling during structural simulation of advanced packaging. Advanced packaging specifically refers to 2.5D, 3D, and 3.5D packaging. Structural simulation is used to analyze the reliability of the packaging structure. Specific structural simulations include simulations such as warping and bump array fracture. This method can be executed by a modeling device for the structural simulation model of advanced chip packaging. The modeling device for the structural simulation model of advanced chip packaging can be implemented in the form of hardware and / or software, and the modeling device for the structural simulation model of advanced chip packaging can be configured in an electronic device. The electronic device can include, but is not limited to, a computer or a server, etc. As Figure 1 shown, the method includes:

[0037] Step 110, obtain packaging structure description data.

[0038] Among them, the packaging structure description data can be used to describe the packaging structure of advanced chip packaging. The language type of the packaging structure description data can include, but is not limited to, DSL (Domain Specific Language) type. The packaging structure description data can include component description parameters (such as component type, component quantity, etc.), component placement parameters, component combination relationships, and component material description data, etc. Components can be understood as various parts or components that make up the package. Components can include, but are not limited to, die components, bump array components, silicon interposer components, substrate components, filling material components, epoxy molding compound components, and through-silicon via components, etc. Component combination relationships can include, but are not limited to, combining a group of components into a logical group, combining a group of components into a physical group, stacking a group of components on top of each other in sequence to form a logical group, and stacking a group of components on top of each other in sequence to form a physical group, etc.

[0039] In the embodiment of the present invention, the packaging structure description data written by the user through the user data input interface can be obtained.

[0040] Optionally, the user can query component material information in a pre-configured material database, and can also define and store component material information in the material database. Among them, different types of engineering data templates are provided for the user in the material database. Based on the material attributes and parameter definitions of the templates, the user can flexibly edit and create various component material description data. The user can also organize and save commonly used material databases for future project use. The data organization of the material database based on specific keywords and the fuzzy naming method similar to natural language abbreviation rules enable the user to input data in a simple table form.

[0041] Step 120: Determine the component spatial layout parameters according to the component placement parameters in the encapsulation structure description data, and perform the assembly block template specification process based on the component description parameters in the encapsulation structure description data to obtain the assembly block specification template.

[0042] Among them, the component placement parameters can be the parameters describing the relative positions of components. The component placement parameters can include the offsets of the center position of this component relative to the center of another component in the front-back, left-right, up-down directions; when this component is placed above another component, the left-right and front-back offsets of the center of this component relative to the center of another component; when this component is placed below another component, the left-right and front-back offsets of the center of this component relative to the center of another component; place this component while keeping the left-right and front-back positions unchanged so that the top surface of this component has the same height as the bottom surface of another component; place this component while keeping the left-right and front-back positions unchanged so that the bottom surface of this component has the same height as the top surface of another component; place this component while keeping the front-back and up-down positions unchanged so that the right surface of this component has the same position as the left surface of another component; place this component while keeping the front-back and up-down positions unchanged so that the left surface of this component has the same position as the right surface of another component; place this component while keeping the up-down and left-right positions unchanged so that the back surface of this component has the same position as the front surface of another component; place this component while keeping the up-down and left-right positions unchanged so that the front surface of this component has the same position as the back surface of another component; place this component while keeping the left-right and front-back positions unchanged so that the bottom surface of this component has the same height as the bottom surface of another component; place this component while keeping the left-right and front-back positions unchanged so that the top surface of this component has the same height as the top surface of another component; place this component while keeping the front-back and up-down positions unchanged so that the left surface of this component has the same position as the left surface of another component; place this component while keeping the front-back and up-down positions unchanged so that the right surface of this component has the same position as the right surface of another component; place this component while keeping the up-down and left-right positions unchanged so that the front surface of this component has the same position as the front surface of another component; place this component while keeping the up-down and left-right positions unchanged so that the back surface of this component has the same position as the back surface of another component. The component spatial layout parameters can be used to describe the positions and contact relationships of components in three-dimensional space. The component description parameters can be used to describe the basic information of components in the encapsulation structure.

[0043] Among them, the assembly block template reduction process can be a process of reducing the number of assembly block templates. The assembly block template reduction process can include, but is not limited to, the reduction process of non-singular templates and the reduction process of singular templates. The reduction process of non-singular templates is to directly merge adjacent non-singular templates, which can be understood as combining small block templates into large block templates to reduce the number of templates. The reduction process of singular templates is to align the outer boundary discrete cross-sections of singular templates through an added buffer zone to reduce the types of assembly block templates corresponding to the same component type. A singular template is a region where certain physical quantities (such as stress, strain, temperature gradient, etc.) in the encapsulated structure simulation model appear infinite or discontinuous. The assembly block reduced template can be the assembly block template after the assembly block template reduction process. The assembly block template can be a template that describes the assembly relationship and configuration of components in the encapsulated structure during simulation.

[0044] In an embodiment of the present invention, the component placement parameters can be parsed from the encapsulated structure description data, a spatial positioning system for each component can be established based on the component placement parameters, and a Boolean operation can be performed for each component with other components to obtain the component spatial layout parameters. Furthermore, based on the component description parameters parsed from the encapsulated structure description data, the assembly block template corresponding to the component with the component description parameters can be determined, and the determined assembly block template can be subjected to a reduction process to obtain the assembly block reduced template, so as to reduce the types (which can also be referred to as the number) of assembly block templates through the assembly block template reduction process.

[0045] Step 130: Perform a grid layout on the assembly block reduced template to obtain the assembly block template to be divided, and perform a grid division on the assembly block template to be divided to obtain the assembly block to be spliced.

[0046] Among them, the assembly block template to be divided can be the assembly block template after the grid layout. The assembly block to be spliced can be an instantiated object of the assembly block template to be divided after the grid division.

[0047] In an embodiment of the present invention, each assembly block reduced template can be divided into multiple topological polyhedra, and based on the discretization cross-section position set by the user and the topological polyhedra divided from each assembly block reduced template, the grid layout of each assembly block reduced template can be constructed to obtain the assembly block template to be divided. Furthermore, according to the discretization cross-section position and the grid layout of the assembly block to be divided, the assembly block template to be divided can be subjected to a grid division to obtain the assembly block to be spliced.

[0048] Generally, in the encapsulated structure simulation, the discretization cross-section position is a specific cross-section or position selected during the discretization process of the encapsulated structure.

[0049] Step 140: Layout the assembly block to be spliced according to the component spatial layout parameters to obtain the discretized encapsulated structure simulation model.

[0050] Among them, the discretized packaging structure simulation model can be a structure simulation model of advanced chip packaging created based on the packaging structure description data.

[0051] In the embodiment of the present invention, the to-be-spliced and assembled blocks corresponding to the components can be spliced according to the component space layout parameters to obtain a discretized packaging structure simulation model. The finally obtained discretized packaging structure simulation model can be used for the structure simulation of advanced chip packaging.

[0052] The technical solution of the embodiment of the present invention obtains the packaging structure description data, thereby determines the component space layout parameters according to the component placement parameters in the packaging structure description data, and performs assembly block template specification processing based on the component description parameters in the packaging structure description data to obtain an assembly block specification template. Then, a grid layout is performed on the assembly block specification template to obtain a to-be-partitioned assembly block template, and a grid partition is performed on the to-be-partitioned assembly block template to obtain to-be-spliced and assembled blocks. Further, the to-be-spliced and assembled blocks are laid out according to the component space layout parameters to obtain a discretized packaging structure simulation model. In this solution, the spatial layout of the components can be automatically determined based on the packaging structure description data, and the assembly block templates corresponding to the components are specified to reduce the number of templates and improve the subsequent processing efficiency, effectively avoiding system crashes during the processing of large-scale packaging structures. Moreover, the processes of grid layout, grid partitioning of the templates, and finally splicing and assembling the blocks based on the spatial layout of the components do not require manual intervention, solving the problems of high labor costs and poor processing effects of large-scale packaging structures existing in the existing advanced packaging structure simulation, and being able to reduce the labor costs of advanced packaging structure simulation and improve the processing effects of large-scale packaging structures.

[0053] Embodiment 2

[0054] Figure 2 FIG. is a flowchart of a method for modeling a structure simulation model of advanced chip packaging provided by Embodiment 2 of the present invention. This embodiment is specific based on the above embodiment and gives a specific and optional implementation manner for performing assembly block template specification processing based on the component description parameters in the packaging structure description data to obtain an assembly block specification template. As Figure 2 shown, the method includes:

[0055] Step 210, obtain the packaging structure description data.

[0056] Step 220, determine the component space layout parameters according to the component placement parameters in the packaging structure description data.

[0057] Step 230, perform a space division on the space occupied by all components based on the component description parameters in the packaging structure description data to obtain a space division result, and perform an intersection operation between the space division result and each component to obtain the first type of template and the second type of template of each component.

[0058] The first type of template is a non-singular template (or ordinary template) of a component. The space division result can be a division result obtained by dividing the component boundary in three-dimensional space. The second type of template is a singular template of a component.

[0059] Specifically, based on the component placement parameters in the package structure description data, after determining the component space layout parameters, the components required for the structural simulation of this advanced package can be determined according to the component description parameters, and then the boundaries of the components required for the structural simulation of this advanced package can be determined, and the spatial division is performed in three-dimensional space based on the boundaries of each component to obtain the spatial division result, and then the spatial division result is intersected with the space occupied by each component, that is, the spatial division result is intersected with each component to clear the free space in the component that does not need to be filled with the assembly block template, so as to obtain the first type template and the second type template of each component. When the component is spatially divided, each geometric boundary of the component will become a boundary surface of the spatial division, and all components jointly determine the spatial division of the package structure. If there is no singular template after the current component is spatially divided, the second type template is empty.

[0060] Step 240: Perform assembly block template reduction processing according to the first type template and the second type template of each component to obtain an assembly block reduction template.

[0061] In an embodiment of the present invention, an adapted assembly block template reduction process is determined for the template type specifically corresponding to each component, the first type of templates of the component are directly merged according to the adjacent relationship, and the second type of templates are subjected to assembly block template reduction process by aligning the outer boundary discrete sections to obtain an assembly block reduction template.

[0062] In an optional embodiment of the present invention, assembly block template reduction processing is performed according to the first type template and the second type template of each component to obtain an assembly block reduction template, which may include: when the discrete section positions of the second type template and the first type template of the current component are different, determining the buffer zone to be adjusted of the current component; performing assembly block template reduction processing according to the inner border section position point density, the outer border section position point density and the buffer zone adjustment threshold of the buffer zone to be adjusted of the current component to obtain an assembly block reduction template corresponding to the current component.

[0063] Among them, the buffer to be adjusted can be the extended area of the second-type template when the discrete cross-section positions of the second-type template and the first-type template of the current component are different, occupying the area of the first-type template adjacent to the second-type template in the current component. The point density of the inner border cross-section position can be the point density of the discrete points selected on the adjacent edge between the buffer to be adjusted and the second-type template in the current component. The point density of the outer border cross-section position can be the point density of the discrete points selected on the adjacent edge between the buffer to be adjusted and the first-type template in the current component. The buffer adjustment threshold can be the size threshold of the buffer set in advance.

[0064] In the embodiment of the present invention, if it is determined that the discrete cross-section positions of the second-type template and the first-type template of the current component are different, it indicates that the range of the second-type template of the current component needs to be expanded for subsequent assembly block template regularization processing, that is, according to the preset second-type template range expansion rule, the buffer to be adjusted of the current component is determined. Furthermore, based on the discrete cross-section point positions of the second-type template and the first-type template of the current component, the point density of the inner border cross-section position and the point density of the outer border cross-section position of the buffer to be adjusted of the current component are determined. And on the premise that the size of the buffer to be adjusted is smaller than the buffer adjustment threshold, the point densities of the discrete cross-section points of the outer border and the inner border of the buffer to be adjusted are adjusted to align the discrete cross-section positions of the current component and other components, and the first-type template of the current component is adjusted according to the buffer to be adjusted, and then the first-type template is regularized to minimize the types of templates of the current component, realize the assembly block template regularization processing, and obtain the assembly block regularization template corresponding to the current component.

[0065] In an alternative embodiment of the present invention, performing assembly block template regularization processing according to the point density of the inner border cross-section position, the point density of the outer border cross-section position, and the buffer adjustment threshold of the buffer to be adjusted of the current component to obtain the assembly block regularization template corresponding to the current component may include: when the point density of the outer border cross-section position of the buffer to be adjusted is less than the point density of the inner border cross-section position, calculating the density difference between the point density of the outer border cross-section position and the point density of the inner border cross-section position; expanding the buffer to be adjusted according to the density difference and the buffer size threshold to obtain the template to be regularized of the current component, performing spatial division based on the expanded buffer to be adjusted, and updating the first-type template; performing assembly block template regularization processing on the first-type template to obtain the assembly block regularization template corresponding to the current component.

[0066] Among them, the template to be regularized can be the template that needs to be subjected to assembly block template regularization processing after dividing the buffer to be adjusted.

[0067] In an embodiment of the present invention, the density of the position points of the outer border section of the buffer to be adjusted can be compared with the density of the position points of the inner border section. If the density of the position points of the outer border section of the buffer to be adjusted is less than the density of the position points of the inner border section, the density difference between the density of the position points of the outer border section and the density of the position points of the inner border section is further calculated. Then, according to the calculated density difference, the buffer to be adjusted is expanded, that is, new discrete section positions are set at a certain interval within the expanded buffer to be adjusted, so that the discrete section positions of the current component are aligned with those of other components, and it is necessary to ensure that the size of the expanded buffer to be adjusted does not exceed the buffer size threshold. Furthermore, the space of the expanded buffer to be adjusted is divided to update the first type of template, and then the updated first type of model is subjected to the assembly block template specification process to obtain the assembly block specification template corresponding to the current component.

[0068] In an alternative embodiment of the present invention, when the discrete section positions of the second type of template and the first type of template of the current component are different, determining the buffer to be adjusted of the current component may include: determining the template size of the second type of template of the current component and obtaining the buffer size ratio coefficient; determining the size of the buffer to be adjusted according to the template size of the second type of template and the buffer size ratio coefficient; in the first type of template adjacent to the second type of template of the current component, a buffer to be adjusted adjacent to the second type of template of the current component is divided according to the size of the buffer to be adjusted.

[0069] Wherein, the buffer size ratio coefficient may be a pre-set ratio describing the proportion of the buffer area to be adjusted in the area of the second type of template.

[0070] In an embodiment of the present invention, the template size of the current second type of template of the current component can be determined, and the buffer size ratio coefficient set by the user is obtained. Then, the product value of the template size of the current second type of template and the buffer size ratio coefficient is used as the size of the buffer to be adjusted (that is, the size of the buffer to be adjusted). Further, in the first type of template adjacent to the current second type of template, a buffer to be adjusted adjacent to the current second type of template and capable of evenly surrounding the second type of template is determined according to the size of the buffer to be adjusted. It should be noted that the determination logic of the buffers to be adjusted for different second type of templates under the current component is the same and will not be elaborated here.

[0071] Step 250: Perform a grid layout on the assembly block specification template to obtain an assembly block template to be divided, and perform grid division on the assembly block template to be divided to obtain an assembly block to be spliced.

[0072] In an alternative embodiment of the present invention, performing a grid layout on the assembly block specification template to obtain the assembly block template to be divided may include: obtaining the cross-section position points corresponding to the assembly block specification template; dividing the assembly block specification template into a plurality of topological solid units according to the cross-section position points and at least one grid layout, and calculating the mean square deviation of the edge lengths of the topological solid units under each grid layout; and determining the assembly block template to be divided according to the mean square deviation of the edge lengths of the topological solid units under each grid layout.

[0073] Among them, the topological solid unit may be a topological hexahedron. The mean square deviation of the edge lengths can be used to describe the dispersion of the edge length distribution of the polyhedron.

[0074] In the embodiment of the present invention, the cross-section position points corresponding to the assembly block specification template can be determined first, and then the assembly block specification template can be divided into a plurality of topological solid units according to the cross-section position points and at least one grid layout configured by the user, and the mean square deviation of the edge lengths of the plurality of topological solid units obtained by dividing the assembly block specification template under each grid layout can be calculated. Thus, the grid layout with the minimum mean square deviation of the edge lengths of the topological solid units is used as the final grid layout, and the assembly block template under this grid layout is used as the assembly block template to be divided.

[0075] Exemplarily, the intersection lines of the cross-section position points and the outer shell of the assembly block specification template are used as the intersection lines of the topological solid units and the outer shell of the assembly block specification template under the internal grid layout of the assembly block specification template, so as to realize the grid layout of the assembly block specification template.

[0076] Step 260: Layout the assembly blocks to be spliced according to the component space layout parameters to obtain a discretized package structure simulation model.

[0077] In an alternative embodiment of the present invention, performing a grid division on the assembly block template to be divided to obtain the assembly blocks to be spliced may include: performing a grid division on the assembly block template to be divided based on the homotopy mapping method and the isometric interpolation method to obtain the assembly blocks to be spliced; after laying out the assembly blocks to be spliced according to the component space layout parameters to obtain a discretized package structure simulation model, it may further include: obtaining boundary condition setting parameters, and outputting a simulation model description file according to the boundary condition setting parameters and the discretized package structure simulation model.

[0078] Among them, the boundary condition setting parameters may be parameters of the physical behavior or constraints of the structural simulation model set by the user on the boundary. The boundary condition setting parameters may include, but are not limited to, surface boundary conditions and point boundary conditions, etc. The simulation model description file may be a simulation file required for chip advanced packaging simulation.

[0079] In an embodiment of the present invention, sampling points of a topological solid element can be determined based on the grid layout of an assembly block template to be partitioned and the discretized cross-section positions set by a user. Then, based on the homotopy mapping of each edge of the topological solid element to a unit line segment, a mapping between the topological solid element and a standard cube is established. Thus, equidistant interpolation is performed on the sampling points of the topological solid element in the mapped standard cube according to the equidistant interpolation method. Through the inverse mapping of the homotopy mapping, that is, the inverse parametric mapping based on edges and faces, the position values of the interpolation points are mapped back to the three-dimensional space to obtain the three-dimensional values of the grid points on the assembly block template to be partitioned, as well as one-dimensional, two-dimensional, and three-dimensional template element units, thereby completing the final grid partitioning and obtaining the assembly blocks to be spliced.

[0080] After laying out the assembly blocks to be spliced according to the component space layout parameters to obtain a discretized package structure simulation model, it is also possible to further obtain the boundary condition setting parameters written by the user, and then generate a simulation model description file for chip advanced package structure simulation according to the boundary condition setting parameters and the discretized package structure simulation model.

[0081] The technical solution of the embodiment of the present invention obtains the package structure description data, thereby determining the component space layout parameters according to the component placement parameters in the package structure description data. Based on the component description parameters, the space occupied by all components is partitioned to obtain a space partitioning result, and the first type of template and the second type of template of each component are obtained by intersecting the space partitioning result with each component. Then, based on the first type of template and the second type of template of each component, the assembly block template reduction process is performed to obtain a reduced assembly block template, and the grid layout of the reduced assembly block template is carried out to obtain an assembly block template to be partitioned. Thus, the assembly block template to be partitioned is grid-partitioned to obtain the assembly blocks to be spliced, so as to lay out the assembly blocks to be spliced according to the component space layout parameters to obtain a discretized package structure simulation model. In this solution, based on the package structure description data, the space layout of the components can be automatically determined, and the assembly block templates corresponding to the components can be reduced to reduce the number of templates and improve the subsequent processing efficiency, effectively avoiding system crashes during the processing of large-scale package structures. Moreover, the processes of grid layout, grid partitioning of the templates, and finally splicing the assembly blocks based on the component space layout do not require manual intervention, solving the problems of high labor costs and poor processing effects of large-scale package structures in existing advanced package structure simulations, and being able to reduce the labor costs of advanced package structure simulations and improve the processing effects of large-scale package structures.

[0082] Embodiment III

[0083] Embodiment III of the present invention provides an alternative embodiment for modeling a structure simulation model of chip advanced packaging. The specific implementation manner can be referred to in the following embodiments. Technical terms that are the same or corresponding to those in the above embodiments are not described herein again.

[0084] Figure 3 This is a functional module diagram of a modeling tool for a structural simulation model of advanced chip packaging provided in Embodiment 3 of the present invention. As Figure 3 shown, the tool includes a domain-specific language module, a space management module, a template extraction module, an assembly block module, a template module, an output module, and a material library module. Among them, the domain-specific language module includes a material description module (equivalent to a configuration module for component material description data), a basic component description module (equivalent to a configuration module for component description parameters), a coordinate system module (equivalent to a configuration module for component placement parameters), and a component combination management module (equivalent to a management module for component combination relationships). The space management module includes a component positioning module and a component Boolean operation module. The template extraction module includes a template recognition module and a template specification module. The assembly block module includes an assembly block management module, an assembly block generation module, and an assembly block splicing module. The template module includes a template management module, a template generation module, and a mesh generation module. The material library module includes a material management module, a material property module, and a database user interface module. The output module includes a cdb file export module, a k file export module, and other solver file type export modules. Figure 3 The arrows in

[0085] The domain-specific language module provides a user programming interface, and users can use natural language to describe the packaging structure.

[0086] The space management module is used to identify the connection and contact relationships of components. Specifically, the component positioning module is used to obtain the spatial positions of each component, establish a spatial positioning system for each component, and establish a mapping relationship between the spatial position and the component through the spatial positioning system. Based on the spatial positioning system, a lookup table of the spatial positions of each component and the assembly block can also be established, a mapping between the component and the assembly block can be established, the assembly block to which the component belongs can be obtained, and the point, edge, and surface mapping relationships between the component and its assembly block can be established. Thus, through the spatial positioning system and the component-assembly block lookup table, the layout of each component assembly block can be established. The component Boolean operation module performs Boolean operations on each component and other components to obtain the connection and contact relationships with each component.

[0087] The number of templates determines the scale of the overall modeling problem. The goal of the template extraction module is to reduce the number of templates and the problem scale, thereby supporting the discretization of large-scale models. Adjacent trivial templates can be combined to form new trivial templates, that is, reducing the number of templates through template reduction. Exemplarily, there may be a large number of bump arrays of different scales in practical applications. There are singular templates in the bump array. To maintain grid consistency, the same singular template needs to add discrete cross-section points to each other due to being adjacent to different singular templates, so as to be consistent with the cross-section positions of adjacent singular templates. After adding cross-section points, a large number of different singular templates will be generated. To reduce the problem of generating new templates due to different cross-section positions of the same template, the assembly block template reduction process can be carried out.

[0088] The process of the assembly block template reduction is as follows: 1) Space division: For the space occupied by all components, according to the geometric boundaries of the components, the space is divided. The division result is intersected with each component, and the components are divided into assembly block placeholders. According to the component types in the geometric model, the attributes of the placeholders can be trivial templates or singular templates. As Figure 4 shown, Figure 4 in the lower left and lower right corners, the dark blue areas are the singular template areas of the bump array components, and the light blue areas are the trivial template areas of the bump array components.

[0089] 2) Calculate the discrete cross-section positions: According to the discretization size set by the user, the equal division principle is used to determine the discrete cross-section positions of the singular templates and the trivial templates.

[0090] 3) Determine the buffer to be adjusted: Compare the discrete cross-section positions of the singular templates and the adjacent trivial templates. If the cross-section positions are the same, no buffer to be adjusted is set. If the cross-section positions are different, according to the size of the singular template, a certain proportion of trivial templates are wrapped around the singular template as the buffer to be adjusted. As Figure 5 shown, Figure 5 in the orange area is the added buffer to be adjusted, and the inside of the buffer to be adjusted is a trivial template. Figure 5The outer border of the orange area is the outer border of the buffer to be adjusted, and the green dotted line is the inner border of the buffer to be adjusted. The size of the buffer to be adjusted needs to be dynamically adjusted according to the difference in the point density of the cross-section positions of the current inner and outer borders. When the point density of the cross-section positions that need to be added to the inner border is too large, it will cause the grid size after discretization to be too small. The size of the buffer to be adjusted can be increased, but it is necessary to ensure that the size of the buffer to be adjusted is within a certain range and cannot be expanded indefinitely. If the buffer to be adjusted is too large, it will cause subsequent simulations to be restricted. Therefore, when the calculated buffer layer size is greater than the buffer adjustment threshold, stop increasing the buffer layer size and add a new singular template. The new singular template increases the discrete cross-section points of the inner border of the buffer to be adjusted by changing the grid size, thereby increasing the point density of the discrete cross-section of the inner border of the buffer to be adjusted.

[0091] 4) Determine the peripheral trivial template area adjacent to the buffer to be adjusted: Since the buffer to be adjusted occupies part of the trivial template, it is necessary to perform spatial division according to the buffer to obtain a new trivial template. For trivial templates, adjacent trivial templates can be normalized into one template. For example, Figure 6 Regions A and B in can be combined into one template.

[0092] 5) Determine the latest discretized cross-section positions of each template: For subsequent discretization, it is necessary to determine the cross-section positions of each template. First, determine the discretized cross-section positions of the final buffer, and then determine the discretized cross-section positions of each trivial template according to the final buffer. Figure 6 An example of the cross-section position division in the vertical direction is given. To ensure that the number of singular templates is not increased and the discretized cross-section positions of the singular templates are not changed, it is necessary to adjust the cross-section point positions of the outer and inner borders of the buffer to be adjusted so that the point densities are the same. In Figure 6 the outer border of the buffer to be adjusted is the outer border of the orange area, and the corresponding inner border is the green dotted line. According to the discretized cross-section obtained in step 2), compare the point densities of the cross-section positions of the outer and inner borders of the buffer to be adjusted at this time to ensure that the point density of the outer border is greater than or equal to that of the inner border. If the point density of the cross-section position of the outer border is less than the point density of the cross-section position of the inner border, adjust the grid size of the outer border so that the point density of the cross-section position of the outer border is greater than or equal to that of the inner border.

[0093] After the cross-section positions of the buffer to be adjusted are determined, the positions can be passed to the adjacent trivial templates. In this way, the collected templates only contain a small number of trivial templates, some singular templates, and several buffer templates that have become larger after adjustment, greatly reducing the number of templates and making it possible to process large-scale bump arrays.

[0094] The template module is configurable according to the geometric characteristics of advanced packaging, adaptively matches the assembly block template, provides a configuration method for the assembly block, and an adaptive grid layout and division method.

[0095] The template management module manages various assembly block templates (such as cube assembly block templates, cube-embedded sphere templates, cube-embedded ellipsoid templates, cube-embedded lantern templates, etc.) according to geometric shapes and grid layout methods.

[0096] The template generation module divides the assembly block into multiple topological hexahedrons through grid layout. A reasonable grid layout is the key to ensuring grid quality.

[0097] Select the optimal grid layout under the currently determined discretization conditions: Use the intersection lines of the position points of each cross-section and the outer shell of the assembly block specification template as the intersection lines of the topological solid units and the outer shell of the assembly block specification template under the internal grid layout of the assembly block specification template to achieve the grid layout of the assembly block specification template. Calculate the mean square deviation of the edge lengths of each topological hexahedron under the current layout, and select the one with the smallest mean square deviation from multiple layouts as the accepted grid layout. Calculate the parametric representation of each edge of each topological hexahedron (optional but not limited to equal arc length, equal central angle parameterization methods). Calculate the parametric representation of each face of each topological hexahedron, further establish the topological relationships of the body, face, and edge, and obtain the assembly block template to be divided.

[0098] The grid division module, after determining the internal geometric shape and grid layout of the assembly block template to be divided, divides the grid through the following steps. According to the grid layout and the discretization cross-sections set by the user, calculate the sampling point parameters on each edge of the topological hexahedron. Calculate the homotopy mapping of each edge of the topological hexahedron to the unit line segment (see Figure 7 ), and establish the mapping between the topological hexahedron and the standard cube. For each topological hexahedron, perform equidistant interpolation in its standard cube. Through the inverse mapping of the homotopy mapping and the composite inverse mapping of the edge and face parameterizations, map the position values of the interpolation points back to the original three-dimensional space to obtain the three-dimensional values of the grid points. Further construct one-dimensional, two-dimensional, and three-dimensional template element units to obtain the final grid division and establish the mapping relationship between the template geometry and the one-dimensional, two-dimensional, and three-dimensional template element units.

[0099] The assembly block is an instance of the template and is the basic unit used to actually build the geometric model. The assembly block management module generates assembly block instances (generated by the assembly block generation module) based on different templates according to the user's requirements, and groups and manages the assembly blocks according to the user's requirements. The assembly block splicing module provides the function of placing the positions of the assembly blocks and automatically fuses the grid units (points, lines, and faces) within the group. The assembly block generation module generates assembly block instances and determines the actual positions of the assembly blocks in three-dimensional space. Add the assembly blocks to the assembly block group specified by the user. The assembly block group automatically identifies the position relationships of each vertex according to the tolerance specified by the user and performs the fusion operation of the points. Establish the global index of the grid and convert the geometric grid mapping relationship of the template into the geometric grid mapping relationship of the assembly block.

[0100] Based on the output capabilities of a specific solver file format, the unified integration of the modeling tool, the material database module, and the solver becomes possible.

[0101] An output module that outputs solver files meeting the requirements of different solvers. The input of the solver is a simulation model description file, which is the output file of the above-mentioned modeling tool. The simulation model description file may specifically include finite elements (i.e., meshes), component materials, and boundary conditions, etc.

[0102] This solution solves the problem that large-scale mesh generation in structural simulation of advanced packaging is prone to crashing, simplifies the modeling process of structural simulation in advanced packaging, and improves the degree of automation in modeling structural simulation in advanced packaging.

[0103] Embodiment 4

[0104] Figure 8 It is a schematic structural diagram of a modeling device for a structural simulation model of advanced chip packaging provided in Embodiment 4 of the present invention. As Figure 8 shown, the device includes:

[0105] A data acquisition module 310, configured to acquire packaging structure description data;

[0106] An assembly block specification template determination module 320, configured to determine component space layout parameters according to the component placement parameters in the packaging structure description data, and perform assembly block template specification processing based on the component description parameters in the packaging structure description data to obtain an assembly block specification template;

[0107] A mesh layout and division module 330, configured to perform mesh layout on the assembly block specification template according to the assembly block specification template to obtain an assembly block template to be divided, and perform mesh division on the assembly block template to be divided to obtain an assembly block to be spliced;

[0108] An assembly block layout module 340, configured to layout the assembly block to be spliced according to the component space layout parameters to obtain a discretized packaging structure simulation model.

[0109] In the technical solution of the embodiment of the present invention, by obtaining the package structure description data, the component space layout parameters are determined according to the component placement parameters in the package structure description data, and based on the component description parameters in the package structure description data, the assembly block template specification process is carried out to obtain the assembly block specification template. Furthermore, the grid layout of the assembly block specification template is performed to obtain the assembly block template to be divided, and the grid division of the assembly block template to be divided is carried out to obtain the assembly block to be spliced. Further, according to the component space layout parameters, the assembly block to be spliced is laid out to obtain the discretized package structure simulation model. In this solution, based on the package structure description data, the spatial layout of the components can be automatically determined, and the assembly block templates corresponding to the components can be specified to reduce the number of templates and improve the subsequent processing efficiency, effectively avoiding system crashes during the processing of large-scale package structures. Moreover, the processes of grid layout, grid division of the templates, and finally splicing the assembly blocks based on the spatial layout of the components do not require manual intervention, solving the problems of high labor costs and poor processing effects of large-scale package structures in the existing advanced package structure simulation, and being able to reduce the labor costs of advanced package structure simulation and improve the processing effects of large-scale package structures.

[0110] Optionally, the assembly block specification template determination module 320 is specifically configured to perform spatial division on the space occupied by all components based on the component description parameters in the package structure description data to obtain a spatial division result, and perform an intersection operation between the spatial division result and each component to obtain the first type of template and the second type of template for each component; and perform the assembly block template specification process according to the first type of template and the second type of template for each component to obtain the assembly block specification template.

[0111] Optionally, the assembly block specification template determination module 320 is specifically configured to determine the buffer to be adjusted for the current component when the discrete cross-section positions of the second type of template and the first type of template of the current component are different; and perform the assembly block template specification process according to the inner border cross-section position point density, the outer border cross-section position point density, and the buffer adjustment threshold of the buffer to be adjusted for the current component to obtain the assembly block specification template corresponding to the current component.

[0112] Optionally, the assembly block specification template determination module 320 is specifically configured to calculate the density difference between the outer border cross-section position point density and the inner border cross-section position point density when the outer border cross-section position point density of the buffer to be adjusted is less than the inner border cross-section position point density; expand the buffer to be adjusted according to the density difference and the buffer size threshold to obtain the template to be specified for the current component, perform spatial division based on the expanded buffer to be adjusted, and update the first type of template; and perform the assembly block template specification process on the first type of template to obtain the assembly block specification template corresponding to the current component.

[0113] Optionally, the grid layout and division module 330 is specifically configured to determine the template size of the second type template of the current component, and obtain the buffer size ratio coefficient; determine the buffer size to be adjusted according to the template size of the second type template and the buffer size ratio coefficient; in the first type template adjacent to the second type template of the current component, divide the buffer to be adjusted adjacent to the second type template of the current component according to the buffer size to be adjusted.

[0114] Optionally, the grid layout and division module 330 is specifically configured to obtain the cross-sectional position points corresponding to the assembly block specification template; divide the assembly block specification template into multiple topological solid units according to the cross-sectional position points and at least one grid layout, and calculate the mean square deviation of the edge lengths of the topological solid units under each grid layout; determine the assembly block template to be divided according to the mean square deviation of the edge lengths of the topological solid units under each grid layout.

[0115] Optionally, the grid layout and division module 330 is specifically configured to perform grid division on the assembly block template to be divided based on the homotopy mapping method and the equidistant interpolation method to obtain the assembly block to be spliced.

[0116] Optionally, the modeling device for the structure simulation model of chip advanced packaging further includes obtaining boundary condition setting parameters, and outputting a simulation model description file according to the boundary condition setting parameters and the discretized packaging structure simulation model.

[0117] The modeling device for the structure simulation model of chip advanced packaging provided by the embodiments of the present invention can execute the modeling method for the structure simulation model of chip advanced packaging provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0118] Embodiment 5

[0119] Figure 9 FIG. shows a schematic structural diagram of an electronic device that can be used to implement the embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, personal digital assistants, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0120] As Figure 9As shown, the electronic device 10 includes at least one processor 11 and a memory communicatively connected to the at least one processor 11, such as ROM 12, RAM 13, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 into the RAM 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, ROM 12, and RAM 13 are connected to each other through the bus 14. The I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0121] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disc, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0122] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the modeling method of the structural simulation model of chip advanced packaging.

[0123] In some embodiments, the modeling method of the structural simulation model of chip advanced packaging can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the modeling method of the structural simulation model of chip advanced packaging described above can be executed. Alternatively, in other embodiments, the processor 11 can be configured to execute the modeling method of the structural simulation model of chip advanced packaging in any other appropriate way (for example, by means of firmware).

[0124] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0125] The computer program for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer program can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0126] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0127] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball), by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input received from the user can be in any form (including acoustic input, voice input, or tactile input).

[0128] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0129] A computing system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system and solves the defects of traditional physical hosts and VPS servers, such as difficult management and weak business scalability.

[0130] The embodiment of the present application also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the modeling method of the structure simulation model of the advanced chip packaging provided in any embodiment of the present application. This program product and the modeling method of the structure simulation model of the advanced chip packaging disclosed in each embodiment of the present application belong to the same inventive concept, and thus will not be elaborated herein.

[0131] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0132] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A modeling method for a structural simulation model of advanced chip packaging, characterized in that Including: Obtain encapsulated structure description data; Determine component spatial layout parameters according to the component placement parameters in the encapsulated structure description data, and perform assembly block template specification processing based on the component description parameters in the encapsulated structure description data to obtain an assembly block specification template; Perform grid layout on the assembly block specification template to obtain an assembly block template to be partitioned, and perform grid partitioning on the assembly block template to be partitioned to obtain assembly blocks to be spliced; Layout the assembly blocks to be spliced according to the component spatial layout parameters to obtain a discretized encapsulated structure simulation model.

2. The method according to claim 1, characterized in that, The performing assembly block template specification processing based on the component description parameters in the encapsulated structure description data to obtain an assembly block specification template includes: Based on the component description parameters in the encapsulated structure description data, perform spatial partitioning on the space occupied by all components to obtain a spatial partitioning result, and perform intersection with each component based on the spatial partitioning result to obtain a first type template and a second type template for each component; Perform assembly block template specification processing according to the first type template and the second type template of each component to obtain the assembly block specification template.

3. The method according to claim 2, wherein The performing assembly block template specification processing according to the first type template and the second type template of each component to obtain the assembly block specification template includes: When the discrete cross-section positions of the second type template and the first type template of the current component are different, determine the buffer to be adjusted for the current component; Perform assembly block template specification processing according to the inner border cross-section position point density, the outer border cross-section position point density, and the buffer adjustment threshold of the buffer to be adjusted for the current component to obtain the assembly block specification template corresponding to the current component.

4. The method according to claim 3, wherein The performing assembly block template specification processing according to the inner border cross-section position point density, the outer border cross-section position point density, and the buffer adjustment threshold of the buffer to be adjusted for the current component to obtain the assembly block specification template corresponding to the current component includes: When the outer border cross-section position point density of the buffer to be adjusted is less than the inner border cross-section position point density, calculate the density difference between the outer border cross-section position point density and the inner border cross-section position point density; According to the density difference and the buffer size threshold, expand the buffer to be adjusted to obtain the template to be specified for the current component, perform spatial partitioning based on the expanded buffer to be adjusted, and update the first type template; Perform assembly block template specification processing on the first type template to obtain the assembly block specification template corresponding to the current component.

5. The method according to claim 3, wherein The determining the buffer to be adjusted for the current component when the discrete cross-section positions of the second type template and the first type template of the current component are different includes: Determine the template size of the second type template of the current component and obtain the buffer size ratio coefficient; Determine the size of the buffer to be adjusted according to the template size of the second type template and the buffer size ratio coefficient. In the first-type template adjacent to the second-type template of the current component, according to the size of the buffer to be adjusted, the buffer to be adjusted adjacent to the second-type template of the current component is divided.

6. The method according to claim 1, wherein The grid layout of the assembly block specification template to obtain the assembly block template to be divided includes: Obtain the cross-section position points corresponding to the assembly block specification template; According to the cross-section position points and at least one grid layout, divide the assembly block specification template into multiple topological solid units, and calculate the mean square deviation of the edge lengths of the topological solid units under each grid layout; Determine the assembly block template to be divided according to the mean square deviation of the edge lengths of the topological solid units under each grid layout.

7. The method according to claim 1, characterized in that, The grid division of the assembly block template to be divided to obtain the assembly block to be spliced includes: Based on the homotopy mapping method and the isometric interpolation method, perform grid division on the assembly block template to be divided to obtain the assembly block to be spliced; After the layout of the assembly block to be spliced according to the component space layout parameters to obtain the discrete packaging structure simulation model, it further includes: Obtain the boundary condition setting parameters, and according to the boundary condition setting parameters and the discrete packaging structure simulation model, output a simulation model description file.

8. A modeling device for a structural simulation model of advanced chip packaging, characterized in that, It includes: A data acquisition module for acquiring packaging structure description data; An assembly block specification template determination module for determining component space layout parameters according to the component placement parameters in the packaging structure description data, and performing assembly block template specification processing based on the component description parameters in the packaging structure description data to obtain an assembly block specification template; A grid layout and division module for performing grid layout on the assembly block specification template according to the assembly block specification template to obtain an assembly block template to be divided, and performing grid division on the assembly block template to be divided to obtain an assembly block to be spliced; An assembly block layout module for laying out the assembly block to be spliced according to the component space layout parameters to obtain a discrete packaging structure simulation model.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the modeling method of the structural simulation model for advanced packaging of chips according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a processor to implement the modeling method of the structural simulation model for advanced packaging of chips according to any one of claims 1-7 when executed.

Images