Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, the gate drive circuit comprises a frequency division signal line and a plurality of cascaded gate drive units, and each gate drive unit comprises a cascade transmission unit, an output unit, a cascade transmission frequency division control unit and an output frequency division control unit, partition frequency division display can be achieved through cooperation of the frequency division signal lines and the multiple cascaded gate drive units, on the basis, the ratio of the capacity of the first capacitor to the capacity of the second capacitor is set to be larger than or equal to the preset value, the coupling pull-down effect on the second node can be increased at low frequency, and the frequency division display effect is improved. Therefore, insufficient charging of the stage transmission output unit is improved by reducing the voltage of the second node, a low-voltage stage transmission signal can be stably output at low frequency, the condition of stage transmission failure at low frequency in partition frequency division display is improved, and the display quality at low frequency is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] There is usually a hierarchical relationship between the gate driving units in the gate driving circuit of the display panel, so as to sequentially open the sub-pixels of the corresponding rows to achieve zoned and frequency-controlled display (different display areas can achieve the same or different refresh rates).

[0003] However, in the case of zone-by-zone frequency display, level transmission failure is prone to occur at low frequencies, resulting in display abnormalities. Summary of the invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem of failure of level transmission in low-frequency display during zone-by-zone frequency division.

[0005] In a first aspect, the present application provides a gate drive circuit, which includes a frequency division signal line and a plurality of cascaded gate drive units, the frequency division signal line is used to transmit a frequency division control signal to the plurality of gate drive units, the gate drive unit includes a stage transmission unit, an output unit, a stage transmission frequency division control unit and an output frequency division control unit, the stage transmission unit includes a stage transmission receiving unit and a stage transmission output unit, the stage transmission receiving unit is used to receive the stage transmission signal of the previous stage, the stage transmission output unit is electrically connected to the stage transmission receiving unit through a first node and a second node, and is used to output the stage transmission signal of the current stage according to the signal of the first node and the signal of the second node; the output unit is electrically connected to the stage transmission output unit through a second node and a third node, and is used to output a gate control signal according to the signal of the second node and the signal of the third node; the stage The transmission frequency division control unit is electrically connected to the stage transmission receiving unit through the fourth node, and is electrically connected to the stage transmission output unit through the first node, and is used to control the signal of the first node according to the frequency division control signal to control the stage transmission output unit to output the stage transmission signal of the current stage; the output frequency division control unit is connected between the first node and the third node, and is used to control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of the current stage; wherein, the stage transmission receiving unit includes a first control unit and a second control unit connected, and the second control unit includes a first capacitor connected between the first control unit and the second node; the stage transmission output unit includes a second capacitor connected between the second node and the output end of the stage transmission output unit; the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is greater than or equal to a preset value.

[0006] In a second aspect, the present application provides a display panel, which includes the above-mentioned gate driving circuit.

[0007] The gate driving circuit and display panel provided by the present application can achieve partitioned and frequency-divided display through the cooperation of the frequency-divided signal line and a plurality of cascaded gate driving units. On this basis, by setting the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor to be greater than or equal to a preset value, the coupling pull-down effect on the second node can be increased at low frequencies, thereby improving the insufficient charging of the stage transmission unit by reducing the voltage of the second node. Furthermore, a low-voltage stage transmission signal can be stably output at low frequencies, improving the situation of stage transmission failure at low frequencies in partitioned and frequency-divided display and enhancing the display quality at low frequencies. Description of the Drawings

[0008] The following will, by describing the specific embodiments of the present application in detail with reference to the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0009] Figure 1 It is a schematic structural diagram of the gate driving circuit provided by an embodiment of the present application.

[0010] Figure 2 It is a circuit schematic diagram of the gate driving unit provided by an embodiment of the present application.

[0011] Figure 3 and Figure 4 It is a schematic structural diagram of the display panel provided by an embodiment of the present application.

[0012] Figure 5 and Figure 6 It is a circuit diagram of the pixel driving circuit provided by an embodiment of the present application.

[0013] Figure 7 and Figure 8 are respectively Figure 5 and Figure 6 Waveform diagrams of some signals in

[0014] Figure 9 It is a waveform diagram of some signals in the single-stage gate driving unit provided by an embodiment of the present application.

[0015] Figures 10 to 15 It is a waveform diagram of some signals in the multi-stage gate driving unit provided by an embodiment of the present application.

[0016] Figure 16 It is a waveform diagram of the data signal transmitted on the same data line and the frequency-division control signal corresponding to the gate driving unit. Detailed Description of the Embodiments

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0018] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0019] In this article, no distinction is made between the source and drain of a transistor, and the two can be exchanged. The terms "low voltage" and "high voltage" represent two voltages with relatively small and relatively large voltage values, respectively. They can represent the two voltage values of the same signal at different times, or the two voltage values of different signals at the same time or different times. Additionally, it should be noted that the accompanying drawings only provide the structures that are relatively closely related to the present application, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the inventive points clear at a glance, rather than indicating that the actual device is exactly the same as the attached Figure 1 drawing, and it is not a limitation on the actual device.

[0020] Referring to "embodiment" in this article means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The occurrence of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0021] The present application provides a gate driving circuit, and the gate driving circuit includes but is not limited to the following embodiments and combinations of the following embodiments.

[0022] In one embodiment, as Figure 1 shown, the gate driving circuit 10 includes a frequency-divided signal line FDL and a plurality of cascaded gate driving units 20. The frequency-divided signal line FDL is used to transmit a frequency-divided control signal FD to the plurality of gate driving units 20. As Figure 2As shown in the figure, the gate driving unit 20 includes a stage transmission unit 201, an output unit 202, a stage transmission frequency division control unit 203, and an output frequency division control unit 204. The stage transmission unit 201 includes a stage transmission receiving unit 2011 and a stage transmission output unit 2012. The stage transmission receiving unit 2011 is used to receive the stage transmission signal generated by the previous-stage gate driving unit 20. The stage transmission output unit 2012 is electrically connected to the stage transmission receiving unit 2011 through the first node P and the second node Q, and is used to output the stage transmission signal of the current stage according to the signals of the first node P and the second node Q. The output unit 202 is electrically connected to the stage transmission output unit 2012 through the second node Q and the third node S, and is used to output the gate control signal of the current stage according to the signals of the second node Q and the third node S. The stage transmission frequency division control unit 203 is electrically connected to the stage transmission receiving unit 2011 through the fourth node R, and is electrically connected to the stage transmission output unit 2012 through the first node P, and is used to control the signal of the first node P according to the frequency division control signal FD to control the stage transmission output unit 2012 to output the stage transmission signal of the current stage. The output frequency division control unit 204 is connected between the first node P and the third node S, and is used to control the signal of the third node S according to the frequency division control signal FD to control the output unit 202 to output the gate control signal of the current stage.

[0023] Specifically, Figure 1 Taking n (n≥2) cascaded gate driving units 20 as an example for illustration, the first-stage gate driving unit 20 can use the first start signal STV1 or the second start signal STV2 (with opposite phases) as its corresponding "gate control signal of the previous stage", and the gate control signal Scan(1) of the current stage output accordingly is transmitted to the next-stage (the second stage) gate driving unit 20, and so on. The nth-stage gate driving unit 20 can generate and output the gate control signal Scan(n) of the current stage (the nth stage) according to the gate control signal Scan(n - 1) of the (n - 1)th stage. Figure 2 Taking the ith-stage gate driving unit 20 as an example for illustration, the ith-stage gate driving unit 20 can generate and output the gate control signal Scan(i) of the current stage (the ith stage) according to the gate control signal Scan(i - 1) of the (i - 1)th stage.

[0024] It can be understood that, on the one hand, in this embodiment, there is a stage transmission frequency division control unit 203 connected between the stage transmission receiving unit 2011 and the stage transmission output unit 2012, which can control the signal of the first node P (whether it can be affected by the fourth node R) according to the frequency division control signal FD, so as to control the signal transmitted to the stage transmission output unit 2012, and further determine the specific situation of the stage transmission signal output by the stage transmission output unit 2012 of this stage (whether there is a stage transmission effective pulse), so as to determine whether to drive the next-stage gate driving unit 20. If the stage transmission signal has a stage transmission effective pulse, it can be considered that the stage transmission receiving unit 2011 in the next-stage gate driving unit 20 can work normally. Similarly, combined with the stage transmission frequency division control unit 203 of this stage, the specific situation of the stage transmission signal output by the stage transmission output unit 2012 of this stage can be determined. On the other hand, in this embodiment, there is also an output frequency division control unit 204 connected between the first node P and the third node S, which can control the signal of the third node S according to the frequency division control signal FD, so as to control the specific situation (whether there is a gate effective pulse) of the gate control signal of this stage output by the output unit 202 (that is, the signal transmitted to the corresponding multiple sub-pixels Pi in the display panel to control whether the sub-pixel Pi is turned on), so as to determine whether to turn on the corresponding multiple sub-pixels Pi. If the gate control signal has a gate effective pulse, it can be considered that the corresponding multiple sub-pixels Pi can be refreshed for later light emission.

[0025] It should be understood that for a plurality of cascaded gate driving units 20, if the plurality of gate control signals output by the plurality of gate driving units 20 in the first part each output a gate effective pulse in one frame of every n1 frames, the plurality of gate control signals output by the plurality of gate driving units 20 in the second part each output a gate effective pulse in one frame of every n2 frames, and the plurality of gate control signals output by the plurality of gate driving units 20 in the third part each output a gate effective pulse in one frame of every n3 frames, then it can be considered that the three display areas respectively corresponding to the three parts of sub-pixels Pi corresponding to these three parts of gate driving units 20 have corresponding three refresh rates of (1 / n1)×m, (1 / n2)×m, (1 / n3)×m, where m is the least common multiple of n1, n1, and n1.

[0026] In summary, in this embodiment, the gate control signal for determining the refresh rate of any display area of the display panel is directly determined by the corresponding output frequency division control unit 204 and the current frequency division control signal FD. One input terminal of the output frequency division control unit 204 is connected to the first node P, and the other input terminal is connected to the third node S. The third node S is connected to the first node P through the output frequency division control unit 204. That is, it can be considered that the signal of the third node S is jointly determined by the output frequency division control unit 204 and the frequency division control signal FD loaded to the output frequency division control unit 204. Therefore, the gate control signal is jointly determined by the stage transmission frequency division control unit 203, the output frequency division control unit 204, and the frequency division control signal FD loaded to the stage transmission frequency division control unit 203 and the output frequency division control unit 204. By reasonably setting these three elements, the refresh rate of the corresponding display area can be determined. Further, the above three elements corresponding to different gate driving units 20 in different display areas of the display panel can be reasonably set to achieve different refresh rates respectively.

[0027] Among them, in this embodiment, there is no limitation on whether the stage transmission frequency division control unit 203 in different gate driving units 20 is differentially set, whether the output frequency division control unit 204 is differentially set, and whether the time periods during which the frequency division control signal FD acts effectively are differentially set. For the convenience of circuit design, the stage transmission frequency division control unit 203 and the output frequency division control unit 204 in multiple-stage gate driving units 20 can be respectively set to be the same. Correspondingly, the time periods during which the frequency division control signal FD acts effectively on different gate driving units 20 can be differentially set to achieve differential setting of the refresh rates of different display areas.

[0028] In one embodiment, as Figure 1 and Figure 2 shown, the frequency division control signal FD includes a first frequency division control signal FD1 and a second frequency division control signal FD2. The frequency division signal line FDL includes a first frequency division signal line FDL1 for transmitting the first frequency division control signal FD1 and a second frequency division signal line FDL2 for transmitting the second frequency division control signal FD2. Among them, the first frequency division signal line FDL1 is electrically connected to the output frequency division control unit 204 to control the signal of the third node S. Among them, the second frequency division signal line FDL2 is electrically connected to the stage transmission frequency division control unit 203 to control the signal of the first node P.

[0029] It can be understood that in this embodiment, by specifically setting the frequency division signal line FDL as an independent first frequency division signal line FDL1 and a first frequency division signal line FDL2, an independent first frequency division control signal FD1 and a second frequency division control signal FD2 (the two may not necessarily be the same) can be transmitted respectively to independently control the working states of the output frequency division control unit 204 and the stage transmission frequency division control unit 203, thereby respectively controlling the specific conditions of the stage transmission signal and the gate control signal generated by the gate driving unit 20 of this stage.

[0030] Specifically, the effective action period of the first frequency division control signal FD1 corresponding to each level of the gate driving unit 20 and the effective action period of the second frequency division control signal FD2 corresponding to each level of the gate driving unit 20 can be reasonably set to meet different situations. For each level of the gate driving unit 20, it can include but is not limited to the following situations:

[0031] In case 1, the second frequency division control signal FD2 is reasonably set so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 has a level transmission effective pulse, thereby controlling the level transmission receiving unit 2011 in the next-level gate driving unit 20 to work normally.

[0032] Based on situation 1, it may include but is not limited to the following situations:

[0033] Case 1.1, the first frequency division control signal FD1 is reasonably set so that the gate control signal generated and output by the output frequency division control unit 204 has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission.

[0034] Case 1.2, the first frequency division control signal FD1 is reasonably set so that the gate control signal generated and output by the output frequency division control unit 204 does not have a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi not to turn on, that is, not refreshing the corresponding multiple sub-pixels Pi for later light emission.

[0035] Further, in Case 1, if the second frequency division control signal FD2 is set for each period when each stage of the gate driving unit 20 is effectively acting, such that each stage transmission signal has a stage transmission effective pulse, that is, each stage transmission signal is uninterrupted, then at this time, by setting the first frequency division control signal FD1, it is possible to control whether each stage of the gate control signal has a gate effective pulse. Combining the above discussion, arbitrary frequency division of multiple display areas can be achieved (compared with the previous display area, the refresh rate of the subsequent display area can increase or decrease). That is, in one frame, by respectively controlling the relatively front several stages and the relatively back several stages of the gate control signals to have and not have gate effective pulses in sequence, or not have and have gate effective pulses in sequence.

[0036] In Case 2, the second frequency division control signal FD2 is reasonably set such that the signal of the fourth node R cannot act on the signal of the first node P, so that the stage transmission signal generated and output by the stage transmission frequency division control unit 203 does not have a stage transmission effective pulse (determined by the signal of the first node P), thereby controlling that the stage transmission receiving unit 2011 in the next stage of the gate driving unit 20 cannot work properly. At the same time, since the signal of the third node S connected to the output unit 202 is also determined by the signal of the first node P, it can also be considered here that the signal of the third node S at this time will also cause the gate control signal of this stage not to have a gate effective pulse. Therefore, it can be considered that the gate control signals from the current stage to the last stage do not have gate effective pulses, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combining the above discussion, that is, only frequency reduction of multiple display areas can be achieved.

[0037] In Case 3, the first frequency division control signal FD1 is reasonably set such that the output frequency division control unit 204 can control the third node S to be acted on by the first node P, and further enable the output unit 202 to be acted on by the first node P.

[0038] Based on Case 3, it may specifically include but is not limited to the following situations:

[0039] In Case 3.1, the second frequency division control signal FD2 is reasonably set such that the signal of the fourth node R can act on the signal of the first node P, so that the stage transmission signal generated and output by the stage transmission frequency division control unit 203 has a stage transmission effective pulse, thereby controlling that the stage transmission receiving unit 2011 in the next stage of the gate driving unit 20 can work properly. Since the signal of the first node P can also act on the third node S to act on the output unit 202, the gate control signal generated and output by the output frequency division control unit 204 also has a gate effective pulse at this time, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission.

[0040] Case 3.2: Reasonably set the second frequency division control signal FD2 so that the signal of the fourth node R can act on the signal of the first node P, so that the stage transmission signal generated and output by the stage transmission frequency division control unit 203 does not have a stage transmission effective pulse. Similarly, as in "Case 2", it can be known that the signal of the first node P at this time cannot invalidate the signal of the third node S either, that is, it will also cause the gate control signal of this stage not to have a gate effective pulse. Therefore, it can be considered that the gate control signals from the gate control signal of the current stage to the gate control signal of the last stage do not have gate effective pulses, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission.

[0041] Among them, in Case 3, if the effective action period of the first frequency division control signal FD1 corresponding to each stage of the gate driving unit 20 is set so that the third node S of each stage is acted on by the first node P, then at this time, by setting the second frequency division control signal FD2, it can be controlled whether the signal of the fourth node R acts on the signal of the first node P, so as to control whether the stage transmission signal generated and output by each stage of the stage transmission frequency division control unit 203 has a stage transmission effective pulse. Combining the above discussion, the frequency reduction of multiple display areas can be achieved.

[0042] Case 4: Reasonably set the first frequency division control signal FD1 so that the output frequency division control unit 204 cannot control the third node S to be acted on by the first node P, and further make the output unit 202 not be acted on by the first node P, that is, regardless of the signals of the first node P and the second node Q, the first frequency division control signal FD1 will act on the output frequency division control unit 204, so that the signal of the third node S will cause the gate control signal of this stage not to have a gate effective pulse. Therefore, it can be considered that the gate control signals from the gate control signal of the current stage to the gate control signal of the last stage do not have gate effective pulses, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combining the above discussion, that is, only the frequency reduction of multiple display areas can be achieved.

[0043] In an embodiment, as Figure 2As shown, the stage transfer receiving unit 2011 includes a first control unit 20111, a second control unit 20112, and an input unit 20113. The first control unit 20111 is electrically connected to a clock signal line (including but not limited to a first clock signal line CKL1 and a second clock signal line CKL2, and the first clock signal XCK and the second clock signal CK respectively loaded thereon may be symmetric about the time axis. Here, the voltage value at the intersection of the time axis and the voltage axis is not limited, and both may include two different voltage values) and a fourth node R, and is used to control the signal of the fourth node R according to the clock signal transmitted by the clock signal line. The second control unit 20112 is electrically connected to the clock signal line and a second node Q, and is used to control the signal of the second node Q according to the clock signal. The input end of the input unit 20113 is electrically connected to the upper-stage gate driving unit 20 to load the stage transfer signal generated by the upper-stage gate driving unit 20, and the output end of the input unit 20113 is electrically connected to the first control unit 20111 and the second control unit 20112.

[0044] It should be noted that for the convenience of description in this application, in the schematic diagram, only the second stage transfer output transistor T9 is located below the first stage transfer output transistor T10 as an example (that is, the second node Q is located below the first node P for illustration. Similarly, the second output transistor T21 is located below the first output transistor T22 as an example. In fact, the present application protects the connection relationship of multiple electronic devices and is not limited to the positional relationship. Based on the input unit 20113 loading the stage transfer signal generated by the upper-stage gate driving unit 20, as Figure 2 shown, for the NScan circuit, since the stage transfer frequency division control unit 203 is connected to the first node P located above, it can be considered that the fourth node R is also set above. At this time, it can be considered that the first control unit 20111 also needs to be set near the upper part to control the voltage of the fourth node R (further combined with the stage transfer frequency division control unit 203 to control the voltage of the first node P), and the voltage of the second node Q needs to be controlled by the second control unit 20112 set near the lower part.

[0045] In an embodiment, as Figure 2 shown, the stage transfer frequency division control unit 203 and the output frequency division control unit 204 are both electrically connected to the first node P (that is, at this time, the gate driving unit 20 is taken as an example of the NScan circuit for illustration). The input unit 20113 includes an input transistor T3. The gate of the input transistor T3 is loaded with a clock signal (for example, connected to the first clock signal line CKL1 to load the first clock signal XCK). The source of the input transistor T3 is configured as the input end of the input unit 20113, and the drain of the input transistor T3 is configured as the output end of the input unit 20113.

[0046] In an embodiment, as Figure 2As shown, the second control unit 20112 includes a first capacitor C1 connected between the first control unit 20111 and the second node Q; the stage transmission output unit includes a second capacitor C6 connected between the second node Q and the output end of the stage transmission output unit; the ratio of the capacitance of the first capacitor C1 to the capacitance of the second capacitor C6 is greater than or equal to a preset value.

[0047] It can be understood that the gate driving circuit 10 provided in this application can achieve partitioned and frequency-divided display through the cooperation of the frequency-divided signal line FDL and multiple cascaded gate driving units 20. On this basis, by setting the ratio of the capacitance of the first capacitor C1 to the capacitance of the second capacitor C6 to be greater than or equal to a preset value, the coupling pull-down effect on the second node Q can be increased at low frequencies, thereby improving the insufficient charging of the stage transmission output unit 2012 by reducing the voltage of the second node Q. Furthermore, a stage transmission signal with a low voltage can be stably output at low frequencies, improving the stage transmission failure situation at low frequencies in the partitioned and frequency-divided display and enhancing the display quality at low frequencies.

[0048] In one embodiment, the preset value can be 1.3, 1.4, 1.5, or 1.6, so that the charging effect of the second stage transmission output transistor T9 can be improved through the lower voltage of the second node Q, thereby ensuring the effectiveness of the stage transmission.

[0049] In some embodiments, the capacitance of the first capacitor C1 is less than or equal to 600 farads and greater than or equal to 100 farads.

[0050] It should be noted that in this embodiment, the capacitance of the second capacitor C6 can be configured according to the capacitance of the first capacitor C1, and there is no need to limit the specific range of the capacitance of the second capacitor C6. If the capacitance of the first capacitor C1 is too large, the occupied area of the first capacitor C1 will be too large, resulting in a too large border. At the same time, the voltage of node E will be too high and abnormal; if the capacitance of the first capacitor C1 is too small, the coupling pull-down effect will be reduced, resulting in too high a voltage of the second node Q at low frequencies and reducing the effectiveness of the stage transmission.

[0051] In some embodiments, the capacitance of the second capacitor C6 is less than or equal to 500 farads and greater than or equal to 100 farads.

[0052] It should be noted that in this embodiment, the capacitance of the first capacitor C1 can be configured according to the capacitance of the second capacitor C6, and there is no need to limit the specific range of the capacitance of the first capacitor C1. If the capacitance of the second capacitor C6 is too large, the occupied area of the first capacitor C1 will be too large, resulting in a too large border; if the capacitance of the second capacitor C6 is too small, the coupling pull-down effect will be reduced, resulting in too high a voltage of the second node Q at low frequencies and reducing the effectiveness of the stage transmission.

[0053] In some of these embodiments, such asFigure 2 As shown, the second control unit 20112 further includes a first transistor T1, a second transistor T2, and a third transistor T16. The gate of the first transistor T1 is electrically connected to the drain of the fourth transistor T4. The source of the first transistor T1 is loaded with a first voltage. The drain of the first transistor T1 is electrically connected to the source of the second transistor T2. The drain of the second transistor T2 is loaded with a clock signal. The gate of the second transistor T2 is also loaded with a stage transfer signal generated by the upper gate driving unit 20. A first capacitor C1 is electrically connected between the gate and the drain of the second transistor T2. The gate and the source of the third transistor T16 are both electrically connected to the gate of the second transistor T2. The drain of the third transistor T16 is electrically connected to the second node Q.

[0054] In one embodiment, as Figure 2 shown, the second control unit 20112 further includes an eighth transistor T13. The gate of the eighth transistor T13 (is electrically connected to the control line CL to) is loaded with a control signal. The source of the eighth transistor T13 is loaded with a first voltage. The drain of the eighth transistor T13 is electrically connected to the second node Q.

[0055] In one embodiment, as Figure 2 shown, the second control unit 20112 further includes a ninth transistor T12. The source and the drain of the ninth transistor T12 are electrically connected to the drain of the input transistor T3 and the second node Q respectively. The gate of the ninth transistor T12 is connected to the second voltage line.

[0056] In one embodiment, as Figure 2 shown, the second control unit 20112 further includes a tenth transistor T14. The source of the tenth transistor T14 is loaded with a stage transfer signal generated by the upper gate driving unit 20. The gate of the tenth transistor T14 is loaded with a clock signal (the first clock signal XCK). The drain of the tenth transistor T14 is electrically connected to the gate of the second transistor T2.

[0057] Similarly, the second control unit 20112 may further be provided with a twelfth transistor T15 for maintaining a lower voltage at the gate of the second transistor T2. The gate of the twelfth transistor T15 may be loaded with a second voltage. The source and the drain of the twelfth transistor T15 may be electrically connected to the drain of the tenth transistor T14 and the gate of the second transistor T2 respectively.

[0058] It can be understood that while the tenth transistor T14 can be used to control the voltage of the gate of the second transistor T2, by further providing a third transistor T16 connected between the second node Q and the gate of the second transistor T2, the second node Q is not directly electrically connected to the first capacitor C1, so as to avoid being affected by the coupling effect of the first capacitor C1 and maintain a relatively low voltage at the second node Q. Among them, the first capacitor C1 can be used to maintain the voltage of the corresponding node and play a coupling role.

[0059] In one embodiment, as Figure 2 shown, the stage transfer output unit 2012 includes a first stage transfer output transistor T10 and a second stage transfer output transistor T9. The gate of the first stage transfer output transistor T10 is electrically connected to the first node P. The source of the first stage transfer output transistor T10 is electrically connected to the first voltage line to load the first voltage VGH. The drain of the first stage transfer output transistor T10 is electrically connected to the stage transfer output terminal OUT in the gate driving unit 20 for outputting the stage transfer signal. The gate of the second stage transfer output transistor T9 is electrically connected to the second node Q. The source of the second stage transfer output transistor T9 is electrically connected to the second voltage line to load the second voltage VGL. The drain of the second stage transfer output transistor T9 is electrically connected to the stage transfer output terminal OUT.

[0060] Specifically, the first node P can control the turning-on situation of the first stage transfer output transistor T10 to control whether the first voltage can be transmitted to the stage transfer output terminal OUT. The second node Q can control the turning-on situation of the second stage transfer output transistor T9 to control whether the second voltage can be transmitted to the stage transfer output terminal OUT. Combining the above discussion, in the present application, a third frequency division transistor T17 connected between the fourth node R and the first node P or the second node Q is provided to control whether the first node P or the second node Q can receive the signal of the fourth node R, so as to control the turning-on situation of the first output transistor T22 or the second output transistor T21, thereby controlling the specific situation of the stage transfer signal generated and output by the stage transfer output terminal OUT.

[0061] For example, when the first stage transfer output transistor T10 is turned on and the second stage transfer output transistor T9 is turned off, the gate control signal can be equal to the first voltage. Another example is when the first stage transfer output transistor T10 is turned off and the second stage transfer output transistor T9 is turned on, the generated stage transfer signal can be equal to the second voltage. Another example is when both are turned off, the generated stage transfer signal can be equal to the previous voltage. Another example is when both are turned on, the generated stage transfer signal can be between the first voltage and the second voltage.

[0062] In one embodiment, as Figure 2As shown, the first-stage transmission output unit 2012 further includes a fourth capacitor C3. The first end of the fourth capacitor C3 is connected to the source of the first-stage transmission output transistor T10, and the second end of the fourth capacitor C3 is connected to the gate of the first-stage transmission output transistor T10.

[0063] It should be noted that the fourth capacitor C3 can be used to maintain the voltage of the corresponding node and play a coupling role. The seventh transistor T11 and the ninth transistor T12 can ensure that they are turned on only when the source voltages of both are low enough to maintain a low voltage at their drains, which is beneficial to the turn-on of the first-stage transmission output transistor T10 and the second-stage transmission output transistor T9 respectively.

[0064] In one embodiment, as Figure 2 shown, the first control unit 20111 includes a fourth transistor T4, a fifth transistor T6, and a sixth transistor T7. The gate of the fourth transistor T4 is loaded with a clock signal (such as the first clock signal XCK), the source of the fourth transistor T4 is loaded with a second voltage, and the drain of the fourth transistor T4 is electrically connected to the gate of the fifth transistor T6 and the drain of the eleventh transistor T5. The drain of the fifth transistor T6 is electrically connected to the source of the sixth transistor T7. The source of the fifth transistor T6 and the gate of the sixth transistor T7 are both loaded with a clock signal, and the drain of the sixth transistor T7 is electrically connected to the fourth node R.

[0065] In one embodiment, as Figure 2 shown, the first control unit 20111 may further include a seventh transistor T11 and a third capacitor C2. The gates of the seventh transistor T11 and the ninth transistor T12 can both be loaded with a second voltage to maintain conduction. The source and drain of the seventh transistor T11 are electrically connected to the drain of the fourth transistor T4 and the gate of the fifth transistor T6 respectively, and the third capacitor C2 is electrically connected between the gate and the drain of the fifth transistor T6.

[0066] In one embodiment, as Figure 2 shown, the first control unit 20111 may further include an eleventh transistor T5. The gate of the eleventh transistor T5 is electrically connected to the drain of the input transistor T3, the source of the eleventh transistor T5 is loaded with a clock signal (such as the first clock signal XCK), and the drain of the eleventh transistor T5 is connected to the node C.

[0067] In one embodiment, as Figure 2As shown, the output frequency division control unit 204 includes a first frequency division transistor T18. The gate of the first frequency division transistor T18 is connected to the first frequency division signal line FDL. The source of the first frequency division transistor T18 is electrically connected to the first node P or the second node Q, and the drain of the first frequency division transistor T18 is electrically connected to the third node S. Among them, the first frequency division control signal FD1 is used to control the electrical connection or disconnection between the third node S and the first node P or the second node Q.

[0068] Among them, as can be seen from the above discussion, the first frequency division control signal FD1 can act on the output frequency division control unit 204 to control whether the third node S is affected by the first node P or the second node Q. Further, in this embodiment, it is illustrated that the first frequency division control signal FD1 can act on the gate of the first frequency division transistor T18 in the output frequency division control unit 204 to control the electrical connection or disconnection between the third node S and the first node P or the second node Q.

[0069] Specifically, if it is electrically connected, it can be considered that the third node S can be affected by the first node P or the second node Q, which is equivalent to the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output unit 202 has a gate effective pulse (i.e., the above-mentioned case 3). If it is disconnected, it can be considered that the third node S cannot be affected by the first node P or the second node Q. Since neither the first node P nor the second node Q used to control the generation of the stage transmission signal can act on the output unit 202, it can be considered that the gate control signal generated and output by the output unit 202 does not have a gate effective pulse (i.e., the above-mentioned case 4).

[0070] In one embodiment, as Figure 2 shown, the output frequency division control unit 204 further includes a second frequency division transistor T20. The gate of the second frequency division transistor T20 is electrically connected to the sixth node of the stage transmission unit 201. The source of the second frequency division transistor T20 is electrically connected to the first frequency division signal line FDL, and the drain of the second frequency division transistor T20 is electrically connected to the gate of the first frequency division transistor T18. Among them, the first frequency division control signal FD1 and the signal of the sixth node are used to control the electrical connection or disconnection between the third node S and the first node P or the second node Q. Among them, the signal of the sixth node is also used to control the stage transmission signal and the gate control signal output by the gate driving unit 20 of this stage.

[0071] It can be understood that in this embodiment, a second frequency division transistor T20 electrically connected to the gate of the first frequency division transistor T18 is further provided, and the turning-on situation of the second frequency division transistor T20 is determined by the signal of the sixth node, and the signal of the sixth node is also used to control the stage transmission signal and the gate control signal output at this stage. That is, it can be considered that the state of the signal of the sixth node can feedback the states of both the stage transmission signal and the gate control signal at this stage. In this way, it can be ensured that when the states of both the stage transmission signal and the gate control signal generated at this stage are appropriate, the turning-on of the second frequency division transistor T20 is controlled, and then the first frequency division control signal FD1 is transmitted to the gate of the first frequency division transistor T18 of this stage to control the turning-on situation of the first frequency division transistor T18. On the premise that the stage transmission signal and the gate control signal of each stage can be output as correct waveforms, the differential setting of the refresh rates of different display areas can be realized.

[0072] In one embodiment, as Figure 2 shown, the output frequency division control unit 204 further includes a sixth capacitor C5, and the sixth capacitor C5 is connected between the first voltage line and the node X.

[0073] It should be noted that in this embodiment, the specific connection relationship between the sixth node and the above modules is not limited, and only the limitation of "the signal of the sixth node is also used to control the stage transmission signal and the gate control signal output by the gate driving unit 20 at this stage" needs to be satisfied. For example, the sixth node can be electrically connected to the first node P or the second node Q, or even the sixth node can be the first node P or the second node Q. In this application, the sixth node is taken as the node D as an example for illustration (based on Figure 2 the second frequency division transistors T20 in Figure 9 are P-type transistors and N-type transistors respectively, and both can refer to the analysis in the following text about

[0074] Specifically, combined with the analysis in the following text about Figure 2 and Figure 9 , it can be known that based on the stage transmission signal generated at this stage having a stage transmission effective pulse (that is, the signals of the first node P and the second node Q are both effective signals), if the gate control signal at this stage needs to output a gate effective pulse, it can be considered that the voltage of the signal of the sixth node after the time node that can ensure the complete output of the gate effective pulse at this stage (for example, the end point of the fifth stage t5 in Figure 9 ) can be used to control the transmission of the first frequency division control signal FD1 to the gate of the first frequency division transistor T18 of this stage. For example, if the second frequency division transistor T20 is a P-type transistor, it can be considered that the voltage of the sixth node is a higher voltage and a lower voltage respectively before and after the time node of the complete output of the gate effective pulse at this stage, so as to ensure that the second frequency division transistor T20 will be turned on after the complete output of the gate effective pulse at this stage.

[0075] Specifically, if the gate control signal of this stage does not need to output a gate valid pulse, it can be known from the above discussion that the first frequency division control signal FD1 corresponding to the starting point (voltage jump) of the effective action period of this stage can be set at the moment when the voltage corresponding to the gate valid pulse of this stage appears in the signal of the sixth node (for example, at the starting point of the third stage t3 in Figure 9 ), to ensure that the electrical connection between the third node S and the first node P is cut off before the gate valid pulse of this stage is output.

[0076] In one embodiment, as Figure 1 and Figure 2 shown, the stage transmission frequency division control unit 203 includes a third frequency division transistor T17. The gate of the third frequency division transistor T17 is electrically connected to the second frequency division signal line FDL2. The source of the first frequency division transistor T18 is electrically connected to the stage transmission receiving unit 2011 through the fourth node R. The drain of the third frequency division transistor T17 is electrically connected to the first node P. Among them, the second frequency division control signal FD2 is used to control the electrical connection or disconnection between the fourth node R and the first node P.

[0077] Among them, it can be known from the above discussion that the second frequency division control signal FD2 can act on the stage transmission frequency division control unit 203 to control whether the first node P is affected by the fourth node R. Further, in this embodiment, it is illustrated that the second frequency division control signal FD2 can act on the gate of the third frequency division transistor T17 in the stage transmission frequency division control unit 203 to control the electrical connection or disconnection between the fourth node R and the first node P.

[0078] Specifically, if they are electrically connected, it can be considered that the first node P can be affected by the fourth node R, which is equivalent to that the signal of the fourth node R can control whether the stage transmission signal generated and output by the stage transmission output unit 2012 has a stage transmission valid pulse (i.e., the above-mentioned case 1). If they are disconnected, it can be considered that the first node P cannot be affected by the fourth node R. Since the fourth node R used to control the stage transmission signal generated by this stage cannot act on the stage transmission output unit 2012, it can be considered that the stage transmission signal generated and output by the stage transmission output unit 2012 does not have a stage transmission valid pulse (i.e., the above-mentioned case 2).

[0079] In one embodiment, as Figure 2As shown, the output unit 202 includes a first output transistor T22 and a second output transistor T21. The gate of the first output transistor T22 is electrically connected to the third node S. The source of the first output transistor T22 is electrically connected to the first voltage line. The drain of the first output transistor T22 is electrically connected to the gate output terminal OUTA in the gate driving unit 20 for outputting a gate control signal. The gate of the second output transistor T21 is electrically connected to the first node P or the second node Q. The source of the second output transistor T21 is electrically connected to the second voltage line. The drain of the second output transistor T21 is electrically connected to the gate output terminal OUTA.

[0080] In one embodiment, as Figure 2 shown, the output unit 202 further includes a fifth capacitor C4. The fifth capacitor C4 is connected between the gate and the source of the first output transistor T22.

[0081] Similarly to the above discussion, the third node S can control the turning-on situation of the first output transistor T22 to control whether the first voltage can be transmitted to the gate output terminal OUTA. The first node P or the second node Q can control the turning-on situation of the second output transistor T21 to control whether the second voltage can be transmitted to the gate output terminal OUTA. Combining the above discussion, it can be known that in the present application, by providing a first frequency-dividing transistor T18 connected between the third node S and the first node P or the second node Q to control whether the third node S can receive the signal of the first node P or the second node Q, the turning-on situation of the first output transistor T22 or the second output transistor T21 can be controlled, so as to control the specific situation of the gate control signal generated and output by the gate output terminal OUTA.

[0082] In one embodiment, the gate driving unit 20 is electrically connected to at least one corresponding pixel driving circuit 302. The gate output terminal OUTA is electrically connected to the pixel transistors in each corresponding pixel driving circuit 302, and the first voltage is greater than the second voltage. Wherein, when the pixel transistor is an N-type transistor, as Figure 2 shown, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing transistor T18 are both electrically connected to the first node P (at this time, it can be considered that the gate driving unit 20 is the i-th level NScan circuit, the generated gate control signal is the NScano(i) signal, the stage transmission signal is the NScan(i) signal, and the stage transmission signal of the previous stage is the NScan(i - 1) signal).

[0083] Among them, in this embodiment, the architecture of the pixel driving circuit 302 is not limited. It can be considered that the pixel transistors therein can control the turning-on situation of the corresponding sub-pixel Pi under the control of the gate control signal output by the gate driving unit 20. Specifically, in this embodiment, based on the first voltage being greater than the second voltage, when the pixel transistor is an N-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing transistor T18 are both electrically connected to the first node P, so as to control the turning-on situations of both the first-stage transfer output transistor T10 and the first output transistor T22, so as to control whether the larger first voltage (which can be the effective voltage of the N-type transistor) can be transmitted to the gate of the N-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on. When the pixel transistor is a P-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing transistor T18 are both electrically connected to the second node Q, so as to control the turning-on situations of the second-stage transfer output transistor T9 and the second output transistor T21, so as to control whether the smaller second voltage (which can be the effective voltage of the P-type transistor) can be transmitted to the gate of the P-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on.

[0084] According to the above discussion, when the durations of the effective voltages required for turning on the N-type or P-type pixel transistors are equal respectively, it can be considered that among the NScano signal and the PScano signal output by the NScan circuit and the PScan circuit respectively, the voltage value of the gate effective pulse of the former (such as but not limited to equal to the first voltage) is greater than the voltage value of the gate effective pulse of the latter (such as but not limited to equal to the second voltage), and the pulse widths of the gate effective pulses of both can be equal.

[0085] Furthermore, since the stage transfer receiving unit 2011 can receive the stage transfer signal generated by the upper stage, according to the stage transfer function of the stage transfer signal, the first start signal STV1 and the second start signal STV2 respectively loaded to the first-stage NScan circuit and the first-stage PScan circuit can also be obtained by translating the stage transfer signals (NScan(1), PScan(1)) generated by their respective first-stage gate driving units 20 along the negative direction of the time axis by the same distance, that is, the voltage values of the stage transfer effective pulses of both can be equal to the first voltage and the second voltage respectively. Among them, the first start signal STV1, the second start signal STV2, the NScano signal, the PScano signal, the NScan signal and the PScan signal can all be periodic signals.

[0086] Among them, in the present application, taking the transistors in the gate driving unit 20 as all P-type transistors as an example, the operation of some signals in some states is described as follows: When powering on, the control signal transmitted by CL can control the eighth transistor T13 to turn on to transmit the first voltage to the second node Q. In the later stage, when there is a low voltage in the first clock signal and a low voltage in the (i-1)-th stage gate control signal NScano(i-1), the gate control signal NScano(i-1) controls both the eleventh transistor T5 and the second output transistor T21 to turn on. The second voltage is transmitted to the stage output terminal OUT through the second output transistor T21, and the first clock signal controls the fourth transistor T4 to turn on. The second voltage is transmitted to the gate of the fifth transistor T6 to control it to turn on. At this time, the high voltage in the second clock signal controls the sixth transistor T7 to turn off. In the later stage, when there is a high voltage in the first clock signal, the input transistor T3, the fifth transistor T6, and the fourth transistor T4 turn off. At this time, it can be considered that the second output transistor T21 remains on. The low voltage in the second clock signal controls the sixth transistor T7 to turn on, and the fourth node R is still not loaded with voltage, and the stage output terminal OUT still outputs the second voltage.

[0087] It should be noted that the present application does not limit the type of each transistor in the gate driving unit 20. For example, they can all be P-type transistors, or some can be N-type transistors and the other part can be P-type transistors. The corresponding signals can also be matched and set according to the type of the transistors. Specifically, reference can be made to the principle description in the full text regarding "all the transistors in the gate driving unit 20 are P-type transistors".

[0088] Furthermore, the gate driving unit 20 in the present application can also but is not limited to being an EM circuit. The difference between the EM circuit and the NScan circuit is that the first start signal STV1 is replaced by the third start signal STV3. The third start signal STV3 can be understood as obtaining the first start signal STV1 by translating a certain distance along the negative or positive direction of the time axis, and the waveforms of the two do not overlap. Similarly, the third start signal STV3 can also be a periodic signal.

[0089] The display panel provided by the present application includes but is not limited to the following embodiments and combinations of the following embodiments.

[0090] In one embodiment, in combination with Figures 3 to 6 as shown, the display panel 100 includes the gate driving circuit 10 as described in any of the above.

[0091] It can be understood that since the display panel 100 provided in the present application includes the gate driving circuit 10, it is also possible to achieve partitioned and frequency-divided display through the cooperation of the frequency-dividing signal line FDL and a plurality of cascaded gate driving units 20. On this basis, by setting the ratio of the capacitance of the first capacitor C1 to the capacitance of the second capacitor C6 to be greater than or equal to a preset value, the coupling pull-down effect on the second node Q can be increased at low frequencies, thereby improving the insufficient charging of the stage transmission output unit 2012 by reducing the voltage of the second node Q. Furthermore, a low-voltage stage transmission signal can be stably output at low frequencies, improving the stage transmission failure situation at low frequencies in the partitioned and frequency-divided display and enhancing the display quality at low frequencies.

[0092] In some embodiments, the display panel further includes a plurality of sub-pixels Pi located in the display area, and the plurality of sub-pixels Pi are connected to the gate driving circuit 10; wherein, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C6 both increase as the width of the display area increases.

[0093] It should be noted that as the size (such as the width) of the display area of the display panel increases, the load on the gate driving circuit also increases. At high frequencies, the step voltage of the stage transmission signal decreases. In a harsh high and low temperature environment, at low frequencies, the gate driving circuit 10 outputs a low-level gate control signal to the display area. Due to the lack of coupling pull-down effect, the load on the second node Q is relatively large, resulting in a high voltage. The second stage transmission output transistor T9 is insufficiently charged, leading to stage transmission failure and display abnormality at low frequencies.

[0094] In this embodiment, since the capacitance of the first capacitor C1 and the capacitance of the second capacitor C6 both increase as the width of the display area increases, the coupling pull-down effect on the second node Q can also be increased at low frequencies, thereby improving the insufficient charging of the stage transmission output unit 2012 by reducing the voltage of the second node Q. Furthermore, a low-voltage stage transmission signal can be stably output at low frequencies, improving the stage transmission failure situation at low frequencies in the partitioned and frequency-divided display and enhancing the display quality at low frequencies.

[0095] The display panel 100 further includes a panel main body 30. The panel main body 30 includes a plurality of sub-pixels Pi and a plurality of scan lines SL. The sub-pixel Pi includes a light-emitting device 301 and a pixel driving circuit 302 for driving the light-emitting device 301 to emit light. The pixel driving circuit 302 includes at least one transistor (i.e., the pixel transistor discussed above). Among them, the gate control signal output by the gate driving unit 20 is transmitted to the gates of a plurality of transistors in the corresponding plurality of pixel driving circuits 302 through the corresponding scan line.

[0096] Among them, Figure 3Taking the display panel 100 including six gate driving circuits 10 (GOA1, GOA2, two GOA3s, GOA4, GOA5, electrically connected to corresponding sub-pixels Pi through the first scan line EML1, the second scan line NSL1, the third scan line PSL, the fourth scan line NSL2, and the fifth scan line EML2 respectively) as an example for illustration: For example, the two GOA3s can be, but are not limited to, the same PScan circuit, that is, the signals (the second start signal STV2) loaded by both and the output signals can be the same respectively, so as to improve the reliability of the PScan signals output by both. For example, GOA1 and GOA5 can be two different EM circuits respectively. For example, the two corresponding third start signals STV3 of both can be different (for example, but not limited to, the pulse width and / or the start time of the effective pulse of both can be different). For example, GOA2 and GOA4 can be two different NScan circuits respectively. For example, the two corresponding first start signals STV1 of both can be different (for example, but not limited to, the pulse width and / or the start time of the effective pulse of both can be different).

[0097] Figure 4 and Figure 3 The difference from... is that the six gate driving circuits 10 include two GOA1', GOA2', two GOA3', GOA4', which are electrically connected to corresponding sub-pixels Pi through the sixth scan line EML', the seventh scan line NSL1', the eighth scan line PSL1', and the ninth scan line NSL2' respectively. Similarly, the two GOA1' can be, but are not limited to, the same EM circuit, GOA2' and GOA4' can be two different NScan circuits respectively. For example, the two corresponding first start signals STV1 of both can be different, and the two GOA3s can be, but are not limited to, the same PScan circuit.

[0098] It should be noted that Figure 3 and Figure 4 only show the connection relationships between multiple gate driving units 20 in the same gate module with each other, and the connection relationships between each of them and multiple sub-pixels Pi. As for the signal lines connected to each gate driving unit 20, reference can be made to Figure 1 and Figure 2 and the relevant text descriptions above.

[0099] Specifically, as shown in combination with Figure 3 and Figure 5 shown Figure 5 includes Figure 3The pixel driving circuit 302 corresponding to the setting mode of the gate driving circuit 10 therein. The pixel driving circuit 302 may include a data transistor M2. A data signal Vdata is loaded at the source of the data transistor M2. The drain of the data transistor is electrically connected to the source of the driving transistor M1. The gate of the data transistor M2 (for example, a P-type transistor) may be electrically connected to the third scan line PSL to load a PScan signal.

[0100] Among them, the pixel driving circuit 302 may further include a reset transistor M4 and a compensation transistor M3. The gate of the reset transistor M4 (for example, an N-type transistor) may be electrically connected to the scan line NSL1 to load an NScan1 signal. The reset transistor M4 is configured to transmit a reset signal VI1 to the gate of the driving transistor M1 for resetting. The gate of the compensation transistor M3 (for example, an N-type transistor) may be electrically connected to the fourth scan line NSL2 to load an NScan2 signal. The source and drain of the compensation transistor M3 are electrically connected to the drain and gate of the driving transistor M1 respectively.

[0101] Among them, the pixel driving circuit 302 may further include an initialization transistor M7. The gate of the initialization transistor M7 (for example, a P-type transistor) is electrically connected to the fifth scan line EML2 to load an EM2 signal. The drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (a low voltage signal VSS may be loaded at the other end of the light-emitting device 301). The initialization transistor M7 is configured to transmit an initialization signal VI2 to one end of the light-emitting device 301 for initialization.

[0102] Among them, the pixel driving circuit 302 further includes a reset transistor M8. The gate of the reset transistor M8 (for example, a P-type transistor) may be electrically connected to the fifth scan line EML2 to load an EM2 signal. The drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1. The reset transistor M8 is configured to transmit a reset signal VI3 to the source of the driving transistor M1 to reset its voltage.

[0103] Among them, the pixel driving circuit 302 may further include a first light-emitting control transistor M5 and a second light-emitting control transistor M6. A first high voltage VDD is loaded at the source of the first light-emitting control transistor M5. The drain of the first light-emitting control transistor M5 is electrically connected to the source of the driving transistor M1. The source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one end of the light-emitting device 301 respectively. The gates of both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (for example, both are P-type transistors) are electrically connected to the first scan line EML1 to load an EM1 signal, and are both configured to control the light-emitting time of the light-emitting device 301 according to the EM1 signal.

[0104] Among them, the pixel driving circuit 302 further includes a storage capacitor Cst, and the storage capacitor Cst is connected in series between the source of the first light-emitting control transistor M5 and the gate of the driving transistor M1.

[0105] Among them, the pixel driving circuit 302 further includes a boosting capacitor Cboost, and the boosting capacitor Cboost is connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0106] Based on the above discussion, as Figure 7 shown, Figure 7 for Figure 6 the timing diagram corresponding to the pixel driving circuit 302 in

[0107] In the first reset stage tim1, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the input terminal, output terminal, and control terminal (source, drain, and gate) of the driving transistor M1 are reset according to the reset signal VI3.

[0108] In the second reset stage tim2, the reset transistor M4 is turned on according to the corresponding NScano1 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate and drain of the driving transistor M1 are reset according to the initialization signal VI2.

[0109] In the data writing stage tim3, the data transistor M2 is turned on according to the corresponding PScano signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate of the driving transistor M1 is written with the data signal Vdata.

[0110] In the light-emitting stage tim4, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo1 signal, so that the driving transistor M1 generates a driving current to drive the corresponding light-emitting device 301 to emit light.

[0111] Further, between the light-emitting stage tim4 and the data writing stage tim3, a third reset stage tin may further be included. In the third reset stage tin, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the source and drain of the driving transistor M1 are reset according to the reset signal VI3.

[0112] It should be noted that byFigure 4 and Figure 3 From the differences in the settings of the gate driving circuit 10, in combination with Figure 4 and Figure 6 as shown, Figure 6 includes Figure 4 the pixel driving circuit 302 corresponding to the setting method of the gate driving circuit 10 in Figure 6 can only be driven by the same EM circuit, so it can only be electrically connected to the same sixth scan line EML' and loaded with the same signal (unlike Figure 5 in which it can be electrically connected to the first scan line EML1 and the fifth scan line EML2 to be loaded with two different signals).

[0113] Specifically, as Figure 6 shown, compared with Figure 5 the difference is that the reset transistor M8 is removed, the first scan line EML1 is replaced by the sixth scan line EML', the second scan line NSL1 is replaced by the seventh scan line NSL1', the third scan line PSL is replaced by the eighth scan line PSL1', the fourth scan line NSL2 is replaced by the ninth scan line NSL2', and the fifth scan line EML2 is also replaced by the upper-level eighth scan line PSL1'.

[0114] Based on the above discussion, as Figure 8 shown, Figure 8 is Figure 6 the timing diagram corresponding to the pixel driving circuit 302 in

[0115] In the first reset stage tim1', the reset transistor M4 is turned on according to the corresponding NScano1'(i) signal, so that the gate of the driving transistor M1 is reset according to the initialization signal VI1.

[0116] In the second reset stage tim2', the initial transistor M7 is turned on according to the corresponding PScano1'(i - 1) signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the compensation transistor M3 is turned on according to the corresponding NScano1'(2) signal.

[0117] In the data writing stage tim3', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal, and the compensation transistor M3 is turned on according to the corresponding NScano2'(i) signal, so that the gate of the driving transistor M1 can write the data signal Vdata.

[0118] In the third reset stage tim4', the initial transistor M7 is turned on according to the corresponding PScano1'(i - 1) signal, so that the anode of the light-emitting device 301 is reset again according to the initialization signal VI2.

[0119] In the coupling stage tim5', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal. At this time, regardless of the data signal Vdata, since the compensation transistor M3 is cut off, it will not affect the gate voltage of the driving transistor M1. However, since the gate voltage of the data transistor M2 decreases, it will also cause the gate voltage of the driving transistor M1 to increase.

[0120] In the light-emitting stage tim6', the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo'(i) signal, so that the driving transistor M1 generates a driving current to drive the corresponding light-emitting device 301 to emit light. Since the gate voltage of the driving transistor M1 in the coupling stage tim5' rises to be greater than the data voltage given by the data signal Vdata in the data writing stage tim3', the light-emitting device 301 will have a greater brightness. It can also be considered that the upper limit of the data voltage can be effectively reduced and the power consumption can be saved.

[0121] According to the above analysis, in the writing frame WF, in order to realize the normal light emission of each row of sub-pixels Pi, that is, each gate driving unit 20 (each of GOA1 to GOA5, each of GOA1' to GOA4') needs to output corresponding gate effective pulses in the corresponding time period to control the corresponding transistors in the pixel driving circuit 302 to turn on, so as to realize the corresponding functions to turn on the sub-pixels Pi. It can also be considered that if the gate driving unit 20 cannot output the corresponding gate effective pulses in the corresponding time period, the sub-pixels Pi in the corresponding row will not be able to emit light.

[0122] Such as Figure 5 and Figure 6As shown, if the PScano signal and the PScano1'(i) signal do not have a gate-effective (low voltage) pulse, the data transistor M2 cannot be turned on, resulting in the data signal being unable to be written to the source of the driving transistor M1 and the sub-pixel Pi being unable to be turned on. If the EM1 signal and the EMo'(i) signal do not have a gate-effective (low voltage) pulse, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 cannot be turned on, resulting in the driving current not being formed and the sub-pixel Pi being unable to be turned on. If the NScano2 signal and the NScano2'(i) signal do not have a gate-effective (high voltage) pulse, the compensation transistor M3 cannot be turned on, resulting in the data signal being unable to be written to the gate of the driving transistor M1 and the sub-pixel Pi being unable to be turned on. Of course, if the EMo2 signal, the NScano1 signal, and the NScano1'(i) signal do not have an effective pulse, it will also have a certain impact on the light emission of the sub-pixel Pi.

[0123] Specifically, based on Figure 5 the pixel driving circuit 302 shown, at least one of the three gate driving units 20 respectively used to generate the PScano signal, the EMo1 signal, and the NScano2 signal in the present application can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204 discussed above. Based on Figure 6 the pixel driving circuit 302 shown, at least one of the three gate driving units 20 respectively used to generate the PScano1'(i) signal, the EMo'(i) signal, and the NScano2'(i) signal in the present application can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204. In this way, on the premise that the start signals (such as the first start signal STV1, the second start signal STV2, and the third start signal STV3) in the first-stage gate driving unit 20 have been set, in each frame, and in combination with the setting of the frequency division control signal FD (refer to the discussion of cases 1 to 4 above), it is possible to control whether the first node P (for Figure 2 speaking) is electrically connected to the fourth node R, and control whether the third node S is electrically connected to the first node P (for Figure 2 speaking), so that the output gate control signal has or does not have a gate-effective pulse, to control whether the sub-pixel Pi in the corresponding row is turned on (refreshed).

[0124] In an embodiment, as Figure 3 and Figure 4As shown, the display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the plurality of gate driving units 20 include a plurality of first gate driving units 2001 cascaded, and a plurality of second gate driving units 2002 cascaded after the plurality of first gate driving units 2001. Among them, the plurality of sub-pixels Pi include a plurality of first sub-pixels Pi1 electrically connected to the plurality of first gate driving units 2001, and a plurality of second sub-pixels Pi2 electrically connected to the plurality of second gate driving units 2002, and the plurality of first sub-pixels Pi constitute a first display area, and the plurality of second sub-pixels Pi constitute a second display area. In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area. In the frequency increase mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

[0125] In combination with the above discussion, it can be seen that the present application can control whether the level transmission signal generated by this stage has a level transmission valid pulse and whether the gate control signal has a gate valid pulse by setting the above-mentioned level transmission frequency division control unit 203 and output frequency division control unit 204 in the gate driving unit.

[0126] Specifically, here Figure 2 As an example, the i-th level NScan circuit shown here is based on Figure 2 The transistors in are all P-type transistors (i.e., low voltage is effective), the third frequency-dividing transistor T17 is turned on (i.e., the second frequency-dividing control signal FD2 is at its lower voltage), the first clock signal line CKL1 and the second clock signal line CKL2 transmit the first clock signal and the second clock signal respectively, and the combination Figure 8 The working sequence of the NScan circuit shown in the figure is described, which may include but is not limited to the following 6 working stages:

[0127] In the first stage t1, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i - 1) generated by the previous stage is set low: the sixth transistor T7 is in the off state according to the second clock signal line CK. The fourth transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low stage transfer signal NScan(i - 1) is transmitted to the node D, the second node Q, and the node F, causing the eleventh transistor T5, the thirteenth transistor T8, the second stage transfer output transistor T9, the second transistor T2, and the third transistor T16 to turn on according to NScan(i - 1). The second voltage VGL is transmitted to the node C and the node B, the high second clock signal line CK is transmitted to the node E, and the first voltage VGH is transmitted to the node P (the fourth node R), causing the fifth transistor T6 and the first transistor T1 to turn on according to the second voltage VGL. The high second clock signal line CK is transmitted to the node A to charge the third capacitor C2 to be equal to the voltage difference between the node A and the node B. The first voltage VGH is transmitted to the node E (the voltage of the node E can be between the first voltage VGH and the high voltage of the second clock signal line CK) to charge the first capacitor C1 to be equal to the voltage difference between the node E and the node F to charge the first capacitor C1, causing the voltage of the node F to be coupled and increased. Since the first stage transfer output transistor T10 is off and the second stage transfer output transistor T9 is on, the generated gate control signal NScano(i) is at a low voltage.

[0128] In the second stage t2, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i - 1) generated by the previous stage is set low: The fourth transistor T4, the input transistor T3, and the tenth transistor T14 are in the off state according to the first clock signal XCK. The gate of the eleventh transistor T5, the node D, the second node Q, and the node F maintain the previous voltage. The second transistor T2 remains on, and the low second clock signal line CK is transmitted to the node E. The voltage of the node F is further pulled down by the falling coupling of the first capacitor C1 with the second clock signal CK, so that the third transistor T16 remains on. The voltage of the node F is transmitted to the node D, but the voltage of the node D also rises due to the coupling effect of the rising of the first clock signal XCK transmitted by the first clock signal line CKL1 in the circuit layout. The third transistor T16 is turned off. Due to the action of the ninth transistor T12, the voltage of the second node Q can be prevented from changing following the voltage of the node D, and the second-stage transfer output transistor T9 still remains on. The eleventh transistor T5 still remains on, and the high first clock signal XCK is transmitted to the node C and the node B, and the first transistor T1 and the fifth transistor T6 are turned off. The thirteenth transistor T8 is turned on according to the voltage of the node D, and the first voltage VGH is transmitted to the first node P (the fourth node R) to turn off the first-stage transfer output transistor T10. At the same time, the low second clock signal line CK turns on the sixth transistor T7, and the first voltage VGH is further transmitted to the node A to charge the third capacitor C2 to be equal to the voltage difference between the node A and the node B. Since the first-stage transfer output transistor T10 is turned off and the second-stage transfer output transistor T9 is turned on, the generated gate control signal NScano(i) is at a low voltage.

[0129] In the third stage t3, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i - 1) generated by the previous stage is set high: the sixth transistor T7 is in the off state according to the second clock signal line CK. The fourth transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the set-high stage transfer signal NScan(i - 1) is transmitted to node D, node Q, node F, and the gate of the eleventh transistor T5, and the second voltage VGL is transmitted to node C and node B. The second stage transfer output transistor T9 is turned off, and the eleventh transistor T5 is turned off according to the set-high stage transfer signal NScan(i - 1). The first transistor T1 and the fifth transistor T6 are turned on according to the second voltage VGL, and the first voltage VGH is transmitted to node E to charge the first capacitor C1 to be equal to the voltage difference between node E and node F. The set-high second clock signal line CK is transmitted to node A to charge the third capacitor C2 to be equal to the voltage difference between node A and node B. The thirteenth transistor T8 is turned off according to the set-high stage transfer signal NScan(i - 1), and the first node P (the fourth node R) maintains the previous (high) voltage through the fourth capacitor C3, so that the first stage transfer output transistor T10 is turned off. Since the first stage transfer output transistor T10 is turned off and the second stage transfer output transistor T9 is turned off, that is, the stage transfer output terminal OUT is floating, the generated gate control signal NScano(i) is maintained at a low voltage.

[0130] In the fourth stage t4, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i - 1) generated by the previous stage is set high: The input transistor T3, the fourth transistor T4, and the tenth transistor T14 are in the off state according to the first clock signal XCK. The gate of the eleventh transistor T5, the node D, the second node Q, and the node C maintain the previous voltage. The eleventh transistor T5 is turned off according to the previous high voltage, the second stage transfer output transistor T9 is turned off according to the previous high voltage of the second node Q, the thirteenth transistor T8 is turned off according to the high voltage of the node D, the first transistor T1 and the fifth transistor T6 are turned on according to the previous low voltage of the node C, and the second transistor T2 is turned off according to the previous high voltage of the node F. The first voltage VGH is transmitted to the node E through the first transistor T1, that is, the voltage of the node E basically does not change. Combining with the coupling effect of the first capacitor C1, the voltage of the node F can also remain basically unchanged. The second clock signal CK set low is transmitted to the node A through the fifth transistor T6. Combining with the coupling effect of the third capacitor C2, the voltage of the node B also decreases. The sixth transistor T7 is turned on according to the second clock signal CK, and the low voltage at point A is transmitted to the node P (the fourth node R) through the sixth transistor T7, thereby turning on the first stage transfer output transistor T10. Since the first stage transfer output transistor T10 is turned on and the second stage transfer output transistor T9 is turned off, the generated gate control signal NScano(i) is a high voltage.

[0131] In the fifth stage t5, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i-1) generated by the previous stage is set low: the sixth transistor T7 is in the off state according to the second clock signal line CK. The fourth transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low stage transfer signal NScan(i-1) is transmitted to the node D, the second node Q, and the gate of the eleventh transistor T5 through the input transistor T3. The second stage transfer output transistor T9 is turned on according to the low voltage of the second node Q, and the second transistor T2 is turned on according to the voltage of the node F to enable the high second clock signal line CK to be transmitted to the node E to charge the first capacitor C1 to be equal to the voltage difference between the node E and the node F. The eleventh transistor T5 is turned on to enable the low first clock signal XCK to be transmitted to the node C and the node B, and the first transistor T1 is turned on according to the low first clock signal XCK and the second voltage VGL, and the first voltage VGH is transmitted to the node E through the first transistor T1 (the voltage of the node E can be between the first voltage VGH and the high voltage of the second clock signal line CK). Based on the equality of the first voltage VGH and the high voltage of the second clock signal line CK, the voltage of the node E remains almost unchanged, the voltage of the node F remains almost unchanged, and the third transistor T16 is turned off, which can prevent the first capacitor C1 from affecting the falling speed of the voltage of the second node Q. The fifth transistor T6 is turned on according to the low voltage of the node B to enable the high second clock signal line CK to be transmitted to the node A to charge the third capacitor C2 to be equal to the voltage difference between the node A and the node B. The thirteenth transistor T8 is turned on according to the low voltage of the node D to enable the first voltage VGH to be transmitted to the first node P (the fourth node R), thereby turning off the first stage transfer output transistor T10. Since the first stage transfer output transistor T10 is turned off and the second stage transfer output transistor T9 is turned on, the generated gate control signal NScano(i) is at a low voltage.

[0132] In the sixth stage t6, the stage transfer signal NScan(i-1) generated by the previous stage is set low, the first clock signal XCK and the second clock signal line CK are alternately set low and high, driving the voltage of the node F to couple downward. Each time the voltage of the node F couples downward, the voltage will gradually decrease, approaching -16V, and the voltage of the corresponding second node Q gradually decreases, approaching -20V. In the first few cycles after the eleventh transistor T5 in the fifth stage, the downward coupling of the voltage of the node F is more obvious, and the voltage of the second node Q is greatly affected by the voltage of the node F. In the later stage, the third transistor T16 is turned off, and the voltage of the second node Q tends to be stable and will not be affected by the voltage of the node F.

[0133] It should be noted that the gate driving unit provided in the present application is provided with the above-mentioned tenth transistor T14, twelfth transistor T15, and third transistor T16. On the one hand, when the stage transfer signal NScan(i - 1) of the previous stage writes a low voltage to the second node Q and the node F, at this time, the voltage of the second node Q can flow out from both the third transistor T16 and the ninth transistor T12, and the second node Q is not directly connected to the first capacitor C1 (blocked by the third transistor T16) to maintain the voltage. Therefore, the voltage of the second node Q can drop faster, which is beneficial to the turn-on of the second-stage transfer output transistor T9. On the other hand, the second node Q is not directly connected to the first capacitor C1 (blocked by the third transistor T16), so the fluctuation of the voltage of the node E will not drive the change of the voltage of the second node Q, and the third transistor T16 plays a role similar to a diode, and the voltage of the second node Q will not be pulled up by the node F.

[0134] Combined with the above discussion, referring to Figure 2 and Figure 9 it can be seen that if the stage transfer signal NScan(i - 1) generated by the previous stage is always set low (excluding valid high-voltage pulses), it can be considered that the second node Q and the node D are always maintained at a low voltage to always turn on the second-stage transfer output transistor T9 and the thirteenth transistor T8, and to always turn off the first-stage transfer output transistor T10, so that the stage transfer signal NScan(i) output by this stage is always at a low voltage (excluding valid high-voltage pulses).

[0135] Combined with the above discussion, referring to Figure 2 and Figure 9 it can be seen that if the third frequency-dividing transistor T17 is turned off (that is, the second frequency-dividing control signal FD2 is at its higher voltage) period, that is, the connection between the first node P and the fourth node R is disconnected. At this time, the voltage of the first node P can only be determined by the turn-on state of the thirteenth transistor T8 and the coupling effect of the fourth capacitor C3.

[0136] Specifically, in the first stage t1, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off. In the second stage t2, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off. In the third stage t3, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-stage transmission output transistor T10 is turned off. In the fourth stage t4, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-stage transmission output transistor T10 is turned off. In the fifth stage t5, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off. In the sixth stage t6, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off. Therefore, it can be considered that the first-stage transmission output transistor T10 is turned off in each stage, and the gate control signal is related to the on-state of the second-stage transmission output transistor T9, specifically as follows:

[0137] In the first stage t1, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated at this stage is a low voltage.

[0138] In the second stage t2, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated at this stage is a low voltage.

[0139] In the third stage t3, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is floating, so the stage transmission signal NScano(i) generated at this stage is maintained at a low voltage.

[0140] In the fourth stage t4, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is floating, so the stage transmission signal NScano(i) generated at this stage is maintained at a low voltage.

[0141] In the fifth stage t5, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated at this stage is a low voltage.

[0142] In the sixth stage t6, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated at this stage is a low voltage.

[0143] In summary, if the third frequency - dividing transistor T17 is turned off (i.e., the second frequency - dividing control signal FD2 is at its higher voltage) during a period, the stage - transfer signal NScan(i) generated by this stage is at a low voltage. If the third frequency - dividing transistor T17 is turned on (i.e., the second frequency - dividing control signal FD2 is at its lower voltage) during a period, under the alternating high - and low - voltage action of the stage - transfer signal NScan(i - 1) generated by the previous stage, the first clock signal XCK, and the second clock signal CK, the stage - transfer signal NScan(i) generated by this stage can form a stage - transfer effective pulse (such as a high - voltage pulse) in a corresponding time period (for example, between the start of the fourth stage t4 and the end of the fifth stage in Figure 9 ), so as to act on the corresponding transistor (such as Figure 5 and Figure 6 the compensation transistor M3 in) in the pixel driving circuit 302 of the corresponding row to turn on (refresh) the light - emitting devices 301 of the corresponding row.

[0144] It can be understood that in this application, the stage - transfer signal generated by the gate driving unit 20 of this stage is only transferred to the gate driving unit 20 of the next stage, and the generated gate control signal is only loaded to the sub - pixels Pi of the corresponding row of this stage. Combining the above analysis, in one frame, if the first node P in the gate driving unit 20 of this stage (for Figure 2 speaking) is not electrically connected to the fourth node R, regardless of whether the third node S is electrically connected to the first node P or the second node Q, the gate control signal of this stage does not have an effective pulse, which causes the sub - pixels Pi of the corresponding row of this stage to be unable to be turned on. At the same time, the stage - transfer signal of this stage does not have a stage - transfer effective pulse, so it is also unable to control the operation of the gate driving unit 20 of the next stage, resulting in the stage - transfer signal and the gate control signal of the next stage not having a stage - transfer effective pulse and a gate effective pulse respectively (that is, the sub - pixels Pi of the corresponding row of the next stage are also unable to be turned on). By analogy, the sub - pixels Pi of the subsequent rows are all unable to be turned on. That is, only when the first node P in the gate driving unit 20 of each stage (for Figure 2 speaking) is electrically connected to the fourth node R, can we further control whether the third node S is electrically connected to the first node P or the second node Q to control whether the sub - pixels Pi of each row are turned on.

[0145] It should be understood that if the number of frames in which multiple first sub - pixels Pi are turned on is more than the number of frames in which multiple second sub - pixels Pi are turned on in consecutive multiple frames, it means that the first display area has a higher refresh rate than the second display area, and vice versa.

[0146] Among them, if you want to implement the frequency - reduction mode (the refresh rate of the first display area to the second display area decreases), the following method can be adopted: in consecutive multiple frames, in at least one frame at the front (for example, Figure 10In Frame1), it is possible to control the stage transmission signals and gate control signals generated at all levels (for example Figure 10 in NScano(1) to NScano(6) in it) each have a stage transmission valid pulse and a gate valid pulse pl. In at least one later frame (for example Figure 10 in Frame 4), control the stage transmission signals and gate control signals generated by each first gate driving unit 2001 (for example Figure 10 in NScano(1) to NScano(2) in it) respectively have a stage transmission valid pulse and a gate valid pulse pl, and control the stage transmission signals generated by each second gate driving unit 2002 not to have a stage transmission valid pulse so that the corresponding gate control signals (for example Figure 10 in NScano(3) to NScano(6) in it) also do not have a gate valid pulse, or only the generated gate control signals (for example Figure 10 in NScano(3) to NScano(6) in it) do not have a gate valid pulse.

[0147] Specifically, here in combination with Figure 2 and related discussions, it can be known that in the frequency reduction mode, taking the first frequency division transistor T18 as a P-type transistor as an example here, there are the following two implementation methods:

[0148] Method 1, please refer to but not limited to Figure 10 , the first frequency division control signal FD1 (that is, its voltage is equal to the low voltage) is used to control the third node S in each stage gate driving unit 20 to be electrically connected to the first node P (for Figure 2 ). Within one frame, the second frequency division control signal FD2 is used to control the first node P or the second node Q in the first gate driving unit 2001 to be electrically connected to the fourth node R to control the output gate control signal to have a gate valid pulse pl to turn on the corresponding light emitting device 301. Within the frame, the second frequency division control signal FD2 is also used to control the disconnection between the first node P or the second node Q and the fourth node R in the second gate driving unit 2002 to control the output gate control signal not to have a gate valid pulse pl to not turn on the corresponding light emitting device 301.

[0149] Method 2, the difference from Method 1 is that the second frequency division control signal FD2 (that is, its voltage is equal to the low voltage) is used to control the fourth node R in each stage gate driving unit 20 to be electrically connected to the first node P (for Figure 2For example). Within one frame, the first frequency division control signal FD1 is used to control the third node S in the first gate driving unit 2001 to be electrically connected to the first node P or the second node Q, so as to control the output gate control signal to have a gate effective pulse pl to turn on the corresponding light-emitting device 301. Within the frame, the first frequency division control signal FD1 is also used to control an open circuit between the third node S and the first node P or the second node Q in the second gate driving unit 2002, so as to control the output gate control signal not to have a gate effective pulse pl to not turn on the corresponding light-emitting device 301.

[0150] Regardless of whether method 1 or method 2 is adopted, for the first-stage gate driving unit 20 to the sixth-stage gate driving unit 20, assuming that the refresh rates of the first two stages (the first stage to the second stage) of the gate driving unit 20, the middle two stages (the third stage to the fourth stage) of the gate driving unit 20, and the last two stages (the fifth stage to the sixth stage) of the gate driving unit 20 are 120HZ, 60HZ, and 30HZ respectively, according to the above content, within four consecutive frames (Frame 1 to Frame 4), it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, the gate control signals NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 and Frame 3, and the gate control signals NScano(5) to NScano(6) only have gate effective pulses pl in Frame 1.

[0151] That is, the frequency division control signal FD needs to be set as follows (taking method 1 as an example for illustration):

[0152] The first frequency division control signal FD1 is at a low voltage in Frame 1 to Frame 4 to turn on the six first frequency division transistors T18 corresponding to the first-stage to sixth-stage gate driving units 20, so that the gate control signal generated by each can be the same as the corresponding stage transmission signal.

[0153] The second frequency division control signal FD2 is at a low voltage corresponding to each stage in Frame 1 to turn on the six third frequency division transistors T17 corresponding to the first-stage to sixth-stage gate driving units 20, so that the six stage transmission signals NScan(1) to NScan(6) and the six gate control signals NScano(1) to NScano(6) all have gate effective pulses pl in Frame 1.

[0154] The second frequency division control signal FD2 is at a low voltage before tf1 in Frame 2 to turn on two third frequency division transistors T17 corresponding to the gate driving units 20 of the first to second levels, so that NScano(1) to NScano(2) both have gate effective pulses pl in Frame 2, and is at a high voltage after tf1 to turn off four third frequency division transistors T17 corresponding to the gate driving units 20 of the third to sixth levels, so that NScano(3) to NScano(6) do not have gate effective pulses pl in Frame 2.

[0155] The second frequency division control signal FD2 is at a low voltage before tf2 in Frame 3 to turn on four third frequency division transistors T17 corresponding to the gate driving units 20 of the first to fourth levels, so that NScan(1) to NScan(4) both have gate effective pulses pl in Frame 3, and is at a high voltage after tf2 to turn off two third frequency division transistors T17 corresponding to the gate driving units 20 of the fifth to sixth levels, so that NScan(5) to NScan(6) do not have gate effective pulses pl in Frame 3.

[0156] The analysis of the second frequency division control signal FD2 in Frame 4 can refer to the analysis in Frame 2.

[0157] Of course, as analyzed above, in contrast Figure 10 it is also possible to make the second frequency division control signal FD2 be at a low voltage in Frames 1 to 4 to turn on six third frequency division transistors T17 corresponding to the gate driving units 20 of the first to sixth levels, so that each level transfer signal generated has a level transfer effective pulse respectively.

[0158] Furthermore, by controlling the first frequency division control signal FD1 in each frame to have or not have a gate effective pulse during the period when it effectively acts on the corresponding gate driving unit, the corresponding frequency division setting is achieved.

[0159] In summary, the display panel can be at least divided into a first region, a second region, and a third region. The first region (corresponding to the action of the 1st to 2nd level gate driving units 20) has data written (i.e., 4 data refreshes are performed) by being loaded with valid pulses pl in each of Frame 1 to Frame 4. The second region (corresponding to the action of the 3rd to 4th level gate driving units 20) has data written (i.e., 2 data refreshes are performed) by being loaded with gate valid pulses pl in both Frame 1 and Frame 3, that is, its refresh rate is half of that of the first region. Similarly, the second region (corresponding to the action of the 5th to 6th level gate driving units 20) has data written (i.e., 1 data refresh is performed) only in Frame 1 by being loaded with valid pulses pl, and its refresh rate is 1 / 4 of that of the first region. In the above example, the refresh rates of the first region, the second region, and the third region can be a, (1 / 2)×a, and (1 / 4)×a respectively, where a is an integer multiple of 4, and 4 frames need to be divided. For example, they are respectively equal to 120HZ, 60HZ, and 30HZ.

[0160] Here, for the convenience of explanation, it is only taken as an example that the display panel is divided into 3 regions, and each region corresponds to the action of 2-level gate control signals, and the refresh rates of the three can be a, (1 / 2)×a, and (1 / 4)×a respectively. Those skilled in the art should understand that the number of region divisions of the display panel and the number of rows of sub-pixels Pi included in each region can be changed, and the corresponding refresh rates can also be adjusted. Here, it is only to show the difference in refresh rates of multiple regions and the resulting frame setting requirements. If the refresh rate of each latter region among the 3 regions is 1 / 3 of the refresh rate of the former region, then 9 frames need to be shown so that the refresh times of the 3 regions are in a 3-fold relationship, that is, in the 9 frames, the three regions are refreshed 9 times, 3 times, and 1 time respectively.

[0161] Specifically, if you want to implement the up-frequency mode (the frequency rises from the first display area to the second display area), the following method can be adopted: In a continuous multi-frame, in at least one frame at the front (such as Figures 11 to 15 Frame 1 in Figures 11 to 12 ), it can be controlled that the stage transfer signals and gate control signals generated by all levels respectively have stage transfer valid pulses and gate valid pulses. In at least one frame at the back (such as Figures 13 to 14 Frame 4 in Figure 15 Frame 3 in Figures 11 to 12 NScan(1) to NScan(2) in Figures 13 to 14from NScan(3) to NScan(4) in Figure 15 from NScan(1) to NScan(4) in Figure 15 , the stage transfer signals and gate control signals generated by each second gate driving unit 2002 each have a stage transfer valid pulse and a gate valid pulse (for example Figures 11 to 12 from NScan(3) to NScan(4) in Figures 13 to 14 from NScan(5) to NScan(6) in Figure 15 from NScan(5) to NScan(6) in Figures 13 to 14 ).

[0162] Specifically, taking the combination of Figure 2 and related discussions as an example, in the up - frequency mode, please refer to but not limited to Figures 11 to 15 , taking the third frequency - dividing transistor T17 as a P - type transistor here, that is, the second frequency - dividing control signal FD2 (for example, its voltage is equal to the low voltage) is used to control the fourth node R in each gate driving unit 20 to be electrically connected to the first node P (for Figure 2 ). In one frame, the first frequency - dividing control signal FD1 is used to control the third node S and the first node P in the first gate driving unit 2001 (for Figure 2 ) to be open - circuited, so as to control that the output gate control signal does not have a gate valid pulse and does not turn on the corresponding light - emitting device 301. In the frame, the first frequency - dividing control signal FD1 is used to control the first node P in the second gate driving unit 2002 (for Figure 2 ) to be electrically connected to the fourth node R, so as to control that the output gate control signal has a gate valid pulse and turns on the corresponding light - emitting device 301.

[0163] For example Figure 11 as shown, for the above - mentioned first 2 - stage gate driving units 20, middle 2 - stage gate driving units 20, and last 2 - stage gate driving units 20, their refresh rates are 30HZ, 120HZ, and 60HZ respectively. Then, according to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have a gate valid pulse pl in Frame 1, NScano(3) to NScano(4) have a gate valid pulse pl in Frame 1 to Frame 4, and the gate control signals NScano(5) to NScano(6) have a gate valid pulse pl in Frame 1 and Frame 3.

[0164] That is, the frequency - dividing control signal FD needs to be set as follows:

[0165] The second frequency division control signal FD2 is at a low voltage from Frame 1 to Frame 4 to turn on all six third frequency division transistors T17 corresponding to the gate driving units 20 of the first to sixth stages, so that each stage transmission signal generated has a stage transmission effective pulse.

[0166] The first frequency division control signal FD1 is at a low voltage corresponding to each stage in Frame 1 to turn on the six first frequency division transistors T18 corresponding to the gate driving units 20 of the first to sixth stages, enabling the third node S to be electrically connected to the first node P or the second node Q, so that the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0167] The first frequency division control signal FD1 is at a high voltage before tf1 and after ft2 in Frame 2 to turn off the two first frequency division transistors T18 corresponding to the gate driving units 20 of the first, second, fifth, and sixth stages, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have gate effective pulses pl in Frame 2, and is at a low voltage between tf1 and ft2 to turn on the two first frequency division transistors T18 corresponding to the gate driving units 20 of the first and third stages, so that NScano(1) to NScano(3) do not have gate effective pulses pl in Frame 2.

[0168] The first frequency division control signal FD1 is at a high voltage before tf3 in Frame 3 to turn off the two first frequency division transistors T18 corresponding to the gate driving units 20 of the first and second stages, so that NScano(1) to NScano(2) do not have gate effective pulses pl in Frame 3, and is at a low voltage after tf3 to turn on the four first frequency division transistors T18 corresponding to the gate driving units 20 of the third to sixth stages, so that NScano(3) to NScano(6) have gate effective pulses pl in Frame 3.

[0169] The analysis of the first frequency division control signal FD1 in Frame 4 can refer to the analysis in Frame 2.

[0170] Similarly, for example Figure 12As shown, the refresh rates of the above-mentioned first 2-stage gate driving units 20, middle 2-stage gate driving units 20, and last 2-stage gate driving units 20 are 60HZ, 120HZ, and 30HZ respectively. According to the above content, it can be set as follows within Frame 1 to Frame 4: NScano(1) to NScano(2) have gate active pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate active pulses pl in Frame 1 to Frame 4, and the gate control signals NScano(5) to NScano(6) have gate active pulses pl only in Frame 1.

[0171] That is, the frequency division control signal FD needs to be set as follows:

[0172] The second frequency division control signal FD2 is the same as Figure 11 the same setting in the above to make the stage transfer signals generated by each stage of the gate driving unit 20 all have stage transfer active pulses.

[0173] The first frequency division control signal FD1 corresponds to a low voltage for each stage in Frame 1. Similarly, to make the 6 gate control signals NScano(1) to NScano(6) also have gate active pulses pl in Frame 1.

[0174] The first frequency division control signal FD1 is a high voltage before tf1 and after ft2 in Frame 2. Similarly, to make NScano(1) to NScano(2), NScano(5) to NScano(6) not have gate active pulses pl in Frame 2, and is a low voltage between tf1 and ft2. Similarly, to make NScano(3) to NScano(4) have gate active pulses pl in Frame 2.

[0175] The first frequency division control signal FD1 is a low voltage before tf3 in Frame 3. Similarly, to make NScano(1) to NScano(4) have gate active pulses pl in Frame 3, and is a high voltage after tf3. Similarly, to make NScano(5) to NScano(6) not have gate active pulses pl in Frame 3.

[0176] The analysis of the first frequency division control signal FD1 in Frame 4 can refer to the analysis in Frame 2.

[0177] Similarly, for example Figure 13As shown, the refresh rates of the above-mentioned first 2-stage gate driving units 20, middle 2-stage gate driving units 20, and last 2-stage gate driving units 20 are 120HZ, 30HZ, and 60HZ respectively. According to the above content, it can be set as follows within Frame 1 to Frame 4: NScano(1) to NScano(2) have gate effective pulses pl within Frame 1 to Frame 4, NScano(3) to NScano(4) only have gate effective pulses pl within Frame 1, and the gate control signals NScano(5) to NScano(6) have gate effective pulses pl within Frame 1 and Frame 3.

[0178] That is, the frequency division control signal FD needs to be set as follows:

[0179] The second frequency division control signal FD2 is the same as Figure 11 the same setting in the above to ensure that the stage transfer signals generated by each stage of the gate driving unit 20 all have stage transfer effective pulses.

[0180] The first frequency division control signal FD1 corresponds to a low voltage for each stage within Frame 1. Similarly, to ensure that the 6 gate control signals NScano(1) to NScano(6) also have gate effective pulses pl within Frame 1.

[0181] The first frequency division control signal FD1 is at a low voltage before tf1 within Frame 2. Similarly, to ensure that NScano(1) to NScano(2) have gate effective pulses pl within Frame 2, and is at a high voltage after tf1. Similarly, to ensure that NScano(3) to NScano(6) do not have gate effective pulses pl within Frame 2.

[0182] The first frequency division control signal FD1 is at a low voltage before tf2 and after ft3 within Frame 3. Similarly, to ensure that NScano(1) to NScano(2), NScano(5) to NScano(6) have gate effective pulses pl within Frame 3, and is at a high voltage between tf2 and ft3. Similarly, to ensure that NScano(3) to NScano(4) do not have gate effective pulses pl within Frame 3.

[0183] The analysis of the first frequency division control signal FD1 within Frame 4 can refer to the analysis within Frame 2.

[0184] Similarly, for example Figure 14As shown, the refresh rates of the above-mentioned first 2-stage gate driving units 20, middle 2-stage gate driving units 20, and last 2-stage gate driving units 20 are 60HZ, 30HZ, and 120HZ respectively. According to the above content, it can be set as follows within Frame 1 to Frame 4: NScano(1) to NScano(2) have gate active pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) only have gate active pulses pl in Frame 1, and the gate control signals NScano(5) to NScano(6) have gate active pulses pl from Frame 1 to Frame 4.

[0185] That is, the frequency division control signal FD needs to be set as follows:

[0186] The second frequency division control signal FD2 is the same as Figure 11 the same setting in the above to ensure that the stage transmission signals generated by each stage of the gate driving unit 20 all have stage transmission active pulses.

[0187] The first frequency division control signal FD1 is at a low voltage corresponding to each stage in Frame 1. Similarly, so that the 6 gate control signals NScano(1) to NScano(6) also have gate active pulses pl in Frame 1.

[0188] The first frequency division control signal FD1 is at a high voltage before tf1 in Frame 2. Similarly, so that NScano(1) to NScano(4) do not have gate active pulses pl in Frame 2, and is at a low voltage after tf1. Similarly, so that NScano(5) to NScano(6) have gate active pulses pl in Frame 2.

[0189] The first frequency division control signal FD1 is at a low voltage before tf2 and after ft3 in Frame 3. Similarly, so that NScano(1) to NScano(2), NScano(5) to NScano(6) have gate active pulses pl in Frame 3, and is at a high voltage between tf2 and ft3. Similarly, so that NScano(3) to NScano(4) do not have gate active pulses pl in Frame 3.

[0190] The analysis of the first frequency division control signal FD1 in Frame 4 can refer to the analysis in Frame 2.

[0191] Similarly, for example Figure 15As shown, the refresh rates of the above-mentioned first 2-stage gate driving units 20, middle 2-stage gate driving units 20, and last 2-stage gate driving units 20 are 30HZ, 60HZ, and 120HZ respectively. According to the above content, it can be set that within Frame 1 to Frame 4: NScano(1) to NScano(2) only have the gate active pulse pl in Frame 1, NScano(3) to NScano(4) have the gate active pulse pl in Frame 1 and Frame 3, and the gate control signals NScano(5) to NScano(6) have the gate active pulse pl in Frame 1 to Frame 4.

[0192] That is, the frequency division control signal FD needs to be set as follows:

[0193] The second frequency division control signal FD2 is the same as Figure 11 the same setting in the above to make the stage transfer signals generated by each stage of the gate driving unit 20 all have the stage transfer active pulse.

[0194] The first frequency division control signal FD1 is at a low voltage corresponding to each stage in Frame 1. Similarly, so that the 6 gate control signals NScano(1) to NScano(6) also all have the gate active pulse pl in Frame 1.

[0195] The first frequency division control signal FD1 is at a high voltage before tf1 in Frame 2. Similarly, so that NScano(1) to NScano(4) do not have the gate active pulse pl in Frame 2, and are at a low voltage after tf1. Similarly, so that NScano(5) to NScano(6) have the gate active pulse pl in Frame 2.

[0196] The first frequency division control signal FD1 is at a high voltage before tf2 in Frame 3. Similarly, so that NScano(1) to NScano(2) do not have the gate active pulse pl in Frame 3, and are at a low voltage after tf2. Similarly, so that NScano(3) to NScano(6) have the gate active pulse pl in Frame 3.

[0197] The analysis of the first frequency division control signal FD1 in Frame 4 can refer to the analysis in Frame 2.

[0198] Combined with Figures 10 to 15Regarding the relevant discussion, the display panel can be further divided into m regions corresponding to m cascaded gate driving units 20 in sequence. The corresponding m refresh rates can be expressed as a / (j1), a / (j2), up to a / (jm), where j1 to jm are all positive integers, and the m refresh rates are all positive integers. Then the number of frames should be set to the least common multiple of these m numbers j1 to jm. For example, if there are two refresh rates of 120Hz and 1Hz, then there should be 120 frames in one cycle. Similarly, reference can be made to the above description regarding "m being the least common multiple of n1, n1, n1".

[0199] In summary, according to the refresh rate relationships among the above-mentioned first region, second region A2, and third region, the first frequency division control signal FD1 and the second frequency division control signal FD2 can be reasonably controlled. For example, the first region A1, the second region A2, and the third region A3 are respectively used for video playback, the comment area screen (which can be scrolled according to requirements), and the keyboard screen, that is, the refresh rates of the three decrease in sequence. At this time, the above method of continuously maintaining the first frequency division control signal FD1 at a low voltage in multiple frames and relying on the transition of the second frequency division control signal FD2 from an effective (low) voltage to an ineffective (high) voltage can be adopted, or the method of continuously maintaining the second frequency division control signal FD2 at a low voltage in multiple frames and relying on the transition of the first frequency division control signal FD1 from an effective (low) voltage to an ineffective (high) voltage can be adopted. Another example is that the first region A1, the second region A2, and the third region A3 are respectively used for date display, video playback, and the comment area screen (which can be scrolled according to requirements), that is, the refresh rates of the three show a trend of rising first and then falling. At this time, only by continuously maintaining the second frequency division control signal FD2 at a low voltage in multiple frames to maintain that each stage can output an effective stage transmission pulse, and relying on the transition of the first frequency division control signal FD1 from an ineffective (high) voltage to an effective (low) voltage and then from an effective (low) voltage to an ineffective (high) voltage can it be achieved.

[0200] Among them, the frame in which the gate of the multi-stage gate control signal corresponding to any region has a gate effective pulse can be called the writing frame of this region, which is used to turn on the sub-pixels Pi so that the corresponding at least one data string can be respectively loaded onto the corresponding at least one row of sub-pixels Pi. The frame without a gate effective pulse can be called the holding frame of this region, so that the corresponding at least one row of sub-pixels Pi are respectively maintained as the corresponding at least one data string. For example Figures 10 to 15 Frame 1 in is simultaneously the writing frame of the three regions corresponding to the first 2 stages, the middle 2 stages, and the last 2 stages of the gate driving unit 20. Figures 11 to 12 Frame 2 and Frame 4 in are simultaneously the writing frame of one region corresponding to the middle 2 stages of the gate driving unit 20, and are also simultaneously the holding frame of one region corresponding to the first 2 stages and the last 2 stages of the gate driving unit 20. Figures 13 to 14Frame 3 in it is both the holding frame for a region corresponding to the middle two-stage gate driving unit 20 and the writing frame for a region corresponding to the first two stages and the last two stages of the gate driving unit 20. Figures 14 to 15 Frame 2 and Frame 4 in it are both the holding frames for a region corresponding to the first two stages and the middle two-stage gate driving unit 20 and the writing frames for a region corresponding to the last two stages of the gate driving unit 20.

[0201] Continuing the above discussion, it can be considered that in the writing frame, the gate active pulse in the gate control signal turns on the corresponding row of sub-pixels Pi, so that multiple sub-data in the corresponding data string are respectively transmitted to the corresponding multiple sub-pixels Pi. Therefore, it is possible to determine whether this frame is the writing frame for the sub-pixels Pi in the subsequent row or the holding frame for the sub-pixels Pi in the previous row according to whether the two data strings corresponding to the adjacent two rows of sub-pixels Pi change (that is, whether the two voltage values corresponding to the adjacent two sub-data transmitted by the data line electrically connected to any column of sub-pixels Pi are the same, that is, whether the data signal transmitted by this data line undergoes a jump).

[0202] As Figure 16 shown, if the data signal source transmitted by this data line undergoes a jump, due to progressive scanning, that is, the data signals transmitted by each data line will all undergo an effective jump hop1 at the same time (that is, the gate control signal of the corresponding stage needs to have a gate active pulse to turn on the sub-pixels Pi in the corresponding row to load the multiple sub-data after the jump), the frequency division control signal FD can be set to control the generation of the corresponding gate active pulse before the corresponding data string appears to ensure the turning on of the sub-pixels Pi in the corresponding row. Based on the fact that both the first frequency division transistor T18 and the second frequency division transistor T20 are P-row transistors, that is, both the first frequency division control signal FD1 and the first frequency division control signal FD1 are set to a low voltage to turn on the above two.

[0203] Specifically, taking Figure 5 as an example, Figure 7 the NScano2 signal and the NScano1 signal in it respectively represent the signals loaded on the gates of M3 and M4 (both are P-type transistors) in Figure 5 ; the con(M3) signal and the con(M4) signal in Figure 16 can respectively represent the total frequency division control signal FD in the two NScan circuits for generating the NScano2 signal and the NScano1 signal. The "total frequency division control signal FD" can be understood as the signal after the sum operation of the first frequency division control signal FD1 and the second frequency division control signal FD2 in the NScan circuit, that is, only when both are at the effective (low) voltage, the "total frequency division control signal FD" will be at the effective (low) voltage, otherwise both are at the ineffective (high) voltage.

[0204] Referring to the above discussion about Figure 5 and Figure 7 , the NScano2 signal needs to be at an effective (high) voltage earlier than the NScano1 signal, so as to enable the compensation transistor M3 to be turned on during the first reset stage tim1, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2. After that, during the second reset stage tim2, the reset transistor M4 is turned on, so that the gate of the driving transistor M1 can be reset according to the initialization signal VI2. Therefore, as shown in Figure 16 , for example, the con(M3) signal and the con(M4) signal corresponding to the two NScan circuits can be respectively changed from an ineffective (high) voltage to an effective (low) voltage 32 line cycles and 16 line cycles before the "sub-data valid transition hop1", so as to sequentially turn on the compensation transistor and the reset transistor. Combining with Figure 2 's related discussion, the first reset stage tim1 and the second reset stage tim2 of the corresponding row sub-pixels Pi can be sequentially completed.

[0205] Furthermore, still based on Figure 5 shown, the frequency division control signal FD (which can also be called the con(M2) signal) in the PScan circuit for generating the PScano signal can be controlled to change from an ineffective (high) voltage to an effective (low) voltage before (less than 16 line cycles) the "sub-data valid transition hop1", or equal to the "sub-data valid transition hop1" (not shown in Figure 16 ) to turn on the data transistor, and continuously during the period when the data signal transmitted to the data line changes from the valid transition hop1 to the invalid transition hop2, so as to perform the data writing stage tim3.

[0206] Still further, still based on Figure 5 shown, after the "sub-data invalid transition hop2", the frequency division control signal FD (which can also be called the con(M5 / 6) signal) in the EM circuit for generating the EMo1 signal can be controlled to change from an ineffective (high) voltage to an effective (low) voltage (not shown in Figure 16 ) to turn on the first light-emitting control transistor and the second light-emitting control transistor, and continuously during the period when the data signal transmitted to the data line changes from the valid transition hop1 to the invalid transition hop2, so as to perform the light-emitting stage tim4.

[0207] Among them, still based on Figure 5 shown, between the light-emitting stage tim4 and the data writing stage tim3, the frequency division control signal FD (which can also be called the con(M7 / 8) signal) in the EM circuit for generating the EMo2 signal can also be controlled to change from an ineffective (high) voltage to an effective (low) voltageFigure 16 is not shown in the figure) to turn on the initial transistor and the reset transistor for the third reset phase tin.

[0208] Among them, the above "line period" can be understood as the sum of the on-time of each row of sub-pixels Pi and the line blanking time. Figure 16 In only one frame, for the first 878 rows of sub-pixels Pi, they are in the hold frame (that is, the duration of the corresponding con(M3) signal and con(M4) signal being in the invalid (high) voltage is first maintained for 878 line periods), and the con(M3) signal and con(M4) signal respectively jump from the valid (low) voltage to the invalid (high) voltage 30 line periods and 14 line periods before the "sub-data invalid transition hop2". For the subsequent 878 rows of sub-pixels Pi, they are also in the hold frame (that is, the duration of the corresponding con(M3) signal and con(M4) signal being in the invalid (high) voltage is also maintained for 878 line periods).

[0209] In summary, in this embodiment, the waveform of the "total frequency division control signal FD" in at least one corresponding gate driving unit 20 can be set according to the "sub-data valid transition hop1" and "sub-data valid transition hop1" of the data signal transmitted on the data line. For example, in the low-frequency region, the Source signal is a constant voltage signal in the hold frame. At this time, the "total frequency division control signal FD" can be equal to the invalid (high) voltage, so that no effective gate pulse can be output. Another example is that in the high-frequency region, when the Source signal has a "sub-data valid transition hop1", it can trigger the "total frequency division control signal FD" to jump to the valid (low) voltage, so that the effective gate pulse is normally output. And from the above analysis, it can be seen that the transition time of the "total frequency division control signal FD" in the gate driving unit 20 for different transistors in the pixel driving circuit 302 can be at the "sub-data valid transition hop1" or before or after it to respectively achieve different working stages.

[0210] It should be noted that, combined with the above discussion about Figure 2 and Figure 9 in any stage of the gate driving unit 20, if at least one of the first clock signal and the second clock signal is equal to the constant voltage, it will cause the corresponding stage transmission signal and gate control signal not to have the stage transmission effective pulse and the gate effective pulse respectively, so that the sub-pixels Pi of the corresponding row cannot be refreshed (i.e., cannot be turned on).

[0211] Furthermore, the gate driving circuit 10 includes n stages of gate driving units 20 connected in cascade in sequence, where n is a positive integer greater than or equal to 2, and the n stages of gate driving units 20 are all loaded with the same clock signal (for example Figures 10 to 15Each of the six - level gate driving units 20 is loaded with a first clock signal and a second clock signal (it can be considered that the positions where the first clock signal and the second clock signal are loaded in two adjacent levels are opposite). Within one frame, when the clock signal is effectively applied to the gate driving units 20 from the i - th level to the (i + k)-th level, it alternately equals the first clock voltage and the second clock voltage (which can be the high voltage and the low voltage in the first clock signal and the second clock signal respectively, that is, it can control the multiple rows of sub - pixels Pi corresponding to the gate control signals of the i - th level to the (i + k)-th level to turn on). Both i and k are positive integers greater than or equal to 1. Among them, when the gate control signals output by the gate driving units 20 from the (i + k + 1)-th level to the n - th level do not include gate effective pulses, the clock signal is constantly equal to the first clock voltage or the second clock voltage during the period when it is effectively applied to the gate driving units 20 from the (i + k + 1)-th level to the n - th level (which also just satisfies that the corresponding multiple sub - pixels Pi are not turned on).

[0212] It can be understood that since the gate control signals from the i - th level to the (i + k)-th level each have a gate effective pulse, and the gate control signals from the (i + k + 1)-th level to the n - th level each do not have a gate effective pulse. Based on this, in this embodiment, the period when the clock signal is effectively applied to the gate driving units 20 from the (i + k + 1)-th level to the n - th level is set to be equal to a constant voltage, which not only conforms to the condition that "the gate control signals from the (i + k + 1)-th level to the n - th level each do not have a gate effective pulse", but also can save power consumption.

[0213] Furthermore, to ensure that the gate effective pulse of the gate control signal of the (i + k)-th level is completely generated (to avoid interruption due to the clock signal becoming a constant - voltage signal), the clock signal can be set to be equal to the constant - voltage signal after the gate effective pulse is completely generated.

[0214] It should be noted that it must be satisfied that the gate control signals of the last several levels each do not have a gate effective pulse. If there is at least one of the gate control signals of the last levels having a gate effective pulse, then the voltage of the gate driving units 20 corresponding to several levels of gate control signals that do not have a gate effective pulse in front of it when the clock signal is effectively applied to them cannot be set to a constant voltage, because this will also cause the stage - transfer signal acting on the next level not to be generated, and it will be impossible to realize that at least one of the subsequent gate control signals has a gate effective pulse.

[0215] Specifically, for example Figure 10As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal (the two may be equal or unequal) can be set to be equal to at least one of a high voltage and a low voltage after the end of the gate active pulse in NScano(2). In Frame 3, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end of the gate active pulse in NScano(4).

[0216] Similarly, for example Figure 11 As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end of the gate active pulse in NScano(4).

[0217] Similarly, for example Figure 12 As shown, in Frame 2 to Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end of the gate active pulse in NScano(4).

[0218] Similarly, for example Figure 13 As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end of the gate active pulse in NScano(2).

[0219] As discussed above, for example Figure 14 and Figure 15 As shown, in Frame 1 and Frame 4, since both NScano(5) and NScano(6) (i.e., corresponding to the last two-stage gate driving units 20) have gate active pulses, the first clock signal and the second clock signal need to be continuously maintained to be alternately set to the first clock voltage and the second clock voltage in each frame to ensure that the stage transmission signal of each stage can be generated until the generation of the 6th, i.e., the gate control signal, is controlled.

[0220] The present application provides a gate driving circuit and a display panel, including the frequency-divided signal lines and a plurality of cascaded gate driving units as described above. The gate driving unit includes the level transfer unit and the output unit as described above. Among them, a level transfer frequency division control unit electrically connected to the level transfer receiving unit through the first node or the second node (also electrically connected to the level transfer output unit through the fourth node) and an output frequency division control unit connected between one of the first node and the second node and the third node are further provided. The two are respectively used to control the signal of one of the first node and the second node according to the frequency division control signal to control the level transfer output unit to output the level transfer signal of the current stage, and control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of the current stage, so that the invalidation of the gate control signal does not affect the invalidation of the level transfer signal. The sequential down-frequency mode of multiple regions of the display panel can be realized by setting whether the level transfer signal has a level transfer valid pulse, and the arbitrary frequency conversion mode of multiple regions of the display panel can be realized by setting whether the gate control signal has a gate valid pulse (since the level transfer valid pulse can always exist).

[0221] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0222] The gate driving circuit and the display panel provided by the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements on some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit, characterized in that, It includes a frequency-divided signal line and a plurality of cascaded gate driving units. The frequency-divided signal line is used to transmit a frequency-divided control signal to the plurality of gate driving units. The gate driving unit includes: A stage transmission unit, including a stage transmission receiving unit and a stage transmission output unit. The stage transmission receiving unit is used to receive the stage transmission signal of the previous stage. The stage transmission output unit is electrically connected to the stage transmission receiving unit through a first node and a second node, and is used to output the stage transmission signal of this stage according to the signals of the first node and the second node; An output unit, which is electrically connected to the stage transmission output unit through the second node and a third node, and is used to output a gate control signal according to the signals of the second node and the third node; A stage transmission frequency-divided control unit, which is electrically connected to the stage transmission receiving unit through a fourth node and is electrically connected to the stage transmission output unit through the first node, and is used to control the signal of the first node according to the frequency-divided control signal to control the stage transmission output unit to output the stage transmission signal of this stage; An output frequency-divided control unit, which is connected between the first node and the third node, and is used to control the signal of the third node according to the frequency-divided control signal to control the output unit to output the gate control signal of this stage; Wherein, the stage transmission receiving unit includes a first control unit and a second control unit connected. The second control unit includes a first capacitor connected between the first control unit and the second node; the stage transmission output unit includes a second capacitor connected between the second node and the output end of the stage transmission output unit; the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is greater than or equal to a preset value.

2. The gate driving circuit according to claim 1, wherein The preset value is equal to 1.

6.

3. The gate driving circuit according to claim 2, wherein The capacitance of the first capacitor is less than or equal to 600 farads and greater than or equal to 100 farads.

4. The gate driving circuit according to claim 2, wherein The capacitance of the second capacitor is less than or equal to 500 farads and greater than or equal to 100 farads.

5. The gate driving circuit according to any one of claims 1-4, characterized in that, The second control unit further includes: A first transistor, the first pole of the first transistor is connected to a first voltage line, the control pole of the first transistor is connected to the first control unit, and the second pole of the first transistor is connected to the first end of the first capacitor; A second transistor, the first pole of the second transistor is connected to the second pole of the first transistor and the first end of the first capacitor, the control pole of the second transistor is connected to the second end of the first capacitor, and the second pole of the second transistor is connected to a second clock line; A third transistor, the first pole of the third transistor is connected to the control pole of the third transistor and the control pole of the second transistor, and the second pole of the third transistor is connected to the second node and the first end of the second capacitor.

6. The gate driving circuit according to claim 5, wherein The stage transmission output unit further includes: A first stage transmission output transistor, the first pole of the first stage transmission output transistor is connected to the first voltage line, the control pole of the first stage transmission output transistor is connected to the first node, and the second pole of the first stage transmission output transistor is connected to the second end of the second capacitor; A second-stage transfer output transistor, a first pole of the second-stage transfer output transistor is connected to a second pole of the first-stage transfer output transistor and a second end of the second capacitor, a control pole of the second-stage transfer output transistor is connected to the second node and a first end of the second capacitor, and a second pole of the second-stage transfer output transistor is connected to a second voltage line.

7. The gate driving circuit according to claim 5, characterized in that, The first control unit includes: A fourth transistor, a first pole of the fourth transistor is connected to the second voltage line, a control pole of the fourth transistor is connected to a first clock line, and a second pole of the fourth transistor is connected to a control pole of the first transistor; A fifth transistor, a first pole of the fifth transistor is connected to a second clock line, and a control pole of the fifth transistor is connected to a second pole of the fourth transistor; A sixth transistor, a first pole of the sixth transistor is connected to a second pole of the fifth transistor, a control pole of the sixth transistor is connected to the second clock line, and a second pole of the sixth transistor is connected to the fourth node.

8. The gate driving circuit according to claim 7, wherein The first control unit further includes: A seventh transistor, a first pole of the seventh transistor is connected to a control pole of the first transistor and a second pole of the fourth transistor, a control pole of the seventh transistor is connected to the second voltage line, and a second pole of the seventh transistor is connected to a control pole of the fifth transistor; A third capacitor, a first end of the third capacitor is connected to a control pole of the fifth transistor, and a second end of the third capacitor is connected to a second pole of the fifth transistor.

9. A display panel, characterized in that, The display panel includes the gate driving circuit according to any one of claims 1-8.

10. The display panel according to claim 9, wherein The display panel further includes a plurality of sub-pixels located in a display area, and the plurality of sub-pixels are connected to the gate driving circuit; Wherein, capacitances of the first capacitor and the second capacitor both increase as a width of the display area increases.

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