Electronic circuit

Abstract

The disclosure provides an electronic circuit. The electronic circuit includes an electronic component, a driving transistor, a first emission transistor, a first reset transistor, and a capacitor. The driving transistor is electrically connected to the electronic component. The power supply voltage drives the electronic component through the driving transistor. The first end of the first emission transistor is electrically connected to a power supply voltage. One end of the first reset transistor receives a reset signal. The first end of the capacitor is electrically connected to the control end of the driving transistor. The second end of the capacitor is electrically connected with the first reset transistor and the first emission transistor. When the electronic component is driven, the first end of the driving transistor and the first end of the first transmitting transistor receive a power supply voltage. The electronic circuit has a parasitic capacitance coupling compensation effect.

Description

Technical Field

[0001] The present disclosure relates to an electronic circuit, and more particularly to an electronic circuit having a parasitic capacitance coupling compensation effect. Background Art

[0002] Please refer to Figure 1 , Figure 1 which is a schematic diagram of an existing electronic circuit. The electronic circuit 10 may be a light-emitting circuit or a pixel circuit. The electronic circuit 10 includes a driving transistor TDR, an emitting transistor TEM, and an electronic element EE. The electronic element EE may be any form of light-emitting element. The driving transistor TDR, the emitting transistor TEM, and the electronic element EE are connected in series with each other. A first end of the driving transistor TDR receives a power supply voltage ARVDD'. A first end of the emitting transistor TEM is electrically connected to a second end of the driving transistor TDR. The electronic element EE is electrically connected between a second end of the emitting transistor TEM and a reference voltage ARVSS. The driving transistor TDR can supply the received power supply voltage ARVDD' to the emitting transistor TEM according to a voltage value VG at a control end of the driving transistor TDR. The emitting transistor TEM responds to an enabling signal EM to drive the electronic element EE using the power supply voltage ARVDD'.

[0003] There is a parasitic capacitance Cgd between a second end of the driving transistor TDR and a control end of the driving transistor TDR. The power supply voltage ARVDD' is lower than a reference voltage source ARVDD. Therefore, when the driving transistor TDR is turned on according to the voltage value VG, the voltage value VG is changed by the voltage value of the power supply voltage ARVDD' through the parasitic capacitance Cgd. It should be noted that the resistance value of the wiring impedance R is different according to different positions of the electronic circuit 10 on the substrate. The voltage value of the power supply voltage ARVDD' received by the driving transistor TDR is also different. In other words, according to different positions of the electronic circuit 10 on the substrate, the result of the voltage value VG being changed is also different. The above situation will cause different change amounts of the voltage value VG of multiple electronic circuits 10 at each position, resulting in uneven light emission of the electronic element EE.

[0004] In addition, for example, in the operation of low gray levels, when the enabling signal EM has a duty cycle, the voltage value VA at a second end of the driving transistor TDR will pull down the voltage value VG through the parasitic capacitance Cgd. At this time, an instantaneous large current will flow through the emitting transistor TEM and the electronic element EE, so that the electronic element EE provides incorrect light emission in the operation of low gray levels.

[0005] Therefore, how to provide coupling compensation for the parasitic capacitance Cgd of the electronic circuit 10 is one of the research focuses of those skilled in the art. Summary of the Invention

[0006] The present disclosure is directed to an electronic circuit having a parasitic capacitance coupling compensation effect.

[0007] According to an embodiment of the present disclosure, the electronic circuit includes an electronic component, a driving transistor, a first emitting transistor, a first reset transistor, and a capacitor. The driving transistor is electrically connected to the electronic component. A power supply voltage drives the electronic component through the driving transistor. A first end of the first emitting transistor is electrically connected to the power supply voltage. One end of the first reset transistor receives a reset signal. A first end of the capacitor is electrically connected to a control end of the driving transistor. A second end of the capacitor is electrically connected to the first reset transistor and the first emitting transistor. When the electronic component is driven, a first end of the driving transistor and a first end of the first emitting transistor receive the power supply voltage.

[0008] Based on the above, when the electronic component is driven, a first end of the driving transistor and a first end of the first emitting transistor jointly receive the power supply voltage. In this way, the capacitive coupling of the parasitic capacitance between a second end of the driving transistor and a control end of the driving transistor can be compensated by the capacitive coupling of the capacitor. Description of the Drawings

[0009] Figure 1 is a schematic diagram of an existing electronic circuit;

[0010] Figure 2 is a schematic diagram of an electronic circuit according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of an electronic circuit according to an embodiment of the present invention;

[0012] Figure 4 is a signal timing diagram according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of an electronic circuit according to an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of an electronic circuit according to an embodiment of the present invention;

[0015] Figure 7 is a signal timing diagram according to an embodiment of the present invention;

[0016] Figure 8 is a schematic diagram of an electronic circuit according to an embodiment of the present invention.

[0017] Description of the Reference Numerals

[0018] 10, 100, 200, 200', 300, 400: Electronic circuit

[0019] 210, 310: Data control circuit

[0020] ARVDD: Reference voltage source

[0021] ARVDD’: Power supply voltage

[0022] ARVSS: Reference voltage

[0023] C1, C2, Cp: Capacitors

[0024] Cgd: Parasitic capacitance

[0025] EE: Electronic component

[0026] EM: Enable signal

[0027] N: Node

[0028] PRE_EM: Pre - enable signal

[0029] R: Wiring impedance

[0030] RST: Reset signal

[0031] SD: Data signal

[0032] SN: Drive signal

[0033] T1, TDR: Drive transistors

[0034] T2: First emission transistor

[0035] T3, T3_1, T3_2: First reset transistors

[0036] T4, T4_1, T4_2: Second reset transistors

[0037] T5: Second emission transistor

[0038] TC1, TC2, TC3: Control transistors

[0039] TD, TD_1, TD_2: Data transistors

[0040] TD1: During reset

[0041] TD2: During data input

[0042] TD3: During drive

[0043] TEM: Emission transistor

[0044] TP, TP_1, TP_2: Compensation transistors

[0045] V1: Voltage signal

[0046] VA, VG: Voltage values

[0047] VC: Control voltage

[0048] VGH: Reference high voltage Detailed implementation manners

[0049] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings as described below. It should be noted that for the purpose of clear illustration and easy understanding by the reader, each of the accompanying drawings of the present disclosure shows a part of the electronic device, and some elements in each of the accompanying drawings may not be drawn to scale. In addition, the number and size of each device shown in the accompanying drawings are only illustrative and are not intended to limit the scope of the present disclosure.

[0050] Certain terms are used throughout the description and the following claims to refer to specific elements. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to elements. This application does not intend to distinguish between elements that have different names but the same function. In the following description and in the claims, the terms "comprising", "including" and "having" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Thus, when the terms "comprising", "including" and / or "having" are used in the description of the present disclosure, it will indicate the presence of corresponding features, regions, steps, operations and / or elements, but not limited to the presence of one or more corresponding features, regions, steps, operations and / or elements.

[0051] It should be understood that when an element is referred to as being "coupled to", "connected to" or "conducted to" another element, the element can be directly connected to the other element and can directly establish an electrical connection, or there can be intermediate elements between these elements for relaying the electrical connection (indirect electrical connection). In contrast, when an element is referred to as being "directly coupled to", "directly conducted to" or "directly connected to" another element, there are no intermediate elements.

[0052] Although terms such as first, second, third, etc. may be used to describe different component elements, such component elements are not limited by these terms. The terms are only used to distinguish the component elements in the specification from other component elements. The claims may not use the same terms, but may use terms such as first, second, third, etc. relative to the order required for the elements. Thus, in the following description, the first component element may be the second component element in the claims.

[0053] According to an embodiment of the present disclosure, the electronic device may include a display device, a splicing device, a touch electronic device, a sensing device, an antenna device, a packaging device, a curved electronic device, or a non-rectangular electronic device, but is not limited thereto. The electronic device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The electronic device may include electronic components, and the electronic components may be passive components or active components, such as capacitors, resistors, inductors, diodes, driving components, transistors, etc. The diode may include a light-emitting diode (LED) or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna or an antenna device of varactor diodes, but is not limited thereto. The packaging device may be used in wafer level packaging (WLP) technology or panel level packaging (PLP) technology, such as a chip first or RDL first process. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. In addition, the electronic device may be a bendable or flexible electronic device. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. to support the display device or the splicing device.

[0054] In the present disclosure, embodiments use "pixel" or "pixel unit" as a unit for describing a specific area including at least one functional circuit for at least one specific function. The area of a "pixel" depends on the unit for providing a specific function, and adjacent pixels may share the same part or wire, but may also include its own specific part therein. For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also have its own transistor or capacitor.

[0055] It should be noted that the technical features in the following-described different embodiments can be replaced, reorganized, or mixed with each other without departing from the spirit of the present disclosure to form another embodiment.

[0056] Please refer to Figure 2 , Figure 2 which is a schematic diagram of an electronic circuit shown according to an embodiment of the present invention. In this embodiment, the electronic circuit 100 includes an electronic component EE, a driving transistor T1, a first emission transistor T2, a first reset transistor T3, and a capacitor Cp. The driving transistor T1 is electrically connected to the electronic component. In this embodiment, the electronic circuit 100 can be, for example, a light-emitting circuit or a pixel circuit. The electronic component EE can be, for example, a light-emitting element in any form (however, the present disclosure is not limited thereto). The first end of the driving transistor T1 receives a power supply voltage ARVDD'. The power supply voltage ARVDD' can drive the electronic component EE through the driving transistor T1. The first end of the first emission transistor T2 is electrically connected to the power supply voltage ARVDD'. The second end of the driving transistor T1 is electrically connected to an electrode of the electronic component EE. The other electrode of the electronic component EE is electrically connected to a reference voltage ARVSS.

[0057] The first end of the first emission transistor T2 is electrically connected to the power supply voltage ARVDD'. One end of the first reset transistor T3 receives a reset signal RST. The first end of the capacitor Cp is electrically connected to the control end of the driving transistor T1. The second end of the capacitor Cp (i.e., node N) is electrically connected to the first reset transistor T3 and the first emission transistor T2. When the electronic component EE is driven, the first end of the driving transistor T1 and the first end of the first emission transistor T2 receive the power supply voltage ARVDD'.

[0058] Generally speaking, the resistance value of the wiring impedance R is different depending on the position of the electronic circuit 100 on the substrate. The voltage value of the power supply voltage ARVDD' received by the driving transistor T1 is also different. In other words, the result of the voltage value VG at the control end of the driving transistor T1 being changed is different depending on the position of the electronic circuit 100 on the substrate. The above situation will cause uneven light emission of the electronic components EE of the multiple electronic circuits 100 at each position. In addition, during low gray-scale operation, when the enable signal EM has a duty cycle and the driving transistor T1 is turned on, the voltage value VA at the second end of the driving transistor T1 will be pulled down by the voltage value VG through the parasitic capacitance Cgd. At this time, a transient large current will flow through the electronic component EE, causing the electronic component EE to provide incorrect light emission during low gray-scale operation.

[0059] It is worth mentioning here that when the electronic component EE is driven, the first ends of the driving transistor T1 and the first emitting transistor T2 jointly receive the power supply voltage ARVDD'. In this way, the capacitive coupling of the parasitic capacitance Cgd between the second end and the control end of the driving transistor T1 can be compensated by the capacitive coupling of the capacitor Cp.

[0060] In this embodiment, the wiring impedance R is an equivalent resistor of the connection line. Based on the resistance value of the wiring impedance R, the power supply voltage ARVDD' is lower than the reference voltage source ARVDD.

[0061] Taking this embodiment as an example, the second end of the first emitting transistor T2 is electrically connected to the second end of the capacitor Cp. The control end of the first emitting transistor T2 receives the enabling signal EM. The first emitting transistor T2 performs a switching operation in response to the duty cycle of the enabling signal EM. The first end of the first reset transistor T3 is electrically connected to the second end of the first emitting transistor T2 and the second end of the capacitor Cp. The second end of the first reset transistor T3 is electrically connected to the reference high voltage VGH. The control end of the first reset transistor T3 receives the reset signal RST. When the enabling signal EM has a duty cycle and the driving transistor T1 is turned on, the capacitive coupling of the capacitor Cp is generated according to the power supply voltage ARVDD'. The capacitive coupling of the parasitic capacitance Cgd is also generated according to the power supply voltage ARVDD'. It should be noted that the capacitive coupling of the capacitor Cp compensates (or cancels) the capacitive coupling of the parasitic capacitance Cgd. In other words, compared with the capacitive coupling of the parasitic capacitance Cgd, the capacitor Cp provides a reverse capacitive coupling. The capacitive coupling of the capacitor Cp reduces the non-ideal variation of the voltage value VG caused by the capacitive coupling of the parasitic capacitance Cgd.

[0062] In this embodiment, the capacitance value of the capacitor Cp is designed to be equal to the capacitance value of the parasitic capacitance Cgd. Therefore, the capacitive coupling of the capacitor Cp can completely cancel the capacitive coupling of the parasitic capacitance Cgd.

[0063] In this embodiment, the driving transistor T1, the first emitting transistor T2, and the first reset transistor T3 are respectively implemented by P-type transistors, but the present disclosure is not limited thereto. In some embodiments, the driving transistor T1, the first emitting transistor T2, and the first reset transistor T3 are respectively implemented by N-type transistors, but the present disclosure is not limited thereto.

[0064] Please refer to Figure 3 , Figure 3It is a schematic diagram of an electronic circuit shown according to an embodiment of the present invention. In this embodiment, the electronic circuit 200 includes an electronic component EE, a driving transistor T1, a first emitting transistor T2, a first reset transistor T3, a second reset transistor T4, a second emitting transistor T5, and capacitors C1 and Cp. A first end of the driving transistor T1 receives a power supply voltage ARVDD'. A first end of the first emitting transistor T2 receives the power supply voltage ARVDD'. A second end of the first emitting transistor T2 is electrically connected to a second end of the capacitor Cp. A control end of the first emitting transistor T2 receives an enabling signal EM. A first end of the first reset transistor T3 is electrically connected to the second end of the first emitting transistor T2 and the second end of the capacitor Cp. A second end of the first reset transistor T3 is electrically connected to a reference high voltage VGH. A control end of the first reset transistor T3 receives a reset signal RST. A first end of the capacitor Cp is electrically connected to a control end of the driving transistor T1. The second end of the capacitor Cp is electrically connected to the first end of the first reset transistor T3 and the second end of the first emitting transistor T2. The capacitor C1 is electrically connected between the first end of the driving transistor T1 and the control end of the driving transistor T1.

[0065] In this embodiment, one end of the second reset transistor T4 is electrically connected to the first end of the capacitor Cp. The other end of the second reset transistor T4 is electrically connected to the first reset transistor T3.

[0066] Taking this embodiment as an example, the first end of the second reset transistor T4 is electrically connected to the first end of the capacitor Cp. The second end of the second reset transistor T4 is electrically connected to a reference voltage ARVSS. The control ends of the first reset transistor T3 and the second reset transistor T4 receive the reset signal RST.

[0067] In this embodiment, a first end of the second emitting transistor T5 is electrically connected to a second end of the driving transistor T1. A second end of the second emitting transistor T5 is electrically connected to an electrode of the electronic component EE. A control end of the second emitting transistor T5 receives the enabling signal EM. The other electrode of the electronic component EE is electrically connected to the reference voltage ARVSS.

[0068] In this embodiment, the voltage value of the reference voltage ARVSS is less than or equal to 0 volts. It is worth mentioning here that the other electrode of the electronic component EE and the second end of the second reset transistor T4 are electrically connected to the reference voltage ARVSS. Therefore, the layout area of the electronic circuit 200 can be reduced.

[0069] In some embodiments, the second end of the second reset transistor T4 is electrically connected to another reference voltage. The voltage value of the other reference voltage is less than the voltage value of the power supply voltage ARVDD' minus the threshold voltage value of the driving transistor T1.

[0070] In this embodiment, when the enable signal EM has a duty cycle and the driving transistor T1 is turned on, the capacitive coupling of the capacitor Cp is generated according to the power supply voltage ARVDD'. The capacitive coupling of the parasitic capacitor Cgd is also generated according to the power supply voltage ARVDD'. The capacitive coupling of the capacitor Cp compensates (or cancels out) the capacitive coupling of the parasitic capacitor Cgd.

[0071] In this embodiment, the electronic circuit 200 further includes a data transistor TD and a compensation transistor TP. The first end of the data transistor TD receives the data signal SD. The second end of the data transistor TD is electrically connected to the second end of the capacitor Cp. The control end of the data transistor TD receives the driving signal SN. The first end of the compensation transistor TP is electrically connected to the control end of the driving transistor T1. The second end of the compensation transistor TP is electrically connected to the second end of the driving transistor T1. The control end of the compensation transistor TP receives the driving signal SN.

[0072] In this embodiment, the driving transistor T1, the first emission transistor T2, the first reset transistor T3, the second reset transistor T4, the second emission transistor T5, the data transistor TD, and the compensation transistor TP are respectively implemented by P-type transistors, but the present disclosure is not limited thereto.

[0073] Please refer to Figure 3 and Figure 4 , Figure 4 is a signal timing diagram shown according to an embodiment of the present invention. In this embodiment, during the reset period TD1, the voltage value of the reset signal RST is at a low level. Therefore, during the reset period TD1, the first reset transistor T3 and the second reset transistor T4 are turned on. The voltage values at both ends of the capacitor Cp are reset. Taking this embodiment as an example, during the reset period TD1, the voltage value at the second end of the capacitor Cp is approximately equal to the voltage value of the reference high voltage VGH. The voltage value at the first end of the capacitor Cp is approximately equal to the voltage value of the reference voltage ARVSS. During the reset period TD1, there is a reset voltage difference (i.e., "VGH - ARVSS") between the second end and the first end of the capacitor Cp.

[0074] During the reset period TD1, the voltage values of the driving signal SN and the enable signal EM are respectively at a high level. Therefore, during the reset period TD1, the first emission transistor T2, the second emission transistor T5, the data transistor TD, and the compensation transistor TP are turned off. The electronic component EE does not emit light during the reset period TD1.

[0075] In this embodiment, the voltage value of the reference high voltage VGH is higher than the highest voltage value of the data signal SD. Therefore, when the data signal SD is received, the voltage value at the second end of the capacitor Cp can be ensured to be pulled down during the data input period TD2, so that the control terminal of the driving transistor T1 has information for compensating the threshold voltage value of the driving transistor T1.

[0076] During the data input period TD2, the voltage values of the reset signal RST and the enable signal EM are both high levels. Therefore, during the data input period TD2, the first emission transistor T2, the first reset transistor T3, the second reset transistor T4, and the second emission transistor T5 are turned off. The voltage value of the driving signal SN is at a low level. Therefore, during the data input period TD2, the data transistor TD and the compensation transistor TP are turned on. The second end of the capacitor Cp receives the data signal SD. The voltage value at the first end of the capacitor Cp is approximately equal to the voltage value of the power supply voltage ARVDD’ minus the absolute value of the threshold voltage value of the driving transistor T1 (i.e., “VG<ARVDD’ - |Vth_T1|). In other words, during the data input period TD2, the control terminal of the driving transistor T1 has information for compensating the threshold voltage value of the driving transistor T1.

[0077] During the driving period TD3, the voltage values of the reset signal RST and the driving signal SN are both high levels. Therefore, during the data input period TD2, the first reset transistor T3, the second reset transistor T4, the data transistor TD, and the compensation transistor TP are turned off. During the driving period TD3, the enable signal EM has a duty cycle. Therefore, during the driving period TD3, the first emission transistor T2 and the second emission transistor T5 perform switching operations in response to the duty cycle of the enable signal EM.

[0078] During the driving period TD3, when the enable signal EM has a duty cycle and the driving transistor T1 is turned on, the capacitive coupling of the capacitor Cp compensates (or cancels out) the capacitive coupling of the parasitic capacitance Cgd.

[0079] Please refer to Figure 5 , Figure 5 is a schematic diagram of an electronic circuit shown according to an embodiment of the present invention. In this embodiment, the electronic circuit 200’ includes an electronic element EE, a driving transistor T1, a first emission transistor T2, a first reset transistor T3, a second reset transistor T4, a second emission transistor T5, capacitors C1, Cp, and a data control circuit 210. The implementation manners of the electronic element EE, the driving transistor T1, the first emission transistor T2, the first reset transistor T3, the second reset transistor T4, the second emission transistor T5, and the capacitors C1, Cp have been clearly described in the embodiment of Figure 3 and will not be repeated here.

[0080] In this embodiment, the data control circuit 210 is electrically connected to the control terminal of the driving transistor T1. The data control circuit 210 generates a control voltage VC according to the data signal SD and provides the control voltage VC to the control terminal of the driving transistor T1. Therefore, the voltage value VG at the control terminal of the driving transistor T1 can be increased based on the change of the data signal SD, which enables the range of the operating current flowing through the driving transistor T1, the second emission transistor T5, and the electronic component EE to be increased.

[0081] In this embodiment, the data control circuit 210 includes control transistors TC1, TC2, TC3, and a capacitor C2. The first end of the capacitor C2 is electrically connected to the control terminal of the driving transistor T1. The first end of the control transistor TC1 receives the data signal SD. The second end of the control transistor TC1 is electrically connected to the second end of the capacitor C2. The control terminal of the control transistor TC1 receives the driving signal SN. The first end of the control transistor TC2 receives the voltage signal V1. The second end of the control transistor TC2 is electrically connected to the second end of the capacitor C2. The control terminal of the control transistor TC2 receives the enable signal EM. The first end of the control transistor TC3 is electrically connected to the reference high voltage VGH. The second end of the control transistor TC3 is electrically connected to the second end of the capacitor Cp. The control terminal of the control transistor TC3 receives the reset signal RST.

[0082] It should be noted that the data control circuit 210 also receives the data signal SD, the enable signal EM, and the driving signal SN. Therefore, the change of the control voltage VC follows the change of the voltage value at the second end of the capacitor Cp. In this way, the change amount of the voltage value VG can be amplified.

[0083] In this embodiment, the control transistors TC1, TC2, and TC3 are respectively implemented by P-type transistors, but the present disclosure is not limited thereto.

[0084] It should be understood that Figure 4 the signal timing diagram of

[0085] Please refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of an electronic circuit shown according to an embodiment of the present invention. Figure 7is a signal timing diagram shown according to an embodiment of the present invention. In this embodiment, the electronic circuit 300 includes an electronic component EE, a driving transistor T1, a first emitting transistor T2, a first reset transistor T3, a second reset transistor T4, a second emitting transistor T5, a capacitor C1, Cp, and a data control circuit 310. The data control circuit 310 includes control transistors TC1, TC2, TC3, and a capacitor C2.

[0086] Different from Figure 5 the electronic circuit 200' is that in the electronic circuit 300 of this embodiment, the control terminals of the first emitting transistor T2 and the control transistor TC2 respectively receive a pre-enabling signal PRE_EM. After the data input period TD2 and before the driving period TD3, the voltage value of the pre-enabling signal PRE_EM changes from a high level to a low level. Therefore, after the data input period TD2 and before the driving period TD3, the first emitting transistor T2 and the control transistor TC2 are turned on in response to the pre-enabling signal PRE_EM. The voltage value at the second end of the capacitor Cp is first limited to the voltage value of the power supply voltage ARVDD' before the driving period TD3. Therefore, during the driving period TD3, the decrease amount of the voltage value VG is limited. In this way, under the operation of low gray levels, the voltage value VA at the second end of the driving transistor T1 is pulled down by the parasitic capacitance Cgd, and the decrease amount of the voltage value VG is reduced. In this way, under the operation of low gray levels, there will be no instantaneous large current flowing through the driving transistor T1, the second emitting transistor T5, and the electronic component EE, so that the electronic component EE does not provide incorrect light emission during the operation of low gray levels.

[0087] In some embodiments, the electronic circuit 300 may not include the data control circuit 310.

[0088] Please refer to Figure 8 , Figure 8It is a schematic diagram of an electronic circuit shown according to an embodiment of the present invention. In this embodiment, the electronic circuit 400 includes electronic components EE, a driving transistor T1, a first emitting transistor T2, first reset transistors T3_1, T3_2, second reset transistors T4_1, T4_2, a second emitting transistor T5, data transistors TD_1, TD_2, compensation transistors TP_1, TP_2, and capacitors C1, Cp. The first end of the driving transistor T1 receives the power supply voltage ARVDD'. The first end of the first emitting transistor T2 receives the power supply voltage ARVDD'. The second end of the first emitting transistor T2 is electrically connected to the second end of the capacitor Cp. The control end of the first emitting transistor T2 receives the enabling signal EM. The first end of the first reset transistor T3 is electrically connected to the second end of the first emitting transistor T2 and the second end of the capacitor Cp. The first end of the capacitor Cp is electrically connected to the control end of the driving transistor T1. The capacitor C1 is electrically connected between the first end of the driving transistor T1 and the control end of the driving transistor T1.

[0089] The first end of the second emitting transistor T5 is electrically connected to the second end of the driving transistor T1. The second end of the second emitting transistor T5 is electrically connected to the electrode of the electronic component EE. The control end of the second emitting transistor T5 receives the enabling signal EM. The other electrode of the electronic component EE is electrically connected to the reference voltage ARVSS.

[0090] The first reset transistors T3_1, T3_2 are connected in series with each other between the reference high voltage VGH and the second end of the capacitor Cp. The control ends of the first reset transistors T3_1, T3_2 receive the reset signal RST. In other words, as Figure 3 , Figure 5 and Figure 6 the first reset transistor T3 as shown can be replaced by the first reset transistors T3_1, T3_2.

[0091] The second reset transistors T4_1, T4_2 are connected in series with each other between the reference voltage ARVSS and the first end of the capacitor Cp. The control ends of the second reset transistors T4_1, T4_2 receive the reset signal RST. In other words, as Figure 3 , Figure 5 and Figure 6 the second reset transistor T4 as shown can be replaced by the second reset transistors T4_1, T4_2.

[0092] The first end of the data transistor TD_1 receives the data signal SD. The first end of the data transistor TD_2 is electrically connected to the second end of the data transistor TD_1. The second end of the data transistor TD_2 is electrically connected to the second end of the capacitor Cp. The control ends of the data transistors TD_1, TD_2 receive the driving signal SN. In other words, as Figure 3 ,Figure 5 and Figure 6 and Figure 5 the data transistors TD can be replaced with data transistors TD_1 and TD_2.

[0093] The compensation transistors TP_1 and TP_2 are connected in series with each other between the control terminal of the driving transistor T1 and the second terminal of the driving transistor T1. The control terminals of the compensation transistors TP_1 and TP_2 receive a driving signal SN. In other words, as Figure 3 , Figure 5 and Figure 6 the compensation transistor TP can be replaced with compensation transistors TP_1 and TP_2.

[0094] In this embodiment, the series connection configurations of the first reset transistors T3_1 and T3_2, the series connection configurations of the second reset transistors T4_1 and T4_2, the series connection configurations of the data transistors TD_1 and TD_2, and the series connection configurations of the compensation transistors TP_1 and TP_2 can reduce the leakage current of the electronic circuit 400.

[0095] In this embodiment, the driving transistor T1, the first emission transistor T2, the first reset transistors T3_1 and T3_2, the second reset transistors T4_1 and T4_2, the second emission transistor T5, the data transistors TD_1 and TD_2, and the compensation transistors TP_1 and TP_2 are respectively implemented by P-type field effect transistors, but the present disclosure is not limited thereto.

[0096] It should be understood that Figure 4 the signal timing diagram of

[0097] It should be understood that, as Figure 5 and Figure 6 the control transistor TC1 can be replaced with a plurality of control transistors connected in series with each other. As Figure 5 and Figure 6 the control transistor TC3 can be replaced with a plurality of control transistors connected in series with each other.

[0098] In summary, when the electronic component is driven, the first terminal of the driving transistor and the first terminal of the first emission transistor jointly receive a power supply voltage. In this way, the capacitive coupling of the parasitic capacitance located between the second terminal and the control terminal of the driving transistor can be compensated by the capacitive coupling of the capacitor.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limiting them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic circuit, characterized in that, The electronic circuit includes: Electronic components; A driving transistor electrically connected to the electronic component, wherein a power supply voltage drives the electronic component through the driving transistor; A first emission transistor, a first end of the first emission transistor being electrically connected to the power supply voltage; A first reset transistor, one end of the first reset transistor receiving a reset signal; and A capacitor, a first end of the capacitor being electrically connected to a control end of the driving transistor, a second end of the capacitor being electrically connected to the first reset transistor and the first emission transistor, wherein when the electronic component is driven, a first end of the driving transistor and a first end of the first emission transistor receive the power supply voltage.

2. The electronic circuit according to claim 1, wherein: The control end of the first reset transistor receives the reset signal, A first end of the first reset transistor is electrically connected to a second end of the first emission transistor and a second end of the capacitor, and A second end of the first reset transistor is electrically connected to a reference high voltage.

3. The electronic circuit according to claim 2, wherein The electronic circuit further includes: A data transistor, a first end of the data transistor receiving a data signal, a second end of the data transistor being electrically connected to a second end of the capacitor, a control end of the data transistor receiving a driving signal; and A compensation transistor, a first end of the compensation transistor being electrically connected to a control end of the driving transistor, a second end of the compensation transistor being electrically connected to a second end of the driving transistor, a control end of the compensation transistor receiving the driving signal.

4. The electronic circuit according to claim 3, wherein, A voltage value of the reference high voltage is higher than a highest voltage value of the data signal.

5. The electronic circuit according to claim 1, characterized in that, The electronic circuit further includes: A second reset transistor, one end of the second reset transistor being electrically connected to a first end of the capacitor, the other end of the second reset transistor being electrically connected to the first reset transistor.

6. The electronic circuit according to claim 5, wherein: A first end of the second reset transistor is electrically connected to a first end of the capacitor, A second end of the second reset transistor is electrically connected to a reference voltage, and The control end of the first reset transistor and the control end of the second reset transistor receive the reset signal.

7. The electronic circuit according to claim 1, characterized in that, The electronic circuit further includes: A second emission transistor, a first end of the second emission transistor being electrically connected to the driving transistor, a second end of the second emission transistor being electrically connected to the electronic component.

8. The electronic circuit according to claim 1, characterized in that, The electronic circuit further includes: A data control circuit electrically connected to a control end of the driving transistor, configured to generate a control voltage according to a data signal and provide the control voltage to the control end of the driving transistor.

9. The electronic circuit according to claim 1, wherein: The control end of the first emission transistor receives an enabling signal, and During driving, the first emission transistor performs a switching operation in response to a duty cycle of the enabling signal.

10. The electronic circuit according to claim 1, wherein The control end of the first emission transistor receives a pre-enabling signal, and After data input and before driving, the first emission transistor is turned on in response to the pre-enable signal.

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