Storage and calculation integrated unit, storage and calculation integrated device and data writing and calculation method

Abstract

The invention discloses a storage and calculation integrated unit, a storage and calculation integrated device and a data writing and calculation method. The unit comprises a first spin-orbit coupling layer, a second spin-orbit coupling layer and a plurality of magnetic tunnel junctions, the plurality of magnetic tunnel junctions comprise a first magnetic tunnel junction and a second magnetic tunnel junction which are arranged on the first spin-orbit coupling layer, and a third magnetic tunnel junction and a fourth magnetic tunnel junction which are arranged on the second spin-orbit coupling layer; one end, close to the second magnetic tunnel junction, of the first spin-orbit coupling layer is electrically connected with one end, close to the third magnetic tunnel junction, of the second spin-orbit coupling layer through a switch element; the top of the first magnetic tunnel junction and the top of the fourth magnetic tunnel junction are electrically connected with a first signal line for inputting VCMA voltage, and the top of the second magnetic tunnel junction and the top of the third magnetic tunnel junction are electrically connected with a second signal line for inputting VCMA voltage. The power consumption can be reduced, and the operation accuracy is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices. More specifically, it relates to a computing-in-memory unit, device, data writing and operation method. Background Art

[0002] In recent years, deep neural networks have made breakthroughs in many fields such as image recognition, natural language processing, and speech recognition, and have gradually expanded to edge devices, including mobile terminals, wearable devices, and Internet of Things devices. However, the computing power and energy budget of these devices are usually limited. Therefore, how to design an efficient and lightweight neural network architecture has become one of the hot research issues. To meet the needs of edge computing scenarios, the computing-in-memory technology that can significantly reduce the energy consumption of deep neural networks has been proposed. This technology directly performs arithmetic operations in the memory, eliminating the bottleneck of data transfer in the traditional von Neumann architecture, thereby greatly improving the energy efficiency ratio. Currently, computing-in-memory solutions based on traditional memories and new non-volatile memories are widely studied.

[0003] Among new memories, the spin-transfer torque magnetic random access memory (STT-Magnetic random access memory, STT-MRAM) is considered a strong candidate for computing-in-memory technology due to its advantages in read / write speed, storage density, durability, and process compatibility. The core device of STT-MRAM is the magnetic tunnel junction (Magnetic tunnel junction, MTJ), which has binary characteristics and is therefore very suitable for binary neural networks. Compared with full-precision networks, binary neural networks significantly reduce the computational complexity and storage requirements by using binary activation input and weight data, making them more suitable for resource-constrained edge devices. However, in existing computing-in-memory devices using STT-MRAM, the resistance of the STT-MTJ in STT-MRAM is small, only in the order of 10 kΩ, and a large operation current will be generated during the operation process, resulting in a large operation power consumption problem. Moreover, STT-MTJ has a low switching ratio, making the voltage difference of the operation output voltage small and difficult to be quantified by the circuit, so the operation accuracy is low. Summary of the Invention

[0004] An object of the present application is to provide a computing-in-memory unit that uses spin-orbit torque magnetic random access memory (Spin-orbit torque-MRAM, SOT-MRAM) to implement the computing-in-memory function, reduce the power consumption of the computing-in-memory unit, and improve the operation accuracy. Another object of the present application is to provide a data writing method for the computing-in-memory unit. Still another object of the present application is to provide a computing-in-memory device. Yet another object of the present application is to provide a data operation method for the computing-in-memory device.

[0005] To achieve the above object, the present application adopts the following technical solutions: The present application discloses a memory - in - computing unit, including a first spin - orbit coupling layer, a second spin - orbit coupling layer, and a plurality of magnetic tunnel junctions disposed on the first spin - orbit coupling layer and the second spin - orbit coupling layer; The plurality of magnetic tunnel junctions include a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the first spin - orbit coupling layer, and a third magnetic tunnel junction and a fourth magnetic tunnel junction disposed on the second spin - orbit coupling layer; One end of the first spin - orbit coupling layer close to the second magnetic tunnel junction is electrically connected to one end of the second spin - orbit coupling layer close to the third magnetic tunnel junction through a switching element; The tops of the first magnetic tunnel junction and the fourth magnetic tunnel junction are electrically connected to a first signal line for inputting a VCMA voltage, and the tops of the second magnetic tunnel junction and the third magnetic tunnel junction are electrically connected to a second signal line for inputting a VCMA voltage.

[0006] Optionally, a first end of the switching element is electrically connected to one end of the first spin - orbit coupling layer close to the second magnetic tunnel junction, a second end is electrically connected to one end of the second spin - orbit coupling layer close to the third magnetic tunnel junction, and a control end is electrically connected to a write signal line. The switching element is turned on in response to a write signal input to the write signal line.

[0007] Optionally, one end of the first spin - orbit coupling layer close to the first magnetic tunnel junction is electrically connected to a first metal wire, and one end of the second spin - orbit coupling layer close to the fourth magnetic tunnel junction is electrically connected to a second metal wire.

[0008] Optionally, it further includes a VCMA regulation module for determining the VCMA voltages of the first signal line and the second signal line based on data to be written.

[0009] Optionally, when writing the first data, the VCMA regulation module inputs a VCMA voltage to the first signal line to make the voltage - controlled magnetic anisotropy of the first magnetic tunnel junction and the fourth magnetic tunnel junction less than that of the second magnetic tunnel junction and the third magnetic tunnel junction; when writing the second data, the VCMA regulation module inputs a VCMA voltage to the second signal line to make the voltage - controlled magnetic anisotropy of the second magnetic tunnel junction and the third magnetic tunnel junction less than that of the first magnetic tunnel junction and the fourth magnetic tunnel junction.

[0010] The present application also discloses a data writing method for the memory - in - computing unit as described above, including: Inputting a write signal to the switching element to turn on the switching element; Input a VCMA voltage to the first signal line based on the data to be written; Based on the target resistance states of the first magnetic tunnel junction and the fourth magnetic tunnel junction corresponding to the data to be written, input an SOT current through the first metal wire and the second metal wire to make the resistance states of the first magnetic tunnel junction and the fourth magnetic tunnel junction opposite; Input a VCMA voltage to the second signal line based on the data to be written; Based on the target resistance states of the second magnetic tunnel junction and the third magnetic tunnel junction corresponding to the data to be written, input an SOT current through the first metal wire and the second metal wire to make the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite, and the resistance states of the third magnetic tunnel junction and the fourth magnetic tunnel junction opposite.

[0011] This application also discloses a memory - computing integrated device, including a plurality of memory - computing integrated units arranged in an array as described above. Among them, the plurality of memory - computing integrated units in each row share the first signal line, the second signal line, and the write signal line, and the plurality of memory - computing integrated units in each column share the first metal wire and the second metal wire; The device further includes a plurality of decoders respectively corresponding to the memory - computing integrated units in each row, and the decoder is electrically connected to the first signal line and the second signal line of the corresponding row; The decoder is configured to transmit a first voltage and a second voltage corresponding to the activation data to the first signal line and the second signal line based on the activation data; The device further includes a plurality of amplifiers respectively corresponding to the memory - computing integrated units in each column, and the positive input terminal and the negative input terminal of the amplifier are electrically connected to the first metal wire and the second metal wire of the corresponding column respectively; The amplifier is configured to output an operation result through the output terminal based on the magnitudes of the output signals output from the first metal wire and the second metal wire.

[0012] Optionally, the activation data includes a first activation value and a second activation value; When the activation data is the first activation value, the decoder transmits the first voltage and the second voltage to the first signal line and the second signal line respectively; When the activation data is the second activation value, the decoder transmits the second voltage and the first voltage to the first signal line and the second signal line respectively.

[0013] Optionally, when the output signal output from the first metal wire is greater than the output signal output from the second metal wire, the amplifier outputs a first operation result; When the output signal output from the first metal wire is less than the output signal output from the second metal wire, the amplifier outputs a second operation result; When the output signal output by the first metal wire is equal to the output signal output by the second metal wire, the amplifier outputs a third operation result.

[0014] The present application also discloses a data operation method for the memory - in - computing device as described above, including: Keeping the switching element in an off state; Based on the input activation data, the decoder transmits a first voltage and a second voltage to the first signal line and the second signal line of the corresponding row respectively, or transmits a second voltage and a first voltage to the first signal line and the second signal line of the corresponding row respectively; Based on the output signals output by all the memory - in - computing units of the corresponding column through the first metal wire and the second metal wire, the amplifier outputs an operation result.

[0015] The beneficial effects of the present application are as follows: In the memory - in - computing unit of the present application, two magnetic tunnel junctions are respectively arranged on the first spin - orbit coupling layer and the second spin - orbit coupling layer, and one end of the two spin - orbit coupling layers is connected through a switching element. When the switching element is turned on, an SOT current is input to the two spin - orbit coupling layers connected electrically. The magnitudes of the SOT currents on the two spin - orbit coupling layers are equal and the directions are opposite. At the same time, the first magnetic tunnel junction and the fourth magnetic tunnel junction are electrically connected to the first signal line, and the second magnetic tunnel junction and the third magnetic tunnel junction are electrically connected to the second signal line. By changing the voltage - controlled magnetic anisotropy (VCMA) voltage of the first signal line and the second signal line, the voltage - controlled magnetic anisotropy of the magnetic tunnel junctions connected to different signal lines is changed, so that the magnitudes of the SOT currents required for changing the resistance states of the magnetic tunnel junctions corresponding to different signal lines are different. Then, while reducing the voltage - controlled magnetic anisotropy of the corresponding magnetic tunnel junction through the VCMA voltage and controlling the magnitude of the input SOT current, the resistance states of the two magnetic tunnel junctions connected to the same signal line can be deterministically changed. Then, the corresponding relationship between the resistance states of the four magnetic tunnel junctions and the data to be written can be set, and the writing and storage of two different data are realized by controlling the VCMA voltage and the SOT current.

[0016] Moreover, two magnetic tunnel junctions are arranged on one spin - orbit coupling layer, and the corresponding magnetic tunnel junctions on different spin - orbit coupling layers are electrically connected to the same signal line. By controlling the signal voltages of the two signal lines, two different activation data can be formed. Then, using this memory - in - computing unit, the logical operation function of two different activation data and two different weight data stored in the memory - in - computing unit can be realized.

[0017] In summary, the present application forms a multi-functional memory-computation integrated unit capable of storing data and performing logical operations through SOT-MRAM. By using SOT-MRAM, a high magnetoresistive tunnel junction resistance can be achieved, significantly reducing the operation current to lower power consumption. Moreover, the high magnetoresistive tunnel junction resistance of SOT-MRAM can increase the voltage difference between the output signals of different MTJs, improving the operation accuracy. Additionally, the memory-computation integrated unit of the present application only requires one switching element, with a smaller unit area, which can significantly improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following further elaborates on the specific embodiments of the present application with reference to the accompanying drawings.

[0019] Figure 1 Schematic diagram showing the structure of a specific embodiment of the memory-computation integrated unit of the present application; Figure 2 One of the schematic diagrams showing the write operation of a specific embodiment of the memory-computation integrated unit of the present application; Figure 3 Another schematic diagram showing the write operation of a specific embodiment of the memory-computation integrated unit of the present application; Figure 4 Schematic diagram showing the structure of a specific embodiment of the memory-computation integrated device of the present application; Figure 5 Schematic diagram showing the structure of a computer device including the memory-computation integrated device of the present application. SPECIFIC EMBODIMENTS

[0020] To more clearly illustrate the present application, the following further describes the present application with reference to preferred embodiments and the accompanying drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not limit the protection scope of the present application.

[0021] In the description of the present application, unless otherwise clearly defined and limited, the terms "connected", "connected to", and "fixed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0022] In the present application, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween.

[0023] In the description of this embodiment, the orientation or positional relationships such as "upper", "lower", "left", and "right" are based on the orientation or positional relationships shown in the drawings. They are only for convenience of description and simplifying the operations, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. In addition, the terms "first" and "second" are only used for distinction in description and have no special meanings.

[0024] According to one aspect of this application, this embodiment discloses a computing-in-memory unit. As Figure 1 、 Figure 2 and Figure 3 shown, in this embodiment, the computing-in-memory unit includes a first spin-orbit torque layer SOT1, a second spin-orbit torque layer SOT2, and a plurality of magnetic tunnel junctions disposed on the first spin-orbit torque layer SOT1 and the second spin-orbit torque layer SOT2.

[0025] The plurality of magnetic tunnel junctions include a first magnetic tunnel junction MTJ1 and a second magnetic tunnel junction MTJ2 disposed on the first spin-orbit torque layer SOT1, and a third magnetic tunnel junction MTJ3 and a fourth magnetic tunnel junction MTJ4 disposed on the second spin-orbit torque layer SOT2.

[0026] One end of the first spin-orbit torque layer SOT1 close to the second magnetic tunnel junction MTJ2 is electrically connected to one end of the second spin-orbit torque layer SOT2 close to the third magnetic tunnel junction MTJ3 through a switching element N1.

[0027] The tops of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are electrically connected to a first signal line BL for inputting a VCMA voltage, and the tops of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are electrically connected to a second signal line BLB for inputting a VCMA voltage.

[0028] In the memory - in - computing unit of this application, two magnetic tunnel junctions are respectively arranged on the first spin - orbit coupling layer SOT1 and the second spin - orbit coupling layer SOT2. One end of the two spin - orbit coupling layers 1 is connected through the switching element N1. When the switching element N1 is turned on, an SOT current is input to the two spin - orbit coupling layers 1 connected electrically. The magnitudes of the SOT currents on the two spin - orbit coupling layers 1 are equal and the directions are opposite. At the same time, the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are electrically connected to the first signal line BL, and the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are electrically connected to the second signal line BLB. By changing the voltage - controlled magnetic anisotropy of the magnetic tunnel junctions connected to different signal lines through the VCMA voltages of the first signal line BL and the second signal line BLB, the magnitudes of the SOT currents required to change the resistance states of the magnetic tunnel junctions corresponding to different signal lines are different. Then, while reducing the voltage - controlled magnetic anisotropy of the corresponding magnetic tunnel junctions through the VCMA voltage and controlling the magnitude of the input SOT current, the resistance states of the two magnetic tunnel junctions connected to the same signal line can be deterministically changed. Thus, the corresponding relationship between the resistance states of the four magnetic tunnel junctions and the data to be written can be set, and the writing and storage of two different data can be achieved by controlling the VCMA voltage and the SOT current.

[0029] Moreover, two magnetic tunnel junctions are arranged on one spin - orbit coupling layer 1, and the corresponding magnetic tunnel junctions on different spin - orbit coupling layers 1 are electrically connected to the same signal line. By controlling the signal voltages of the two signal lines, two different activation data can be formed. Then, using this memory - in - computing unit, the logical operation function between the two different activation data and the two different weight data stored in the memory - in - computing unit can be realized.

[0030] In summary, this application forms a multifunctional memory - in - computing unit capable of storing and performing logical operations through SOT - MRAM. Using SOT - MRAM can achieve a high magnetic tunnel junction resistance, significantly reduce the operation current to lower the power consumption. Moreover, the high magnetic tunnel junction resistance of SOT - MRAM can increase the voltage difference between the output signals of different MTJs, improving the operation accuracy. And, the memory - in - computing unit of this application only requires one switching element N1, with a smaller unit area, which can significantly improve the storage density.

[0031] In an optional embodiment, the first end of the switching element N1 is electrically connected to the end of the first spin - orbit coupling layer SOT1 close to the second magnetic tunnel junction MTJ2, the second end is electrically connected to the end of the second spin - orbit coupling layer SOT2 close to the third magnetic tunnel junction MTJ3, and the control end is electrically connected to the write signal line WL. The switching element N1 is turned on in response to the write signal input to the write signal line WL.

[0032] Specifically, it can be understood that in this embodiment, the switching element N1 can be a three-terminal device, such as a transistor. Among them, the first end and the second end of the three-terminal device are electrically connected to one end of the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 respectively. Thus, when the switching element N1 is turned on, the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 can form a path, and the SOT current input by the first spin-orbit coupling layer SOT1 is input into the second spin-orbit coupling layer SOT2 through the switching element N1. For the magnetic tunnel junctions of the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2, the magnitudes of the SOT currents input by the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 are equal and the directions are opposite. Thus, the purpose of writing the magnetic tunnel junctions on the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 into opposite resistance states can be achieved.

[0033] Optionally, the structure of the first spin-orbit coupling layer SOT1 and the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 thereon is exactly the same as that of the second spin-orbit coupling layer SOT2 and the third magnetic tunnel junction MTJ3 and the fourth magnetic tunnel junction MTJ4 thereon. When an SOT current greater than the critical switching current of the free layer 2 of the magnetic tunnel junction is input from one end of the first spin-orbit coupling layer SOT1 close to the first magnetic tunnel junction MTJ1 and one end of the second spin-orbit coupling layer SOT2 close to the fourth magnetic tunnel junction MTJ4, the resistance state of the magnetic tunnel junction can be changed to the first resistance state. On the contrary, when an SOT current greater than the critical switching current of the free layer 2 of the magnetic tunnel junction is input from one end of the first spin-orbit coupling layer SOT1 close to the second magnetic tunnel junction MTJ2 and one end of the second spin-orbit coupling layer SOT2 close to the third magnetic tunnel junction MTJ3, the resistance state of the magnetic tunnel junction can be changed to the second resistance state. Among them, when the first resistance state is a high resistance state, the second resistance state is a low resistance state; when the first resistance state is a low resistance state, the second resistance state is a high resistance state. Of course, in other embodiments, the structure of the first spin-orbit coupling layer SOT1 and the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 thereon can also be set to be different from that of the second spin-orbit coupling layer SOT2 and the third magnetic tunnel junction MTJ3 and the fourth magnetic tunnel junction MTJ4 thereon, as long as the inventive purpose of the present application can be achieved. The present application does not limit this.

[0034] Preferably, the first spin-orbit coupling layer SOT1 and the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 thereon can be fabricated by the same process flow as the second spin-orbit coupling layer SOT2 and the third magnetic tunnel junction MTJ3 and the fourth magnetic tunnel junction MTJ4 thereon to simplify the process.

[0035] Preferably, the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 can be arranged side by side in the same direction to provide a memory-computation integrated unit with a compact structure.

[0036] In an alternative embodiment, one end of the first spin-orbit coupling layer SOT1 close to the first magnetic tunnel junction MTJ1 is electrically connected to the first metal wire SL, and one end of the second spin-orbit coupling layer SOT2 close to the fourth magnetic tunnel junction MTJ4 is electrically connected to the second metal wire SLB.

[0037] Specifically, the other ends of the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 that are not connected to the switching element N1 can be respectively connected to the first metal wire SL and the second metal wire SLB, and an SOT current can be input into the path formed by the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2 through the first metal wire SL and the second metal wire SLB.

[0038] In an alternative embodiment, the memory-computation integrated unit further includes a VCMA regulation module for determining the VCMA voltages of the first signal line BL and the second signal line BLB based on the data to be written.

[0039] Specifically, in order to achieve the individual deterministic writing of different magnetic tunnel junctions on the first spin-orbit coupling layer SOT1 and the second spin-orbit coupling layer SOT2, a VCMA voltage is input into the first signal line BL and the second signal line BLB through the VCMA regulation module to regulate the voltage-controlled magnetic anisotropy of the magnetic tunnel junctions connected to the first signal line BL or the second signal line BLB, so that the voltage-controlled magnetic anisotropy of one of the magnetic tunnel junctions on the spin-orbit coupling layer 1 is reduced and it is easier to write, making the critical switching currents of the free layers 2 of the two magnetic tunnel junctions on the spin-orbit coupling layer 1 different, that is, the magnitudes of the SOT currents capable of deterministically changing the resistance states of the magnetic tunnel junctions are different. Then, by inputting an SOT current within the intermediate range between the two critical switching currents, the purpose of deterministically changing the resistance state of one of the two magnetic tunnel junctions while the resistance state of the other magnetic tunnel junction remains unchanged can be achieved, realizing the individual deterministic resistance state change of each magnetic tunnel junction on each spin-orbit coupling layer 1.

[0040] In an alternative embodiment, the VCMA regulation module is configured to, when writing data, input a VCMA voltage to the first signal line BL to make the voltage-controlled magnetic anisotropy of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 less than that of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3, and input an SOT current to deterministically change the resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4; input a VCMA voltage to the second signal line BLB to make the voltage-controlled magnetic anisotropy of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 less than that of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4, and input an SOT current to deterministically change the resistance states of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3.

[0041] Specifically, it can be understood that the VCMA regulation module and the SOT current cooperate to achieve successful storage of the data to be written in the memory-computation integrated unit through two-step deterministic changes in the resistance states of the magnetic tunnel junctions. In the first step, the VCMA regulation module selects the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4, and changes their resistance states through the SOT current, while the resistance states of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 remain unchanged; in the second step, the VCMA regulation module selects the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3, and changes their resistance states through the SOT current, while the resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 remain unchanged. Thus, the deterministic changes in the resistance states of the first magnetic tunnel junction MTJ1 to the fourth magnetic tunnel junction MTJ4 are achieved.

[0042] In a preferred embodiment, the low-resistance state resistances of the first magnetic tunnel junction MTJ1 to the fourth magnetic tunnel junction MTJ4 are greater than 100 kΩ to reduce power consumption, and the resistance of the magnetic tunnel junction can be made greater than 100 kΩ by increasing the thickness of the barrier layer 3 of the magnetic tunnel junction.

[0043] The following takes the first data as "+1" and the second data as "-1" as an example to illustrate the data writing process of the memory-computation integrated unit of the present application, including the following steps: If writing the data "+1": S11: Transmit a high-level enable signal VDD to the write signal line WL to make the control end of the switching element N1 conduct under the action of the write signal.

[0044] S12: Based on the data to be written, which is “+1”, input a high level VDD as the VCMA voltage to the first signal line BL, ground the second signal line BLB to GND, make the voltage-controlled magnetic anisotropy of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 less than that of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3. As a result, the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are more easily written, and the critical switching current of their free layer 2 is I1; the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are not easily written, and the critical switching current of their free layer 2 is I2, where I1 < I2.

[0045] S13: Connect the first metal line SL to a high level VW, connect the second metal line SLB to a low level GND, and input a first SOT current in the direction from the first metal line SL to the second metal line SLB to the spin-orbit coupling layer 1. The magnitude of this first SOT current is greater than I1 and less than I2. Under the action of the first SOT current, the resistance state of the first magnetic tunnel junction MTJ1 becomes a low-resistance state, and the resistance state of the fourth magnetic tunnel junction MTJ4 becomes a high-resistance state. The resistance states of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 remain unchanged.

[0046] S14: Input a high level VDD as the VCMA voltage to the second signal line BLB, ground the first signal line BL to GND, make the voltage-controlled magnetic anisotropy of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 less than that of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4. As a result, the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are more easily written, and the critical switching current of their free layer 2 is I3; the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are not easily written, and the critical switching current of their free layer 2 is I4, where I3 < I4.

[0047] S15: Connect the first metal line SL to a low level GND, connect the second metal line SLB to a high level VW, and input a second SOT current in the direction from the second metal line SLB to the first metal line SL to the spin-orbit coupling layer 1. The magnitude of this second SOT current is greater than I3 and less than I4. Under the action of the second SOT current, the resistance state of the second magnetic tunnel junction MTJ2 becomes a high-resistance state, and the resistance state of the third magnetic tunnel junction MTJ3 becomes a low-resistance state. The resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 remain unchanged. Thus, the writing of the data “+1” is completed.

[0048] If writing the data “-1”: S21: Transmit a high level enable signal VDD to the write signal line WL, and make the control terminal of the switching element N1 conduct under the action of the write signal.

[0049] S22: Input a high level VDD as the VCMA voltage to the first signal line BL based on the data to be written "-1", ground the second signal line BLB to GND, make the voltage-controlled magnetic anisotropy of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 less than that of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3. The first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are more easily written, and the critical switching current of their free layer 2 is I1; the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are not easily written, and the critical switching current of their free layer 2 is I2, and I1 < I2.

[0050] S23: Connect the first metal line SL to the low level GND, connect the second metal line SLB to the high level VW, and input a third SOT current in the direction from the second metal line SLB to the first metal line SL to the spin-orbit coupling layer 1. The magnitude of this third SOT current is greater than I1 and less than I2. Under the action of the third SOT current, the resistance state of the first magnetic tunnel junction MTJ1 becomes the high-resistance state, the resistance state of the fourth magnetic tunnel junction MTJ4 becomes the low-resistance state, and the resistance states of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 remain unchanged.

[0051] S24: Input a high level VDD as the VCMA voltage to the second signal line BLB, ground the first signal line BL to GND, make the voltage-controlled magnetic anisotropy of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 less than that of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4. The second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 are more easily written, and the critical switching current of their free layer 2 is I3; the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 are not easily written, and the critical switching current of their free layer 2 is I4, and I3 < I4.

[0052] S25: Connect the first metal line SL to the high level VW, connect the second metal line SLB to the low level GND, and input a fourth SOT current in the direction from the first metal line SL to the second metal line SLB to the spin-orbit coupling layer 1. The magnitude of this fourth SOT current is greater than I3 and less than I4. Under the action of the fourth SOT current, the resistance state of the second magnetic tunnel junction MTJ2 becomes the low-resistance state, the resistance state of the third magnetic tunnel junction MTJ3 becomes the high-resistance state, and the resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 remain unchanged. Thus, the writing of the data "-1" is completed.

[0053] Based on the same principle, this application also discloses a memory - in - computing device. The memory - in - computing device includes a plurality of memory - in - computing units as described in this embodiment arranged in an array. Among them, a plurality of memory - in - computing units in each row share a first signal line BL, a second signal line BLB, and a write signal line WL, and a plurality of memory - in - computing units in each column share a first metal line SL and a second metal line SLB.

[0054] The device further includes a plurality of decoders respectively corresponding to the memory - in - computing units in each row, and the decoder is electrically connected to the first signal line BL and the second signal line BLB of the corresponding row.

[0055] The decoder is configured to transmit a first voltage and a second voltage corresponding to the activation data to the first signal line BL and the second signal line BLB based on the activation data.

[0056] The device further includes a plurality of amplifiers respectively corresponding to the memory - in - computing units in each column, and the positive input terminal and the negative input terminal of the amplifier are electrically connected to the first metal line SL and the second metal line SLB of the corresponding column respectively.

[0057] The amplifier is configured to output an operation result through an output terminal based on the magnitudes of the output signals output from the first metal line SL and the second metal line SLB.

[0058] The multiple memory - in - computing units of the memory - in - computing device of this application are arranged in an array. During logical operations, the switching element N1 is disconnected. A plurality of memory - in - computing units in each row share the first signal line BL and the second signal line BLB. Then, the decoder can form corresponding first and second voltages based on the input activation data and apply them to the first signal line BL and the second signal line BLB. The voltages on the first signal line BL and the second signal line BLB pass through the magnetoresistive tunnel junctions connected correspondingly to form output signals, which are respectively output to the amplifier through the electrically connected first metal line SL and the second metal line SLB. A plurality of memory - in - computing units in each column of the memory - in - computing device share the first metal line SL and the second metal line SLB. Then, the output signals of all the first metal lines SL and the second metal lines SLB in the same column are cumulatively averaged and then output to the amplifier. The amplifier outputs an operation result based on the magnitude of the output signal after cumulative averaging of the corresponding first metal line SL and the second metal line SLB. This process can be used in a logic operation circuit. Thus, the memory - in - computing device can not only store data but also perform logical operations on the weight data stored in the memory - in - computing units, realizing the memory - in - computing function.

[0059] In an alternative embodiment, the activation data includes a first activation value and a second activation value. When the activation data is the first activation value, the decoder transmits the first voltage and the second voltage to the first signal line BL and the second signal line BLB, respectively; when the activation data is the second activation value, the decoder transmits the second voltage and the first voltage to the first signal line BL and the second signal line BLB, respectively.

[0060] Specifically, since the decoder can output two different voltages, namely the first voltage and the second voltage, to the first signal line BL and the second signal line BLB, different voltages input to different signal lines can represent two activation values. Each memory and computing unit can store two weight data. Then, under the action of the voltages on the first signal line BL and the second signal line BLB, the output signals output by each memory and computing unit through the first metal line SL and the second metal line SLB are the dot product results of the activation data and the weight data stored in the memory and computing unit. On this basis, the output signals output to the amplifier after all the decoders act on the memory and computing units arranged in an array are the matrix dot product results of the activation data matrix formed by all the decoders and the weight data matrix formed by the memory and computing units arranged in an array. The memory and computing device of the present application can implement the logical operation of two matrices. Further, the amplifier outputs the operation result based on the magnitudes of the output signals of the first metal line SL and the second metal line SLB, which is equivalent to further performing a sign function operation on the dot product result of the two matrices.

[0061] In an alternative embodiment, when the output signal output by the first metal line SL is greater than the output signal output by the second metal line SLB, the amplifier outputs a first operation result.

[0062] When the output signal output by the first metal line SL is less than the output signal output by the second metal line SLB, the amplifier outputs a second operation result.

[0063] When the output signal output by the first metal line SL is equal to the output signal output by the second metal line SLB, the amplifier outputs a third operation result.

[0064] Specifically, the amplifier can output three different operation results based on the magnitudes of the output signals of the first metal line SL and the second metal line SLB, thereby realizing a further sign function operation on the dot product result of the two matrices.

[0065] In a specific example, as Figure 4 shown, the memory and computing device includes memory and computing units arranged in N rows and M columns (W 0,0 、W 1,0… W M-1,0； W 0,1 、W 1,1…W M-1,1… W 0,N-1 、W 1, N-1… W M-1, N-1 ), each row of the memory - computing unit is correspondingly provided with a decoder, and the N decoders respectively receive N activation data (IN0, IN 1… IN N-1 ), each column of the memory - computing unit is correspondingly provided with an amplifier, and each row of the memory - computing units shares the first signal lines (BL0, BL 1… BL N-1 ), the second signal lines (BLB0, BLB 1… BLB N-1 ), the write signal lines (WL0, WL 1… WL N-1 ), each column of the memory - computing units shares the first metal lines (SL0, SL 1… SL M-1 ), and the second metal lines (SLB0, SLB 1… SLB M-1 ), and the amplifier of each column of the memory - computing units receives the output signals (V SUM0 、V SUM1… V SUMM-1 ) accumulated and averaged by the first metal lines and the output signals (V SUMB0 、V SUMB1… V SUMBM-1 ) accumulated and averaged by the second metal lines, and then can output the operation results (SUM0, SUM 1… SUM M-1 ). Then the memory - computing device can implement the following data logic operation functions:

[0066] Among them, W 0,0 、W 1,0… W M-1,0； W 0,1 、W 1,1… W M-1,1… W 0,N-1 、W 1, N-1… W M-1, N-1 are Figure 4 the weight data stored in the memory - computing units W 0,0 、W 1,0… W M-1,0； W 0,1 、W 1,1… W M-1,1… W 0,N-1 、W 1, N-1… W M-1, N-1 . The definition of the sign function is: if the result is greater than 0, the output is +1; if the result is less than 0, the output is -1; if the result is 0, the result is randomly +1 or -1.

[0067] Taking the first data as "+1", the second data as "-1", the first activation value as "+1", and the second activation value as "-1" as an example, the data operation method of the in-memory computing device of the present application will be described. The method includes the following steps: S31: Ground the write signal line WL to GND to keep the switching element N1 off.

[0068] S32: Each row decoder forms a first voltage and a second voltage based on the input activation data. Among them, the first voltage is a high level and the second voltage is a low level. When the activation data is the first activation value "+1", the first voltage is transmitted to the first signal line BL, and the second voltage is transmitted to the second signal line BLB, so that the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 are voltage-divided to form an output signal and transmitted to the first metal wire SL through the first spin-orbit coupling layer SOT1; the fourth magnetic tunnel junction MTJ4 and the third magnetic tunnel junction MTJ3 are voltage-divided to form an output signal and transmitted to the second metal wire SLB through the second spin-orbit coupling layer SOT2.

[0069] On the contrary, when the activation data is the second activation value "-1", the second voltage is transmitted to the first signal line BL, and the first voltage is transmitted to the second signal line BLB, so that the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 are voltage-divided to form an output signal and transmitted to the first metal wire SL through the first spin-orbit coupling layer SOT1; the fourth magnetic tunnel junction MTJ4 and the third magnetic tunnel junction MTJ3 are voltage-divided to form an output signal and transmitted to the second metal wire SLB through the second spin-orbit coupling layer SOT2.

[0070] During the data operation process, the corresponding relationship between the weight data stored in a single in-memory computing unit and each signal is shown in Table 1. Among them, HRS and LRS respectively represent the high-resistance state and the low-resistance state of the magnetic tunnel junction, VIH and VIL respectively represent the input high level and low level, VOH and VOL respectively represent the level of the output signal output from the in-memory computing unit to the metal wire, and VOH > VOL.

[0071] Table 1

[0072] S33: The amplifier corresponding to each column of the memory and computing unit obtains the operation result based on the output signals of the first metal line SL and the second metal line SLB. If the accumulated average output signal of the first metal line SL is greater than the accumulated average output signal of the second metal line SLB, the first operation result +1 is output. If the accumulated average output signal of the first metal line SL is less than the accumulated average output signal of the second metal line SLB, the second operation result -1 is output. If the accumulated average output signal of the first metal line SL is equal to the accumulated average output signal of the second metal line SLB, the third operation result is output, and the third operation result is a random result of +1 or -1. Then, the memory and computing device can perform the operation of the sign function on the result after matrix dot multiplication. The definition of the sign function is as follows: if the result is greater than 0, the output is +1; if the result is less than 0, the output is -1; if the result is 0, the output is a random +1 or -1.

[0073] In an alternative embodiment, the first magnetic tunnel junction MTJ1 to the fourth magnetic tunnel junction MTJ4 may include a fixed layer 4, a barrier layer 3, and a free layer 2 arranged in sequence from top to bottom. The bottom surface of the free layer 2 is fixedly connected to the spin-orbit coupling layer 1. It can be understood that the resistance of the magnetic tunnel junction depends on the magnetization directions of the fixed layer 4 and the free layer 2, and the magnetization directions of the free layer 2 and the fixed layer 4 are determined by the magnetic moment directions. The flipping of the magnetic moment direction depends on the SOT current input by the spin-orbit coupling layer 1. If the SOT current is greater than the critical flipping current of the free layer 2, the magnetic moment direction of the free layer 2 undergoes a deterministic flip corresponding to the SOT current. Thus, by controlling the magnitude of the SOT current, the magnetic moment direction of the free layer 2 of the magnetic tunnel junction can be controlled to control the resistance state change of the magnetic tunnel junction.

[0074] Among them, when the magnetic moment directions of the fixed layer 4 and the free layer 2 are the same, the magnetic tunnel junction is in a low-resistance state (low resistance state). When the magnetic moment directions of the fixed layer 4 and the free layer 2 are opposite, the magnetic tunnel junction is in a high-resistance state (high resistance state). The high-resistance state and the low-resistance state of the magnetic tunnel junction can be pre-corresponded to different data respectively. For example, it is preset that the high-resistance state corresponds to the data "1" and the low-resistance state corresponds to the data "0". Then, by inputting current or voltage to the magnetic tunnel junction through the reading circuit, according to the change of the current or voltage, it can be determined whether the resistance state of the magnetic tunnel junction is a high-resistance state or a low-resistance state, and according to the resistance state of the magnetic tunnel junction, the data stored in the magnetic tunnel junction can be determined as "1" or "0". Among them, the ranges of the high-resistance state and the low-resistance state are determined by common technical means in the art. Those skilled in the art can determine the resistance value ranges of the high-resistance state and the low-resistance state of the magnetic tunnel junction according to common knowledge, and this application will not elaborate here.

[0075] Optionally, the shape of the magnetic tunnel junction on the spin-orbit coupling layer 1 can be any one of shapes such as a cube, a cylinder, a cube, or an elliptical cylinder. The bottom surface shape of at least one magnetic tunnel junction provided on the spin-orbit coupling layer 1, that is, the lower surface of the free layer 2 is coupled to the spin-orbit coupling layer 1.

[0076] Preferably, the spin-orbit coupling layer 1 can be selected as a rectangle, so that the top surface area of the spin-orbit coupling layer 1 is larger than the area occupied by a plurality of magnetic tunnel junctions provided on the spin-orbit coupling layer 1, that is, a plurality of magnetic tunnel junctions can be arranged on the spin-orbit coupling layer 1, and the outer edges of the plurality of magnetic tunnel junctions are located inside the outer edges of the spin-orbit coupling layer 1. Among them, the spin-orbit coupling layer 1 is preferably selected as a heavy metal strip thin film or an antiferromagnetic strip thin film.

[0077] In a preferred embodiment, when the memory and computing integrated unit inputs current to the spin-orbit coupling layer 1 and the magnetic tunnel junction, it can be input by setting electrodes on the spin-orbit coupling layer 1 and the magnetic tunnel junction. For example, a top electrode is provided on the top of the magnetic tunnel junction, and an input electrode and an output electrode are respectively provided on opposite sides of the spin-orbit coupling layer 1. Among them, preferably, the material of the electrode can be any one of tantalum Ta, aluminum Al, gold Au, or copper Cu.

[0078] Preferably, the materials of the free layer 2 and the fixed layer 4 can be ferromagnetic metals, and the material of the barrier layer 3 can be an oxide. The magnetic tunnel junction has perpendicular magnetic anisotropy, which means that the magnetization directions of the free layer 2 and the fixed layer 4 forming the magnetic tunnel junction are along the vertical direction. Among them, the ferromagnetic metal can be a mixed metal material formed by at least one of materials such as cobalt iron CoFe, cobalt iron boron CoFeB, or nickel iron NiFe, and the proportions of the mixed metal materials can be the same or different. The oxide can be one of oxides such as magnesium oxide MgO or aluminum oxide Al2O3, which is used to generate the tunneling magnetoresistance effect. In practical applications, other feasible materials can also be used for the ferromagnetic metal and the oxide, and the present application does not limit this.

[0079] The free layer 2 of the magnetic tunnel junction is in contact and fixed with the spin-orbit coupling layer 1. The layers of the magnetic tunnel junction and the spin-orbit coupling layer 1 can be sequentially plated on the substrate in order from bottom to top by traditional methods such as ion beam epitaxy, atomic layer deposition, or magnetron sputtering, and then a plurality of magnetic tunnel junctions are prepared by traditional nano-device processing techniques such as photolithography and etching.

[0080] In a preferred embodiment, the spin-orbit coupling layer 1 is a spin-orbit coupling layer 1 composed of a heavy metal thin film, an antiferromagnetic thin film, or other materials. The heavy metal thin film or the antiferromagnetic thin film can be made rectangular, and its top area is preferably larger than the bottom area of the contour formed by all the magnetic tunnel junctions, so as to be able to arrange one or more magnetic tunnel junctions. The bottom surface shape of the magnetic tunnel junction is completely embedded in the top surface shape of the heavy metal thin film or the antiferromagnetic thin film. Preferably, the material of the spin-orbit coupling layer 1 can be selected from materials such as platinum Pt, tantalum Ta, or tungsten W. In practical applications, the spin-orbit coupling layer 1 can also be formed of other feasible materials, and the present application does not limit this.

[0081] Those skilled in the art can understand that the switching element N1 in this embodiment can be a triode, and in other embodiments, a diode can also be used. When implemented with a triode, an N-type triode or a P-type triode can be used. The high and low levels of various signals can only achieve corresponding functions in cooperation with the type of the triode. Those skilled in the art can know that a low-level signal is required to make a P-type triode conduct, and a high-level signal is required to make an N-type triode conduct. Therefore, an N-type triode or a P-type triode is used and the level of the triode gate (control terminal) is set to achieve the corresponding conduction or disconnection function, so as to achieve the data reading purpose of the present application. In the embodiment of the present application, the control terminal of the triode is the gate, the first terminal can be the source electrode, and the second terminal is the drain electrode, or vice versa. The first terminal can be the drain electrode, and the second terminal is the source electrode. The present application does not limit this and can be reasonably selected according to the type of the triode.

[0082] In addition, the triode provided in the embodiment of the present application can be a field effect triode, which can be an enhancement type field effect triode or a depletion type field effect triode. The triode can use a low-temperature polysilicon TFT, which can reduce the manufacturing cost and product power consumption and has a faster electron mobility. An oxide semiconductor TFT can also be used.

[0083] In this embodiment, the magnetic tunnel junction includes a fixed layer 4 at the top, a free layer 2 in contact with the spin-orbit coupling layer 1, and a barrier layer 3 provided between the fixed layer 4 and the free layer 2. The magnetic tunnel junction is a three-layer structure and only includes one free layer 2. In other embodiments, the free layer 2 can be set to multiple, that is, two or more free layers 2. Then the magnetic tunnel junction includes a fixed layer 4 at the top, multiple free layers 2, and a barrier layer 3 provided between every two adjacent layers. The bottom free layer 2 is in contact with the spin-orbit coupling layer 1. For example, in a specific example, when two free layers 2 are included, the magnetic storage unit structure can include a spin-orbit coupling layer 1, a second free layer 2, a barrier layer 3, a first free layer 2, a barrier layer 3, and a fixed layer 4 arranged in sequence on the spin-orbit coupling layer 1.

[0084] Based on the same principle, the present application also discloses a data writing method for the memory - in - computing unit as described in this embodiment. In this embodiment, the method includes: Input a write signal to the switching element N1 to turn on the switching element N1; Based on the data to be written, input a VCMA voltage to the first signal line BL; Based on the target resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 corresponding to the data to be written, input an SOT current through the first metal line SL and the second metal line SLB to make the resistance states of the first magnetic tunnel junction MTJ1 and the fourth magnetic tunnel junction MTJ4 opposite; Based on the data to be written, input a VCMA voltage to the second signal line BLB; Based on the target resistance states of the second magnetic tunnel junction MTJ2 and the third magnetic tunnel junction MTJ3 corresponding to the data to be written, input an SOT current through the first metal line SL and the second metal line SLB to make the resistance states of the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 opposite, and the resistance states of the third magnetic tunnel junction MTJ3 and the fourth magnetic tunnel junction MTJ4 opposite.

[0085] Since the principle of this method for solving problems is similar to that of the above - mentioned memory - in - computing unit and device, the implementation of this method can refer to the implementation of the above - mentioned memory - in - computing unit and device, which will not be elaborated here.

[0086] Based on the same principle, the present application also discloses a data operation method for the memory - in - computing device as described in this embodiment. The method includes: Keep the switching element N1 in the off state; Through the decoder, transmit a first voltage and a second voltage to the first signal line BL and the second signal line BLB of the corresponding row respectively based on the input activation data, or transmit a second voltage and a first voltage to the first signal line BL and the second signal line BLB of the corresponding row respectively; Output an operation result through the amplifier based on the output signals output by all the memory - in - computing units of the corresponding column through the first metal line SL and the second metal line SLB.

[0087] Since the principle of this method for solving problems is similar to that of the above - mentioned memory - in - computing unit and device, the implementation of this method can refer to the implementation of the above - mentioned memory - in - computing unit and device, which will not be elaborated here.

[0088] Based on the same principle, this embodiment also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and / or the memory includes the computing-in-memory unit as described in this embodiment.

[0089] The computing-in-memory unit illustrated in the above embodiment may be specifically disposed in a product device with a certain function. A typical implementation device is a computer device. Specifically, the computer device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0090] In a typical example, the computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and / or the memory includes the computing-in-memory unit as described in this embodiment.

[0091] Next, refer to Figure 5 , which shows a schematic structural diagram of a computer device 600 suitable for implementing the embodiments of the present application.

[0092] As Figure 5 shown, the computer device 600 includes a central processing unit (CPU) 601, which can perform various appropriate operations and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage section 608 into the random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the computer device 600 are also stored. The CPU 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

[0093] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that the computer program read from it can be installed into the storage section 608 as needed.

[0094] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or a means for implementing the functions specified in multiple blocks.

[0095] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction means that implements the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or a means for implementing the functions specified in multiple blocks.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operating steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or a means for implementing the functions specified in multiple blocks.

[0097] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity or device including the said element.

[0098] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can be implemented in the form of a computer program product applied to one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This application may be described in the general context of computer-executable instructions, such as program modules, executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including storage devices.

[0100] Each embodiment in this specification is described in a progressive manner, and for the same or similar parts among the embodiments, reference may be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and for the relevant parts, reference may be made to the partial description of the method embodiments.

[0101] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A computing-in-memory unit, characterized in that It includes a first spin-orbit coupling layer, a second spin-orbit coupling layer, and a plurality of magnetic tunnel junctions disposed on the first spin-orbit coupling layer and the second spin-orbit coupling layer; The plurality of magnetic tunnel junctions include a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the first spin-orbit coupling layer, and a third magnetic tunnel junction and a fourth magnetic tunnel junction disposed on the second spin-orbit coupling layer; One end of the first spin-orbit coupling layer close to the second magnetic tunnel junction is electrically connected to one end of the second spin-orbit coupling layer close to the third magnetic tunnel junction through a switching element; The tops of the first magnetic tunnel junction and the fourth magnetic tunnel junction are electrically connected to a first signal line for inputting a VCMA voltage, and the tops of the second magnetic tunnel junction and the third magnetic tunnel junction are electrically connected to a second signal line for inputting a VCMA voltage.

2. The in-memory computing unit according to claim 1, wherein The first end of the switching element is electrically connected to one end of the first spin-orbit coupling layer close to the second magnetic tunnel junction, the second end is electrically connected to one end of the second spin-orbit coupling layer close to the third magnetic tunnel junction, and the control end is electrically connected to a write signal line. The switching element conducts in response to a write signal input to the write signal line.

3. The computing-in-memory unit according to claim 1, wherein One end of the first spin-orbit coupling layer close to the first magnetic tunnel junction is electrically connected to a first metal wire, and one end of the second spin-orbit coupling layer close to the fourth magnetic tunnel junction is electrically connected to a second metal wire.

4. The in-memory computing unit according to claim 1, characterized in that It further includes a VCMA regulation module for determining the VCMA voltages of the first signal line and the second signal line based on data to be written.

5. The in-memory computing unit according to claim 4, wherein The VCMA regulation module is configured to, when writing the first data, input a VCMA voltage to the first signal line to make the voltage-controlled magnetic anisotropy of the first magnetic tunnel junction and the fourth magnetic tunnel junction less than that of the second magnetic tunnel junction and the third magnetic tunnel junction; when writing the second data, input a VCMA voltage to the second signal line to make the voltage-controlled magnetic anisotropy of the second magnetic tunnel junction and the third magnetic tunnel junction less than that of the first magnetic tunnel junction and the fourth magnetic tunnel junction.

6. A data writing method for a memory - in - computing unit as described in any one of claims 1 - 5, characterized in that, It includes: Inputting a write signal to the switching element to make the switching element conduct; Inputting a VCMA voltage to the first signal line based on data to be written; Inputting an SOT current through the first metal wire and the second metal wire based on the target resistance states of the first magnetic tunnel junction and the fourth magnetic tunnel junction corresponding to the data to be written to make the resistance states of the first magnetic tunnel junction and the fourth magnetic tunnel junction opposite; Inputting a VCMA voltage to the second signal line based on data to be written; Inputting an SOT current through the first metal wire and the second metal wire based on the target resistance states of the second magnetic tunnel junction and the third magnetic tunnel junction corresponding to the data to be written to make the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite, and the resistance states of the third magnetic tunnel junction and the fourth magnetic tunnel junction opposite.

7. An in-memory computing device, characterized in that, Comprising a plurality of in-memory computing units as described in any one of claims 1-5 arranged in an array, wherein a plurality of in-memory computing units in each row share a first signal line, a second signal line, and a write signal line, and a plurality of in-memory computing units in each column share a first metal line and a second metal line; The device further includes a plurality of decoders respectively corresponding to the in-memory computing units in each row, and the decoder is electrically connected to the first signal line and the second signal line of the corresponding row; The decoder is configured to transmit a first voltage and a second voltage corresponding to the activation data to the first signal line and the second signal line based on the activation data; The device further includes a plurality of amplifiers respectively corresponding to the in-memory computing units in each column, and the positive input terminal and the negative input terminal of the amplifier are respectively electrically connected to the first metal line and the second metal line of the corresponding column; The amplifier is configured to output an operation result through an output terminal based on the magnitudes of the output signals output by the first metal line and the second metal line.

8. The computing-in-memory device according to claim 7, wherein The activation data includes a first activation value and a second activation value; When the activation data is the first activation value, the decoder transmits the first voltage and the second voltage to the first signal line and the second signal line respectively; When the activation data is the second activation value, the decoder transmits the second voltage and the first voltage to the first signal line and the second signal line respectively.

9. The computing-in-memory device according to claim 7, wherein When the output signal output by the first metal line is greater than the output signal output by the second metal line, the amplifier outputs a first operation result; When the output signal output by the first metal line is less than the output signal output by the second metal line, the amplifier outputs a second operation result; When the output signal output by the first metal line is equal to the output signal output by the second metal line, the amplifier outputs a third operation result.

10. A data operation method for a memory-computation integrated device according to any one of claims 7-9, characterized in that, Including: Keeping the switching element in an off state; Based on the input activation data, the decoder transmits a first voltage and a second voltage to the first signal line and the second signal line of the corresponding row respectively, or transmits a second voltage and a first voltage to the first signal line and the second signal line of the corresponding row respectively; The amplifier outputs an operation result based on the output signals output by all the in-memory computing units in the corresponding column through the first metal line and the second metal line.

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