2.5D substrate manufacturing method and packaging structure

Abstract

The present application provides a 2.5D substrate manufacturing method and packaging structure. The 2.5D substrate manufacturing method includes: providing a first carrier with a metal component and an interposer mounted thereon; providing a metal pillar in the interposer; and forming a protective layer covering the metal component and the interposer on the first carrier. A first groove is formed on the metal component. The interposer and the protective layer are ground so that the surfaces of the interposer and the protective layer are lower than the surface of the metal component. A first dielectric layer having a first opening is formed on the surfaces of the interposer and the protective layer; the first opening exposes the metal pillar. A seed layer is formed in the first opening; the seed layer extends to the surface of the metal component and fills the first groove. A wiring layer is formed on the seed layer. This can enhance the bonding strength between the seed layer and the first dielectric layer, prevent corrosion of the sidewalls of the interposer during etching, and improve the quality and precision of the packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D substrate manufacturing method and a packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology has adopted a new design approach, packaging small chips with different functions together to form a heterogeneous integrated chip packaging structure. With the increasing input and output density of chips and the significant increase in the number of chips integrated into a single package, various 2.5D and 3D packaging technologies are being used as multi-chip packaging solutions to connect the pads of adjacent chips within a single package. Therefore, through-silicon via technology has been proposed to form a heterogeneous integrated packaging structure, thereby achieving multi-chip integration and reducing package volume and the number of wiring layers.

[0003] Currently, through-silicon via (TSV) technology is used on substrates to achieve vertical interconnection between chips. Conventional TSV technology typically uses etching or laser drilling to create a through-hole in the substrate, followed by electroplating to deposit a metal layer to form a metal pillar, which is then exposed by etching. This etching process can erode the sidewalls of the interposer, leading to delamination at the junction of the subsequent dielectric layer and the interposer sidewall, compromising packaging quality. Summary of the Invention

[0004] The object of the present invention is to provide a 2.5D substrate manufacturing method and packaging structure, which can prevent the sidewall of the interposer from being corroded, improve the bonding strength between the interposer and the dielectric layer, and improve the packaging quality.

[0005] In a first aspect, the present invention provides a method for manufacturing a 2.5D substrate, comprising:

[0006] Providing a first carrier having a metal component and an interposer mounted thereon; wherein the interposer is located within the metal component; and a metal column is provided within the interposer;

[0007] forming a protective layer covering the metal component and the interposer on the first carrier;

[0008] forming a first groove on the metal component;

[0009] grinding the intermediate layer and the protective layer so that the surfaces of the intermediate layer and the protective layer are lower than the surface of the metal component;

[0010] forming a first dielectric layer having a first opening on the surfaces of the interposer and the protective layer; wherein the first opening exposes the metal pillar;

[0011] forming a seed layer on the first dielectric layer; wherein the seed layer extends to the surface of the metal component and fills the first groove;

[0012] forming a wiring layer on the seed layer;

[0013] removing the seed layer outside the first opening;

[0014] A metal layer and a bump are formed; wherein the metal layer and the wiring layer are electrically connected.

[0015] In an optional embodiment, the thickness of the seed layer is equal to the depth of the first groove; and the first groove extends to a side of the metal component close to the interposer.

[0016] In an optional embodiment, the step of grinding the intermediary layer and the protective layer includes:

[0017] Grinding the interposer, the metal pillar, and the protective layer to the same plane;

[0018] The interposer is etched so that a surface of the interposer is lower than a surface of the protection layer and a surface of the metal pillar.

[0019] In an optional embodiment, after the step of etching the interposer, the step further includes:

[0020] An insulating layer is formed on the surface of the interposer; the surface of the insulating layer is flush with the surface of the protection layer and the surface of the metal pillar respectively.

[0021] In an optional embodiment, in the step of forming a protective layer covering the metal component and the interposer on the first carrier:

[0022] The protection layer is formed between the interposer and the metal component, and between adjacent metal components;

[0023] In the step of forming a seed layer on the first dielectric layer:

[0024] The seed layer is formed by depositing metal by sputtering; the seed layer covers the entire surface of the first dielectric layer and the surface of the metal component.

[0025] In an optional embodiment, the step of forming a wiring layer on the seed layer includes:

[0026] forming a photoresist on the seed layer, covering the photoresist with a photomask, and forming a second opening on the photoresist through an exposure and development process, wherein a portion of the seed layer is exposed through the second opening;

[0027] Using an electroplating process, electroplating metal in the second opening on the seed layer to form a wiring layer; wherein the seed layer serves as an electroplating lead, and the metal component serves as a clamping portion of an electroplating jig;

[0028] removing the photoresist;

[0029] The seed layer that does not overlap with the wiring layer is removed.

[0030] In an optional embodiment, in the step of removing the seed layer that does not overlap with the wiring layer:

[0031] In an optional embodiment, after the step of forming the metal layer and the bump, the method further includes:

[0032] mounting a chip on the bump;

[0033] Plastic-sealing the chip to form a second plastic-sealed body;

[0034] Cutting and separating into individual products; wherein the cutting position is located on the intermediate layer or on the protective layer.

[0035] In a second aspect, the present invention provides a packaging structure, which is manufactured using the 2.5D substrate manufacturing method described in any one of the aforementioned embodiments; the packaging structure comprises:

[0036] an interposer having metal pillars;

[0037] a dielectric layer, wherein a wiring layer electrically connected to the metal pillar is provided in the dielectric layer;

[0038] A seed layer, wherein the seed layer is provided between the wiring layer and the dielectric layer;

[0039] The bump protrudes from the dielectric layer and is electrically connected to the wiring layer.

[0040] The 2.5D substrate manufacturing method and packaging structure provided by the embodiments of the present invention have the following beneficial effects:

[0041] First, a protective layer is formed to cover the interposer, followed by grinding and etching. This prevents the interposer's sidewalls from being eroded during the etching process, improving the bonding strength between the interposer and the dielectric layer. Furthermore, forming a first groove on the metal component facilitates the subsequent formation of a seed layer, enhancing the bonding strength between the wiring layer and the dielectric layer, and improving packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 A schematic diagram of the process of manufacturing an interposer provided in an embodiment of the present invention;

[0044] Figure 2 One of the process diagrams of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0045] Figure 3 for Figure 2 A partial enlarged schematic diagram of point A in the middle;

[0046] Figure 4 for Figure 2 A partial enlarged schematic diagram of point B in the middle;

[0047] Figure 5 The second process diagram of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0048] Figure 6 for Figure 5 A partial enlarged schematic diagram of point C in the middle;

[0049] Figure 7 A schematic diagram of retaining a portion of the seed layer to form a ground wiring during the process of removing the seed layer in the first 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0050] Figure 8 The third process diagram of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0051] Figure 9 The fourth process diagram of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0052] Figure 10 A schematic diagram of a first structural embodiment of the packaging structure provided by the present invention;

[0053] Figure 11 A schematic diagram of a second structure of the packaging structure provided by an embodiment of the present invention;

[0054] Figure 12 A schematic diagram of a third structural embodiment of the packaging structure provided by the present invention;

[0055] Figure 13A schematic diagram of a top view of a packaging structure provided by an embodiment of the present invention;

[0056] Figure 14 A schematic diagram of a fourth structural embodiment of the packaging structure provided by the present invention;

[0057] Figure 15 A fifth structural schematic diagram of the packaging structure provided by an embodiment of the present invention;

[0058] Figure 16 A schematic diagram of a first manufacturing process of an interposer of a packaging structure provided by an embodiment of the present invention;

[0059] Figure 17 A schematic diagram of the main manufacturing process of the fifth structure of the packaging structure provided by an embodiment of the present invention;

[0060] Figure 18 A sixth structural diagram of the packaging structure provided by an embodiment of the present invention;

[0061] Figure 19 A seventh structural schematic diagram of the packaging structure provided by an embodiment of the present invention;

[0062] Figure 20 A schematic diagram of a second structure of an interposer of the packaging structure provided by an embodiment of the present invention;

[0063] Figure 21 A schematic diagram of the main manufacturing process of a seventh structure of the packaging structure provided by an embodiment of the present invention;

[0064] Figure 22 An eighth structural schematic diagram of the packaging structure provided by an embodiment of the present invention;

[0065] Figure 23 One of the main process diagrams of the ninth structure of the package structure provided by the embodiment of the present invention;

[0066] Figure 24 The second schematic diagram of the main process of the ninth structure of the package structure provided by the embodiment of the present invention;

[0067] Figure 25 A tenth structural schematic diagram of a packaging structure provided by an embodiment of the present invention;

[0068] Figure 26 This is a schematic diagram of an eleventh structure of a packaging structure provided by an embodiment of the present invention;

[0069] Figure 27 A schematic diagram of a third structure of an interposer of the packaging structure provided by an embodiment of the present invention;

[0070] Figure 28This is a schematic diagram of the main process of the eleventh structure of the package structure provided by an embodiment of the present invention;

[0071] Figure 29 The second schematic diagram of the main process of the eleventh structure of the package structure provided by the embodiment of the present invention;

[0072] Figure 30 One of the main process diagrams of the second 2.5D substrate manufacturing method provided by an embodiment of the present invention;

[0073] Figure 31 The second schematic diagram of the main process of the second 2.5D substrate manufacturing method provided by the embodiment of the present invention;

[0074] Figure 32 A schematic diagram of the main processes of a third 2.5D substrate manufacturing method is provided for an embodiment of the present invention.

[0075] Icons: 101-first carrier; 102-film; 110-intermediate layer; 111-metal pillar; 112-active wiring layer; 113-protective adhesive; 114-copper pillar; 115-fourth opening; 116-rewiring layer; 117-electrical connection pad; 120-metal component; 121-first groove; 130-protective layer; 140-insulating layer; 150-first dielectric layer; 151-first opening; 152-seed layer; 153-photoresist; 154-second opening; 155-wiring layer; 156- Ground wiring; 160-second dielectric layer; 161-third opening; 162-metal layer; 163-bump; 103-second carrier; 170-chip; 171-first bottom filling glue; 180-second plastic package; 190-conductive layer; 201-first wiring layer; 202-second wiring layer; 203-electrical connection column; 204-metal plating layer; 205-wiring bump; 206-second bottom filling glue; 210-protective film; 211-through groove; 212-third plastic package; 213-electrical connection terminal. DETAILED DESCRIPTION

[0076] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0077] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0078] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0079] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0080] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0081] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0082] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0083] The 2.5D substrate manufacturing method proposed in the embodiment of the present invention is beneficial for preventing the sidewall erosion of the interposer 110 caused by the etching process, improving the bonding strength between the interposer 110 and the dielectric layer, and improving the packaging quality and precision.

[0084] An embodiment of the present invention provides a method for manufacturing a 2.5D substrate, which generally includes the following steps:

[0085] Please combine Figure 1 and Figure 2 Step S1: providing a first carrier 101 mounted with a metal component 120 and an interposer 110 ; wherein the interposer 110 is located inside the metal component 120 ; and a metal pillar 111 is provided inside the interposer 110 .

[0086] Optionally, an interposer 110 is provided. The interposer 110 may be made of a silicon-based or germanium-based substrate material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. The thickness of the interposer 110 is 600 μm to 1500 μm.

[0087] Conductive vias are formed on the interposer 110 by dry etching. Dry etching can be performed using carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or hydrogen (H2) to etch the conductive vias on the interposer 110. Alternatively, the conductive vias can be formed on the interposer 110 by chemical etching using a mixture of hydrofluoric acid (HF), buffered oxide etchant, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2).

[0088] An insulating material is deposited in the hole wall of the conductive through hole using any one of vapor deposition methods such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD or PECVD. The insulating material can be at least one or more of silicon nitride, silicon oxynitride and polyimide.

[0089] The electroplating process is used to electroplate metal in the conductive through hole to form a metal pillar 111. After the TSV interposer 110 is manufactured, the interposer 110 is cut into individual interposers 110 with TSVs by cutting.

[0090] Combine Figures 2 to 4 , provide a first carrier 101, use a coating machine to apply a liquid adhesive layer to the first carrier 101 by spin coating, and then soft bake it on a hot plate to form an adhesive film 102. A single interposer 110 and a metal component 120 are respectively attached to the first carrier 101. Utilizing the adhesive properties of the adhesive film 102 and after baking, the interposer 110 and the metal component 120 can be reliably fixed on the adhesive film 102. The first carrier 101 includes, but is not limited to, materials such as glass, silicon oxide, or metal. The adhesive film 102 is a thermoplastic adhesive. The adhesive film 102 can be separated from the first carrier 101 after being irradiated with ultraviolet light. The material of the adhesive film 102 includes, but is not limited to, polymer composite materials such as epoxy resin and benzocyclobutene.

[0091] It is understood that a plurality of metal components 120 and a plurality of interposers 110 are mounted on the first carrier 101, and each metal component 120 is disposed around the periphery of an interposer 110. The height of the metal component 120 is consistent with the height of the interposer 110. The metal component 120 can be in the shape of a block, a column, or a ring.

[0092] Step S2: forming a protective layer 130 covering the metal component 120 and the intermediary layer 110 on the first carrier 101. A plastic encapsulation process may be used to form the protective layer 130 on the first carrier 101. The plastic encapsulation process includes but is not limited to pressure injection molding or printing injection molding. In this embodiment, the protective layer 130 may be a first plastic encapsulation body. The first plastic encapsulation body is filled between the plurality of metal components 120, and between the metal component 120 and the intermediary layer 110. Optionally, the surface of the protective layer 130, the surface of the intermediary layer 110, and the surface of the metal component 120 are located in the same plane, and the end face of the metal column 111 is flush with the surface of the intermediary layer 110. It should be noted that the material of the protective layer 130 may be a plastic encapsulation body, such as epoxy resin. In some embodiments, the protective layer 130 may also be made of a sacrificial material, such as photoresist.

[0093] Step S3: A first groove 121 is formed on the side of the metal component 120 away from the first carrier 101. A chemical polishing process can be used, using a chemical polishing solution such as ammonia, HF acid, or citric acid. Under the pressure of a polishing pad and the action of centrifugal force, the surface of the metal component 120 is polished to form the first groove 121. The depth of the first groove 121 is H1. The first groove 121 extends to the side of the metal component 120 that is closer to the interposer 110.

[0094] Step S4: Grind the interposer 110 and protective layer 130 on the side away from the first carrier 101 so that the surfaces of the interposer 110 and protective layer 130 are lower than the surface of the metal component 120. Optionally, the same grinding process as step S3 is used to grind the protective layer 130, interposer 110, and metal pillar 111. After grinding, the top surfaces of the protective layer 130, interposer 110, and metal pillar 111 are coplanar. The vertical distance between the ground surface of the interposer 110 and the bottom of the first groove 121 is H2.

[0095] Step S5: Etching the surface of the interposer 110 so that the metal pillars 111 are partially exposed from the surface of the interposer 110. Optionally, a dry etching process is used on the upper surface of the interposer 110 (the surface of the interposer 110 on the side away from the first carrier 101) to remove a portion of the interposer 110, so that the upper end surfaces of the metal pillars 111 are exposed from the surface of the interposer 110. The exposed height of the metal pillars 111 is on the micron level. It should be noted that since the protective layer 130 is coated on the periphery of the interposer 110, the outer peripheral wall of the interposer 110 can be protected. In this etching process, the etching gas only removes the material of the interposer 110 and does not remove the material of the protective layer 130. Therefore, the sidewalls of the interposer 110 can be prevented from being corroded, thereby protecting the sidewalls of the interposer 110 and improving the bonding between the interposer 110 and the dielectric layer in subsequent processes.

[0096] It should be noted that the etching gas can be selected from process gas and carrier gas according to actual needs. The process gas includes but is not limited to any one or more of SF6, CF4 and NF3. The carrier gas includes but is not limited to any one or more of nitrogen, helium and argon. During the etching process, the process gas is decomposed and the gas is partially ionized to form plasma. The fluorine ions in the plasma react with the etched material, and the ions bombard the surface of the etched material, which can knock out the atoms of the etched material, thereby achieving the purpose of etching by using physical energy. The surface materials of the interposer 110 are silicon and silicon oxide. The addition of gases such as nitrogen can improve the etching efficiency. The main reactions that occur during the etching process are as follows:

[0097] SiO2+4F=SiF4↑+O2↑

[0098] The waste gas generated in this process mainly consists of incompletely reacted fluorides and fluorides generated by the reaction.

[0099] Therefore, after the protection layer 130 is provided, the material of the protection layer 130 is different from the material of the interposer 110 , and the protection layer 130 will not be corroded, thereby effectively protecting the sidewall of the interposer 110 .

[0100] In this embodiment, the etching depth of the interposer 110 surface is H3, that is, the exposed height of the metal pillars 111 is H3. After etching, the surface of the interposer 110 is lower than the surface of the protection layer 130 and the surface of the metal pillars 111.

[0101] Step S6: forming an insulating layer 140 on the surface of the interposer 110. The surface of the insulating layer 140 is flush with the surface of the protection layer 130 and the surface of the metal pillar 111.

[0102] An insulating layer 140 is deposited on the surface of the interposer 110 using any of the vapor deposition methods PVCD, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The thickness of the insulating layer 140 is H3. The material of the insulating layer 140 includes, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, polyimide, and titanium nitride.

[0103] Combine Figure 5 and Figure 6 Step S7 : forming a first dielectric layer 150 having a first opening 151 on the surfaces of the interposer 110 and the protective layer 130 ; the first opening 151 exposes the metal pillar 111 .

[0104] Optionally, a first dielectric layer 150 is formed on the surfaces of the interposer 110 and the protective layer 130 using a spin coating process, such as spin coating or spray coating. The material of the first dielectric layer 150 includes, but is not limited to, any one or more organic materials such as polybenzoxazole (PBO), polyimide, and benzocyclobutene. A photomask is applied to the first dielectric layer 150, and an exposure and development process is performed to form a first opening 151 in the first dielectric layer 150. The first opening 151 is a patterned layer opening corresponding to the shape of the wiring layer 155. The height of the first dielectric layer 150 is H2, and the surface of the first dielectric layer 150 is flush with the bottom of the first groove 121.

[0105] Step S8 : forming a seed layer 152 on the first dielectric layer 150 . The seed layer 152 extends to the surface of the metal component 120 and fills the first groove 121 .

[0106] Optionally, a seed layer 152 is formed in the first opening 151 by metal sputtering, and the seed layer 152 is a metal conductive material, including but not limited to any one or more of copper, titanium, nickel, vanadium, chromium, gold, titanium and tungsten. The seed layer 152 can be one or more layers of metal. In this embodiment, the thickness of the seed layer 152 is the depth H1 of the first groove 121, that is, the seed layer 152 fills the first groove 121 on the metal component 120. It is easy to understand that due to the use of metal sputtering, the seed layer 152 can be formed on the entire surface of the metal component 120 and the first dielectric layer 150. In other words, the seed layer 152 can cover the protective layer 130 and the metal component 120 between adjacent interposers 110. The seed layer 152 in the first opening 151 is electrically connected to the metal pillar 111.

[0107] Seed layer 152 can enhance the bonding between wiring layer 155 and first dielectric layer 150, preventing structural delamination. Seed layer 152 can also improve the bonding between wiring layer 155 and metal pillars 111, enhancing electrical conductivity. First groove 121 can control the thickness of seed layer 152, improving subsequent wiring accuracy.

[0108] Step S9: Optionally, after forming the seed layer 152, a photoresist 153 is coated on the surface of the seed layer 152 using a spin coating process. A photomask is used to cover the photoresist 153. An exposure and development process is performed to form a second opening 154 in the photoresist 153. The second opening 154 exposes a portion of the seed layer 152. The second opening 154 is similar in shape to the first opening 151 and is designed based on the required wiring layer 155.

[0109] By using an electroplating process, metal is electroplated in the second opening 154 on the seed layer 152 to form a wiring layer 155. Optionally, in the electroplating process, the metal component 120 can be used as a clamping portion of an electroplating jig. The clamping portion is preferably a portion other than the first groove 121 on the surface of the metal component 120. Using the metal component 120 as the clamping portion of the electroplating jig will not cause damage to the surface of the interposer 110. The seed layer 152 can also be used as an electroplating lead to ensure the uniformity of the electroplating of all wiring layers 155 in the second opening 154, and the thickness of the wiring layer 155 is uniform, thereby improving the electroplating efficiency and electroplating quality of the wiring layer 155.

[0110] Step S10: Using a wet etching process, the photoresist 153 is removed using a developer, and then micro-etching is performed using a chemical etching method to remove the seed layer 152. The chemical etching solution can be a mixture of sulfuric acid and hydrogen peroxide.

[0111] It should be noted that, during the process of removing the seed layer 152, the seed layer 152 that does not overlap with the wiring layer 155 is removed. This ensures that the seed layer 152 remains between the wiring layer 155 and the first dielectric layer 150, thereby improving the bonding strength between the first dielectric layer 150 and the wiring layer 155, and improving the conductivity and bonding strength between the wiring layer 155 and the metal pillars 111.

[0112] Combine Figure 7 , optionally, in some embodiments, in the process of removing the seed layer 152, the seed layer 152 between adjacent first openings 151 can also be removed to prevent the wiring layer 155 from being short-circuited. At the same time, part or all of the seed layer 152 corresponding to the position of the metal component 120 and the protective layer 130 is retained to form a ground wiring 156 or an equipotential wiring. It is easy to understand that it is only necessary to partially retain the seed layer 152 on the surface of the metal component 120 so that the wiring layer 155 can be electrically extended to the surface of the metal component 120. If the seed layer 152 on the metal component 120 is electrically connected to the grounded portion of the wiring layer 155, the seed layer 152 on the surface of the metal component 120 forms a ground wiring 156, which can achieve electrostatic discharge. Alternatively, the seed layer 152 on the metal component 120 can also be electrically connected to the non-grounded portion of the wiring layer 155, which is not specifically limited here.

[0113] Combine Figure 8 Step S11: A second dielectric layer 160 is formed on the surface of the first dielectric layer 150 by a spin coating process, such as spin coating or spray coating. The material of the second dielectric layer 160 includes, but is not limited to, any one or more of silicon nitride, silicon oxynitride, polyimide, and benzocyclobutene. A photomask is used to cover the second dielectric layer 160, and a third opening 161 is formed on the second dielectric layer 160 by an exposure and development process. The third opening 161 exposes the wiring layer 155. Metal is deposited in the third opening 161 to form a metal layer 162. The metal layer 162 is electrically connected to the wiring layer 155. The metal layer 162 can be made of copper or other metal materials. The formation method of the metal layer 162 includes, but is not limited to, sputtering, chemical plating, or electroplating.

[0114] Step S12: Using a ball planting process to form bumps 163 on the metal layer 162. The ball planting method can be electroplating or printing, and the material of the bumps 163 can be a conductive material such as Sn-Ag, Sn-Bi or Sn-Ag-Cu.

[0115] Finally, the first carrier 101 is separated from the interposer 110 by debonding using ultraviolet light, and the first carrier 101 is removed. Thus, the fabrication of one side of the interposer 110 is completed.

[0116] In some embodiments, if only wiring on one side of the interposer 110 needs to be fabricated, the protective layer 130 may be removed by chemical cleaning to obtain an interposer 110 product with a wiring layer 155 on one side.

[0117] Combine Figure 9 It should be noted that in some embodiments, wiring is also required on the other side of the interposer 110, meaning that a single interposer 110 product includes double-sided wiring. After removing the first carrier 101, the side of the interposer 110 with the bumps 163 is mounted on the second carrier 103. Steps S3 to S12 are then performed on the side of the interposer 110 away from the second carrier 103 to complete wiring on the other side, effectively completing substrate fabrication.

[0118] Optionally, a chip 170 may be mounted on the interposer 110. For example, in the case of a flip-chip 170, the bumps of the chip 170 are soldered to the bumps 163 of the interposer 110, thereby electrically connecting the chip 170 to the interposer 110. A first underfill 171 is then applied to fill the gap between the chip 170 and the interposer 110.

[0119] Optionally, the chip 170 is encapsulated in plastic. A second plastic encapsulation body 180 is formed on the interposer 110 to protect the solder joint between the chip 170 and the interposer 110. Optionally, the second plastic encapsulation body 180 can be ground flush with the surface of the chip 170, that is, the second plastic encapsulation body 180 is exposed on the surface of the chip 170. This helps improve heat dissipation performance and reduce package height.

[0120] Remove the second carrier 103 and cut and separate the interposer 110 to form a single product. It should be understood that due to the different cutting positions, single products with different structures can be formed. For example, if the cutting position is on the interposer 110, the metal component 120 and the protective layer 130 are cut and removed together, and the resulting single product is as follows: Figure 10 If the cutting position is on the protective layer 130, there are two cases:

[0121] First, the cutting position is located at the protective layer 130 between the metal component 120 and the intermediary layer 110, then the metal component 120 is cut away, and part of the protective layer 130 is retained. The protective layer 130 protects the side wall of the intermediary layer 110. The structure of a single product is as follows: Figure 11 shown.

[0122] Second, if the cutting position is located at the protective layer 130 on the side of the metal component 120 away from the intermediary layer 110, the metal component 120 will remain in the single product, which can reduce structural warping, improve heat dissipation performance, and increase structural strength and peripheral support. Figure 12 shown.

[0123] Combine Figure 10 , an embodiment of the present invention further provides a packaging structure, which is prepared using the 2.5D substrate manufacturing method of any one of the aforementioned embodiments. The packaging structure includes an interposer 110, an insulating layer 140, a dielectric layer, a seed layer 152, a wiring layer 155 and a bump 163. Among them, the interposer 110 is provided with a metal pillar 111, and the two ends of the metal pillar 111 are respectively exposed from the surface of the interposer 110. The insulating layer 140 covers the surface of the interposer 110 and is flush with the surface of the metal pillar 111. A wiring layer 155 electrically connected to the metal pillar 111 is provided in the dielectric layer. A seed layer 152 is provided between the wiring layer 155 and the dielectric layer. The bump 163 protrudes from the dielectric layer, and the bump 163 is electrically connected to the wiring layer 155.

[0124] Optionally, the dielectric layer includes a stacked first dielectric layer 150 and a second dielectric layer 160. The first dielectric layer 150 is located on a side of the insulating layer 140 away from the interposer 110, and the second dielectric layer 160 is located on a side of the first dielectric layer 150 away from the interposer 110. A wiring layer 155 is located within the first dielectric layer 150. The second dielectric layer 160 includes a metal layer 162 electrically connected to the wiring layer 155. Bumps 163 protrude from the second dielectric layer 160, and the bumps 163 are electrically connected to the metal layer 162. The first dielectric layer 150 and the second dielectric layer 160 are made of the same material.

[0125] Combine Figure 11 Optionally, the periphery of the interposer 110 is covered with a protective layer 130 , and two surfaces of the protective layer 130 are flush with both end surfaces of the metal pillar 111 .

[0126] Combine Figure 12 and Figure 13 Optionally, the packaging structure further includes a metal component 120; the metal component 120 is located on the periphery of the interposer 110; the protective layer 130 is located between the metal component 120 and the interposer 110, and on the side of the metal component 120 away from the interposer 110; the two surfaces of the metal component 120 are respectively higher than the two end surfaces of the metal pillar 111; the surface of the metal component 120 extends into the dielectric layer.

[0127] Combine Figure 14 Optionally, first grooves 121 are provided on both surfaces of the metal component 120, and a conductive layer 190 is provided in the first groove 121. The conductive layer 190 is electrically connected to the wiring layer 155. It should be noted that the conductive layer 190 here is the seed layer 152 sputtered in the preparation process. When the seed layer 152 is removed, the partially retained seed layer 152 forms the conductive layer 190. If the conductive layer 190 is electrically connected to the grounded portion in the wiring layer 155, it becomes the ground wiring 156, which has the function of discharging static electricity.

[0128] In some embodiments, the conductive layer 190 can be electrically connected to the non-grounded portion of the wiring layer 155, and the conductive layer 190 can be provided on both sides of the metal component 120. This can form equipotential wiring, that is, the electric potential on both sides of the metal component 120 is equal, which can prevent the generation of static electricity and avoid electrostatic interference.

[0129] Combine Figure 15In some embodiments, interposer 110 comprises devices such as inductors, piezoelectric devices, resistors, capacitors, transistors, or diodes, and an active wiring layer 112 is provided on interposer 110. A first wiring layer 201 and a second wiring layer 202 are formed on either side of interposer 110, electrically connected to active wiring layer 112. Bumps 163 are connected to each of the first and second wiring layers 201 and 202. A chip 170 is disposed on at least one side of interposer 110, and soldered to bumps 163. A first underfill 171 is applied to the bottom of chip 170 to protect the soldering structure. A second plastic package 180 is provided around chip 170. This creates an integrated circuit (IC) package. An IC package includes a package substrate and one or more IC chips or other electronic modules mounted on the package substrate to provide electrical connections to the IC chips. For example, the IC chip in the IC package may be a system-on-chip (SoC). The IC chip is electrically coupled to other IC chips and / or other components in the IC package by electrically coupling to metal lines in the package substrate. The IC chip can also be electrically coupled to other circuits outside the IC package through electrical connections of external metal interconnects of the IC package. For example, one or more embedded capacitors can provide decoupling capacitance for a power distribution network (PDN) in the IC package to reduce current resistance (IR) drop. As another example, the active wiring layer 112 of the embedded capacitor is disposed between the IC chip and the package substrate to minimize the distance between the embedded capacitor and the IC chip. This can reduce parasitic inductance in the power distribution lines between the embedded capacitor and the IC chip, thereby reducing IR drop in the PDN and also helping to reduce PDN noise.

[0130] Optionally, the first wiring layer 201 and the second wiring layer 202 are electrically connected through an electrical connection column 203. The first wiring layer 201 is directly connected to the active wiring layer 112. The first wiring layer 201 includes a redistribution layer 116. The active wiring layer 112 and the redistribution layer 116 are directly connected. This design has a high degree of integration, can achieve high-density packaging, and can shorten the transmission path, improve transmission efficiency, and reduce transmission loss. The seed layer 152 is electrically connected to the second wiring layer 202, and the seed layer 152 is located on the side of the second wiring layer 202 close to the intermediate layer 110. The design of the seed layer 152 can improve the bonding strength between the wiring layer 155 and the dielectric layer, and can also improve the electrical transmission performance of the wiring layer 155.

[0131] Figure 15 The preparation process of the structure shown is roughly as follows:

[0132] Combine Figure 16 An active wiring layer 112 is formed on the interposer 110. A protective adhesive 113 is provided on the side of the active wiring layer 112 away from the interposer 110. The protective adhesive 113 may be a photoresist. The interposer 110 is cut into individual products.

[0133] Optionally, the side of the interposer 110 away from the protective glue 113 is ground so that the end surface of the metal pillar 111 away from the protective glue 113 is flush with the surface of the interposer 110 .

[0134] Combine Figure 17 , interposer 110 and metal component 120 are mounted on first carrier 101; protective adhesive 113 is flush with metal component 120. The side of interposer 110 with active wiring layer 112 faces away from first carrier 101. Optionally, electrical connector 203 is formed on first carrier 101; electrical connector 203 is located between metal component 120 and interposer 110 and is flush with metal component 120.

[0135] It is understood that after mounting the electrical connector 203 on the first carrier 101 and mounting the metal component 120, the metal component 120 is positioned around the electrical connector 203. During the subsequent molding process, the metal component 120 can block the molding flow, preventing the electrical connector 203 from being bent or broken by the molding flow. Alternatively, if the metal component 120 is a metal block, the mounting of the electrical connector 203 can be omitted, and the electrical connection between the first wiring layer 201 and the second wiring layer 202 can be achieved through the metal component 120.

[0136] The protective layer 130 is formed by plastic encapsulation. The protective layer 130 is polished to expose the protective glue 113 on the interposer 110. During the polishing process, the protective glue 113 protects the active wiring layer 112 and prevents the metal ions generated during the polishing from contaminating the active wiring layer 112.

[0137] A fourth opening 115 is formed in the protective film 113 by exposure and development. A redistribution layer 116 is formed within the fourth opening 115. The redistribution layer 116 is electrically connected to the active wiring layer 112. The protective film 113 is then removed. The protective film 113 is made of photoresist, which allows the fourth opening 115 to be formed directly. This eliminates the need for a single photoresist coating step, simplifies the process, and improves packaging efficiency.

[0138] A dielectric layer is coated on the redistribution layer 116, and exposed and developed to form a patterned opening, and a first wiring layer 201 is formed in the patterned opening. The first wiring layer 201 is electrically connected to the redistribution layer 116. After the first wiring layer 201 is formed, the dielectric layer is further coated to form a metal layer 162 and a bump 163, thereby completing the preparation of one side of the dielectric layer. It should be noted that, in this embodiment, the redistribution layer 116 can be regarded as a part of the first wiring layer 201, that is, the first wiring layer 201 has two layers. The number of layers of the first wiring layer 201 can be one or more layers, which is not specifically limited here. In this structure, the first wiring layer 201 and the active wiring layer 112 are directly connected, the transmission path is short, the transmission efficiency is high, and the integration is high.

[0139] The dielectric layer is flipped over to complete the preparation of the other side. The preparation of the other side is as described in process steps S3 to S12. Steps S5 and S6 can be selectively omitted, that is, the insulating layer 140 can be omitted.

[0140] Combine Figure 18 , the packaging structure may not include the insulating layer 140. In the packaging structure of other embodiments, the insulating layer 140 is also an optional structure.

[0141] Combine Figure 19 In some embodiments, the first wiring layer 201 and the active wiring layer 112 are electrically connected via copper pillars 114. Optionally, a protective adhesive 113 is provided between the first wiring layer 201 and the active wiring layer 112, and a copper pillar 114 is provided within the protective adhesive 113; the thickness of the protective adhesive 113 is greater than the height of the copper pillar 114; one end of the copper pillar 114 is electrically connected to the first wiring layer 201, and the other end is electrically connected to the active wiring layer 112. Compared to directly connecting the first wiring layer 201 and the active wiring layer 112, the use of copper pillars 114 can increase the distance between the first wiring layer 201 and the active wiring layer 112 in the thickness direction, which helps reduce parasitic capacitance effects.

[0142] Or, combined Figure 20 , to prepare Figure 19 In the structure shown, when preparing interposer 110, copper pillars 114 can be provided within protective adhesive 113. Copper pillars 114 are electrically connected to active wiring layer 112. Optionally, the thickness of protective adhesive 113 is greater than the height of copper pillars 114. This allows protective adhesive 113 to protect copper pillars 114 during subsequent polishing processes.

[0143] Combine Figure 21 The interposer 110 is mounted on the first carrier 101 with the copper pillars 114 facing upward. Electrical connectors 203 and metal component 120 are mounted on the first carrier 101. Both the electrical connectors 203 and the interposer 110 are located within the metal component 120. A protective layer 130 is formed on the first carrier 101. Referring to steps S11 and S12 above, a dielectric layer is applied to the protective adhesive 113 to form the first wiring layer 201, the metal layer 162, and the bumps 163.

[0144] Optionally, after forming the protective layer 130, the aforementioned process step S3 can be used to first form the first groove 121 in the metal component 120. Steps S7 to S12 are then repeated to apply a dielectric layer, expose and develop the layer, and then electroplate the seed layer 152. A photoresist 153 is applied, exposed and developed to form patterned openings, thereby forming the first wiring layer 201. The photoresist 153 and a portion of the seed layer 152 are then removed. A metal layer 162 and bumps 163 are then formed.

[0145] It should be noted that in some embodiments, the step of mounting the electrical connection posts 203 on the first carrier 101 can be omitted. Instead, after forming the bumps 163, laser holes are formed in the first plastic package (protective layer 130) and then electroplated with filler metal to achieve electrical connection between the first wiring layer 201 and the second wiring layer 202.

[0146] In some embodiments, the thickness of the protective glue 113 may also be flush with the surface of the copper pillar 114. Figure 22 As shown in FIG. 1 , when the protective layer 130 is ground, the surface of the copper pillar 114 can be exposed. During the grinding process, the protective glue 113 can also prevent metal ions from contaminating the active wiring layer 112.

[0147] Combine Figure 23 and Figure 24 In some embodiments, the first wiring layer 201 is directly electrically connected to the active wiring layer 112. The preparation process can also be roughly as follows:

[0148] An active wiring layer 112 is formed on the interposer 110. The number of active wiring layers 112 can be one or more layers, depending on the design. When the interposer 110 is mounted on the first carrier 101, the active wiring layer 112 faces the first carrier 101. Steps S3 through S12 are performed on the side of the interposer 110 facing away from the first carrier 101 to form the second wiring layer 202 and bumps 163. The interposer 110 is flipped over, the first carrier 101 is removed, and steps S11 and S12 are performed on the side with the active wiring layer 112 to form the first wiring layer 201 and bumps 163.

[0149] In other words, the process is flexible. When mounting the interposer 110 , the active wiring layer 112 may be arranged with one side facing the first carrier 101 or with one side facing away from the first carrier 101 .

[0150] It is understood that the electrical connection posts 203 can be mounted on the first carrier 101 when the metal component 120 is mounted. Alternatively, after forming the protective layer 130, holes can be opened in the protective layer 130 and metal is electroplated to form the electrical connection posts 203, or the electrical connection posts 203 can be formed by electroplating on the carrier, such as Figure 28 , no specific limitation is given here.

[0151] Figure 15 In the structure shown, the chip 170 is mounted on the side of the interposer 110 having the active wiring layer 112. This arrangement shortens the transmission path, improves the transmission efficiency, and reduces the loss.

[0152] Combine Figure 25Chip 170 can also be mounted on the side of interposer 110 away from active wiring layer 112. This arrangement connects second wiring layer 202 to chip 170, while first wiring layer 201 connects to the active wiring layer. According to the capacitance calculation formula: C = εS / d, a greater distance d between active wiring layer 112 and second wiring layer 202 connected to chip 170 reduces the effects of parasitic current and capacitance, resulting in less interference with chip 170.

[0153] Of course, in some embodiments, chips 170 can be mounted on both sides of the interposer 110, which is not specifically limited here. The second plastic package 180 covers the chip 170, and the surface of the second plastic package 180 can be flush with the surface of the chip 170, or higher than the surface of the chip 170, that is, completely covering the chip 170.

[0154] Combine Figure 26 The interposer 110 is provided with an electrical connection pad 117 connected to the active wiring layer 112 ; the first wiring layer 201 or the second wiring layer 202 is provided with a wiring bump 205 , and the electrical connection pad 117 is connected to the wiring bump 205 .

[0155] Optionally, electrical connection pads 117 on interposer 110 are electrically connected to first wiring layer 201 using soldering, and a second underfill 206 is applied beneath interposer 110 to protect the soldering structure. Second wiring layer 202 is connected to chip 170 via bumps 163, with a seed layer 152 disposed between second wiring layer 202 and the dielectric layer. One end of electrical connection post 203 is electrically connected to first wiring layer 201, and the other end is electrically connected to second wiring layer 202.

[0156] Combine Figures 27 to 29 , Figure 26 The structure shown in FIG. 1 is prepared as follows:

[0157] A first carrier 101 coated with an adhesive film 102 is provided, and a metal coating 204 is formed on the first carrier 101 by electroplating, deposition, sputtering, etc. Electrical connection posts 203 and wiring bumps 205 are provided on the metal coating 204 .

[0158] An active wiring layer 112 and electrical pads 117 are provided on the interposer 110. The active wiring layer 112 is electrically connected to the metal pillars 111, and the electrical pads 117 are electrically connected to the active wiring layer 112. The metal component 120 and the interposer 110 are mounted; the electrical pads 117 of the interposer 110 are mounted to the first carrier 101. The electrical pads 117 are soldered to the corresponding wiring bumps 205. A second underfill 206 is applied beneath the interposer 110 to protect the soldered structure.

[0159] The electrical connection pillar 203 is mounted between the interposer 110 and the metal component 120 .

[0160] A protective layer 130 is formed on the first carrier 101. Steps S3 to S12 are performed to complete the preparation of one side of the interposer 110.

[0161] The interposer 110 is flipped over, the first carrier 101 is removed, and the metal plating layer 204 is removed by micro-etching to expose the wiring bumps 205. Steps S3, S7 to S12 are performed to complete the fabrication of the other side of the interposer 110. Steps S3, S7 to S10 may be optionally omitted.

[0162] Combine Figure 30 and Figure 31 In some embodiments, after completing the steps of forming the metal layer 162 and the bump 163 on one side of the interposer 110 , the method further includes:

[0163] Remove the first carrier 101 and attach the second carrier 103 to the side where the bump 163 is located.

[0164] A protective film 210 is formed on the side where the first carrier 101 is removed, and the protective film 210 covers the interposer 110; the metal component 120 and the protective layer 130 are removed. The metal component 120 and the protective layer 130 can be removed in two separate processes, with no particular restriction on the order of the two processes. The metal component 120 can be removed using an etching process. The protective layer 130 can be removed using a photoresist wash process. It should be noted that in this embodiment, if a photoresist wash process is required, the protective layer 130 can be made of a sacrificial material such as photoresist.

[0165] Optionally, after removing the metal component 120 or the protective layer 130, the protective film 210 is removed using a debonding process. In this embodiment, the metal component 120, the protective film 210, and the protective layer 130 are removed in sequence. Of course, the protective film 210 can also be removed last, which is not specifically limited here.

[0166] Cut the dielectric layer corresponding to the position of the metal component 120 to form a through groove 211. A third plastic package body 212 covering the intermediary layer is formed on the second carrier 103. The third plastic package body 212 fills the through groove 211; the through groove 211 can be used as a cutting path to improve cutting accuracy. The third plastic package body 212 is formed by injection molding or printing technology. It is easy to understand that when cutting, the second carrier 103 is removed, and the third plastic package body 212 in the through groove 211 is cut to avoid cutting the intermediary layer 110. The materials of the third plastic package body 212 and the surface of the intermediary layer 110 are different. The cutting machine can recognize the different grayscales of the two materials, which is conducive to improving the recognition of the cutting machine, thereby improving cutting accuracy and cutting efficiency.

[0167] It should be noted that in conventional reconstructed wafers, the product surface is completely covered by the plastic package, and there is no marking of the cutting line, so the cutting machine cannot accurately locate the cutting line. However, this embodiment facilitates the cutting machine to identify the cutting line.

[0168] Combine Figure 32 Optionally, the step of forming the wiring layer 155 on the seed layer 152 includes:

[0169] A first wiring layer 201 is formed on the seed layer 152; the first wiring layer 201 includes electrical connection terminals 213 extending beyond the interposer 110. After forming the through-slots 211, electrical connectors 203 are formed on the dielectric layer; the connectors 203 are connected to the electrical connection terminals 213. The pre-formed electrical connection terminals 213 serve as a seed layer for the electroplating of the connectors 203, improving electroplating efficiency and facilitating the formation of the connectors 203. This eliminates the need for forming an additional seed layer for electroplating the connectors 203, simplifying the process and improving efficiency.

[0170] The third plastic package 212 encapsulates the electrical connector 203 and the interposer 110. A second wiring layer 202 is formed on the side of the interposer 110 away from the second carrier 103. The second wiring layer 202 is electrically connected to the electrical connector 203. The formation of the second wiring layer 202 and subsequent processes can be seen in steps S9 to S12 above. Steps S3 to S8 can be performed optionally and are not specifically limited here.

[0171] Of course, the electrical connection column 203 can also be formed by laser grooving and then filling with metal after the third plastic package body 212 is formed, which is not specifically limited here.

[0172] It should be noted that the electrical connector 203 can be fabricated during the formation of the first wiring layer 201, including but not limited to electroplating, mounting, or laser grooving followed by metal filling. That is, the electrical connector 203 is already formed on the interposer 110 product before the first carrier 101 is removed and the second carrier 103 is mounted. This way, when the protective film 210 is applied, it covers the interposer 110 and the electrical connector 203, protecting them and preventing damage to the connector 203 and interposer 110 during the removal of the metal component 120.

[0173] The 2.5D substrate manufacturing method and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including:

[0174] First, a protective layer 130 is formed to cover the interposer 110, and then the interposer 110 is ground and etched. This prevents the sidewalls of the interposer 110 from being corroded during the etching process, thereby improving the bonding strength between the interposer 110 and the dielectric layer. Furthermore, the formation of a first groove 121 on the metal component 120 facilitates the subsequent formation of the seed layer 152, strengthens the bonding strength between the wiring layer 155 and the dielectric layer, and enhances the packaging quality. In this embodiment, the provision of an active wiring layer 112 on the interposer 110 shortens the transmission path, improves transmission efficiency, reduces transmission loss, and achieves a more compact structure, thereby achieving high-density integrated packaging.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a 2.5D substrate, characterized in that: include: A first carrier is provided on which metal components and an interposer are mounted; wherein each of the metal components is arranged around the periphery of one of the interposers; and a metal column is provided in the interposer; forming a protective layer covering the metal component and the interposer on the first carrier; forming a first groove on the metal component; grinding the intermediate layer and the protective layer so that the surfaces of the intermediate layer and the protective layer are lower than the surface of the metal component; forming a first dielectric layer having a first opening on the surfaces of the interposer and the protective layer; wherein the first opening exposes the metal pillar; forming a seed layer on the first dielectric layer; the seed layer extends to the surface of the metal component and fills the first groove; the thickness of the seed layer is equal to the depth of the first groove; forming a wiring layer on the seed layer; removing the seed layer outside the first opening; A metal layer and a bump are formed; wherein the metal layer and the wiring layer are electrically connected.

2. The 2.5D substrate manufacturing method according to claim 1, characterized in that: The step of grinding the intermediate layer and the protective layer includes: Grinding the interposer, the metal pillar, and the protective layer to the same plane; The interposer is etched so that a surface of the interposer is lower than a surface of the protection layer and a surface of the metal pillar.

3. The 2.5D substrate manufacturing method according to claim 2, characterized in that: After the step of etching the interposer, the method further includes: An insulating layer is formed on the surface of the interposer; the surface of the insulating layer is flush with the surface of the protection layer and the surface of the metal pillar respectively.

4. The 2.5D substrate manufacturing method according to claim 1, characterized in that: In the step of forming a protective layer covering the metal component and the interposer on the first carrier: The protection layer is formed between the interposer and the metal component, and between adjacent metal components; In the step of forming a seed layer on the first dielectric layer: The seed layer is formed by depositing metal by sputtering; the seed layer covers the entire surface of the first dielectric layer and the surface of the metal component.

5. The 2.5D substrate manufacturing method according to claim 1, characterized in that: The step of forming a wiring layer on the seed layer comprises: forming a photoresist on the seed layer, covering the photoresist with a photomask, and forming a second opening on the photoresist through an exposure and development process, wherein a portion of the seed layer is exposed through the second opening; Using an electroplating process, electroplating metal in the second opening on the seed layer to form a wiring layer; wherein the seed layer serves as an electroplating lead, and the metal component serves as a clamping portion of an electroplating jig; removing the photoresist; The seed layer that does not overlap with the wiring layer is removed.

6. The 2.5D substrate manufacturing method according to claim 1, characterized in that: After the steps of forming the metal layer and the bump, the method further includes: mounting a chip on the bump; Plastic-sealing the chip to form a second plastic-sealed body; Cutting and separating into individual products; wherein the cutting position is located on the intermediate layer or on the protective layer.

7. The method for manufacturing a 2.5D substrate according to claim 1, wherein: In the step of providing a first carrier having a metal component and an interposer mounted thereon: forming an active wiring layer on the interposer; A protective glue is provided on a side of the active wiring layer away from the interposer; The interposer and the metal component are mounted on the first carrier; the protective adhesive is flush with the metal component.

8. The method for manufacturing a 2.5D substrate according to claim 7, wherein: The step of mounting the interposer and the metal component on the first carrier further includes: forming an electrical connection post on the first carrier; the electrical connection post is located between the metal component and the interposer; the electrical connection post is flush with the metal component; The side of the interposer provided with the active wiring layer faces away from the first carrier; The step of forming a first groove on the metal component further includes: The first carrier is removed, and the first groove is formed on a side of the metal component away from the active wiring layer.

9. The method for manufacturing a 2.5D substrate according to claim 7, wherein: After the step of mounting the interposer and the metal component on the first carrier, the method further includes: A fourth opening is formed on the protective glue by exposure and development; and a redistribution layer is formed in the fourth opening; and the redistribution layer is electrically connected to the active wiring layer.

10. The method for manufacturing a 2.5D substrate according to claim 7, wherein: The step of providing a protective glue on a side of the active wiring layer away from the interposer further comprises: A copper column electrically connected to the active wiring layer is formed on a side of the active wiring layer away from the interposer; The protective glue covers the copper column; A first wiring layer is formed that is electrically connected to the copper pillar.

11. The method for manufacturing a 2.5D substrate according to claim 1, wherein: In the step of providing a first carrier having a metal component and an interposer mounted thereon: forming an active wiring layer on the interposer; The side of the interposer provided with the active wiring layer is mounted on the first carrier; The step of forming a first groove on the metal component further includes: The first groove is formed on a side of the metal component facing away from the first carrier.

12. The method for manufacturing a 2.5D substrate according to claim 1, wherein: The step of providing a first carrier having a metal component and an interposer mounted thereon comprises: The first carrier is formed with a metal coating, and the metal coating is provided with electrical connection columns and wiring bumps; Mounting the metal component and the interposer; wherein the interposer is provided with an active wiring layer and electrical connection pads; the active wiring layer is electrically connected to the metal pillars, and the electrical connection pads are electrically connected to the active wiring layer; the electrical connection pads of the interposer are welded to the wiring bumps; and the electrical connection pads are located between the interposer and the metal component; In the step of forming a first groove on the metal component: The first groove is formed on a side of the metal component facing away from the first carrier.

13. The method for manufacturing a 2.5D substrate according to claim 1, wherein: After the steps of forming the metal layer and the bumps, the method further includes: Remove the first carrier and attach the second carrier to the side with the bump; forming a protective film on the side where the first carrier is removed, wherein the protective film covers the interposer; removing the metal component and the protective layer; removing the protective film; cutting the dielectric layer corresponding to the position of the metal component to form a through groove; A third plastic packaging body covering the intermediate layer is formed on the second carrier; the third plastic packaging body fills the through groove; and the through groove serves as a cutting path.

14. The method for manufacturing a 2.5D substrate according to claim 13, wherein: The step of forming a wiring layer on the seed layer comprises: forming a first wiring layer on the seed layer; the first wiring layer including an electrical connection terminal extending outside the interposer; After the step of forming the through groove, the method further includes: forming an electrical connection post on the dielectric layer; the electrical connection post is connected to the electrical connection end; The third plastic package covers the electrical connection column; A second wiring layer is formed on a side of the interposer away from the second carrier; the second wiring layer is electrically connected to the electrical connection pillar.

15. A packaging structure, characterized in that: Prepared by the 2.5D substrate manufacturing method according to any one of claims 1 to 14; the packaging structure comprises: an interposer having metal pillars; a dielectric layer, wherein a wiring layer electrically connected to the metal pillar is provided in the dielectric layer; A seed layer, wherein the seed layer is provided between the wiring layer and the dielectric layer; The bump protrudes from the dielectric layer and is electrically connected to the wiring layer.

16. The packaging structure according to claim 15, wherein: At least one end of the metal column is exposed from the surface of the intermediary layer; the insulating layer covers the surface of the intermediary layer and is flush with the surface of the metal column.

17. The packaging structure according to claim 15, wherein: The outer periphery of the intermediary layer is covered with a protective layer, and two surfaces of the protective layer are flush with both end surfaces of the metal column respectively.

18. The packaging structure according to claim 15, wherein: An active wiring layer electrically connected to the metal pillar is provided on the interposer, the wiring layer comprising a first wiring layer and a second wiring layer provided on both sides of the interposer, the first wiring layer and the active wiring layer being electrically connected, and the first wiring layer and the second wiring layer being electrically connected to the bumps respectively; The seed layer is electrically connected to the second wiring layer, and the seed layer is located on a side of the second wiring layer close to the interposer.

19. The packaging structure according to claim 18, wherein: A protective adhesive is provided between the first wiring layer and the active wiring layer, and a copper pillar is provided in the protective adhesive; one end of the copper pillar is electrically connected to the first wiring layer, and the other end is electrically connected to the active wiring layer; Alternatively, the first wiring layer includes a redistribution layer, and the redistribution layer is directly connected to the active wiring layer.

20. The packaging structure according to claim 18, wherein: It also includes a chip; the bumps on at least one side of the intermediary layer are electrically connected to the chip, and the chip is covered with a second plastic package.

21. The packaging structure according to claim 18, wherein: The intermediary layer is provided with electrical connection points connected to the active wiring layer; the first wiring layer or the second wiring layer is provided with wiring bumps, and the electrical connection points are connected to the wiring bumps.

22. The packaging structure according to any one of claims 15 to 21, characterized in that: It also includes an electrical connection column, the wiring layer includes a first wiring layer and a second wiring layer arranged on both sides of the intermediate layer, one end of the electrical connection column is electrically connected to the first wiring layer, and the other end is electrically connected to the second wiring layer.

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