VCSEL chip preparation method and VCSEL chip

Abstract

The invention relates to the technical field of semiconductor lasers, in particular to a preparation method of a VCSEL chip and the VCSEL chip. The preparation method comprises the following steps: manufacturing an epitaxial wafer, and obtaining the required epitaxial wafer through an epitaxial growth technology; masks are prepared, corresponding patterns are manufactured on the substrate through the photoresist, and a first mask and a second mask are obtained; etching the pattern on the first mask to the epitaxial wafer in an etching manner to obtain a first table surface; the VCSEL after the first table top is obtained is put into wet oxidation equipment to be oxidized; etching the pattern on the second mask to a VCSEL (Vertical Cavity Surface Emitting Laser) in an etching manner to obtain a second table surface; the VCSEL is provided with an N-type electrode through evaporation, and is provided with a P-type electrode and P / N ohmic contact through sputtering. According to the embodiment of the invention, the pattern is etched through the pattern structure on the mask to obtain the P-type DBR layer, thereby obtaining a step structure, reducing the overall equivalent resistance of the VCSEL, improving the heat dissipation, and improving the heat stability and high-speed modulation performance of a chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and specifically, to a method for manufacturing a VCSEL chip and a VCSEL chip. Background Art

[0002] A VCSEL is a semiconductor laser structure in which an optical resonator is formed in a direction perpendicular to the semiconductor epitaxial wafer, and the emitted laser beam is perpendicular to the surface of the substrate.

[0003] Vertical cavity surface emitting lasers often use GaAs (gallium arsenide) material as the substrate. However, as is well known, the heat dissipation performance of GaAs material is not good, and the refractive index of GaAs material will change with the increase of temperature. Therefore, when the chip works at high temperature, the performance of the device will decline.

[0004] In the process of realizing the present invention, the inventors of the present invention found that: at present, high-speed modifiable VCSELs are the focus of the current industry. At present, VCSELs with a 25 GHz bandwidth have been mass-produced, and there are many challenges in further improving the modulation speed of VCSELs. If you want to further increase the modulation bandwidth of VCSELs, mainly consider two aspects: on the one hand, it is necessary to further reduce the memory of such chips, and it is difficult to further reduce the internal resistance of such chips using conventional designs to improve the modulation bandwidth; on the other hand, it is necessary to further improve the heat dissipation performance of such devices. And the current VCSEL chip structure cannot solve the problems of excessive internal resistance and poor heat dissipation effect well at the same time, which restricts the development of high-speed modifiable VCSELs. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a VCSEL chip, a semiconductor laser of the VCSEL chip, and a control method that overcome the above problems or at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present invention provides a method for manufacturing a VCSEL chip, the steps including: Fabricate an epitaxial wafer to obtain the required epitaxial wafer through epitaxial growth technology; Prepare a mask, make a corresponding pattern on the substrate with photoresist to obtain a first mask and a second mask; By means of etching, etch the pattern on the first mask onto the VCSEL to obtain a first mesa; Put the VCSEL after obtaining the first mesa into a wet oxidation device for oxidation; By means of etching, etch the pattern on the second mask onto the VCSEL to obtain a second mesa; The N-type electrode of the VCSEL is set by evaporation plating, and the P-type electrode and the P / N ohmic contact are set by sputtering; Among them, the first mask is used to fabricate a special-shaped mask through a two-photon polymerization 3D printing process. The cross-section of the special-shaped mask is a convex structure that gradually decreases from the bottom to the top, and the side surface of the convex structure is evenly provided with bosses from the bottom to the top in sequence.

[0007] Furthermore, the first mask is used to fabricate a special-shaped mask through a two-photon polymerization 3D printing process. The specific steps include: On the wafer, a positive photoresist is printed into a soft mask by using a 3D printing process; Then, a convex structure with a multi-layer structure is printed above the soft mask. The convex structures are stacked in sequence from bottom to top, and the cross-sectional area of the convex structure gradually becomes smaller from the bottom to the top; Among them, bosses are arranged on the outer surface of the convex structure, and the bosses are set to correspond to each layer in the convex structure one by one in sequence.

[0008] Furthermore, the height of the raised bosses is controlled to be 1 - 1.5 μm.

[0009] Furthermore, the heights of the layers of the convex structure are the same, and the height of each layer of the convex structure is controlled to be 1 - 1.5 μm.

[0010] Furthermore, the boss includes a first side surface and a second side surface. The first side surface is parallel to the wafer, and the second side surface is perpendicular to the wafer.

[0011] Furthermore, the distance between the second side surfaces of adjacent bosses is controlled to be 0.1 - 1 μm.

[0012] Furthermore, after obtaining the first mesa, the accuracy of the bosses on the first mesa is also measured by a profilometer; using a profilometer to measure is to randomly select the etching depths of four to six points on the surface of the first mesa to determine the accuracy of etching.

[0013] Furthermore, the growth process of the epitaxial wafer adopts metal-organic chemical vapor deposition or molecular beam epitaxy.

[0014] Furthermore, the N-type electrode is made of an AuGeNi alloy plating material with a thickness of 500 Å; the P-type electrode is Ti / Au with a thickness of 500 Å / 3000 Å.

[0015] In a second aspect, a VCSEL chip is disclosed, which is prepared by using the preparation method of any one of the above-mentioned VCSEL chip preparation methods.

[0016] The beneficial effects of the above technical solutions provided by the embodiments of the present invention at least include: In an embodiment of the present invention, a method for fabricating a VCSEL chip is provided. In order to make the surface of the P-type DBR layer have a stepped structure, in the embodiment, by designing the pattern structure on the mask and etching the pattern into the P-type DBR layer through an etching process, a stepped structure is obtained.

[0017] For the fabricated VCSEL chip, by setting the surface of the P-type DBR layer of the VCSEL to have a stepped structure, and each step of the stepped structure respectively corresponding to each layer in the P-type DBR layer, the overall performance of the P-type DBR layer is effectively improved. As a result, the overall equivalent resistance of the VCSEL can be effectively reduced, and at the same time, the heat dissipation performance is improved, thereby realizing the improvement of the thermal stability and high-speed modulation performance of the chip.

[0018] Other features and advantages of the present invention will be described in the following specification, and in part, will become apparent from the specification or be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the written specification and the drawings.

[0019] The technical solution of the present invention will be further described in detail below through the drawings and embodiments. Description of the Drawings

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally denoted by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0021] Figure 1 is a schematic structural diagram of a traditional VCSEL chip; Figure 2 is a schematic diagram of the VCSEL chip according to the first embodiment of the present invention; Figure 3 is the present invention Figure 2 schematic diagram from another perspective; Figure 4 is the present invention Figure 4 partial enlarged view of D; Figure 5 is the LIV curve diagram of a traditional VCSEL chip; Figure 6 is the LIV curve diagram of the VCSEL chip of this embodiment; Figure 7 is a schematic diagram of the first mask according to the first embodiment of the present invention; Figure 8 is the present invention Figure 7A partial enlarged view of; Figure 9 The present invention Figure 7 A schematic diagram from another perspective; Figure 10 The present invention Figure 9 B is a partial enlarged view; Figure 11 is a schematic diagram of a first mask according to a second embodiment of the present invention; Figure 12 The present invention Figure 11 A partial enlarged view of C; Figure 13 is a flow chart of a method for preparing a VCSEL chip of the present invention; Figure 14 is a schematic diagram of a first mask according to a third embodiment of the present invention; Figure 15 The present invention Figure 14 Schematic diagram from another perspective; Figure 16 The present invention Figure 15 A partial enlarged view of F.

[0022] Indicated in the figure: 10. P-type DBR part; 11. Active part; 12. N-type DBR part; 13. Substrate; 14. P electrode; 20. First mask; 21. Pattern layer; 22. Substrate; 210. Protruding structure; 211. Boss. DETAILED DESCRIPTION

[0023] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0024] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0025] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0026] In addition, terms such as "first", "second", etc. are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. In the description of the present invention, the meaning of "a plurality" is more than two, unless otherwise specifically defined.

[0027] In this application, unless otherwise clearly defined and limited, terms such as "installed", "connected", "coupled", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] In this application, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0029] Example: A VCSEL is a semiconductor laser structure that forms an optical resonator in a direction perpendicular to the semiconductor epitaxial wafer and emits a laser beam perpendicular to the substrate surface. It is widely used in fields such as consumer electronics, military, and medical, such as 3D sensing, AR / VR, robotics, lidar, consumer electronics, intelligent manufacturing, the Internet of Things, data centers, etc. Specific applications include intelligent driving, video surveillance, lidar, machine vision, gesture recognition, face recognition, etc.

[0030] The DBR serves as the mirror of the resonant cavity and is formed by the alternating epitaxial growth of high- and low-refractive-index dielectrics or semiconductor materials. The optical thickness of each layer of material is 1 / 4 of the laser wavelength. Using the principles of thin-film interference and reflection phase change, when light passes through a thin film, it undergoes two reflections at the upper and lower surfaces. The thickness of the thin film affects the optical path difference between the two reflections. If the thickness of the thin film is controlled to be an integer multiple of (1 / 4 + N) wavelengths, the optical path difference between the two reflections is (1 / 2 + 2N), and the optical path difference corresponds to a 180° phase change. Therefore, the two reflections at the upper and lower interfaces are finally in phase, and the superposition enhances, that is, the overall reflection coefficient is increased. For the alternating epitaxial growth of high- and low-refractive-index dielectrics or semiconductor materials, when light travels from an optically denser medium to an optically thinner medium, a 180° phase change also occurs at the interface. Therefore, the light passing through each layer of DBR will increase the reflection coefficient by a certain amount. For the DBR on the light-emitting surface, a smaller reflection coefficient is obtained by appropriately reducing the number of its layers to ensure that the laser can pass through and emit.

[0031] The entire process of the current VCSEL chip can be divided into two major parts: epitaxial growth and chip manufacturing. Among them, the epitaxial process is crucial, and the quality of the epitaxial structure basically determines the performance of the VCSEL device. Currently, major manufacturers generally use the MOCVD method for growth, with a total thickness of about 8 - 10 μm and a total of more than 200 layers in the whole structure. Generally, each single layer is grown first, and after determining the quality, composition, carrier concentration, growth rate, etc. of the single layer through various testing equipment, the entire structure is further epitaxially grown. Changes in the parameters of each layer, such as the number of DBR layers, doping concentration, or changes in the heterojunction structure of the active region, will have a relatively large impact on the overall characteristics of the VCSEL.

[0032] Refer to the appendix Figure 1 As shown, generally, a VCSEL includes a substrate 13, a first reflective portion, an active portion, a second reflective portion, and electrodes.

[0033] The substrate 13 allows the growth of each layer that makes up the VCSEL. The substrate 13 provides a space for each layer to grow, obtains power from the electrode to be arranged at the lower end of the substrate 13, and transmits it to the first reflective portion. Correspondingly, the laser (light) can be output from the active portion using the power recognized to each reflective portion. Among them, the substrate 13 can be made of GaAs, but it is not necessarily limited to this, and it can also be made of GaN, SiC, ZnC, Si, or sapphire, etc.

[0034] The first reflective portion can be implemented as an n-type semiconductor layer coated with an n-type coating agent and can be composed of any one of semiconductor materials containing Al, such as AlGaAs, AlGaInP, and AlInP. The first reflective portion can be composed of at least one n-type semiconductor layer or can also include layers forming a distributed Bragg reflector or “distributed Bragg reflector” (DBR). The first reflective portion can be formed on the substrate by any one of methods such as Epitaxy chemical vapor deposition method (CVD), sputtering, metalorganic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxy (HVPE).

[0035] The active portion is the layer where electrons generated in the first reflective portion meet and recombine with holes generated in the second reflective portion, and light is generated by the recombination of electrons and holes. The active portion can include a single quantum well (Single Quantum Well, SQW) or a multiple quantum well (Multiple Quantum Well, MQW) structure having multiple quantum well layers. If a multiple quantum well structure is included, the cavity layer has a structure in which well layers (at micro-conduction) and barrier layers (at micro-conduction) with different energy bands are alternately stacked one or more times.

[0036] The well layer / barrier layer of the active portion can be composed of AlGaInP / AlGaInP, AlGaInP / AlInP, AlGaAs / AlGaAs, AlGaAs / GaAs, or AlGaAs / InGaAs, etc.

[0037] An oxide film layer is formed on the top of the active portion.

[0038] The oxide film layer undergoes an oxidation process to form an oxidized portion of a certain length, and the diameter of the opening is determined according to the length of the oxidized portion. The oxide film layer is composed of aluminum (Al) with a concentration higher than that of the first and second reflective portions. The higher the aluminum concentration, the greater the oxidation rate. As the oxide film layer is implemented with a relatively higher aluminum concentration than the positive reflective portion, selective oxidation can be performed during subsequent oxidation. For example, the oxide film layer can be implemented with 98% AlGaAs, while each reflective portion can be implemented with 92% AlGaAs.

[0039] The second reflective portion can be composed of a semiconductor material coated with a p-type coating agent, or can be composed of any one of semiconductor materials containing Al, such as AlGaAs, AlGaInP, and AlInP, or can be composed of GaP. The second reflective portion can be composed of at least one layer or can also include layers forming a DBR. The second reflective portion can be formed on the cavity layer by any one of methods such as Epitaxy chemical vapor deposition method (CVD), sputtering, metalorganic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxy (HVPE).

[0040] An electrode is formed on the second reflective portion to supply power to the second reflective portion.

[0041] The inventors of the present application continued to study how to effectively solve the problems that the VCSEL chip structure cannot simultaneously solve the problems of excessive internal resistance and poor heat dissipation. The inventors' research included at least: how to change the overall internal resistance and heat dissipation effect of the VCSEL by changing the number of DBR layers, doping concentration, or the heterojunction structure of the active region, and by changing the structure of the DBR layer. After a large number of repeated studies, the inventors proposed the VCSEL chip and laser of the present application.

[0042] Refer to the attached Figure 2 As shown, in the embodiment of the present invention, a VCSEL chip is provided. The VCSEL chip is used for a semiconductor laser and includes: An N electrode, an N-type DBR portion 12, an active portion 11, a P-type DBR portion 10, and a P electrode 14, and the N electrode, the N-type DBR portion 12, the active portion 11, the P-type DBR portion 10, and the P electrode 14 are stacked in sequence from bottom to top; Wherein, the P-type DBR portion 10 is arranged as a multi-layer structure stacked in sequence, and the lateral area of each layer of the multi-layer structure gradually becomes smaller from bottom to top; And, between adjacent layers of the multi-layer structure, it is arranged that: the edge distance of the upper end surface of the DBR layer in the lower position has a distance from the edge of the lower end surface of the DBR layer in the upper position.

[0043] It can be understood that in order to solve the problems of excessive internal resistance and poor heat dissipation existing in the current high-speed modifiable VCSEL, the embodiment is to set the cross-section of the P-type DBR portion 10 to a structure that gradually becomes smaller from bottom to top, and at the same time set a stepped structure on the outer surface of the P-type DBR portion 10. By the stepped structure, the outer surface area of the P-type DBR portion 10 is effectively increased, thereby effectively solving the problem of poor heat dissipation. At the same time, the stepped P-type DBR portion 10 can effectively reduce the overall equivalent series resistance of the chip, that is, reduce the internal resistance of the VCSEL chip, thereby realizing the improvement of the thermal stability and high-speed modulation performance of the chip.

[0044] In the embodiment, the active portion 11 is specifically an undoped active region, and the active portion 11 includes a light-emitting quantum well and its barrier layer. Both the N-type DBR portion 12 and the P-type DBR portion 10 are composed of two different component materials (such as Al0.1GaAs and Al0.9GaAs), and the two different component materials are arranged alternately layer by layer. Because of the use of two different component materials, they have different refractive indexes.

[0045] Refer to the attached Figure 3 and4 As shown, specifically in the embodiment, the step structure here can be considered as follows: between adjacent layers of the multi-layer structure, it is set that the distance from the upper end face edge of the lower DBR layer to the lower end face edge of the upper DBR layer. The step structure can also be considered as: the lower DBR layer protrudes a part compared to the upper DBR layer, thus forming a staggered stepped structure.

[0046] At the same time, it can also be considered that the adjacent two layers from bottom to top are set such that a part of the upper end face of the lower DBR layer is exposed outside, that is, the lower DBR layer protrudes a part relative to the upper DBR layer arranged above this DBR layer, so that the outer surface of the P-type DBR part 10 is provided with a step structure.

[0047] Here, the lower position refers to: in two adjacent layers of the multi-layer structure, the layer located on the lower side is the lower position; and the upper position refers to: in two adjacent layers of the multi-layer structure, the layer located on the upper side is the upper position. For example, in an embodiment, for two stacked DBR layers, the position of the lower layer is called the lower position, and the position of the upper layer is called the upper position.

[0048] It can be understood that the VCSEL chip of this embodiment is generally the same as the existing VCSEL chip structure, and it can also be understood that this embodiment is an improvement based on the existing VCSEL chip. The difference of the VCSEL chip of this embodiment is that: by setting a stepped structure on the outer surface of the P-type DBR part 10, to solve the defects existing in the existing high-speed modifiable VCSEL chip, effectively reduce the internal resistance of the VCSEL chip, and at the same time, it can also increase the heat dissipation effect, effectively ensuring the thermal stability and high-speed modulation performance of the VCSEL chip.

[0049] Figure 5 is the LIV curve graph of the traditional VCSEL chip; Figure 6 is the LIV curve graph of the VCSEL chip of this embodiment. Here, the LIV curve graph refers to the curve relationship graph between the laser current (I), voltage (V) and optical output power (P). Through the LIV curve graph, the output power situation of the laser at different working points can be understood, and then its performance can be evaluated.

[0050] Among them, Figure 5 in the VCSEL laser, the number of layers of the P-type DBR part 10 is 32 layers, Width = 35 and Width0 = 20, which are all the same as Figure 6 in the VCSEL laser, the number of layers of the P-type DBR part 10 is 32 layers, Width = 35 and Width0 = 20, and the step of the P-type DBR part 10 is L = 1um.

[0051] Through the relationship between the output voltage and the output current, it can be obtained that, attachedFigure 5 The internal resistance R of the VCSEL chip is 182 Ω, Figure 6 The internal resistance R of the VCSEL chip is 164 Ω. It can be seen that by designing a stepped structure on the surface of the P-type DBR part 10, the internal resistance of the VCSEL chip can be effectively reduced by 10% under the condition that other designs are basically the same, thereby increasing the response speed and bandwidth of the device.

[0052] As described above, by setting the outer surface of the P-type DBR part 10 as a stepped structure, the overall internal resistance of the VCSEL is reduced. After the internal resistance is reduced, the heat generated by the internal resistance can be reduced, thereby reducing the heat to a certain extent.

[0053] Refer to the appendix Figure 4 As shown, in a further embodiment, the distance L is controlled to be 0.8 - 2 μm. At the same time, the height H of the stepped protrusion can also be controlled, and the control height is 0.8 - 2 μm.

[0054] By appropriately setting a difference between the cross-sections of two adjacent layers in the multi-layer P-type DBR part 10, where there is a certain difference in size between two adjacent layers, by effectively controlling this difference, it is ensured that the internal resistance of the vcsel chip can be effectively reduced while increasing the heat dissipation effect of the vcsel chip.

[0055] In some embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower end surface of the upper layer in two adjacent layers of the multi-layer P-type DBR part 10 is controlled to be 1 μm; in some other embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower end surface of the upper layer in two adjacent layers of the multi-layer P-type DBR part 10 is controlled to be 1.5 μm; in still some other embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower end surface of the upper layer in two adjacent layers of the multi-layer P-type DBR part 10 is controlled to be 2 μm.

[0056] Refer to the appendix Figure 2 As shown, in a further embodiment, the cross-sectional shape of the P-type DBR part 10 includes a circle, an ellipse or a rectangle.

[0057] That is to say, according to the actual situation, the cross-section of the P-type DBR part 10 can be etched into different shapes. In this example, the cross-section of the P-type DBR part 10 is etched into a circle through the first mask 20. Of course, it can also be etched into other shapes, such as an ellipse or a rectangle, etc.

[0058] In a further embodiment, the number of layers of the P-type DBR part 10 is 16 - 40 layers.

[0059] That is to say, the actual number of layers of the P-type DBR part 10 can be set according to actual requirements. In actual use, in some embodiments, the actual number of layers of the P-type DBR part 10 is set to 32 layers, that is, a structure of 16 pairs; in some other embodiments, the actual number of layers of the P-type DBR part 10 is set to 16 layers, that is, a structure of 8 pairs; in still some other embodiments, the actual number of layers of the P-type DBR part 10 is set to 40 layers, that is, a structure of 20 pairs. Since the number of layers of the P-type DBR part 10 may also affect the overall VCSEL performance, it is necessary to set the actual number of layers according to the actual situation.

[0060] In a further embodiment, the thickness H of each layer of the P-type DBR part 10 is controlled to be 1 - 1.5 um.

[0061] In some embodiments, the thickness of each layer of the P-type DBR part 10 is controlled to be 1.2 um. When the P-type DBR part 10 has a 32-layer structure, the total thickness is 38.4 um; in some other embodiments, the thickness of each layer of the P-type DBR part 10 is controlled to be 0.8 um. When the P-type DBR part 10 has a 40-layer structure, the total thickness is 32 um; when the thickness of each layer of the P-type DBR part 10 is controlled to be 1.6 um, and the P-type DBR part 10 has a 16-layer structure, the total thickness is 25.6 um.

[0062] In a further embodiment, the P-type DBR part 10 is made of materials Al0.1GaAs and Al0.9GaAs.

[0063] In an embodiment, the P-type DBR part 10 is composed of two materials with different components (Al0.1GaAs and Al0.9GaAs), and the two materials with different components are arranged alternately layer by layer to obtain the P-type DBR part 10.

[0064] In a further embodiment, the N-type electrode is a AuGeNi alloy plating material with a thickness of 500 Å; the P-type electrode is Ti / Au with a thickness of 500 Å / 3000 Å.

[0065] Based on the same inventive concept, a VCSEL laser is also disclosed, including: the VCSEL chip described in any one of the above.

[0066] For the specific examples and descriptions of the beneficial effects of the VCSEL laser in this embodiment, reference can be made to the description of the above VCSEL chip, which will not be elaborated here.

[0067] Based on the same inventive concept, please refer to the appendix Figure 13 , and a method for manufacturing a VCSEL chip is also disclosed, and the steps include: Step S001: Fabricate an epitaxial wafer, and obtain the required epitaxial wafer through epitaxial growth technology.

[0068] Embodiment: When fabricating a VCSEL chip, it is formed by depositing a complex multi-layer film structure on a substrate 13 through a metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process.

[0069] The growth on the substrate 13 is a key step in the entire process, which directly determines the quality and performance of the device. Usually, the substrate 13 is gallium arsenide. In some embodiments, the steps are to alternately grow GaAs and AlAs on the substrate 13, and the alternating growth layers finally form a Bragg reflector. Since GaAs and AlAs have significantly different refractive indices, but their lattice constants are basically the same, many layers can be alternately grown without generating dislocations, which is why a high-reflectivity mirror effect can be achieved. During the growth process, parameters such as growth rate, temperature, and pressure need to be controlled to obtain a high-quality epitaxial layer.

[0070] Epitaxial growth: Place the cut silicon wafer in a high-temperature furnace, and grow a semiconductor material with a specific energy level structure on the epitaxial layer through chemical vapor deposition to obtain an epitaxial wafer.

[0071] Embodiment: Before proceeding to the next process, it is also necessary to clean the epitaxial wafer and detect the cleanliness of the epitaxial wafer to prevent foreign objects from affecting other processes and thus causing problems with defective products.

[0072] The specific steps include: cleaning the epitaxial wafer with acetone and isopropyl alcohol chemical reagents for 5 minutes in sequence, then cleaning with deionized water in sequence, and finally spin-drying. Then, check the surface of the cleaned and dried epitaxial wafer under a microscope, specifically check for foreign objects, dust, contamination, color patterns, water stains, etc. To ensure the cleanliness of the epitaxial wafer, prevent it from affecting the subsequent process steps, and reduce the occurrence of defective products.

[0073] Step S002: Prepare a mask, make a corresponding pattern of photoresist on the substrate to obtain a first mask 20 and a second mask.

[0074] In the embodiment, except that the structure of the first mesa is different from that of the existing VCSEL chip, the structures of the second mesa and the electrode are the same as those of the existing VCSEL chip structure. That is, during lithography, the etching process of the first mesa is different from the existing etching process, while the etching processes of the second mesa and the electrode are the same as the traditional etching process.

[0075] In order to obtain a stepped structure on the outer surface of the VCSEL chip, a first mask 20 was prepared in the embodiment. During photolithography, the stepped structure can be etched on the epitaxial wafer through the first mask 20. Since other structures are the same as the traditional structures, the masks required for photolithography in other stages, such as the second mask, can refer to the existing mask manufacturing process. The manufacturing process steps of the first mask 20 are as follows: First Embodiment: Further in the embodiment, the first mask 20 is fabricated by a two-photon polymerization 3D printing process. The specific steps include: On the substrate 22, a positive photoresist is printed into a soft mask by a 3D printing process; A plurality of uniform convex structures 210 are printed above the soft mask, and bosses 211 are printed uniformly on the surface of each convex structure 210 along a direction.

[0076] Refer to the attached Figure 7 As shown, further in the embodiment, the first mask 20, for the photolithography pattern of the VCSEL chip, includes: A substrate 22 and a pattern layer 21, and the pattern layer 21 is provided on one side of the substrate 22; Wherein, a plurality of convex structures 210 are provided on the side surface of the pattern layer 21 away from the substrate 22, and the convex structures 210 are arranged side by side in a straight line direction, and bosses 211 are uniformly provided on the surface of the convex structures 210.

[0077] It can be understood that due to the current structure of the high-speed modifiable VCSEL chip, there are problems such as large internal resistance and poor heat dissipation effect. In order to obtain a P-type DBR part 10 with reduced internal resistance and good heat dissipation effect when performing P-type DBR part 10 photolithography on the VCSEL chip. In the embodiment, a pattern layer 21 is provided above the substrate 22, and a plurality of convex structures 210 are provided on the side surface of the pattern layer 21 away from the substrate 22, and the convex structures 210 are arranged side by side in a straight line direction, and bosses 211 are uniformly provided on the surface of the convex structures 210. In this way, the convex structures 210 of the pattern layer 21 and the bosses 211 on the convex structures 210 can be used to obtain the required structure in the P-type DBR part 10 through an etching technique, so that the VCSEL chip has a better heat dissipation effect and at the same time reduces the internal resistance of the VCSEL chip.

[0078] During real-time operation, when preparing the VCSEL chip, this mask is set on the photolithography machine to perform photolithography on the epitaxial wafer, and the pattern on the pattern layer 21 of this mask can be etched onto the epitaxial wafer to obtain the required shape and pattern, so that the VCSEL chip prepared using this mask can achieve reduced internal resistance and better heat dissipation performance.

[0079] Since a plurality of convex structures 210 are provided on the side surface of the pattern layer 21 of the mask away from the substrate 22, and the convex structures 210 are arranged side by side in a straight line direction, and convex platforms 211 are uniformly provided on the surface of the convex structures 210. During photolithography, the thinner positions on the pattern layer 21 will disappear first, and then other parts will gradually disappear, so that the pattern on the pattern layer 21 is photolithographed onto the epitaxial wafer, and the outer surface of the P-type DBR portion 10 has a stepped shape. The convex structure 210 is configured as a structure that gradually bulges toward the center on both sides.

[0080] Refer to the attached Figure 8 As shown, further in the embodiment, the convex platforms 211 are uniformly arranged in a straight line and connected end to end along the side surface of the convex structure 210.

[0081] It can be understood that the convex platforms 211 are arranged along the edge of the side surface of the convex structure 210 in sequence, and the convex platforms 211 are arranged in an end-to-end manner. That is, by providing the pattern layer 21 on the upper side of the substrate 22, and the pattern layer 21 is provided with a plurality of convex structures 210. During photolithography, since the convex structure 210 is a gradually bulging structure, and the convex platforms 211 are uniformly provided on the convex structure 210, a stepped structure can be effectively formed on the surface of the P-type DBR portion 10 during continuous photolithography. Ensuring the accuracy during photolithography, forming a stepped structure on the surface of the P-type DBR portion 10 can effectively reduce the overall internal resistance of the chip and improve the heat dissipation efficiency.

[0082] Refer to the attached Figure 9 and 10 As shown, further in the embodiment, the protruding height of the convex platform 211 is controlled to be 1 - 1.5 μm.

[0083] It can be understood that the height difference between two side surfaces of two adjacent convex platforms 211 that are respectively parallel to the substrate 22 is 0.8 - 2 μm. In the embodiment, by controlling the protruding height of the convex platform 211, the structural height obtained by the P-type DBR portion 10 during photolithography can be realized. It can also be considered that by controlling the height of the convex platform 211 provided, the height when forming a stepped structure on the surface of the P-type DBR portion 10 during photolithography can be realized.

[0084] In some embodiments, the height of the boss 211 can be set according to the thickness of each layer in the P-type DBR portion 10 obtained by epitaxial wafer growth. For example, when the thickness of each layer in the P-type DBR portion 10 is 1 um, the height of the boss 211 is set to 1 um when manufacturing the boss 211 of the mask; when the thickness of each layer in the P-type DBR portion 10 is 2 um, the height of the boss 211 is set to 2 um when manufacturing the boss 211 of the mask; when the thickness of each layer in the P-type DBR portion 10 is 0.8 um, the height of the boss 211 is set to 0.8 um when manufacturing the boss 211 of the mask.

[0085] Refer to the appendix Figure 10 As shown, in a further embodiment, the boss 211 includes a first side surface, and the first side surface is connected to the substrate 22.

[0086] In an embodiment, in order to ensure the stepped shape of the P-type DBR portion 10 of the VCSEL chip, so that the overall VCSEL chip obtains the required structure, so that the overall internal resistance of the P-type DBR portion 10 can be effectively reduced and the heat dissipation effect will be better. In the embodiment, at least one first side surface is provided on the boss 211, and the first side surface is parallel to the substrate 22.

[0087] In an embodiment, the first side surface can be a flat surface or other flat surfaces. It can be understood that by setting the shape of the first side surface of the boss 211, the required selection can be obtained in the P-type DBR portion 10 during photolithography. For example, in the embodiment, the first side surface is set as a flat surface, and the first side surface is arranged parallel to the substrate 22. During photolithography of the epitaxial wafer, a corresponding flat surface can be obtained on the P-type DBR portion 10.

[0088] In a further embodiment, the distance between the protruding structures 210 is 0 - 1 um.

[0089] It can be understood that the distance between the protruding structures 210 can be considered as the distance between the closest positions between two adjacent protruding structures 210. And this distance can be 0, or the two can be separated by a certain distance.

[0090] In some embodiments, the distance between two adjacent protruding structures 210 is set to 0, that is, the closest positions of the two are in contact with each other; in other embodiments, the distance between two adjacent protruding structures 210 is set to 0.5 um, that is, the closest positions of the two have a certain distance; in still other embodiments, the distance between two adjacent protruding structures 210 is set to 0.8 um, that is, the closest positions of the two have a certain distance.

[0091] Refer to the appendix Figure 11As shown, in a further embodiment, the transverse cross-sectional shape of the convex structure 210 is triangular or trapezoidal.

[0092] It can be understood that the transverse cross-section here can be considered as the cross-section opposite to the end face of the convex structure 210, or it can also be considered that the convex structure 210 is a structure extending in one direction, and the cross-section here is the cross-section perpendicular to the extension direction.

[0093] In one embodiment, the transverse cross-section of the convex structure 210 is set as a triangular structure, and fillets can be provided at the triangular angles. When lithography is performed, the cross-sectional area of the pattern will show a phenomenon of gradually decreasing or an equal-proportion reduction of the triangular cross-section; in another embodiment, the transverse cross-section of the convex structure 210 is set as a trapezoidal structure, and fillets can be provided at the trapezoidal angles. When lithography is performed, the cross-sectional area of the pattern will show a phenomenon of gradually decreasing of the trapezoidal cross-section. Of course, the convex structure 210 can also be designed into other shapes according to the actual chip design requirements, which are not listed one by one here.

[0094] In a further embodiment, the pattern layer 21 is a film layer made of positive photoresist.

[0095] It can be understood that in order to ensure that the P-type DBR part 10 of the VCSEL chip obtains a stepped shape, in the embodiment, the pattern layer 21 is made of positive photoresist. During lithography, since the convex structure 210 on the pattern layer 21 is a gradually convex structure and a boss 211 is provided on the convex structure 210, due to the pattern layer 21 made of positive photoresist during lithography, the pattern gradually disappears, and here the disappearance starts from the part closest to the substrate 22 and gradually proceeds towards the highest part of the boss 211 structure.

[0096] It should be noted that the characteristic of positive photoresist is that after the coating is exposed and developed, the exposed part is dissolved and the unexposed part remains. Therefore, when using positive photoresist for lithography, the photoresist in the exposed part will gradually disappear, while the photoresist in the unexposed part remains to form the required image.

[0097] In a further embodiment, the substrate 22 is a quartz plate.

[0098] Second Embodiment: Referring to the attached Figure 14 As shown, the first mask 20 is fabricated by a two-photon polymerization 3D printing process, and the specific steps include: On the wafer 22, a positive photoresist is printed into a soft mask by a 3D printing process; Next, a convex structure 210 of a multi-layer structure is printed above the soft mask. The convex structures 210 are stacked in sequence from bottom to top, and the cross-sectional area of the convex structure gradually decreases from the bottom to the top. Wherein, a boss 211 is arranged on the outer surface of the convex structure, and the bosses 211 are respectively arranged in one-to-one correspondence with each layer in the convex structure 210.

[0099] Refer to the appendix Figure 14 As shown, in the embodiment, the first mask 20 for lithography pattern of the VCSEL chip includes: A substrate 22 and a pattern layer 21, and the pattern layer 21 is arranged on one side surface of the substrate 22. Wherein, a convex structure 210 is arranged on the outer surface of the pattern layer 21 corresponding to each layer, and the convex structure 210 and the boss 211 are set to have the same height.

[0100] It can be understood that due to the current structure of the high-speed modifiable VCSEL chip, there are problems such as large internal resistance and poor heat dissipation effect. In order to obtain a P-type DBR part 10 with reduced internal resistance and good heat dissipation effect when lithographing the P-type DBR part 10 of the VCSEL chip. In the embodiment, a pattern layer 21 is arranged above the substrate 22, and a convex structure 210 is arranged on the side surface of the pattern layer 21 away from the substrate 22, and bosses 211 are evenly arranged on the surface of the convex structure 210. In this way, the convex structure 210 and the bosses 211 of the pattern layer 21 can obtain the required structure in the P-type DBR part 10 through the etching technology, so that the VCSEL chip has a better heat dissipation effect and at the same time reduces the internal resistance of the VCSEL chip. The specific working process and the etching method are similar to those in the above embodiment and will not be elaborated here.

[0101] Refer to the appendix Figure 15 and 16 As shown, in the further embodiment, the bosses 211 are evenly arranged along the side surface of the convex structure 210 in a straight line and connected end to end in sequence.

[0102] It can be understood that on the side surface of the convex structure 210, the bosses 211 are arranged from the bottom to the top, and the bosses 211 are arranged in an end-to-end arrangement. That is, by arranging a pattern layer 21 on the upper side of the substrate 22, and the pattern layer 21 is provided with a convex structure 210. When lithographing, since the convex structure 210 is a structure with a gradually deformed cross-sectional area and the bosses 211 are evenly arranged on the surface of the convex structure 210, a stepped structure can be effectively formed on the surface of the P-type DBR part 10 during continuous lithography. Ensuring the accuracy during lithography, the stepped structure formed on the surface of the P-type DBR part 10 can effectively reduce the overall internal resistance of the chip and improve the heat dissipation efficiency.

[0103] Referring to the attached Figure 15 and 16 As shown, in a further embodiment, the convex height of the boss 211 and the convex structure is controlled to be 1 - 1.5 um.

[0104] It can be understood that the height difference between two side surfaces of two adjacent bosses 211 of the boss 211, which are respectively parallel to the substrate 22, is 0.8 - 2 um. In the embodiment, by controlling the convex height of the boss 211, the structural height obtained by the P-type DBR portion 10 during lithography can be achieved. It can also be considered that by controlling the height of the boss 211, the height when forming a stepped structure on the surface of the P-type DBR portion 10 during lithography can be achieved.

[0105] Among them, the boss includes a first side surface 2110 and a second side surface 2111. The first side surface 2110 is parallel to the wafer, and the second side surface 2111 is perpendicular to the wafer. The distance l between the two second side surfaces 2111 is 0.1 - 1 um.

[0106] In the embodiment, in order to ensure the stepped shape of the P-type DBR portion 10 of the VCSEL chip, so that the overall VCSEL chip obtains the required structure, so that the overall internal resistance of the P-type DBR portion 10 can be effectively reduced and the heat dissipation effect will be better. In the embodiment, at least one first side surface is provided on the boss 211, and the first side surface is parallel to the substrate 22.

[0107] In the embodiment, the first side surface can be a plane or other planes. It can be understood that by setting the shape of the first side surface of the boss 211, the required selection can be obtained on the P-type DBR portion 10 during lithography. For example, in the embodiment, the first side surface is set as a plane, and the first side surface is arranged parallel to the substrate 22. When lithographing the epitaxial wafer, a corresponding plane can be obtained on the P-type DBR portion 10.

[0108] In some embodiments, the height of the boss 211 can be set according to the thickness of each layer in the P-type DBR portion 10 obtained by epitaxial growth. For example, when the thickness of each layer in the P-type DBR portion 10 is 1 um, when manufacturing the convex structure 210 and the boss 211 of the mask, the height of each layer of the convex structure 210 and the boss 211 is set to 1 um; when the thickness of each layer in the P-type DBR portion 10 is 2 um, when manufacturing the convex structure 210 and the boss 211 of the mask, the height of each layer of the convex structure 210 and the boss 211 is set to 2 um; when the thickness of each layer in the P-type DBR portion 10 is 0.8 um, when manufacturing the convex structure 210 and the boss 211 of the mask, the height of each layer of the convex structure 210 and the boss 211 is set to 0.8 um.

[0109] Further, in the embodiment, the pattern layer 21 is a film layer made of positive photoresist.

[0110] It can be understood that in order to ensure that the P-type DBR part 10 of the VCSEL chip has a stepped shape, in the embodiment, by using positive photoresist to make the pattern layer 21, during photolithography, since the convex structure 210 on the pattern layer 21 is a gradually convex structure, and a boss 211 is provided on the convex structure 210, during photolithography, due to the pattern layer 21 made of positive photoresist, the pattern gradually disappears. Here, the disappearance starts from the part closest to the substrate 22 and gradually proceeds towards the highest part of the boss 211 structure.

[0111] It should be noted that the characteristic of positive photoresist is that after the coating is exposed and developed, the exposed part is dissolved and the unexposed part remains. Therefore, when using positive photoresist for photolithography, the photoresist in the exposed part will gradually disappear, while the photoresist in the unexposed part remains to form the required image.

[0112] Step S003: By means of etching, the pattern on the first mask 20 is etched onto the VCSEL to obtain a first mesa.

[0113] In the embodiment, the etching can be achieved by existing etching process methods, which will not be described in detail here. In the embodiment, the existing etching process is adopted to etch the pattern on the first mask 20 onto the epitaxial wafer, so as to obtain a stepped shape in the P-type DBR part 10.

[0114] Further, in the embodiment, after obtaining the first mesa, the accuracy of the boss 211 on the first mesa is also measured by a profiler. The specific operation is to randomly select the etching depths of four to six points on the surface of the first mesa using the profiler to determine the accuracy of the etching. When selecting, through the etching depths at multiple different positions, it is confirmed whether they meet the range value of the etching depth. If they are all within the etching range value, it is considered accurate.

[0115] S004: The VCSEL after obtaining the first mesa is placed in a wet oxidation device for oxidation.

[0116] In the embodiment, when the VCSEL is subjected to wet oxidation, it is between the first mesa etching and the second mesa etching. Specifically, the VCSEL after etching the first mesa is placed in a wet oxidation device for oxidation. The high-aluminum composition layer in the epitaxial structure of the VCSEL will be oxidized by a large amount of water vapor carried by nitrogen. Then, by controlling the oxidation time and rate, and supplemented with an infrared light source charge-coupled device image sensor (CCD) system, the method of real-time observation is used to achieve the purpose of precisely controlling the oxidation aperture size.

[0117] Step S005: Etch the pattern on the second mask onto the VCSEL by etching to obtain a second mesa.

[0118] In the embodiment, the etching process used includes three parts, including etching to obtain the first mesa, the second mesa, and the conductive layer of the P-type electrode region, etc. In the embodiment, the etching process can refer to the existing etching process and will not be described in detail here.

[0119] Moreover, in the embodiment, the etching process steps and parameters of the first mesa, the second mesa, and the conductive layer of the P-type electrode region are the same, except that photolithography is performed using mask plates with different patterns.

[0120] That is, after etching the second mesa, then etch the conductive layer of the P-type electrode region to complete the etching step.

[0121] S006: Set the N-type electrode on the VCSEL by evaporation plating, and set the P-type electrode and P / N ohmic contact by sputtering.

[0122] In the embodiment, after the etching process, in order to provide circuit transmission and reflection, the VCSEL also needs to set the corresponding electrodes through metal evaporation plating and electroplating processes. Specifically as follows: First, use electron beam evaporation coating to obtain the N-type electrode on the VCSEL. The metal material used for the N-type electrode is AuGeNi alloy plating material, and the thickness of the N-type electrode is 500 Å. Next, flatten the VCSEL plated with the N-type electrode through the BCB planarization process. Then, on the top of the first mesa of the VCSEL, use magnetron sputtering coating to set the P-type electrode. Among them, the metal material used for the P-type electrode is Ti / Au, and the thickness of the P-type electrode is 500 Å / 3000 Å. Finally, put the VCSEL plated with the electrodes into a rapid annealing furnace for rapid annealing to achieve the purpose of alloying, so that the electrodes form good ohmic contact with the semiconductor material and improve the electrical characteristics of the device.

[0123] In the embodiment, after the evaporation plating process, it is also necessary to deposit a silicon dioxide protective layer on the VCSEL. Specifically, silicon nitride (Si3N4) or silicon dioxide (SiO2) is used as the passivation insulating protective layer and the outcoupling window protection and antireflection layer by thin film deposition process. The thickness of the passivation insulating protective layer is generally about 2000 Å; the outcoupling window protection and antireflection layer is generally plated with a thin film with an optical thickness of λ / 4.

[0124] In this application, by setting the surface of the P-type DBR part 10 of the VCSEL into a stepped structure, and each step of the stepped structure corresponding to each layer in the P-type DBR part 10 respectively, the overall performance of the P-type DBR part 10 is effectively improved. As a result, the overall equivalent resistance of the VCSEL can be effectively reduced, and at the same time, the heat dissipation is also improved, thereby achieving the improvement of the thermal stability and high-speed modulation performance of the chip.

[0125] However, in order to obtain the stepped structure on the surface of the P-type DBR part 10, in the embodiment, by designing the pattern structure on the mask and etching the pattern into the P-type DBR part 10 through the etching process, a stepped structure is obtained.

[0126] In the embodiment, each step of the stepped structure corresponds to each layer in the P-type DBR part 10 respectively. For example, the P-type DBR part 10 has a total of 32 layers, the height of each layer is 1 um, and there are also 32 steps. The step height of each step is 1 um. It can also be considered that the steps are formed by gradually shifting the layers in the P-type DBR part 10 from the lower right to the upper right.

[0127] For the specific examples and descriptions of the beneficial effects of the method in this embodiment, reference can be made to the description of the saturable absorber above, and details will not be repeated here.

[0128] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. The present disclosure is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A method for preparing a VCSEL chip, characterized in that the steps Including: Fabricating an epitaxial wafer to obtain the required epitaxial wafer through epitaxial growth technology; Preparing a mask, fabricating corresponding patterns on a substrate with photoresist to obtain a first mask and a second mask; By means of etching, etching the patterns on the first mask onto the VCSEL to obtain a first mesa; Putting the VCSEL after obtaining the first mesa into a wet oxidation device for oxidation; By means of etching, etching the patterns on the second mask onto the VCSEL to obtain a second mesa; Setting an N-type electrode on the VCSEL by evaporation plating, and setting a P-type electrode and a P / N ohmic contact by sputtering; Wherein, the first mask is fabricated into a special-shaped mask by a two-photon polymerization 3D printing process, the cross-section of the special-shaped mask is a convex structure gradually decreasing from the bottom to the top, and the side surface of the convex structure is sequentially and evenly provided with bosses from the bottom to the top.

2. The preparation method according to claim 1, wherein The first mask is fabricated into a special-shaped mask by a two-photon polymerization 3D printing process, and the specific steps include: On a wafer, printing a positive photoresist into a soft mask by a 3D printing process; Then printing a convex structure with a multi-layer structure above the soft mask, the convex structure is sequentially stacked from bottom to top, and the cross-sectional area of the convex structure gradually becomes smaller from the bottom to the top; Wherein, bosses are arranged on the outer surface of the convex structure, and the bosses are set to correspond to each layer in the convex structure one by one in sequence.

3. The preparation method according to claim 2, characterized in that, The height of the protrusion of the boss is controlled to be 1-1.5 um.

4. The preparation method according to claim 2, characterized in that, The heights of the layers of the convex structure are the same, and the heights of the layers of the convex structure are controlled to be 1-1.5 um.

5. The preparation method according to claim 2 or 3, characterized in that, The boss includes a first side surface and a second side surface, the first side surface is parallel to the wafer, and the second side surface is perpendicular to the wafer.

6. The preparation method according to claim 5, wherein The distance between the second side surfaces of adjacent bosses is controlled to be 0.1-1 um.

7. The preparation method according to claim 2, wherein After obtaining the first mesa, the accuracy of the boss on the first mesa is also measured by a profilometer; using a profilometer to measure is to randomly select the etching depths of four to six points on the surface of the first mesa to determine the accuracy of etching.

8. The preparation method according to claim 2, characterized in that, The growth process of the epitaxial wafer adopts metal organic chemical vapor deposition method or molecular beam epitaxy method.

9. The preparation method according to claim 2, wherein The N-type electrode is an AuGeNi alloy plating material with a thickness of 500 Å; the P-type electrode is Ti / Au with a thickness of 500 Å / 3000 Å.

10. A VCSEL chip, characterized in that, Prepared by using the preparation method of the VCSEL chip described in any one of claims 1-9.

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