Power factor correction circuit and vehicle

Abstract

The embodiment of the invention provides a power factor correction circuit and a vehicle. The power factor correction circuit comprises an inductor, a switch module, a capacitor and a control module, the switch module comprises a first switch tube and a second switch tube of the same model, and the switch module further comprises a third switch tube and a fourth switch tube; the control module determines a first duty ratio of a target switch tube according to the polarity of an input alternating voltage, an inductive current and an output voltage, the inductive current is a current instantaneous value passing through an inductor, the output voltage is a voltage at two ends of a capacitor, and the target switch tube comprises a first switch tube or a second switch tube; the control module determines a second duty ratio of the target switching tube according to the equivalent junction capacitance, the output voltage and the inductive current of the switching tube and the switching frequency of the switching tube; and the control module determines a target duty ratio of the target switch tube according to the first duty ratio and the second duty ratio. According to the embodiment of the invention, current distortion can be effectively suppressed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a power factor correction circuit and a vehicle. Background Art

[0002] The totem-pole bridgeless power factor correction (PFC) is an efficient power factor correction circuit, and its core advantage lies in being able to improve the power factor and reduce the harmonic pollution to the power grid. The totem-pole bridgeless PFC utilizes the energy storage and discharge characteristics of the inductor and the fast switching of the switching tubes to convert the input alternating current into an input current close to a sine wave, and makes the phase of the input current basically the same as the phase of the input voltage, thereby improving the power factor.

[0003] Single-cycle control is a commonly used control method for the totem-pole bridgeless PFC. Its working principle is to control the duty cycle of the switch so that the average value of the switching variable in each switching cycle is strictly equal to or proportional to the control reference quantity, so that the input current can be controlled to follow the input voltage waveform to achieve low current distortion and high power factor. The above traditional single-cycle control will cause current distortion when the AC voltage passes through the zero point due to the slow discharge characteristic of the junction capacitance at low current operation, thereby increasing the total harmonic distortion (THD) value of the PFC. Summary of the Invention

[0004] The embodiments of the present application provide a power factor correction circuit and a vehicle, which can effectively suppress current distortion.

[0005] In a first aspect, an embodiment of the present application provides a power factor correction circuit, including an inductor, a switching module, a capacitor, and a control module. The switching module includes a first switching transistor and a second switching transistor of the same model, and the switching module further includes a third switching transistor and a fourth switching transistor. A first end of the inductor is connected to a first end of an AC power supply, a second end of the inductor is connected to a first end of the first switching transistor and a second end of the second switching transistor, a second end of the first switching transistor is connected to a first end of the third switching transistor and a first end of the capacitor, a first end of the second switching transistor is connected to a second end of the fourth switching transistor and a second end of the capacitor, and a second end of the AC power supply is connected to a second end of the third switching transistor and a first end of the fourth switching transistor. The control module determines a first duty cycle of a target switching transistor according to the polarity of an input AC voltage, an inductor current, and an output voltage, where the inductor current is an instantaneous value of the current passing through the inductor, and the output voltage is the voltage across the capacitor. The target switching transistor includes the first switching transistor or the second switching transistor. The control module determines a second duty cycle of the target switching transistor according to the equivalent junction capacitance of the target switching transistor, the output voltage, the inductor current, and the switching frequency of the switching transistor. The control module determines a target duty cycle of the target switching transistor according to the first duty cycle and the second duty cycle.

[0006] In the power factor correction circuit according to the embodiment of the present application, the target duty cycle of the target switching transistor is determined by the first duty cycle and the second duty cycle, where the second duty cycle can be dynamically adjusted according to the equivalent junction capacitance of the switching transistor, the output voltage, the inductor current, and the switching frequency of the switching transistor, so that the target duty cycle of the target switching transistor can be dynamically adjusted, thereby effectively suppressing current distortion, and at the same time, there is no need to adjust parameters to adapt to different working conditions.

[0007] In a possible implementation manner, the third switching transistor is a first diode, and the fourth switching transistor is a second diode. In this implementation manner, directly using diodes for the third switching transistor and the fourth switching transistor does not affect the function of the power factor correction circuit in the embodiment of the present application.

[0008] In a possible implementation manner, the second duty cycle of the target switching transistor is determined according to the following formula:

[0009]

[0010] where d is the second duty cycle, C DS is the equivalent junction capacitance, V out is the output voltage, f S is the switching frequency, and i L is the inductor current.

[0011] In this implementation, the second duty cycle of the target switching transistor can be determined based on the equivalent junction capacitance, output voltage, switching frequency, and inductor current. That is to say, the second duty cycle can be dynamically adjusted according to the magnitudes of the actual output voltage, inductor current, and switching frequency, so as to adapt to different working conditions.

[0012] In a possible implementation, the output voltage is within a first preset limit value, the inductor current is within a second preset limit value, and the switching frequency is within a third preset limit value.

[0013] In this implementation, by limiting the magnitudes of the output voltage, inductor current, and switching frequency, optionally, the above-mentioned first preset limit value, second preset limit value, and third preset limit value are set within the normal operating range of the power factor correction circuit, which can prevent the calculated second duty cycle from being too large and avoid the target duty cycle from being too small.

[0014] In a possible implementation, the target duty cycle of the first switching transistor is determined according to the following formula:

[0015] D′ S1 =D S1 +d

[0016] where D′ S1 is the target duty cycle of the first switching transistor, D S1 is the first duty cycle of the first switching transistor, and d is the second duty cycle. The target duty cycle of the second switching transistor is determined according to the following formula:

[0017] D′ S2 =1 - D′ S1

[0018] where D S2 ′ is the target duty cycle of the second switching transistor, and D S1 ′ is the target duty cycle of the first switching transistor.

[0019] In this implementation, the target duty cycle is determined based on the first duty cycle and the second duty cycle, and the second duty cycle is dynamically adjusted according to the magnitudes of the actual output voltage, inductor current, and switching frequency. The first duty cycle is the duty cycle under traditional single-cycle control. Therefore, the target duty cycle can also be dynamically adjusted, so that the target duty cycle can adapt to different working conditions. In addition, the target duty cycles of the first switching transistor and the second switching transistor are complementary, and the target duty cycle of the second switching transistor can be determined by determining the target duty cycle of the first switching transistor.

[0020] In a possible implementation, when the polarity of the input AC voltage is positive, the first duty cycle of the first switching transistor is determined according to the following formula:

[0021]

[0022] When the polarity of the input AC voltage is negative, the first duty cycle of the first switching tube is determined according to the following formula:

[0023]

[0024] The first duty cycle of the second switching tube is determined according to the following formula:

[0025] D S2 = 1 - D S1

[0026] where i L is the inductor current, G in is the loop calculation result, and V out is the output voltage.

[0027] In this implementation manner, according to the above formula, the first duty cycles of the first switching tube and the second switching tube under single-cycle control can be calculated respectively when the polarity of the input AC voltage is positive and when the polarity of the input AC voltage is negative. Based on this first duty cycle, the target duty cycle is determined so that the target duty cycle can be dynamically adjusted.

[0028] In a possible implementation manner, the control module includes a proportional-integral controller, and the loop calculation result is the output value after the proportional-integral controller operates on the difference between the output voltage and the reference voltage.

[0029] In this implementation manner, the loop calculation result is obtained by calculating through a proportional-integral control circuit, and substituting it into the duty cycle calculation formula under single-cycle control can determine the first duty cycle.

[0030] In a possible implementation manner, the equivalent junction capacitance is also determined according to the following formula:

[0031]

[0032] where i DS is the current passing through the target switching tube. Generally, i DS can be replaced by i L ; C DS is the equivalent junction capacitance, V DS is the voltage across the target switching tube. The first switching tube and the second switching tube have the same model, and the above formula is applicable to both switching tubes at the same time.

[0033] In this implementation manner, the equivalent junction capacitance of the above-mentioned switching transistor can be determined according to the above formula, and then the second duty ratio can be determined by substituting it into the calculation formula of the second duty ratio, and further the target duty ratio that can be dynamically adjusted can be obtained.

[0034] In a second aspect, an embodiment of the present application provides a vehicle, which includes an on-vehicle charger, and the on-vehicle charger includes the power factor correction circuit of the first aspect of the embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the following will briefly introduce the drawings required for the description in the embodiments or the background art. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1a is a schematic structural diagram of a power factor correction circuit provided by an embodiment of the present application;

[0037] Figure 1b is a schematic structural diagram of another power factor correction circuit provided by an embodiment of the present application;

[0038] Figure 2a is a schematic flowchart of a control method based on a power factor correction circuit provided by an embodiment of the present application;

[0039] Figure 2b is a schematic diagram of the working mode structure of a power factor correction circuit provided by an embodiment of the present application;

[0040] Figure 2c is a schematic diagram of the working mode structure of another power factor correction circuit provided by an embodiment of the present application;

[0041] Figure 2d is a schematic diagram of the working mode structure of yet another power factor correction circuit provided by an embodiment of the present application;

[0042] Figure 2e is a schematic waveform diagram provided by an embodiment of the present application;

[0043] Figure 2f is another schematic waveform diagram provided by an embodiment of the present application;

[0044] Figure 2g is yet another schematic waveform diagram provided by an embodiment of the present application;

[0045] Figure 3 is yet another schematic flowchart of a control method based on a power factor correction circuit provided by an embodiment of the present application;

[0046] Figure 4 It is a schematic structural diagram of a vehicle provided by an embodiment of the present application.

[0047] The accompanying reference numerals involved in the embodiments of the present application are as follows:

[0048] The first switching tube S1, the second switching tube S2, the third switching tube S3, the fourth switching tube S4, the first diode D1, the second diode D2, the capacitor C, the inductor L, the AC power supply AC, the inductor current i L , the AC voltage of the AC power supply V ac , the output current i out , the output voltage V out , the equivalent junction capacitance C DS , the switching frequency f S , the DS voltage V of S1 DS1 , the DS voltage V of S2 DS2 , the current i of S1 DS1 , the equivalent junction capacitance C of S1 DS1 , the driving voltage V of S2 GS2 , the compensated driving voltage V of S1 GS2 ', the compensated DS voltage V of S1 DS1 ', the compensated DS voltage V of S2 DS2 ', the compensated inductor current i L ', the second duty cycle d, the target duty cycle D of S1 S1 ′, the first duty cycle D of S1 S1 , the target duty cycle D of S2 S2 ′, the loop calculation result G in , the first duty cycle D of S2 S1 , the control module 10, the on-vehicle charger 400, the power factor correction circuit 401. Specific embodiments

[0049] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0050] In the description and claims of this application and the above-mentioned drawings, terms such as "first", "second", etc. are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, products or devices.

[0051] Referring to "embodiment" in this application means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described in this application may be combined with other embodiments.

[0052] The totem-pole bridgeless PFC is an efficient power factor correction circuit, and its core advantage lies in being able to improve the power factor and reduce the harmonic pollution to the power grid. The totem-pole bridgeless PFC utilizes the energy storage and discharge characteristics of the inductor and the fast switching of the switching tubes to convert the input alternating current into an input current close to a sine wave, and makes the phase of the input current basically consistent with the phase of the input voltage, thereby improving the power factor.

[0053] Single-cycle control is a commonly used control method for the totem-pole bridgeless PFC. Its working principle is to control the duty cycle of the switch so that the average value of the switching variable in each switching cycle is strictly equal to or proportional to the control reference quantity, so that the input current can be controlled to follow the input voltage waveform to achieve low current distortion and high power factor, and has a good control effect. At the same time, single-cycle control can effectively suppress the disturbance of the input voltage, making the system have good following characteristics and strong anti-disturbance ability.

[0054] In traditional single-cycle control, when the AC voltage passes through the zero point, the characteristic that the junction capacitance discharges slowly at low current will cause current distortion, thereby increasing the THD value of the PFC. Zero-crossing soft start is a feasible method to solve the zero-crossing current distortion problem under traditional single-cycle control. This method gradually releases the duty cycle in the initial period after the voltage passes through zero to limit the reverse recovery current distortion. However, this method requires setting the soft-start step size and time in advance, and these two parameters need to match the device selection and specific working conditions and do not have unity.

[0055] Based on the above problems, an embodiment of the present application provides a power factor correction circuit that can effectively suppress current distortion, reduce the THD value, and can dynamically adjust the duty cycle of the switching tube to adapt to different device models and specific working conditions (i.e., the circuit operating conditions, including power supply, load, environment, or operating state).

[0056] Please refer to Figure 1a , Figure 1a which is a schematic structural diagram of a power factor correction circuit provided by an embodiment of the present application. As Figure 1a shown, the power factor correction circuit includes: a first switching tube S1, a second switching tube S2, a third switching tube S3, a fourth switching tube S4, a capacitor C, an inductor L, a control module 10, and an AC power supply AC. The current passing through the inductor L is the inductor current i L , the voltage of the AC power supply AC is V ac , the output current is i out , and the output voltage is V out . The first switching tube S1 and the second switching tube S2 are switching tubes of the same model, that is, the equivalent junction capacitance and switching frequency of the first switching tube S1 and the second switching tube S2 are equal.

[0057] The first end of the inductor L is connected to the first end of the AC power supply AC, the second end of the inductor L is connected to the first end of the first switching tube S1 and the second end of the second switching tube S2, the second end of the first switching tube S1 is connected to the first end of the third switching tube S3 and the first end of the capacitor C, the first end of the second switching tube S2 is connected to the second end of the fourth switching tube S4 and the second end of the capacitor C, and the second end of the AC power supply AC is connected to the second end of the third switching tube S3 and the first end of the fourth switching tube S4. Among them, the first switching tube S1 and the second switching tube S2 are high-frequency switching tubes, and their switching frequency is the control frequency set by the control module; the third switching tube S3 and the fourth switching tube S4 are low-frequency switching tubes, and their switching frequency is the AC voltage frequency; the low-frequency switching tubes can also be not turned on throughout the process, and only the body diodes are used for freewheeling.

[0058] When the AC voltage is in the positive half-cycle, the first switching tube S1 serves as a freewheeling tube, the second switching tube S2 serves as an energy storage tube, the third switching tube S3 is turned off, and the fourth switching tube S4 is turned on; when the AC voltage is in the negative half-cycle, the first switching tube S1 serves as an energy storage tube, the second switching tube S2 serves as a freewheeling tube, the third switching tube S3 is turned on, and the fourth switching tube S4 is turned off.

[0059] Among them, the first switching transistor S1 and the second switching transistor S2 can include any one of the following: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or Insulate-Gate Bipolar Transistor (IGBT). MOSFET can also be called MOS tube or MOS transistor. MOSFET can be silicon carbide (SiC) MOSFET or gallium nitride (GaN) MOSFET. SiC MOSFET is a MOSFET using silicon carbide material, and GaN MOSFET is a MOSFET using gallium nitride material.

[0060] The third switching transistor S3 and the fourth switching transistor S4 can include any one of the following: MOS tube, IGBT, diode. Figure 1a The first switching transistor S1, the second switching transistor S2, the third switching transistor S3, and the fourth switching transistor S4 are all exemplified by N-type MOS transistors, and N-type MOS transistors can be abbreviated as NOMS tubes. As Figure 1a shown, the third switching transistor S3 and the fourth switching transistor S4 use MOS tubes.

[0061] Figure 1b In, the third switching transistor S3 and the fourth switching transistor S4 are exemplified by diodes. Please refer to Figure 1b , Figure 1b is a schematic structural diagram of another power factor correction circuit provided by an embodiment of the present application. In the embodiment of the present application, the third switching transistor S3 uses the first diode D1, and the fourth switching transistor S4 uses the second diode D2. The specific connection relationship is as follows: The first end of the inductor L is connected to the first end of the AC power supply AC, the second end of the inductor L is connected to the first end of the first switching transistor S1 and the second end of the second switching transistor S2, the second end of the first switching transistor S1 is connected to the negative electrode of the first diode D1 and the first end of the capacitor C, the first end of the second switching transistor S2 is connected to the positive electrode of the second diode D2 and the second end of the capacitor C, and the second end of the AC power supply AC is connected to the positive electrode of the first diode D1 and the negative electrode of the second diode D2.

[0062] The power factor correction circuit involved in the following embodiments of the present application takes Figure 1b as an example.

[0063] The control module 10 is used to determine the first duty cycle of the first switching transistor S1 and the second switching transistor S2 according to the inductor current and the output voltage, determine the second duty cycle according to the equivalent junction capacitance of the switching transistor, the output voltage, the inductor current, and the switching frequency of the switching transistor. The control module 10 determines the first duty cycle D of the first switching transistor S1 S1The first duty cycles of the switching transistors S1 and S2 are determined based on the first duty cycle d and the second duty cycle D. The target duty cycle is obtained by compensating the first duty cycles of the first switching transistor S1 and the second switching transistor S2 with the second duty cycle, thereby solving the problem of zero-crossing current distortion in single-cycle control and enabling adaptation to different circuit operating conditions without the need to adjust parameters according to device signals or circuit operating conditions.

[0064] Based on Figure 1b the power factor correction circuit shown, an embodiment of the present application provides a control method based on the power factor correction circuit. Please refer to Figure 2a , Figure 2a which is a schematic flowchart of a control method based on a power factor correction circuit provided by an embodiment of the present application. As shown in Figure 2a , the control method based on the power factor correction circuit includes the following steps:

[0065] 201. The control module determines the first duty cycle of the second switching transistor according to the polarity of the input AC voltage, the inductor current, and the output voltage.

[0066] Specifically, when the polarity of the input AC voltage is positive, the first duty cycle D of the first switching transistor S1 is determined according to the following formula:

[0067]

[0068] When the polarity of the input AC voltage is negative, the first duty cycle D of the first switching transistor S1 is determined according to the following formula:

[0069]

[0070] The first duty cycle D of the second switching transistor S2 is determined according to the following formula:

[0071] D S2 = 1 - D S1

[0072] where i L is the inductor current, G in is the loop calculation result, and V out is the output voltage. The duty cycle under traditional single-cycle control can be calculated according to the above formula. However, in traditional single-cycle control, when the AC voltage passes through zero, the slow discharge characteristic of the junction capacitance at low current operation will cause current distortion, thereby increasing the THD value of the PFC. Therefore, it is necessary to optimize the above first duty cycle to suppress zero-crossing current distortion.

[0073] Optionally, the control module includes a proportional-integral controller, and the loop calculation result brought into the formula is the output value after the proportional-integral controller operates on the difference between the output voltage and the reference voltage. Among them, the reference voltage is the voltage parameter when the power factor correction circuit works preset in advance.

[0074] 202. The control module determines the second duty cycle of the target switch tube according to the equivalent junction capacitance of the target switch tube, the output voltage, the inductor current, and the switching frequency of the switch tube.

[0075] Specifically, the second duty cycle is determined according to the following formula:

[0076]

[0077] Among them, d is the second duty cycle, C DS is the equivalent junction capacitance, V out is the output voltage, f S is the switching frequency, i L is the inductor current. Optionally, the output voltage is within the first preset limit, the inductor current is within the second preset limit, and the switching frequency is within the third preset limit. The above first preset limit, second preset limit, and third preset limit are set within the normal working range of the power factor correction circuit. By limiting the magnitudes of the output voltage, inductor current, and switching frequency, it is possible to prevent the calculated second duty cycle from being too large and avoid the target duty cycle from being too small.

[0078] The second duty cycle calculated according to the above formula is related to the equivalent junction capacitance, output voltage, switching frequency, and inductor current. That is to say, the second duty cycle can be dynamically adjusted according to the actual equivalent junction capacitance, output voltage, switching frequency, and inductor current of the switch tube without adjusting parameters, so as to be able to adapt to different working conditions.

[0079] Optionally, the equivalent junction capacitance is also determined according to the following formula:

[0080]

[0081] Among them, i DS is the current passing through the first switch tube. Generally, i DS can be replaced by i L , C DS is the equivalent junction capacitance, V DS is the voltage across the first switch tube. The equivalent junction capacitance of the switch tube is determined according to the above formula, so that the second duty cycle can be determined by substituting it into the calculation formula of the second duty cycle, and then the target duty cycle that can be dynamically adjusted can be obtained.

[0082] 203. The control module determines the target duty cycle of the target switch tube according to the first duty cycle and the second duty cycle.

[0083] Since the first duty cycle of the first switching transistor and the second switching transistor are complementary, and the first duty cycle of the first switching transistor is D S1 , the first duty cycle of the second switching transistor is D S2 = 1 - D S1 . Also, since the target duty cycle D' of the second switching transistor S2 = D S2 - d, therefore, the target duty cycle D' of the second switching transistor S2 = 1 - D S1 - d.

[0084] Also, since the target duty cycles of the first switching transistor and the second switching transistor are complementary, i.e., D' S1 = 1 - D' S2 , therefore, when the target switching transistor is the first switching transistor, the target duty cycle of the target switching transistor is determined according to the following formula:

[0085] D' S1 = D S1 + d

[0086] Therefore, when the target switching transistor is the second switching transistor, the target duty cycle of the target switching transistor is determined according to the following formula:

[0087] D' S2 = 1 - D' S1

[0088] where D' S1 is the target duty cycle of the first switching transistor, D' S2 is the target duty cycle of the second switching transistor, D S1 is the first duty cycle of the first switching transistor, D S2 is the first duty cycle of the second switching transistor, and d is the second duty cycle. The description of the first duty cycle D S1 of the first switching transistor in this step can refer to the description of step 201 above and will not be elaborated here. The target duty cycle is determined according to the first duty cycle and the second duty cycle, and the second duty cycle is dynamically adjusted according to the actual output voltage, inductor current, and switching frequency. The first duty cycle is the duty cycle under traditional single-cycle control, so the target duty cycle can also be dynamically adjusted, enabling the target duty cycle to adapt to different working conditions.

[0089] In the embodiment of the present application, the power factor correction circuit determines the target duty cycle of the target switching transistor through the first duty cycle and the second duty cycle, wherein the second duty cycle can be dynamically adjusted according to the equivalent junction capacitance of the switching transistor, the output voltage, the inductor current, and the switching frequency of the switching transistor, so that the target duty cycle of the target switching transistor can be dynamically adjusted, thereby effectively suppressing current distortion and reducing the THD value. At the same time, it is not necessary to adjust parameters to adapt to different working conditions, and it has universality, unity, and general applicability.

[0090] The following is the derivation of the calculation formula for the above-mentioned target duty cycle.

[0091] Taking the positive half-cycle of the alternating current (AC) voltage as an example, that is, the input voltage polarity is positive, and ignoring the reverse recovery characteristics of the diode, the working mode of the typical single-cycle control is analyzed.

[0092] Please refer to Figure 2b , Figure 2b which is a schematic structural diagram of the working mode of a power factor correction circuit provided by the embodiment of the present application. As Figure 2b shown, working mode 1: The first switching transistor S1 is turned off, the second switching transistor S2 is turned on, the AC power supply charges the inductor L, the inductor current flows through the second switching transistor S2 and the second diode D2, and the output voltage V out is maintained by the capacitor C, and the voltage between the drain (D) and the source (S) of the first switching transistor S1 (hereinafter referred to as the DS voltage) is equal to the output voltage V out . Figure 2b In

[0093] , the thick black line represents the segment that is conducting in working mode 1, and the light gray line represents the segment that is not conducting in working mode 1.

[0094]

[0095] V DS1 = V out (2)

[0096] dt = D S2 T s = (1 - D S1 )T s (3)

[0097] wherein, V ac is the voltage of the AC power supply, is the current of the inductor L during the charging period, V DS1 is the DS voltage of the first switching transistor S1, V outis the output voltage of the power factor correction circuit, D S2 is the duty cycle of the second switching transistor S2 (i.e., the ratio of the conduction time of the second switching transistor to the entire switching period), D S1 is the duty cycle of the first switching transistor S1, T s is a switching period of the switching transistor.

[0098] Please refer to Figure 2c , Figure 2c is a schematic diagram of the working mode structure of another power factor correction circuit provided by an embodiment of the present application. As Figure 2c shown, working mode 2: When the first switching transistor S1 is turned off and the second switching transistor S2 is turned off instantaneously, the junction capacitance of the first switching transistor S1 starts to discharge, and the junction capacitance of the second switching transistor S2 starts to charge. At this time, the current will flow through the junction capacitances of the first switching transistor S1 and the second switching transistor S2, and then through D2. Mode 2 will continue until the discharge of the junction capacitance of the first switching transistor S1 ends. Figure 2c In, the thick black line represents the segment that conducts in working mode 2, and the light gray line represents the segment that does not conduct in working mode 2

[0099] The voltage on the right side of the inductor is not equal to the output voltage V out for a short time after the second switching transistor S2 is turned off, but is equal to the DS voltage of the second switching transistor S2, and there is:

[0100] V DS2 = V out - V DS1 (4)

[0101]

[0102] Among them, V DS2 is the DS voltage of the second switching transistor S2, V DS1 is the DS voltage of the first switching transistor S1, V out is the output voltage of the power factor correction circuit, i DS1 is the current of the first switching transistor S1, C DS1 is the equivalent junction capacitance of the first switching transistor S1.

[0103] Please refer to Figure 2d , Figure 2d is a schematic diagram of the working mode structure of yet another power factor correction circuit provided by an embodiment of the present application. As Figure 2d shown, working mode 3: The first switching transistor S1 is turned off and the second switching transistor S2 is turned on, and the DS voltage of the second switching transistor S2 is equal to the output voltage. Figure 2dAmong them, the dark black lines represent the segments that are conducting in operating mode 3, and the light gray lines represent the segments that are not conducting in operating mode 3. At this time, the PFC is in a discharging state (i.e., the inductor L is in a discharging state), and there is:

[0104]

[0105] V DS2 =V out (7)

[0106] dt=(1 - D S2 )T s =D S1 T s (8)

[0107] Among them, V ac is the voltage of the AC power supply, is the current of the inductor L during discharging, V DS2 is the DS voltage of the second switching transistor S2, V out is the output voltage of the power factor correction circuit, D S2 is the duty cycle of the second switching transistor (i.e., the ratio of the conduction time of the second switching transistor to the entire switching period), D S1 is the duty cycle of the first switching transistor, T s is a switching period of the switching transistor. When the AC voltage is in the negative half - cycle, the operating mode is similar to that in the positive half - cycle, which will not be elaborated here.

[0108] Typical single - cycle control mainly analyzes operating mode 1 and operating mode 3. According to the volt - second balance principle, di L+ =-di L- , combined with equations (1), (3), (6) and (8), there is:

[0109]

[0110] To achieve the purpose that the PFC current follows the input voltage, the purpose of its current control can be expressed by the formula:

[0111] i L =V ac *G in (10)

[0112] Among them, G in is the admittance, which is determined by the calculation result of the loop output. Combining equations (9) and (10), the first duty cycle of the first switching transistor can be obtained as:

[0113]

[0114] The first duty cycle of the second switching transistor is:

[0115]

[0116] Please refer to Figure 2e , Figure 2e , which is a waveform schematic diagram provided by an embodiment of the present application. The above formula (9) is the basic formula for single-cycle control in the ideal switch state, and its working waveform is as shown in Figure 2e . The abscissa is time, and the ordinate is the amplitude of current or voltage. Among them, V GS2 is the driving voltage of the second switch tube S2 (i.e., the voltage between the gate (Gate, G) and the source (Source, S) of the second switch tube S2), V DS1 is the DS voltage of the first switch tube S1, V DS2 is the DS voltage of the second switch tube S2, and i L is the inductor current.

[0117] Please refer to Figure 2f , Figure 2f , which is another waveform schematic diagram provided by an embodiment of the present application. As shown in Figure 2f , the abscissa is time, and the ordinate is the amplitude of current or voltage. Among them, V GS2 is the driving voltage of the second switch tube S2, V DS1 is the DS voltage of the first switch tube S1, V DS2 is the DS voltage of the second switch tube S2, and i L is the inductor current. The solid line is the actual waveform, and the dashed line is the ideal waveform. When the AC voltage passes from the zero crossing of the negative half cycle to the positive half cycle, since the inductor current is relatively low at this time, the current flowing through the first switch tube S1 is relatively low, and the discharge speed of the junction capacitance of the first switch tube S1 is relatively slow. The voltage of V DS2 rises from 0 to V out also takes a longer time. This will cause the energy charged by the PFC within a single switching cycle to be greater than the theoretical value, while the discharged energy is less than the theoretical value, that is, the actual duty cycle of the waveform of V DS1 is relatively large. This will cause energy accumulation, making the actual inductor current greater than the ideal inductor current, resulting in inductor current distortion, and further affecting the THD value. And after this state lasts for multiple cycles, the inductor current will continue to accumulate and rise, forming a current spike( Figure 2e the actual waveform of i L in is higher than the ideal waveform). PFC charging can be the charging of the inductor L.

[0118] Please refer to Figure 2g , Figure 2g , which is yet another waveform schematic diagram provided by an embodiment of the present application. As shown in Figure 2g , the abscissa is time, and the ordinate is the amplitude of current or voltage. Among them, V GS2 is the driving voltage of the second switch tube, and V DS1is the DS voltage of the first switching transistor S1, V DS2 is the DS voltage of the second switching transistor S2, i L is the inductor current, V GS2 ' is the driving voltage of the first switching transistor S1 after compensation, V DS1 ' is the DS voltage of the first switching transistor S1 after compensation, V DS2 ' is the DS voltage of the second switching transistor S2 after compensation, i L ' is the inductor current after compensation. The solid line is the actual waveform, and the dashed line is the ideal waveform. From Figure 2g it can be seen that when the duty cycle of the second switching transistor S2 is not compensated, the actual waveform of i L is higher than the ideal waveform, and current spikes are formed in the inductor current; after the duty cycle of the second switching transistor S2 is compensated, the actual waveform of i L basically coincides with the ideal waveform, and no current spikes are formed in the inductor current, solving the problem of current distortion of the inductor current at the zero crossing in single-cycle control.

[0119] To solve the problem of current distortion at the zero crossing in traditional single-cycle control, an embodiment of the present application designs a method for suppressing zero-crossing current distortion. The principle is to compensate for the duty-cycle overflow part of the waveform of V DS1 caused by operating mode 2 to obtain a compensated duty cycle that enables the PFC to achieve volt-second balance within a single switching cycle. Under the control of the above method, the inductor current after compensation can be Figure 2e highly consistent with the ideal waveform shown, and no current distortion will be caused. The triangular area enclosed by the solid line waveform and the dashed line waveform of V DS1 is the discharge voltage overflow part caused by operating mode 2. The amplitudes of V DS1 and V DS2 are both equal to V out . According to the area equivalence principle, the area of a single triangular area is equal to the area of a rectangle with a pulse width of the compensated duty cycle d, that is:

[0120] dT S V out = S Δ (13)

[0121] where d is the second duty cycle, T s is a switching cycle of the second switching transistor, V out is the output voltage of the power factor correction circuit, and S Δ is the area of the triangular area enclosed by the solid line waveform and the dashed line waveform of V Figure 2f as shown in DS1 .

[0122] Assume that the rising edge time of V DS2 is Δt, then the area of the triangular area can be approximately calculated as:

[0123]

[0124] where Δt is for V DS2 The time when the actual voltage rises from 0 to D out (i.e., the rising edge time, which is also equal to V DS1 The time when the actual voltage drops from V out to 0).

[0125] The rising edge time Δt can be obtained from Equation (5). The current flowing through the switching transistor within the time Δt is regarded as a constant value, and there is:

[0126]

[0127] By combining Equations (10), (11), and (12), we get:

[0128]

[0129] where f s is the switching frequency of the switching transistor. Thus, the theoretical derivation of the compensation duty ratio d value is completed. The target duty ratio D' of the second switching transistor S2 is obtained from the following formula:

[0130] D' S2 = D S2 - d = 1 - D S1 - d (17)

[0131] Then the target duty ratio D' of the first switching transistor S1 is:

[0132] D' S1 = 1 - D' S2 = 1 - D S2 + d = D S1 + d (18)

[0133] Similarly, when the AC voltage is in the negative half - cycle, near the zero - crossing point, there will be a phenomenon that V GS1 is too large, resulting in negative distortion of the current. According to the above analysis, it is necessary to compensate the second duty ratio to reduce the first duty ratio D of the first switching transistor S1 and increase the second duty ratio D of the second switching transistor S2 . At this time, since i L is negative, the first duty ratio of the first switching transistor calculated by Equation (11) is negative, but the actual duty ratio is positive. Therefore, it is necessary to first perform an inversion operation on D S1 . The calculated result of the second duty ratio d is negative. Therefore, after inverting the first duty ratio, Equations (17) and (18) are also applicable to the negative half - cycle.

[0134] Based onFigure 1b The power factor correction circuit shown in the figure, the present application embodiment provides a control method based on the power factor correction circuit. Figure 3 , Figure 3 FIG. 1 is a flowchart of another control method based on a power factor correction circuit provided in an embodiment of the present application. Figure 3 As shown, the block diagram includes an adder, a proportional-integral (PI) controller, a first duty cycle calculation module, a second duty cycle calculation module, a target duty cycle calculation module, and a pulse width modulation (PWM) generator. The flow chart will be described in detail below.

[0135] First, the PFC reference voltage D out_ref With the output voltage V out The difference is input into the PI controller to obtain the loop calculation result G of the output voltage. in , G in The limit value of the output current is the limit value of the output current divided by the effective value of the power supply voltage, that is, G in The value range is Then G in 、i L and V out Substitute into the formula The first duty cycle of the first switch tube under the traditional single-cycle control is calculated, and D is determined by polarity judgment. S1 Whether the inversion operation is needed can be determined by S1 The value range is [0, 1], and the equivalent junction capacitance C DS , output voltage V out , switching frequency f S And the inductor current i L Substitute into the formula The second duty cycle that compensates the first duty cycle can be calculated, where C DS 、V out and f S The values of are limited to the normal working range of the power factor correction circuit, and finally according to D′ S1 =D S1 +d and D′ S2 =1-D′ S1 The target duty cycle can be determined. According to the values of the first duty cycle and the second duty cycle, the value range of the target duty cycle can be determined to be [0, 1]. The PWM generator is based on the target duty cycle D′ S1 and D′ S2 Generates a PWM signal.

[0136] The control method in the embodiments of the present application determines the target duty ratio of the second switching transistor through the first duty ratio and the second duty ratio, where the second duty ratio can be dynamically adjusted according to the equivalent junction capacitance of the switching transistor, the output voltage, the inductor current, and the switching frequency of the switching transistor, so that the target duty ratio of the second switching transistor can be dynamically adjusted, thereby effectively suppressing current distortion. At the same time, it is not necessary to adjust parameters to adapt to different working conditions, and it has generality, unity, and universal applicability.

[0137] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a vehicle provided by the embodiments of the present application. As Figure 4 shown, the vehicle may include an on-vehicle charger 400, and the on-vehicle charger 400 may include the power factor correction circuit 401 provided by the present application. Among them, the on-vehicle charger 400 can be used to charge the vehicle, the vehicle can be an electric vehicle, and the power factor correction circuit 401 can convert alternating current into direct current and be applied in the on-vehicle charger 400 to realize power supply to the vehicle. Moreover, the power factor correction circuit 401 can effectively suppress the distortion generated at the current zero crossing and can dynamically adjust the duty ratio of the switching transistor, thereby reducing the THD value and avoiding adjusting the parameters of circuit devices to adapt to different working conditions of the circuit, and it has generality, unity, and universal applicability.

[0138] Figure 4 For the specific structure and working principle of the power factor correction circuit 401 in Figures 1a to 3 , please refer to the above embodiments shown, and details will not be described here.

[0139] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0140] In several embodiments provided by the present application, it should be understood that the disclosed power factor correction circuit and vehicle can be implemented in other ways. For example, the power factor correction circuit embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

Claims

1. A power factor correction circuit, characterized in that, It includes an inductor, a switching module, a capacitor and a control module. The switching module includes a first switching transistor and a second switching transistor of the same model. The switching module further includes a third switching transistor and a fourth switching transistor; The first end of the inductor is connected to the first end of an AC power supply. The second end of the inductor is connected to the first end of the first switching transistor and the second end of the second switching transistor. The second end of the first switching transistor is connected to the first end of the third switching transistor and the first end of the capacitor. The first end of the second switching transistor is connected to the second end of the fourth switching transistor and the second end of the capacitor. The second end of the AC power supply is connected to the second end of the third switching transistor and the first end of the fourth switching transistor; The control module determines a first duty cycle of a target switching transistor according to the polarity of the input AC voltage, the inductor current and the output voltage. The inductor current is the instantaneous value of the current passing through the inductor, and the output voltage is the voltage across the capacitor. The target switching transistor includes the first switching transistor or the second switching transistor; The control module determines a second duty cycle of the target switching transistor according to the equivalent junction capacitance of the target switching transistor, the output voltage, the inductor current and the switching frequency of the switching transistor; The control module determines a target duty cycle of the target switching transistor according to the first duty cycle and the second duty cycle.

2. The power factor correction circuit according to claim 1, characterized in that, The third switching transistor is a first diode, and the fourth switching transistor is a second diode.

3. The power factor correction circuit according to claim 1 or 2, characterized in that, The second duty cycle of the target switching transistor is determined according to the following formula: where d is the second duty cycle, C DS is the equivalent junction capacitance, V out is the output voltage, f S is the switching frequency, i L is the inductor current.

4. The power factor correction circuit according to claim 3, characterized in that, The output voltage is within a first preset limit value, the inductor current is within a second preset limit value, and the switching frequency is within a third preset limit value.

5. The power factor correction circuit according to claim 1 or 2, characterized in that When the target switching transistor is the first switching transistor, the target duty cycle of the target switching transistor is determined according to the following formula: D′ S1 = D S1 + d Among them, D S1 ′ is the target duty cycle of the first switching transistor, D S1 is the first duty cycle of the first switching transistor, and d is the second duty cycle; When the target switching transistor is the second switching transistor, the target duty cycle of the target switching transistor is determined according to the following formula: D′ S2 = 1 - D′ S1 Among them, D S2 ′ is the target duty cycle of the second switching transistor, D′ S1 is the target duty cycle of the first switching transistor.

6. The power factor correction circuit according to claim 1 or 2, wherein When the polarity of the input AC voltage is positive, the first duty cycle of the first switching transistor is determined according to the following formula: where i L is the inductor current, G in is the loop calculation result, V out is the output voltage; When the polarity of the input AC voltage is negative, the first duty cycle of the first switching transistor is determined according to the following formula: where i L is the inductor current, G in is the loop calculation result, V out is the output voltage.

7. The power factor correction circuit according to claim 6, wherein The first duty cycle of the second switching transistor is determined according to the following formula: D S2 = 1 - D S1 where D S2 is the first duty cycle of the second switching transistor, and the D S1 is the first duty cycle of the first switching transistor.

8. The power factor correction circuit according to claim 6 or 7, characterized in that, The control module includes a proportional-integral controller, and the loop calculation result is the output value after the proportional-integral controller operates on the error value between the output voltage and the reference voltage.

9. The power factor correction circuit according to claim 1 or 2, characterized in that, The equivalent junction capacitance is also determined according to the following formula: wherein, i DS is the current passing through the target switching transistor, and i L is the inductor current. Generally, i DS can be replaced by i L . C DS is the equivalent junction capacitance, and V DS is the voltage across the target switching transistor.

10. A vehicle, characterized in that, The vehicle includes an on-vehicle charger, and the on-vehicle charger includes the power factor correction circuit according to any one of claims 1 to 9.

Images