Current regulation method, current regulation circuit, and electronic equipment

Abstract

The present application discloses a current regulation method, a current regulation circuit, and an electronic device, the current regulation method comprising: obtaining the output current of the regulated output subcircuit; obtaining the regulated output value using the error value between the reference pulse current and the output current; adjusting the regulated output value to within the first threshold range in response to the regulated output value being lower than the first threshold range; generating a drive control signal using the regulated output value; sending the drive control signal to any preset number of power switch subcircuits in response to the reference pulse current being zero, so as to adjust the output current to within the second threshold range; wherein the preset number is less than the total number of power switch subcircuits. Through the above manner, the current regulation method of the present application can not only ensure that the multi-phase interleaved conversion circuit can meet the power supply demand in a timely manner when it is reloaded, but also effectively avoid the load circuit from remaining in a working state when it is unloaded, causing work errors, and avoid unnecessary component losses.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to a current regulation method, a current regulation circuit, and an electronic device. Background Art

[0002] Today, with the increasing variety of electronic devices, the requirements for power supply are also becoming more diverse. This is especially true when nonlinear elements and / or energy storage elements are present in the load circuit. To ensure good power supply quality and stability, the power supply usually needs to maintain a certain output current even when no-load, and it must also ensure that the output current does not exceed a specific threshold. However, the current regulation methods for power supply implemented in the related art are generally unable to guarantee the output current when no-load, or are unable to regulate the output current to within a specific threshold range, resulting in the load circuit remaining in a working state when no-loaded, causing operational errors and unnecessary component losses. Summary of the Invention

[0003] The main technical problem solved by the present application is to provide a current regulation method, a current regulation circuit and an electronic device, which can solve the problem that the current regulation method in the related art cannot adjust the output current to a specific threshold range when no-load, so that the load circuit remains in a working state when no-load, causing work errors and unnecessary component losses.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a current regulation method, which is applied to the current regulation of a multi-phase interleaved conversion circuit, the multi-phase interleaved conversion circuit includes a phase-coupled power switching sub-circuit and a regulation output sub-circuit, and the number of power switching sub-circuits is at least two, wherein the current regulation method includes: obtaining the output current of the regulation output sub-circuit; using the error value between the reference pulse current and the output current to obtain the regulation output value; in response to the regulation output value being lower than the first threshold range, adjusting the regulation output value to within the first threshold range; using the regulation output value to generate a drive control signal; in response to the reference pulse current being zero, sending the drive control signal to any preset number of power switching sub-circuits to adjust the output current to within the second threshold range; wherein the preset number is less than the total number of power switching sub-circuits.

[0005] Among them, before the step of obtaining the adjusted output value by using the error value between the reference pulse current and the output current, it also includes: receiving a power supply adjustment signal sent by the host computer; and adjusting the signal frequency of the reference pulse current in response to the power supply adjustment signal.

[0006] Wherein, in response to the regulated output value being lower than the first threshold range, before the step of adjusting the regulated output value to be within the first threshold range, the method further includes: setting the first threshold range by using a preset number and a second threshold range.

[0007] Among them, in response to the regulated output value being lower than the first threshold range, the step of adjusting the regulated output value to within the first threshold range includes: obtaining the falling edge of the reference pulse current; starting timing in response to the falling edge, so as to adjust the error value to 0 when the accumulated timing is a preset minimum duration; and using the adjusted error value to adjust the regulated output value to within the first threshold range.

[0008] The step of sending the drive control signal to any preset number of power switch sub-circuits in response to the reference pulse current being zero includes: sending the drive control signal to any preset number of power switch sub-circuits in response to a falling edge.

[0009] After the step of sending the drive control signal to any one of any preset number of power switch sub-circuits in response to the falling edge, the method further includes: obtaining the rising edge of the reference pulse current; and sending the drive control signal to each power switch sub-circuit in response to the rising edge.

[0010] The preset minimum duration is greater than or equal to the interval between the falling edge and the start time when the error value is within the third threshold range, and is less than the minimum cycle time of the reference pulse current.

[0011] In which, in response to the regulated output value being lower than the first threshold range, the step of adjusting the regulated output value to within the first threshold range includes: obtaining the falling edge and rising edge of the reference pulse current; starting timing in response to the falling edge, so as to keep the current regulated output value unchanged until the rising edge when the accumulated timing is a preset minimum duration, so as to adjust the regulated output value to within the first threshold range; wherein, the reference pulse current has different signal frequencies.

[0012] Among them, the step of starting timing in response to the falling edge and keeping the current adjustment output value unchanged until the rising edge when the accumulated timing reaches the preset minimum duration includes: starting timing in response to the falling edge and setting the adjustment flag to a low position when the accumulated timing reaches the preset minimum duration; keeping the current adjustment output value unchanged; setting the adjustment flag to a high position in response to the rising edge, and obtaining the adjustment output value using the error value.

[0013] The method of obtaining the regulated output value by using the error value between the reference pulse current and the output current includes: subtracting the output current from the reference pulse current to obtain the error value; and performing proportional-integral regulation on the error value to obtain the regulated output value.

[0014] To solve the above technical problems, another technical solution adopted in this application is: to provide a current regulation circuit, wherein the current regulation circuit is coupled to a multi-phase interleaved conversion circuit; wherein the current regulation circuit adopts the current regulation method described in any of the above items to regulate the current of the multi-phase interleaved conversion circuit.

[0015] To solve the above technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a shell and a current regulating circuit connected to the shell; wherein the current regulating circuit is the current regulating circuit described above.

[0016] The beneficial effects of the present application are as follows: Different from the prior art, the current regulation method provided by the present application obtains the output current of the regulated output sub-circuit, uses the error between the reference pulse current and the output current to obtain the regulated output value, and in response to the regulated output value being lower than the first threshold range, adjusts the regulated output value to within the first threshold range, generates a drive control signal using the regulated output value, and sends the drive control signal to any preset number of power switch sub-circuits in response to the reference pulse current being zero. Thus, when the reference pulse current is zero, by limiting the regulated output value and the controlled number of power switch sub-circuits, the output current is effectively regulated to within the second threshold range, thereby ensuring that the power supply demand of the multi-phase interleaved conversion circuit can be met in a timely manner when the multi-phase interleaved conversion circuit is reloaded, effectively avoiding operational errors caused by the load circuit remaining in an operating state when unloaded, and avoiding unnecessary component loss. Moreover, when the reference pulse current has different frequencies, by limiting the regulated output value to the first threshold range, the consistency and stability of the output current rising phase when the multi-phase interleaved conversion circuit is reloaded are effectively ensured, thereby ensuring good power supply quality and power supply stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0018] Figure 1 This is a flow chart of the first embodiment of the current regulation method of the present application;

[0019] Figure 2 This is a schematic structural diagram of a first embodiment of the current regulating circuit of the present application;

[0020] Figure 3 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S12;

[0021] Figure 4 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S13;

[0022] Figure 5 yes Figure 4 Waveform diagram of an embodiment of a reference pulse current, an error value, and an adjusted output value;

[0023] Figure 6 yes Figure 4 A flow chart of an embodiment of S132;

[0024] Figure 7 This is a flow chart of the second embodiment of the current regulation method of the present application;

[0025] Figure 8 1 is a flow chart of a third embodiment of the current regulation method of the present application;

[0026] Figure 9 This is a structural diagram of a second embodiment of the current regulating circuit of the present application;

[0027] Figure 10 It is a structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Therefore, features specified as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional designations (such as up, down, left, right, front, back, etc.) in the embodiments of this application are intended only to illustrate the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional designations will also change accordingly. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to such process, method, product, or apparatus.

[0030] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0032] Please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a flow chart of the first embodiment of the current regulation method of the present application. Figure 2 This is a schematic diagram of the structure of the first embodiment of the current regulating circuit of the present application. Specifically, it can include the following steps:

[0033] S11: Obtain the output current of the regulated output sub-circuit.

[0034] It is understood that the current regulation method in this embodiment is specifically applied to Figure 2 The current regulation of the first multi-phase interleaved conversion circuit 200 shown in the figure, the first multi-phase interleaved conversion circuit 200 includes a first power switch sub-circuit 201 and a first regulation output sub-circuit 202 coupled to each other; wherein, the first current regulation circuit 100 adopts any current regulation method described in any one of the items in this document to implement current regulation for the first multi-phase interleaved conversion circuit 200.

[0035] It is worth noting that the first multi-phase interleaved conversion circuit 200 can specifically be a multi-phase interleaved BUCK circuit (step-down conversion circuit), or a multi-phase interleaved BOOST circuit (boost conversion circuit), or other forms of circuit topology, which is not limited in this embodiment.

[0036] The number of the first power switch sub-circuits 201 is specifically at least two, such as first power switch sub-circuit 1, first power switch sub-circuit 2, ..., and first power switch sub-circuit n (n being an integer greater than 1). The first power switch sub-circuit 1, the first power switch sub-circuit 2, ..., and the first power switch sub-circuit n are all coupled to the first current regulation circuit 100 and the first regulation output sub-circuit 202. The first regulation output sub-circuit 202 is further configured to be coupled to the load circuit 301.

[0037] In some embodiments, the first current regulating circuit 100 may specifically include a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, a discrete gate or transistor logic device, discrete hardware, and any other reasonable circuit unit with signal processing function, and this application does not limit this.

[0038] Furthermore, the term "coupled" as used herein encompasses both direct and indirect connection methods. Therefore, if a first circuit is described as being coupled to a second circuit, this means that the first circuit may be directly connected to the second circuit via electrical connection, wireless transmission, optical transmission, or other signal connection methods, or may be indirectly connected to the second circuit via other circuits or connection methods.

[0039] Specifically, the first current regulating circuit 100 monitors the output current of the first regulating output sub-circuit 202 in real time, and obtains the output current output to the load circuit 301 by sampling the first regulating output sub-circuit 202 .

[0040] S12: The error value between the reference pulse current and the output current is used to obtain the adjusted output value.

[0041] The first current regulation circuit 100 sets a reference pulse current, or receives a reference pulse current sent by a host computer, to subtract the output current from the reference pulse current to obtain an error value, and uses a PID (Proportional Integral Derivative) controller, a PI controller or any other reasonable feedback control algorithm to obtain an adjusted output value for the error value, which is not limited in this application.

[0042] The reference pulse current may specifically be a periodic pulse waveform or other forms of reference signals.

[0043] It's worth noting that the host computer typically refers to a computer system with powerful computing and data processing capabilities. It's responsible for monitoring the entire control system, issuing commands, collecting data, processing and analyzing data, and interacting with the user. As the "brain" of the system, the host computer processes complex algorithms, performs long-term data storage, and provides a graphical user interface.

[0044] A slave computer is a device or controller directly connected to hardware such as sensors and actuators in a control system. It is responsible for executing specific control instructions from the master computer, such as outputting switch signals, adjusting analog quantities, and collecting data. Slave computers typically perform simple logic analysis and real-time control tasks.

[0045] S13: In response to the regulated output value being lower than the first threshold range, regulating the regulated output value to be within the first threshold range.

[0046] A first threshold range is set according to specific control requirements. If the regulated output value is lower than the first threshold range, it is adjusted to the first threshold range; or it can be understood that when the regulated output value drops to the first threshold range, the regulated output value is kept from decreasing.

[0047] S14: Generate a drive control signal using the adjusted output value.

[0048] According to the regulated output value, corresponding driving control signals are generated, which are used to trigger the switching elements of each first power switch sub-circuit 201 to control the on and off states thereof.

[0049] In some embodiments, the drive control signal may specifically be one or more of any reasonable control signals such as a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal, and this application does not limit this.

[0050] S15: In response to the reference pulse current being zero, sending a drive control signal to any preset number of first power switch sub-circuits to adjust the output current to within a second threshold range.

[0051] When it is detected that the reference pulse current is zero, any preset number of first power switch sub-circuits 201 are selected, where the preset number is smaller than the total number of the first power switch sub-circuits 201 .

[0052] The currently generated drive control signal is sent to these selected parts of the first power switch sub-circuit 201 to adjust the output current to the second threshold range, so that the controlled number of the first power switch sub-circuit 201 can be reduced by limiting, and at the same time the adjusted output value is limited to not exceed the first threshold range, so as to effectively limit the output current of the multi-phase interleaved conversion circuit when it is unloaded to within the second threshold range, thereby ensuring that the power supply demand can be met in time when it is reloaded, and it can also effectively avoid the load circuit from remaining in a working state when it is unloaded, causing work errors, and avoiding unnecessary component losses.

[0053] It can be understood that the second threshold range can be specifically understood as a specific current threshold interval that is reasonably set so that the load circuit 301 can exit the working state and maintain it in a specific standby state when the first multi-phase interleaved conversion circuit 200 is unloaded, that is, when the reference pulse current is zero, so as to cooperate with the first regulation output sub-circuit 202 to wait for the first multi-phase interleaved conversion circuit 200 to quickly enter the working state with load again.

[0054] In addition, the first threshold range can also be specifically understood as a specific threshold interval that is reasonably set to ensure that the output current can be adjusted to within the second threshold range when no-load.

[0055] And because the first threshold range is set to ensure that the output current is limited to the second threshold range when no-load, the first threshold range actually corresponds to a negative regulated output value, which limits the regulated output value to the first threshold range, even if the regulated output value is not lower than the lower limit value of the first threshold range, the lower limit value is a negative value.

[0056] In some embodiments, the second threshold range is smaller than the rated output current of the first multi-phase interleaved conversion circuit 200 in normal working condition. For example, the second threshold range can be any reasonable proportion range such as 5%-25%, 5%-15% or 10%-30% of the rated output current, so as to maintain a certain output current when no-load, thereby ensuring that the output voltage is not lower than a specific voltage drop, such as the voltage drop that maintains the conduction of the diode in the load circuit or the voltage drop that maintains a certain degree of energy storage, and at the same time, it does not drive the load circuit into working condition, thereby causing work errors and unnecessary component losses. The specific range can be determined by the actual application scenario, and this application does not limit this.

[0057] The above scheme effectively adjusts the output current to within the second threshold range by limiting the regulated output value and the controlled number of the first power switch sub-circuit 201 when the reference pulse current is zero, so as to ensure that the first multi-phase interleaved conversion circuit 200 can meet the power supply demand in a timely manner when it is reloaded, and at the same time effectively avoid the load circuit 301 from remaining in a working state when it is unloaded, causing work errors, and avoids unnecessary component losses; and when the reference pulse current has different frequencies, by limiting the regulated output value to within the first threshold range, it also effectively ensures the consistency and stability of the output current rising stage when the first multi-phase interleaved conversion circuit 200 is reloaded, thereby ensuring good power supply quality and power supply stability.

[0058] By monitoring the output current in real time and comparing it with the reference pulse current, it is possible to quickly respond to load changes and keep the output current stable. The staggered operation between multiple first power switch sub-circuits 201 can effectively reduce input / output ripple and improve the efficiency and stability of the system. By setting the first threshold range and the second threshold range, it is ensured that the regulated output value and the output current are always within a reasonable operating range to avoid problems such as overload or undervoltage. In a multi-phase Buck converter, multiple parallel Buck converters operate in an interlaced manner to share the load current. Through the above-mentioned current regulation method, efficient energy transmission can be achieved under different load conditions, and electromagnetic interference can be reduced. This method not only improves the control accuracy and stability of the first multi-phase interleaved conversion circuit 200, but also enhances the flexibility and adaptability of the system, and is suitable for a variety of power electronics applications.

[0059] Furthermore, in one embodiment, before the above S13, the method further includes: setting a first threshold range by using a preset number and a second threshold range.

[0060] It is understandable that the feedback regulation of the output current is actually achieved by adjusting the switching state of each first power switch sub-circuit 201. Different controlled numbers of first power switch sub-circuits 201 correspond to different output current regulation amplitudes; and the drive control signal is generated by the regulated output value. The limit of the regulated output value will also directly affect the limit range of the output current. Therefore, in order to regulate the output current within the second threshold range, it is also necessary to comprehensively consider the different limit ranges of the regulated output value under the premise that different controlled numbers, that is, the preset number of first power switch sub-circuits 201 are controlled by the drive control signal, so as to obtain the first threshold range by using the preset number and the second threshold range setting.

[0061] Please continue reading Figure 3 , Figure 3 yes Figure 1 In one embodiment, the current regulation method of the present application includes, in addition to the above steps S11-S15, further including some more specific steps. Specifically, the above step S12 may further include the following steps:

[0062] S121: Subtract the output current from the reference pulse current to obtain an error value.

[0063] Specifically, the first current regulating circuit 100 subtracts the output current from the currently acquired reference pulse current to obtain an error value.

[0064] S122: Perform proportional-integral adjustment on the error value to obtain an adjustment output value.

[0065] Furthermore, a PID controller, a PI controller or any other reasonable feedback control algorithm is used to calculate the error value to obtain an adjusted output value. The adjusted output signal reflects the energy level or direction that needs to be adjusted so that the output current is close to the reference pulse current.

[0066] See also Figure 4 , Figure 4 yes Figure 1 In one embodiment, the current regulation method of the present application includes, in addition to the above steps S11-S15, further including some more specific steps. Specifically, the above step S13 may further include the following steps:

[0067] S131: Acquire the falling edge and rising edge of the reference pulse current.

[0068] Please continue reading Figure 5 , Figure 5 yes Figure 4 Waveform diagram of an embodiment of the reference pulse current, error value and adjustment output value.

[0069] It's understandable that because the reference pulse current is a pulse signal, it transitions from low to high (i.e., the rising edge) and from high to low (i.e., the falling edge). The high- and low-level transitions of the reference pulse current (i.e., the falling and rising edges) are used as the demarcations, resulting in positive or negative errors, respectively, which can affect subsequent regulation and control.

[0070] Specifically, the first current regulation circuit 100 identifies and detects the falling edge and rising edge of the reference pulse current. For example, this goal can be achieved through any reasonable method such as hardware circuits (such as edge triggers) or software algorithms (for example, writing corresponding codes in embedded systems) or controller counters, and this application does not limit this.

[0071] S132: In response to the falling edge, start timing, and when the accumulated timing reaches a preset minimum duration, keep the current regulated output value unchanged until the rising edge, so as to adjust the regulated output value to within the first threshold range.

[0072] Furthermore, when the falling edge of the reference pulse current is detected, timing starts with the falling edge as the starting moment until the accumulated timing reaches the preset minimum duration t1, and the adjustment output value at the current moment is maintained constant until the next rising edge of the reference pulse current arrives, that is, before the next rising edge arrives, it is ensured that the current adjustment output value no longer increases negatively, so as not to exceed the first threshold range.

[0073] It can be understood that by setting the timing to start at the falling edge of the reference pulse current, and when the accumulated timing reaches the preset minimum duration t1, the current regulated output value is kept unchanged and the cumulative integral does not increase in a negative direction until the next rising edge arrives, thereby ensuring that the regulated output value is at different frequencies of the reference pulse current, that is, when the duration from the current falling edge to the next rising edge of the reference pulse current, or when the reference pulse current is zero current, is different, the cumulative duration of the proportional integral adjustment of the error value between the reference pulse current and the output current is guaranteed to be the preset minimum duration, so that when the next rising edge arrives, a regulated output value with the same initial value can be obtained, so that on the basis of the same initial value, the error value between the current reference pulse current and the output current is again proportionally and integrally adjusted in real time in response to the next rising edge to increase the regulated output value, and the same initial value effectively ensures the consistency and stability of the rising stage of the regulated output value after the next rising edge arrives, thereby ensuring the consistency and stability of the output current adjustment achieved by the drive control signal generated by the regulated output value, that is, ensuring the consistency and stability of the rising stage of the output current in response to the next rising edge of the reference pulse current.

[0074] In some embodiments, the preset minimum duration t1 is greater than or equal to the interval between the falling edge of the reference pulse current and the starting moment when the error value changes to the third threshold range, and is less than the minimum cycle time of the reference pulse current. This application does not limit this.

[0075] It is worth noting that the third threshold range can be understood as a threshold interval in which the error value enters a stable state when the reference pulse current is zero.

[0076] In addition, the minimum cycle time is determined by the power supply requirement of the load circuit 301. For example, the output power requirement range of the load circuit 301 determines the frequency range and maximum frequency of the reference pulse current, and the minimum cycle time is obtained from the maximum frequency.

[0077] It is understandable that if Figure 5 As shown, when the frequency of the reference pulse current is different, the duration of the reference pulse current being zero is different, and the initial value of the regulated output value obtained by the error value when the rising edge of the reference pulse current arrives is different, which in turn causes the drive control signal obtained by the regulated output value to be different, so that when the reference pulse current is low-frequency, the rise time of the regulated output value at the rising edge becomes longer, and there is a risk of causing the output current to drop and become unstable.

[0078] Therefore, by limiting the adjustment output value to remain unchanged from the falling edge to the preset minimum duration t1, it is effectively guaranteed that the adjustment output value has a constant initial value when the rising edge arrives under different frequencies of the reference pulse current, thereby effectively ensuring that the output current is adjusted to within the second threshold range and avoiding drops and instability.

[0079] See also Figure 6 , Figure 6 yes Figure 4 In one embodiment, the current regulation method of the present application includes not only the above-mentioned S131-S132, but also some more specific steps. Specifically, the above-mentioned S132 may further include the following steps:

[0080] S1321: In response to the falling edge, start timing so that when the accumulated timing reaches a preset minimum duration, set the adjustment flag to low.

[0081] It is understandable that, in order to ensure that the regulated output value is not lower than the first threshold range at different frequencies of the reference pulse current, the first current regulating circuit 100 can further set an adjustment flag to achieve control over limiting the regulated output value.

[0082] Specifically, the first current regulating circuit 100 starts timing when detecting the falling edge of the reference pulse current, so as to set the regulating flag to a low position when the accumulated timing reaches a preset minimum duration t1.

[0083] Specifically, the adjustment output value remains unchanged when the adjustment mark is at a low position, and is released from the restriction and changes with the error value when the adjustment mark is at a high position.

[0084] S1322: Keep the current adjustment output value unchanged.

[0085] When the adjustment flag is detected to be low, the current adjustment output value remains unchanged.

[0086] S1323: In response to the rising edge, the adjustment flag is set high, and the error value is used to obtain the adjustment output value.

[0087] When the rising edge of the reference pulse current is detected, the adjustment flag is set high to reuse the currently acquired error value to calculate and obtain the adjustment output value.

[0088] See also Figure 7 , Figure 7 This is a flow chart of the second embodiment of the current regulation method of the present application. The current regulation method of this embodiment is Figure 1 A flow chart of a detailed implementation of the current regulation method in FIG. 1 specifically includes the following steps:

[0089] S21: Obtain the output current of the regulated output sub-circuit.

[0090] Among them, S21 and Figure 1 For details, please refer to S11 and its related text descriptions, which will not be repeated here.

[0091] S22: Receive the power supply adjustment signal sent by the host computer.

[0092] It is worth noting that the host computer can be specifically understood as a system processor that monitors and controls the working status and application scenarios of the load circuit 301 to determine the current power supply requirements of the load circuit 301, such as the output power requirements of the load circuit 301, and then sets the current power supply adjustment signal.

[0093] Specifically, the first current regulating circuit 100 is used to communicate with a host computer and receive a power supply regulating signal sent by the host computer.

[0094] S23: Adjusting the signal frequency of the reference pulse current in response to the power supply adjustment signal.

[0095] Furthermore, in response to the currently acquired power supply adjustment signal, the signal frequency of the reference pulse current is adjusted to adjust the drive control signal obtained using the reference pulse current, thereby adjusting the output current to meet the power supply requirements of the load circuit 301.

[0096] S24: deriving an adjusted output value using the error value between the reference pulse current and the output current.

[0097] S25 : In response to the regulated output value being lower than the first threshold range, regulating the regulated output value to be within the first threshold range.

[0098] S26: Generate a drive control signal using the adjusted output value.

[0099] S27: In response to the reference pulse current being zero, sending a drive control signal to any preset number of power switch sub-circuits to adjust the output current to within a second threshold range.

[0100] Among them, S24, S25, S26 and S27 are Figure 1 S12, S13, S14 and S15 are the same. For details, please refer to S12, S13, S14 and S15 and their related text descriptions, which will not be repeated here.

[0101] See also Figure 8 and Figure 9 ,in, Figure 8 This is a flow chart of the third embodiment of the current regulation method of the present application. Figure 9This is a schematic diagram of the structure of the second embodiment of the current regulation circuit of the present application. The current regulation method of this embodiment is Figure 1 A flow chart of a detailed implementation of the current regulation method in FIG. 1 specifically includes the following steps:

[0102] S31: Obtain the output current of the regulated output sub-circuit.

[0103] It is understandable that the current regulation method in this embodiment can be specifically for Figure 9 The second multi-phase interleaved conversion circuit 400 shown implements current regulation. The second multi-phase interleaved conversion circuit 400 includes a coupled second power switch subcircuit 401 and a second regulated output subcircuit 402. The second power switch subcircuit 401 specifically includes switches Q1, Q2, ..., Qn and diodes D1, D2, ..., Dn. The second regulated output subcircuit 402 includes inductors L1, L2, ..., Ln and an output capacitor C.

[0104] In some embodiments, the second regulation output sub-circuit 402 is also used to couple with the load circuit 301, and the load circuit 301 may specifically include an equivalent diode DF1, an equivalent diode DF2, ..., an equivalent diode DFn and a resistor Ro, and may also include a circuit topology of a diode and any reasonable circuit elements such as a resistor, a capacitor or an inductor, etc., which is not limited in this application.

[0105] The first end of the switch Q1, the first end of the switch Q2, ..., and the first end of the switch Qn are all coupled to the first end of the DC power supply DC. The second ends of the switch Q1, the second ends of the switch Q2, ..., and the second end of the switch Qn are respectively coupled to the second ends of the diode D1, the second ends of the diode D2, ..., and the second end of the diode Dn, and are also respectively coupled to the first end of the inductor L1, the first end of the inductor L2, ..., and the first end of the inductor Ln. The third ends of the switch Q1, the third ends of the switch Q2, ..., and the third end of the switch Qn are all coupled to the second end of the DC power supply DC. A current regulation circuit (not shown) is provided in which the first ends of diodes D1, D2, ..., and Dn are coupled to the second end of the DC power supply DC and the second end of the resistor Ro, and are also coupled to the second end of the output capacitor C. The second ends of inductor L1, L2, ..., and Ln are coupled to the first end of the output capacitor C and the first end of the equivalent diode DF1. The equivalent diode DF1, the equivalent diode DF2, ..., and DFn are sequentially connected in series, and the second end of the equivalent diode DFn is coupled to the first end of the resistor Ro.

[0106] In some embodiments, the switch tube Q1, switch tube Q2, ..., switch tube Qn can specifically be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a triode, a thin film transistor or a field effect transistor or any other reasonable switch tube, and this application does not limit this.

[0107] For the sake of convenience, the second multi-phase interleaved conversion circuit 400 is specifically applied to a switching laser power supply as an example, that is, the load circuit 301 can be specifically understood as an equivalent circuit of a laser pumping circuit. Since the laser pumping circuit usually needs to obtain lasers of different wavelengths and frequencies in actual applications, the requirements for the output power of the second multi-phase interleaved conversion circuit 400 are also different. Correspondingly, in the feedback adjustment of its output current Io, the frequency of the reference signal also needs to be adjusted according to the different power supply requirements, and it is a pulse signal, that is, a reference pulse current.

[0108] It's worth noting that, due to the inherent characteristics of the laser pump circuit, which resembles a load consisting of multiple diodes in series, when the reference pulse current is zero, the second multi-phase interleaved conversion circuit 400 must maintain a certain output current Io to ensure that the output voltage does not fall below the conduction voltage drop of each diode. Furthermore, the output current Io cannot exceed a specific threshold, otherwise the laser pump will emit light even when it is unloaded. In this case, since the actual output current Io must be greater than zero while the reference output current Io is zero, the error between the two is always less than zero. Once the PI feedback control loop is entered, de-integration will be continuously performed. However, since de-integration times vary at different reference pulse current frequencies, the lower the frequency, the greater the de-integration change and the smaller the integral amount. When the output current Io rises again, the initial integral amount will be different, which in turn will lead to different waveforms in the drive control signal. This will result in a longer pulse rise time for the integral amount (i.e., the regulated output value) at low frequencies, and may cause the regulated output value and output current Io to drop.

[0109] Therefore, to address the issue of output current Io not being able to exceed a specific threshold, the no-load output current Io can be reduced by operating some of the multiphases at no load. The issue of different current rise times at different frequencies can be addressed by ensuring that the initial value of the integral at the rising edge of the reference pulse current is the same at different frequencies.

[0110] Specifically, the second current regulating circuit samples and obtains the output current Io flowing through the resistor Ro.

[0111] S32: Obtain an adjusted output value using the error value between the reference pulse current and the output current.

[0112] In some embodiments, the second current regulation circuit can specifically receive the user's setting program instructions, or the host computer can monitor the power supply requirements of the laser pumping circuit and obtain the corresponding power supply adjustment signal to set and adjust the reference pulse current, or directly receive the reference pulse current sent by the host computer that is set and adjusted according to the corresponding power supply requirements. This application does not limit this.

[0113] The second current regulation circuit subtracts the output current Io from the currently acquired reference pulse current to obtain an error value. This error value is then processed using a PID controller, PI controller, or any other reasonable feedback control algorithm to obtain a regulated output value. This regulated output signal reflects the energy level or direction that needs to be adjusted to bring the output current Io closer to the reference pulse current.

[0114] S33: Acquire the falling edge of the reference pulse current.

[0115] like Figure 5 As shown, the falling edge of the reference pulse current is detected in real time, and this goal can be achieved by any reasonable means, such as hardware circuits (such as edge triggers) or software algorithms (such as writing corresponding codes in embedded systems) or controller counters, and this application does not limit this.

[0116] S34: In response to the falling edge, timing is started, so as to adjust the error value to 0 when the accumulated timing reaches a preset minimum duration.

[0117] When the falling edge of the reference pulse current is detected, timing is started with the falling edge as the starting moment, and the error value is adjusted to 0 when the accumulated timing reaches the preset minimum duration t1.

[0118] S35: Using the adjusted error value, adjust the adjustment output value to within the first threshold range.

[0119] The adjusted output value is obtained using the adjusted error value. Since the error value is adjusted to 0 at this time, the adjusted output value is constant to the value at the moment corresponding to the preset minimum duration t1, so as to be maintained within the first threshold range.

[0120] S36: Generate a drive control signal using the adjusted output value.

[0121] Generates the corresponding drive control signal according to the current regulation output value.

[0122] It is worth noting that when there are multiple controlled switching tubes, there are actually multiple driving control signals, and the duty cycles of the driving control signals are the same, but the phases will correspond to the switching tubes Q1, Q2, ..., Qn, respectively, and are delayed by 360 / n degrees in sequence.

[0123] S37: Sending a driving control signal to any preset number of power switch sub-circuits in response to the falling edge to adjust the output current to within a second threshold range.

[0124] When the falling edge of the reference pulse current is detected, the second current regulation circuit specifically sends a drive control signal to any preset number of switch tubes among the switch tubes Q1, the switch tube Q2, ..., and the switch tube Qn, for example, the switch tube Q1, or the switch tube Q2, or the switch tube Q1 and the switch tube Q2, or the switch tube Q2 and the switch tube Qn, and blocks the other switch tubes to reduce the output current Io so that it is maintained within the second threshold range.

[0125] S38: Acquire the rising edge of the reference pulse current.

[0126] Acquire the rising edge of the reference pulse current in real time.

[0127] S39: Sending a driving control signal to each power switch sub-circuit in response to the rising edge.

[0128] When the rising edge of the reference pulse current is detected, that is, when the load circuit 301 needs to re-enter the working state to obtain the output current Io, each drive control signal is sent to the switch tube Q1, the switch tube Q2, ..., the switch tube Qn respectively, so that after the input of the DC power supply is adjusted by the first multi-phase interleaved conversion circuit 200, the output current Io is provided to the load circuit 301.

[0129] This application also provides an electronic device, see Figure 10 , Figure 10 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 40 includes a housing 41 and a third current regulating circuit 42 connected to the housing 41 .

[0130] It should be noted that the third current regulating circuit 42 described in this embodiment is the first current regulating circuit 100 or the second current regulating circuit described in any one of the above embodiments. Figures 1-9 And the related text content will not be repeated here.

[0131] The beneficial effects of the present application are as follows: Different from the prior art, the current regulation method provided by the present application obtains the output current of the regulated output sub-circuit, uses the error between the reference pulse current and the output current to obtain the regulated output value, and in response to the regulated output value being lower than the first threshold range, adjusts the regulated output value to within the first threshold range, generates a drive control signal using the regulated output value, and sends the drive control signal to any preset number of power switch sub-circuits in response to the reference pulse current being zero. Thus, when the reference pulse current is zero, by limiting the regulated output value and the controlled number of power switch sub-circuits, the output current is effectively regulated to within the second threshold range, thereby ensuring that the power supply demand of the multi-phase interleaved conversion circuit can be met in a timely manner when the multi-phase interleaved conversion circuit is reloaded, effectively avoiding operational errors caused by the load circuit remaining in an operating state when unloaded, and avoiding unnecessary component loss. Moreover, when the reference pulse current has different frequencies, by limiting the regulated output value to the first threshold range, the consistency and stability of the output current rising phase when the multi-phase interleaved conversion circuit is reloaded are effectively ensured, thereby ensuring good power supply quality and power supply stability.

[0132] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A current regulation method, applied to current regulation of a multi-phase interleaved conversion circuit, wherein the multi-phase interleaved conversion circuit comprises a power switch subcircuit and a regulation output subcircuit coupled to each other, wherein the number of the power switch subcircuits is at least two, and wherein: The current regulation method comprises: Obtaining an output current of the regulated output subcircuit; Obtaining an adjusted output value using an error value between a reference pulse current and the output current; In response to the regulated output value being lower than a first threshold range, the regulated output value is adjusted to be within the first threshold range; the step of adjusting the regulated output value to be within the first threshold range in response to the regulated output value being lower than the first threshold range comprises: obtaining a falling edge and a rising edge of the reference pulse current; in response to the falling edge, starting timing, so as to maintain the current regulated output value unchanged until the rising edge when the accumulated timing reaches a preset minimum duration, so as to adjust the regulated output value to be within the first threshold range; wherein the reference pulse current has different signal frequencies; generating a drive control signal using the adjustment output value; In response to the reference pulse current being zero, the drive control signal is sent to any preset number of the power switch sub-circuits to adjust the output current to within a second threshold range; wherein the preset number is less than the total number of the power switch sub-circuits.

2. The current regulation method according to claim 1, characterized in that: Before the step of obtaining the adjusted output value by using the error value between the reference pulse current and the output current, the method further includes: Receive the power supply adjustment signal sent by the host computer; The signal frequency of the reference pulse current is adjusted in response to the power supply adjustment signal.

3. The current regulation method according to claim 1, wherein: Before the step of adjusting the regulated output value to be within the first threshold range in response to the regulated output value being lower than the first threshold range, the method further includes: The first threshold range is set using the preset number and the second threshold range.

4. The current regulation method according to claim 1, wherein: In response to the regulated output value being lower than a first threshold range, the step of regulating the regulated output value to be within the first threshold range comprises: Obtaining a falling edge of the reference pulse current; In response to the falling edge, timing is started to adjust the error value to 0 when the accumulated timing reaches a preset minimum duration; The regulated output value is adjusted to be within the first threshold range using the regulated error value.

5. The current regulation method according to claim 4, characterized in that: The step of sending the drive control signal to any preset number of the power switch sub-circuits in response to the reference pulse current being zero includes: The driving control signal is sent to any of the preset number of the power switch sub-circuits in response to the falling edge.

6. The current regulation method according to claim 5, characterized in that: After the step of sending the drive control signal to any one of the preset number of power switch sub-circuits in response to the falling edge, the method further includes: Obtaining a rising edge of the reference pulse current; The driving control signal is sent to each of the power switch sub-circuits in response to the rising edge.

7. The current regulation method according to claim 4, characterized in that: The preset minimum duration is greater than or equal to an interval between the falling edge and a starting moment when the error value is within a third threshold range, and is less than a minimum cycle time of the reference pulse current.

8. The current regulation method according to claim 1, wherein: The step of starting timing in response to the falling edge and maintaining the current regulated output value unchanged until the rising edge when the accumulated timing reaches a preset minimum duration includes: In response to the falling edge, timing is started to set the adjustment flag low when the accumulated timing reaches a preset minimum duration; Maintaining the current adjustment output value unchanged; In response to the rising edge, the adjustment flag is set high, and the adjustment output value is obtained using the error value.

9. The current regulation method according to any one of claims 1 to 8, characterized in that: The adjusting output value obtained by utilizing the error value between the reference pulse current and the output current includes: Subtracting the output current from the reference pulse current to obtain the error value; Proportional-integral adjustment is performed on the error value to obtain the adjustment output value.

10. A current regulating circuit, characterized in that: The current regulating circuit is coupled to the multi-phase interleaved conversion circuit; The current regulating circuit adopts the current regulating method according to any one of claims 1 to 9 to regulate the current of the multi-phase interleaved conversion circuit.

11. An electronic device, characterized in that: The electronic device includes a housing and a current regulating circuit connected to the housing; Wherein, the current regulating circuit is the current regulating circuit as claimed in claim 10.

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