Receiving circuit and memory

Abstract

Embodiments of the present disclosure provide a receiving circuit and a memory, the receiving circuit comprising: a first buffer configured to receive a clock signal and a complementary clock signal, compare the clock signal with the complementary clock signal, and output a first intermediate signal and a second intermediate signal; a second buffer configured to receive the first intermediate signal and the second intermediate signal and amplify a voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal; the DC gain of the first buffer is smaller than the DC gain of the second buffer. The embodiment of the invention is at least beneficial to improving the duty ratio distortion of the clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a receiving circuit and a memory. Background Art

[0002] A clock is a very important component in digital circuits. It provides a stable time reference, enabling various parts in digital circuits to operate according to a predetermined timing sequence.

[0003] In a memory, the clock also plays a very important role. Data in the memory is usually transmitted in a certain timing sequence. The clock signal can control the input and output of data, ensuring that data is read or written at the correct time point. Through the synchronization function of the clock, the memory can cooperate with other digital circuit components to ensure the accuracy and reliability of data transmission. However, due to environmental influences, the clock signal received by the memory may have a duty cycle distortion, which may affect the normal operation of subsequent circuits. Summary of the Invention

[0004] Embodiments of the present disclosure provide a receiving circuit and a memory, which are at least beneficial to correcting the duty cycle of a clock signal.

[0005] On the one hand, an embodiment of the present disclosure provides a receiving circuit, including: a first buffer configured to receive a clock signal and a complementary clock signal, compare the clock signal with the complementary clock signal, and output a first intermediate signal and a second intermediate signal; a second buffer configured to receive the first intermediate signal and the second intermediate signal and amplify the voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal; the DC gain of the first buffer is less than the DC gain of the second buffer.

[0006] In some embodiments, the first buffer includes: a first input module configured to receive the clock signal and the complementary clock signal, connect to an active inductor module through a first node and a second node, and connect to a first current module through a third node and a fourth node; the first current module configured to provide current for the first buffer in response to a first bias voltage signal; the first intermediate signal is output from the first node, and the second intermediate signal is output from the second node.

[0007] In some embodiments, the first buffer further includes: a first capacitor, a first end of the first capacitor is connected to the third node, and a second end is connected to the fourth node.

[0008] In some embodiments, the active inductor module includes: a first active inductor including an N-channel transistor and connected between the first node and the ground terminal; a second active inductor including an N-channel transistor and connected between the second node and the ground terminal.

[0009] In some embodiments, the first active inductor includes: a first NMOS transistor, the gate of the first NMOS transistor is connected to the first end of a first resistor, the drain of the first NMOS transistor is connected to the first node, and the source of the first NMOS transistor is connected to the ground terminal; the first resistor, the second end of the first resistor is connected to the first node; a second capacitor, the first end of the second capacitor is connected to the gate of the first NMOS transistor, and the second end of the second capacitor is connected to the ground terminal.

[0010] In some embodiments, the second active inductor includes: a second NMOS transistor, the gate of the second NMOS transistor is connected to the first end of a second resistor, the drain of the second NMOS transistor is connected to the second node, and the source of the second NMOS transistor is connected to the ground terminal; the second resistor, the second end of the second resistor is connected to the second node; a third capacitor, the first end of the third capacitor is connected to the gate of the second NMOS transistor, and the second end of the third capacitor is connected to the ground terminal.

[0011] In some embodiments, the first input module includes: a first PMOS transistor, the gate of the first PMOS transistor receives the clock signal, the source of the first PMOS transistor is connected to the third node, and the drain of the first PMOS transistor is connected to the first node; a second PMOS transistor, the gate of the second PMOS transistor receives the complementary clock signal, the source of the second PMOS transistor is connected to the fourth node, and the drain of the second PMOS transistor is connected to the second node.

[0012] In some embodiments, the first current module includes: a third PMOS transistor, the gate of the third PMOS transistor receives the first bias voltage signal, the source of the third PMOS transistor is connected to the power supply terminal, and the drain of the third PMOS transistor is connected to the third node; a fourth PMOS transistor, the gate of the fourth PMOS transistor receives the first bias voltage signal, the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain of the fourth PMOS transistor is connected to the fourth node.

[0013] In some embodiments, the second buffer includes: a second input module configured to receive the first intermediate signal and the second intermediate signal, connect a load module through a fifth node and a sixth node, and connect a second current module through a seventh node; the second current module configured to provide current for the second buffer in response to a second bias voltage signal; the first output signal is output from the fifth node, and the second output signal is output from the sixth node.

[0014] In some embodiments, the second input module includes: a fifth PMOS transistor, the gate of the fifth PMOS transistor receives the first intermediate signal, the source of the fifth PMOS transistor is connected to the seventh node, and the drain of the fifth PMOS transistor is connected to the fifth node; a sixth PMOS transistor, the gate of the sixth PMOS transistor receives the second intermediate signal, the source of the sixth PMOS transistor is connected to the seventh node, and the drain of the sixth PMOS transistor is connected to the sixth node; the load module includes: a third resistor connected between the fifth node and the ground terminal; a fourth resistor connected between the sixth node and the ground terminal; the second current module includes: a seventh PMOS transistor, the gate of the seventh PMOS transistor receives the second bias voltage signal, the source of the seventh PMOS transistor is connected to the power supply terminal, and the drain of the seventh PMOS transistor is connected to the seventh node; an eighth PMOS transistor, the gate of the eighth PMOS transistor receives the second bias voltage signal, the source of the eighth PMOS transistor is connected to the power supply terminal, and the drain of the eighth PMOS transistor is connected to the seventh node.

[0015] In some embodiments, the DC gain of the first buffer is less than -20 dB.

[0016] Another aspect of the embodiments of the present disclosure further provides a memory, including the receiving circuit as described in any one of the foregoing.

[0017] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0018] The receiving circuit includes a first buffer and a second buffer. The first buffer receives a clock signal and a complementary clock signal, compares the clock signal with the complementary clock signal, and outputs a first intermediate signal and a second intermediate signal. The second buffer receives the first intermediate signal and the second intermediate signal and amplifies the voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal. The DC gain of the first buffer is less than the DC gain of the second buffer. If the input clock signal has a duty cycle distortion, due to the small DC gain of the first buffer, only the high-frequency components of the clock signal will be amplified, and the DC components in the clock signal will be suppressed. Therefore, the first buffer has a duty cycle correction effect on the clock signal. After correction, further amplification by the second buffer ensures the quality of the received clock signal, which is beneficial for accurate data sampling and transmission using the clock signal subsequently. Description of the Drawings

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a schematic circuit diagram of a receiving circuit provided by an embodiment of the present disclosure;

[0021] Figure 2 It is a waveform diagram of the input and output signals of the receiving circuit provided by an embodiment of the present disclosure;

[0022] Figure 3 It is a functional block diagram of a receiving circuit provided by an embodiment of the present disclosure;

[0023] Figure 4 It is another functional block diagram of a receiving circuit provided by an embodiment of the present disclosure;

[0024] Figure 5 It is a schematic circuit diagram of the first buffer in the receiving circuit provided by an embodiment of the present disclosure;

[0025] Figure 6 It is a schematic circuit diagram of the second buffer in the receiving circuit provided by an embodiment of the present disclosure;

[0026] Figure 7Signal waveform diagram of the first buffer of the receiving circuit provided by an embodiment of the present disclosure; Detailed implementation manners

[0027] The clock is a very important component in digital circuits. It provides a stable time reference, enabling each part in the digital circuit to work according to a predetermined timing sequence. In a memory, the clock also plays a very important role. The data in the memory is usually transmitted in a certain timing sequence. The clock signal can control the input and output of data, ensuring that the data is read or written at the correct time point. Through the synchronization function of the clock, the memory can cooperate with other digital circuit components to ensure the accuracy and reliability of data transmission. The clock signal is also used to control the internal operation timing of the memory. In the memory, various operations (such as reading, writing, refreshing, etc.) need to be carried out according to specific timing sequences. The clock signal can precisely control the execution order and time interval of these operations to ensure the normal operation of the memory.

[0028] Reference Figure 1 , Figure 1 is a schematic circuit diagram of a receiving circuit, which can be used to receive a clock signal. The receiving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first load resistor r1 and a second load resistor r2. The gate of the first transistor M1 receives the clock signal CKt, the source is connected to the drain of the third transistor M3, and the drain is connected to the first end of the first load resistor r1. The gate of the second transistor M2 receives the complementary clock signal CKc, the source is connected to the drain of the fourth transistor M4, and the drain is connected to the first end of the second load resistor r2. The sources of the third transistor M3 and the fourth transistor M4 are both connected to the power supply voltage, the gates are both connected to the bias voltage bias0, and the drains are both connected together with the drains of the first transistor M1 and the second transistor M2. The second ends of the first load resistor r1 and the second load resistor r2 are both connected to the ground terminal. The first transistor M1 and the second transistor M2 receive the clock signal CKt and the complementary clock signal CKc, compare the voltage magnitudes of the two signals, and amplify the voltage difference between the two signals to output two output signals OUT_t and OUT_c.

[0029] However, due to environmental influences, such as the instability of the clock source, the clock signal is affected by factors such as line attenuation, reflection, and interference during transmission. The clock signal received by the memory may have a duty cycle distortion. Duty cycle distortion means that the ratio between the high-level time and the low-level time of the clock signal has changed, resulting in the duty cycle of the clock signal no longer being 50%. Duty cycle distortion may have a negative impact on the normal operation of the circuit. For example, it may cause inaccurate data sampling and timing errors during transmission, which may lead to a decrease in the overall working performance of the memory.

[0030] Reference Figure 2 , there is a duty cycle distortion in the clock signal CKt and the complementary clock signal CKc input to the receiving circuit. In one clock cycle, the high-level time of the clock signal CKt (shown by the solid line) is Tb, and the low-level time is Ta. Its duty cycle is Tb / (Tb + Ta). Figure 2 In the case of Tb > Ta in Figure 2 , so the duty cycle of the clock signal CKt > 50%. The high-level time of the complementary clock signal CKc (shown by the dotted line) is Ta, and the low-level time is Tb. Its duty cycle is Ta / (Tb + Ta). Figure 1 The receiving circuit shown has a certain DC gain, approximately gm*r > 1, where gm is the transconductance of the first transistor M1 and the second transistor M2, and r is the resistance value of the first load resistor r1 and the second load resistor r2. The clock signal CKt has a higher high-level ratio, so the DC component of the clock signal CKt is larger. After passing through Figure 1 the receiving circuit, the DC component is amplified, so the output signal OUT_t is lifted higher, and its intermediate potential is the DC Voltage_OUT_t shown in the figure. Similarly, the output signal OUT_c will be lowered lower, and its intermediate potential is the DC Voltage_OUT_c shown in the figure. Compared with the initial intermediate potential DC Voltage, the high-level time (denoted as Tb1) of the output signal OUT_t becomes longer, and the low-level time (denoted as Ta1) becomes shorter. The duty cycle of the output signal OUT_t becomes further larger. Similarly, the duty cycle of the output signal OUT_c becomes further smaller. Therefore, through this receiving circuit, the duty cycle distortion problem of the clock signal is further aggravated, which is not conducive to the operation of the subsequent circuit.

[0031] From the above analysis, it is found that the main reason for the duty cycle distortion of the clock signal is the offset of the DC component in the clock signal. If the receiving circuit has a relatively high DC gain, then the offset of the DC component in the clock signal will be further amplified, thus aggravating the problem of duty cycle distortion.

[0032] An embodiment of the present disclosure provides a receiving circuit. The receiving circuit includes a first buffer and a second buffer. The first buffer receives a clock signal and a complementary clock signal, compares the clock signal with the complementary clock signal, and outputs a first intermediate signal and a second intermediate signal. The second buffer receives the first intermediate signal and the second intermediate signal, and amplifies the voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal. The DC gain of the first buffer is less than the DC gain of the second buffer. If the input clock signal has a duty cycle distortion, since the first buffer has a small DC gain, it only amplifies the high-frequency components of the clock signal and has an inhibitory effect on the DC component in the clock signal. Therefore, the first buffer has a duty cycle correction effect on the clock signal. After correction, it is further amplified by the second buffer, ensuring the quality of the received clock signal, which is beneficial to subsequent accurate data sampling and transmission using the clock signal.

[0033] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be implemented.

[0034] An embodiment of the present disclosure provides a receiving circuit, which will be described in detail below with reference to the accompanying drawings for the receiving circuit provided by the embodiment of the present disclosure. Figure 3 and Figure 4 are two functional block diagrams of the receiving circuit provided by an embodiment of the present disclosure; Figure 5 and Figure 6 are schematic circuit diagrams of the first buffer and the second buffer in the receiving circuit provided by an embodiment of the present disclosure; Figure 7 is a signal waveform diagram of the first buffer of the receiving circuit provided by an embodiment of the present disclosure.

[0035] Referring to Figure 3 , the receiving circuit includes: a first buffer 101 configured to receive a clock signal CKt and a complementary clock signal CKc, compare the clock signal CKt with the complementary clock signal Ckc, and output a first intermediate signal CKc_dcc and a second intermediate signal CKt_dcc; a second buffer 102 configured to receive the first intermediate signal CKc_dcc and the second intermediate signal CKt_dcc, and amplify the voltage difference between the first intermediate signal CKc_dcc and the second intermediate signal CKt_dcc to output a first output signal OUT_t and a second output signal OUT_c; the DC gain of the first buffer 101 is less than the DC gain of the second buffer 102.

[0036] It can be seen that the receiving circuit provided by the embodiments of the present disclosure includes two buffers. The first buffer 101 has a small DC gain, and its main function is to suppress the DC components of the received clock signal CKt and complementary clock signal CKc. If the input clock signal CKt and complementary clock signal CKc have duty cycle distortion, since the first buffer 101 has a small DC gain, it will only amplify the high-frequency components of the clock signal and has an inhibitory effect on the DC components in the clock signal. Therefore, the first buffer 101 has a duty cycle correction effect on the clock signal. The main function of the second buffer 102 is to amplify the clock signal. Because the clock signal CKt and complementary clock signal CKc received by the memory are often small-swing signals and need to be amplified before being used for subsequent circuit processing. After the first buffer 101 corrects the duty cycle-distorted clock signal and then further amplifies it through the second buffer 102, the quality of the received clock signal is ensured, which is beneficial to accurate data sampling and transmission using the clock signal subsequently.

[0037] In some embodiments, referring to Figure 4 , the first buffer 101 may include: a first input module 112, configured to receive the clock signal CKt and complementary clock signal CKc, connect to an active inductor module 113 through a first node net1 and a second node net2, and connect to a first current module 111 through a third node net3 and a fourth node net4; the first current module 111, configured to provide current for the first buffer 101 in response to a first bias voltage signal bias1; the first intermediate signal CKc_dcc is output from the first node net1, and the second intermediate signal CKt_dcc is output from the second node net2. By controlling the level value of the first bias voltage signal bias1 to adjust the magnitude of the current provided for the first buffer 101, it is beneficial to control the gain magnitude of the first buffer 101. The active inductor module 113 has a high high-frequency impedance and a low low-frequency impedance, so that it can provide a high high-frequency gain and a low DC gain for the first buffer 101.

[0038] In some embodiments, referring to Figure 5 , the first buffer 101 further includes: a first capacitor C1, the first end of the first capacitor is connected to the third node net3, and the second end is connected to the fourth node net4. Since the capacitor has a small impedance to the high-frequency components in the signal and a large impedance to the low-frequency components in the signal, adding the first capacitor C1 between the third node net3 and the fourth node net4 can separate the DC components of the clock signal CKt and complementary clock signal CKc, facilitating duty cycle correction.

[0039] In some embodiments, referring to Figure 5, the active inductor module 113 includes: a first active inductor 1131, including an N-channel transistor, connected between a first node net1 and a ground terminal; a second active inductor 1132, including an N-channel transistor, connected between a second node net2 and a ground terminal. Since the received clock signal CKt and the complementary clock signal CKc are a pair of differential input signals, two active inductors need to be provided as loads to output a second intermediate signal CKt_dcc and a first intermediate signal CKc_dcc from the first node net1 and the second node net2 respectively. Here, N-channel transistors are selected to form the active inductors 1131 and 1132, and P-channel transistors can also be selected to form the active inductors. Specifically, it can be selected according to the voltage magnitudes of the received clock signal CKt and the complementary clock signal CKc, as well as the structure of the first input module 111.

[0040] In some embodiments, referring to Figure 5 , the first active inductor 1131 includes: a first NMOS transistor MN1, the gate of the first NMOS transistor MN1 is connected to the first end of a first resistor R1, the drain of the first NMOS transistor MN1 is connected to the first node net1, and the source of the first NMOS transistor MN1 is connected to the ground terminal; a first resistor R1, the second end of the first resistor R1 is connected to the first node net1; a second capacitor C2, the first end of the second capacitor C2 is connected to the gate of the first NMOS transistor MN1, and the second end of the second capacitor C2 is connected to the ground terminal. Thus, the low-frequency impedance of the first active inductor 1131 is [(1 / gm1) / / r1], and the high-frequency impedance is (R1 / / r1), where gm1 is the transconductance of the first NMOS transistor MN1, r1 is the output resistance of the first NMOS transistor MN1 in the saturation region, and R1 is the resistance value of the first resistor R1. It can be seen that the low-frequency impedance of the first active inductor 1131 is less than the high-frequency impedance.

[0041] In some embodiments, continuing to refer to Figure 5, the second active inductor 1132 includes: a second NMOS transistor MN2, the gate of the second NMOS transistor MN2 is connected to the first end of the second resistor R2, the drain of the second NMOS transistor MN2 is connected to the second node net2, and the source of the second NMOS transistor MN2 is connected to the ground terminal; a second resistor R2, the second end of the second resistor R2 is connected to the second node net2; a third capacitor C3, the first end of the third capacitor C3 is connected to the gate of the second NMOS transistor MN2, and the second end of the third capacitor C3 is connected to the ground terminal. Thus, the low-frequency impedance of the second active inductor 1132 is [(1 / gm2) / / r2], and the high-frequency impedance is (R2 / / r2), where gm2 is the transconductance of the second NMOS transistor MN2, r2 is the output resistance of the second NMOS transistor MN2 when it is in the saturation region, and R2 is the resistance value of the second resistor R2. It can be seen that the low-frequency impedance of the second active inductor 1132 is less than the high-frequency impedance. As described above, by reasonably designing the sizes of the first NMOS transistor MN1 and the second NMOS transistor MN2, and reasonably selecting the resistance values of the first resistor R1 and the second resistor R2, a smaller low-frequency impedance and a larger high-frequency impedance of the first active inductor 1131 and the second active inductor 1132 can be achieved, thereby achieving a lower DC gain and a higher high-frequency gain of the first buffer 101, which is beneficial to suppressing the DC components in the input clock signal CKt and the complementary clock signal CKc and amplifying the high-frequency components therein, so as to achieve the effect of duty cycle correction.

[0042] In some embodiments, referring to Figure 5 , the first input module 112 includes: a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receives the clock signal CKt, the source of the first PMOS transistor MP1 is connected to the third node net3, and the drain of the first PMOS transistor MP1 is connected to the first node net1; a second PMOS transistor MP2, the gate of the second PMOS transistor MP2 receives the complementary clock signal CKc, the source of the second PMOS transistor MP2 is connected to the fourth node net4, and the drain of the second PMOS transistor MP2 is connected to the second node net2. Here, the PMOS transistors are selected as the input pair transistors to receive the clock signal CKt and the complementary clock signal CKc, considering that a part of the received clock signal may be attenuated in the transmission path, the signal level and swing are small, and using PMOS transistors can make the PMOS transistors fully turn on and better receive the clock signal CKt and the complementary clock signal CKc. In other cases, according to the actual signal situation, NMOS transistors can also be selected as the input pair transistors.

[0043] In some embodiments, continuing to refer to Figure 5, the first current module 111 includes: a third PMOS transistor MP3, the gate of the third PMOS transistor MP3 receives a first bias voltage signal bias1, the source of the third PMOS transistor MP3 is connected to the power supply terminal, and the drain of the third PMOS transistor MP3 is connected to the third node net3; a fourth PMOS transistor MP4, the gate of the fourth PMOS transistor MP4 receives the first bias voltage signal bias1, the source of the fourth PMOS transistor MP4 is connected to the power supply terminal, and the drain of the fourth PMOS transistor MP4 is connected to the fourth node net4. By controlling the level value of the first bias voltage signal bias1 to adjust the conduction degree of the third PMOS transistor MP3 and the fourth PMOS transistor MP4, it is beneficial to control the magnitude of the current provided by the first current module 111 to the first buffer 101. The selection of using PMOS transistors to provide current this time is a comprehensive consideration in combination with the first input module 112. In other cases, according to the actual circuit requirements, NMOS transistors can also be selected to provide current.

[0044] Reference Figure 7 , there is a duty cycle distortion in the clock signal CKt and the complementary clock signal CKc input to the first buffer 101. In one clock cycle, the high-level time of the clock signal CKt (shown by the solid line) is Tb, and the low-level time is Ta, and its duty cycle is Tb / (Tb + Ta). Figure 7 In the case of Tb > Ta, so the duty cycle of the clock signal CKt > 50%. The high-level time of the complementary clock signal CKc (shown by the dashed line) is Ta, and the low-level time is Tb, and its duty cycle is Ta / (Tb + Ta). Figure 7 In the case of Tb > Ta, so the duty cycle of the complementary clock signal CKc < 50%. Reference Figure 5, Intuitively analyzed, due to the existence of the first capacitor C1, the DC components of the clock signal CKt and the complementary clock signal CKc are separated in the first buffer 101. For the DC component of the clock signal CKt, the first PMOS transistor MP1, the third PMOS transistor MP3, the first NMOS transistor MN1, and the first resistor R1 together are equivalent to forming a single-ended common-source amplifier, which has a negative DC gain. That is, for the first intermediate signal CKc_dcc output relative to the input clock signal CKt, the signal phase is opposite, but the value of the DC component will be amplified. For the DC component of the complementary clock signal CKc, the second PMOS transistor MP2, the fourth PMOS transistor MP4, the second NMOS transistor MN2, and the second resistor R2 together are equivalent to forming a single-ended common-source amplifier, which has a negative DC gain. That is, for the second intermediate signal CKt_dcc output relative to the input complementary clock signal CKc, the signal phase is opposite, but the value of the DC component will be amplified. Since the duty cycle of the clock signal CKt > 50%, and the duty cycle of the complementary clock signal CKc < 50%, the DC component of the clock signal CKt is greater than the DC component of the complementary clock signal CKc. After the action of two equivalent single-ended common-source amplifiers, the DC component of the first intermediate signal CKc_dcc is greater than the DC component of the second intermediate signal CKt_dcc, so the effect that the first intermediate signal CKc_dcc is overall higher than the second intermediate signal CKt_dcc is presented. As Figure 7 shown, the intermediate potential DC Voltage_CKc_dcc of the first intermediate signal CKc_dcc is higher than the intermediate potential DC Voltage_CKt_dcc of the second intermediate signal CKt_dcc. Compared with the complementary clock signal CKc, the high-level time (denoted as Ta2) of the first intermediate signal CKc_dcc becomes longer, and the low-level time (denoted as Tb2) becomes shorter, and the duty cycle of the first intermediate signal CKc_dcc becomes larger. Similarly, compared with the clock signal CKt, the high-level time (denoted as Tb2) of the second intermediate signal CKt_dcc becomes shorter, and the low-level time (denoted as Ta2) becomes longer, and the duty cycle of the second intermediate signal CKt_dcc becomes smaller. Therefore, through this first buffer 101, the duty cycle distortion problem of the clock signal is corrected, which is beneficial to the operation of the subsequent circuit.

[0045] It can also be considered from another perspective, from Figure 5Understanding the overall circuit structure, as described above, the first active inductor 1131 and the second active inductor 1132 have a low low-frequency impedance. Therefore, the first buffer 101 has a low DC gain and can suppress the DC components in the input clock signal CKt and the complementary clock signal CKc. Since the duty cycle of the clock signal CKt > 50%, compared with the initial intermediate potential DC Voltage, the clock signal CKt has a positive DC component, and the DC component of the corresponding output second intermediate signal CKt_dcc is further reduced. Therefore, the second intermediate signal CKt_dcc is reduced as a whole. Since the duty cycle of the complementary clock signal CKc < 50%, compared with the initial intermediate potential DC Voltage, the complementary clock signal CKc has a negative DC component, and the absolute value of the DC component of the corresponding output first intermediate signal CKc_dcc is reduced. Therefore, the first intermediate signal CKc_dcc is increased as a whole. Compared with the clock signal CKt, the duty cycle of the second intermediate signal CKt_dcc becomes smaller, and compared with the complementary clock signal CKc, the duty cycle of the first intermediate signal CKc_dcc becomes larger, thus achieving the effect of duty cycle correction.

[0046] In some embodiments, the DC gain of the first buffer is less than -20 dB. This can ensure that the DC components in the clock signal CKt and the complementary clock signal CKc are reduced by at least 100 times. Therefore, the first buffer has a better DC suppression effect on the received clock signal CKt and the complementary clock signal CKc, which is beneficial to the correction of duty cycle distortion.

[0047] In some embodiments, referring to Figure 4 , the second buffer 102 includes: a second input module 122 configured to receive the first intermediate signal CKc_dcc and the second intermediate signal CKt_dcc, connect to the load module 123 through the fifth node net5 and the sixth node net6, and connect to the second current module 121 through the seventh node net7; the second current module 121 configured to provide current for the second buffer 102 in response to the second bias voltage signal bias2; the first output signal OUT_t is output from the fifth node net5, and the second output signal OUT_c is output from the sixth node net6. By controlling the level value of the second bias voltage signal bias2 to adjust the magnitude of the current provided for the second buffer 102, it is beneficial to control the gain magnitude of the second buffer 102. The load module 123 has a high impedance, so it can provide a high gain for the second buffer 102, amplify the voltage difference of the duty cycle-corrected clock signal, which is beneficial to subsequent data sampling and transmission.

[0048] In some embodiments, referring to Figure 6, the second input module 122 includes: a fifth PMOS transistor MP5, the gate of the fifth PMOS transistor MP5 receives a first intermediate signal CKc_dcc, the source of the fifth PMOS transistor MP5 is connected to the seventh node net7, and the drain of the fifth PMOS transistor MP5 is connected to the fifth node net5; a sixth PMOS transistor MP6, the gate of the sixth PMOS transistor MP6 receives a second intermediate signal CKt_dcc, the source of the sixth PMOS transistor MP6 is connected to the seventh node net7, and the drain of the sixth PMOS transistor MP6 is connected to the sixth node net6; the load module 123 includes: a third resistor R3 connected between the fifth node net5 and the ground terminal; a fourth resistor R4 connected between the sixth node net6 and the ground terminal; the second current module 121 includes: a seventh PMOS transistor MP7, the gate of the seventh PMOS transistor MP7 receives a second bias voltage signal bias2, the source of the seventh PMOS transistor MP7 is connected to the power supply terminal, and the drain of the seventh PMOS transistor MP7 is connected to the seventh node net7; an eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 receives a second bias voltage signal bias2, the source of the eighth PMOS transistor MP8 is connected to the power supply terminal, and the drain of the eighth PMOS transistor MP8 is connected to the seventh node net7. Here, the three terminals of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are correspondingly connected together, and an equivalent PMOS transistor can also be used to achieve the function of current control. There is no limit to the number of PMOS transistors here, as long as enough current can be provided. The advantage of using two PMOS transistors MP7 and MP8 here is that considering the circuit layout can be symmetrically arranged, making the circuit have better performance. Here, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are selected as input pair transistors, combined with the signal amplitudes of the first intermediate signal CKc_dcc and the second intermediate signal CKt_dcc, to ensure that the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 can be fully turned on and operate in the saturation region. According to the actual situation of the signal, NMOS transistors can also be selected as input pair transistors. By selecting the resistance values of the third resistor R3 and the fourth resistor R4, a higher gain can be provided for the second buffer 102, and the voltage difference of the duty cycle corrected clock signal can be amplified, which is beneficial for subsequent data sampling and transmission.

[0049] Another embodiment of the present disclosure further provides a memory, including the aforementioned receiving circuit. The receiving circuit includes a first buffer and a second buffer. The first buffer receives a clock signal and a complementary clock signal, compares the clock signal with the complementary clock signal, and outputs a first intermediate signal and a second intermediate signal. The second buffer receives the first intermediate signal and the second intermediate signal and amplifies the voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal. The DC gain of the first buffer is less than the DC gain of the second buffer. If the input clock signal has a duty cycle distortion, since the first buffer has a relatively small DC gain, it will only amplify the high-frequency components of the clock signal and has an inhibitory effect on the DC component in the clock signal. Therefore, the first buffer has a duty cycle correction effect on the clock signal. After correction, further amplification by the second buffer ensures the quality of the received clock signal, which is beneficial for subsequent accurate data sampling and transmission using the clock signal and improves the performance of the memory.

[0050] The embodiments provided by the present disclosure are applicable to and not limited to dynamic random access memories, static random access memories (SRAM). Among them, DRAM includes but is not limited to double data rate synchronous dynamic random access memories (DDR), low power double data rate synchronous dynamic random access memories (LPDDR). Double data rate synchronous dynamic random access memories further include DDR4, DDR5, DDR6, etc. Low power double data rate synchronous dynamic random access memories further include LPDDR4, LPDDR5, LPDDR6, etc.

[0051] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined in the claims.

Claims

1. A receiving circuit, characterized in that, Comprising: A first buffer configured to receive a clock signal and a complementary clock signal, compare the clock signal with the complementary clock signal, and output a first intermediate signal and a second intermediate signal; A second buffer configured to receive the first intermediate signal and the second intermediate signal and amplify the voltage difference between the first intermediate signal and the second intermediate signal to output a first output signal and a second output signal; The DC gain of the first buffer is less than the DC gain of the second buffer.

2. The receiving circuit according to claim 1, wherein The first buffer includes: A first input module configured to receive the clock signal and the complementary clock signal, connect to an active inductor module through a first node and a second node, and connect to a first current module through a third node and a fourth node; The first current module configured to provide current for the first buffer in response to a first bias voltage signal; The first intermediate signal is output from the first node, and the second intermediate signal is output from the second node.

3. The receiving circuit according to claim 2, wherein The first buffer further includes: A first capacitor, the first end of the first capacitor is connected to the third node, and the second end is connected to the fourth node.

4. The receiving circuit according to claim 3, characterized in that The active inductor module includes: A first active inductor including an N-channel transistor connected between the first node and the ground terminal; A second active inductor including an N-channel transistor connected between the second node and the ground terminal.

5. The receiving circuit according to claim 4, wherein The first active inductor includes: A first NMOS transistor, the gate of the first NMOS transistor is connected to the first end of a first resistor, the drain of the first NMOS transistor is connected to the first node, and the source of the first NMOS transistor is connected to the ground terminal; The first resistor, the second end of the first resistor is connected to the first node; A second capacitor, the first end of the second capacitor is connected to the gate of the first NMOS transistor, and the second end is connected to the ground terminal.

6. The receiving circuit according to claim 5, wherein The second active inductor includes: A second NMOS transistor, the gate of the second NMOS transistor is connected to the first end of a second resistor, the drain of the second NMOS transistor is connected to the second node, and the source of the second NMOS transistor is connected to the ground terminal; The second resistor, the second end of the second resistor is connected to the second node; A third capacitor, the first end of the third capacitor is connected to the gate of the second NMOS transistor, and the second end is connected to the ground terminal.

7. The receiving circuit according to claim 2, wherein The first input module includes: A first PMOS transistor, the gate of the first PMOS transistor receives the clock signal, the source of the first PMOS transistor is connected to the third node, and the drain of the first PMOS transistor is connected to the first node; A second PMOS transistor, the gate of the second PMOS transistor receives the complementary clock signal, the source of the second PMOS transistor is connected to the fourth node, and the drain of the second PMOS transistor is connected to the second node.

8. The receiving circuit according to claim 2, characterized in that The first current module includes: A third PMOS transistor, the gate of the third PMOS transistor receives the first bias voltage signal, the source of the third PMOS transistor is connected to the power supply terminal, and the drain of the third PMOS transistor is connected to the third node; A fourth PMOS transistor, wherein a gate of the fourth PMOS transistor receives the first bias voltage signal, a source of the fourth PMOS transistor is connected to a power supply terminal, and a drain of the fourth PMOS transistor is connected to the fourth node.

9. The receiving circuit according to claim 1, wherein The second buffer includes: A second input module configured to receive the first intermediate signal and the second intermediate signal, connect to a load module through a fifth node and a sixth node, and connect to a second current module through a seventh node; The second current module configured to provide current for the second buffer in response to a second bias voltage signal; The first output signal is output from the fifth node, and the second output signal is output from the sixth node.

10. The receiving circuit according to claim 9, wherein The second input module includes: A fifth PMOS transistor, wherein a gate of the fifth PMOS transistor receives the first intermediate signal, a source of the fifth PMOS transistor is connected to the seventh node, and a drain of the fifth PMOS transistor is connected to the fifth node; A sixth PMOS transistor, wherein a gate of the sixth PMOS transistor receives the second intermediate signal, a source of the sixth PMOS transistor is connected to the seventh node, and a drain of the sixth PMOS transistor is connected to the sixth node; The load module includes: A third resistor connected between the fifth node and a ground terminal; A fourth resistor connected between the sixth node and a ground terminal; The second current module includes: A seventh PMOS transistor, wherein a gate of the seventh PMOS transistor receives the second bias voltage signal, a source of the seventh PMOS transistor is connected to a power supply terminal, and a drain of the seventh PMOS transistor is connected to the seventh node; An eighth PMOS transistor, wherein a gate of the eighth PMOS transistor receives the second bias voltage signal, a source of the eighth PMOS transistor is connected to a power supply terminal, and a drain of the eighth PMOS transistor is connected to the seventh node.

11. The receiving circuit according to claim 1, wherein, The DC gain of the first buffer is less than -20 dB.

12. A memory, characterized in that, A receiving circuit includes the receiving circuit according to any one of claims 1-11.

Images