Low-power Sigma-Delta modulator

Abstract

The invention discloses a low-power-consumption Sigma-Delta modulator, and belongs to the field of analog integrated circuit design. A low-power Sigma-Delta modulator comprises a first operational amplifier unit, a second operational amplifier unit, a third operational amplifier unit, a comparator and a digital-to-analog converter. The first operational amplifier unit is constructed as a first-stage integrator, the second operational amplifier unit is constructed as a second-stage integrator and a third-stage integrator, and the third operational amplifier unit is constructed as a fourth-stage integrator and an active adder. According to the Sigma-Delta modulator, the function of a four-order SDM can be achieved only through three operational amplifiers, the number of the operational amplifiers in the Sigma-Delta modulator of a four-order CIFF structure is reduced from traditional five to three, power consumption is reduced by about 40%, the area is reduced by about 40%, and the requirements for low power consumption and microminiaturization of an MEMS sensor are met.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and particularly relates to a low-power Sigma-Delta modulator. Background Art

[0002] With the rapid development of integrated circuit technology, especially along with the development of MEMS inertial sensor technology, the requirements for the power consumption and area of various MEMS inertial sensor interface chips such as MEMS accelerometer sensors, gyroscope sensors, and pressure sensors are becoming more stringent.

[0003] As the core circuit of the MEMS inertial sensor interface chip, the Sigma-Delta modulator (SDM) circuit with too high power consumption will cause adverse effects such as increased temperature, increased thermal noise, and parameter drift, resulting in reduced chip life and poor stability. For the traditional 4th-order CIFF structure SDM, it is necessary to configure a separate operational amplifier for each integrator and summing module, resulting in high circuit power consumption and large physical area, and it is difficult to meet the requirements of MEMS sensors for miniaturization and low power consumption.

[0004] Therefore, it is necessary to optimize and improve the traditional 4th-order CIFF structure SDM circuit to reduce its power consumption and area, and further meet the requirements of high stability and miniaturization of MEMS inertial sensors. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a low-power Sigma-Delta modulator to reduce the power consumption of the Sigma-Delta modulator circuit and reduce the area of the Sigma-Delta modulator circuit.

[0006] The present invention is realized through the following technical solutions: A low-power Sigma-Delta modulator, comprising:

[0007] A first operational amplifier unit, the first operational amplifier unit is configured to sample a differential input signal in the clock Φ1 and Φ1d phases, and integrate the difference between the differential input signal and a feedback signal in the clock Φ2 and Φ2d phases;

[0008] A second operational amplifier unit, the second operational amplifier unit is configured to integrate the differential output signal output by the first operational amplifier unit in the clock Φ1 and Φ1d phases, sample the integrated differential output signal, and integrate the sampled differential output signal in the clock Φ2 and Φ2d phases, and sample the differential output signal output by the first operational amplifier unit in the clock Φ2 and Φ2d phases;

[0009] The third operational amplifier unit is configured to integrate the differential output signal output by the second operational amplifier unit during the clock Φ1 and Φ1d phases, and perform reset and sampling as an active adder, and sample the differential output signal output by the second operational amplifier unit during the clock Φ2 and Φ2d phases, and perform summation as an active adder;

[0010] The comparator is configured to quantify the summation result of the active adder during the clock Φ2 and Φ2d phases and output a bitstream result;

[0011] The digital-to-analog converter is configured to output a reference voltage according to the bitstream result during the clock Φ2 and Φ2d phases, and feedback the reference voltage as a feedback signal to the first operational amplifier unit;

[0012] Among them, the clock Φ1 and the clock Φ2 are two-phase non-overlapping clocks, the clock Φ1d is the delayed phase clock of the clock Φ1, and the clock Φ2d is the delayed phase clock of the clock Φ2.

[0013] Further, the first operational amplifier unit includes a first operational amplifier A1, a sampling capacitor C S11 and C S12 , an integrating capacitor C I11 and C I12 , and switches S1 to S8;

[0014] The first end of S1 serves as the positive differential signal input terminal, the first end of S3 serves as the first feedback signal terminal, and the second end of S1 is respectively connected to the second end of S3 and the first end of C S11 . The second end of C S11 is respectively connected to the first end of S5 and the first end of S7. The second end of S5 is grounded, and the second end of S7 is connected to the positive input terminal of A1;

[0015] The first end of S2 serves as the negative differential signal input terminal, the first end of S4 serves as the second feedback signal terminal, and the second end of S2 is respectively connected to the second end of S4 and the first end of C S12 . The second end of C S12 is respectively connected to the first end of S6 and the first end of S8. The second end of S6 is grounded, and the second end of S8 is connected to the negative input terminal of A1;

[0016] The first end of C I11 is connected to the positive input terminal of A1, the second end of C I11 is connected to the negative output terminal of A1, the first end of C I12 is connected to the negative input terminal of A1, and the second end of C I12 is connected to the positive output terminal of A1.

[0017] Further, the second operational amplifier unit includes a second operational amplifier A2 and sampling capacitors C S21 and C S22 , sampling capacitors C S31 and C S32 , integrating capacitors C I21 and C I22 , integrating capacitors C I31 and C I32 , and switches S9 to S 26 ;

[0018] The first ends of C S21 are respectively connected to the negative output end of A1 and the first end of S9. The second end of S9 is grounded. The second ends of C S21 are respectively connected to the first end of S 11 and the first end of S 13 . The second end of S 11 is grounded. The second end of S 13 is connected to the first end of S 15 . The second end of S 15 is connected to the positive input end of A2;

[0019] The first ends of C S22 are respectively connected to the positive output end of A1 and the first end of S 10 . The second end of S 10 is grounded. The second ends of C S22 are respectively connected to the first end of S 12 and the first end of S 14 . The second end of S 12 is grounded. The second end of S 14 is connected to the first end of S 16 . The second end of S 16 is connected to the negative input end of A2;

[0020] The first end of C I21 is connected to the first end of S 15 . The second end of C I21 is connected to the first end of S 23 . The second end of S 23 is connected to the negative output end of A2. The first end of S 17 is connected to the positive input end of A2. The second end of S 17 is respectively connected to the first end of S 19 and the first end of C I31 . The second end of C I31 is connected to the first end of S 25 . The second end of S 25 is connected to the negative output end of A2. The second end of S 19 is respectively connected to the first end of S 21 and the first end of C S31is connected to the first end, S 21 is grounded at the second end, C S31 The second end of is connected to S 23 at the first end;

[0021] C I22 The first end of is connected to S 16 at the first end, C I22 The second end of is connected to S 24 at the first end, S 24 The second end of is connected to the positive output terminal of A2, S 18 The first end of is connected to the negative input terminal of A2, S 18 The second end of is respectively connected to S 20 at the first end and C I32 at the first end, C I32 The second end of is connected to S 26 at the first end, S 26 The second end of is connected to the positive output terminal of A2, S 20 The second end of is respectively connected to S 22 at the first end and C S32 at the first end, S 22 The second end of is grounded, C S32 The second end of is connected to S 24 at the first end.

[0022] Furthermore, the third operational amplifier unit includes a third operational amplifier A3, a sampling capacitor C S41 and C S42 , an integrating capacitor C I41 and C I42 , switches S 27 ~S 52 , a feed-forward summing capacitor C A01 、C A11 、C A21 、C A31 、C A41 、C A02 、C A12 、C A22 、C A32 、C A42 , a feedback capacitor C F11 and C F12 ;

[0023] C S41 The first end of is connected to the first end of S 25 The second end of C S41 is respectively connected to the first end of S 27 and the first end of S 29 The second end of S 27 is grounded, S 29 The second end of is connected to S31 is connected to the first end of, S 31 The second end of is connected to the positive input terminal of A3; C S42 The first end of is connected to S 26 The first end of is connected to, C S42 The second ends of are respectively connected to S 28 The first end of and S 30 The first end of is connected to, S 28 The second end of is grounded, S 30 The second end of is connected to S 32 The first end of is connected to, S 32 The second end of is connected to the negative input terminal of A3;

[0024] S 39 The first end of is connected to the positive differential signal input terminal, S 39 The second end of is connected to C A01 The first end of and S 51 The first end of is connected to, S 51 The second end of is grounded, C A01 The second end of is respectively C A11 The first end of, C A21 The first end of, C A31 The first end of and S 33 The first end of is connected to, C A11 The second end of is connected to the positive output terminal of A1, C A21 The second end of is respectively connected to S 23 The first end of and S 35 The first end of is connected to, S 35 The second end of is grounded, C A31 The second end of is respectively connected to S 26 The first end of and S 37 The first end of is connected to, S 37 The second end of is grounded, S 33 The second end of is connected to the positive input terminal of A3; S 40 The first end of is connected to the negative differential signal input terminal, S 40 The second end of is connected to C A02 The first end of and S 52 The first end of is connected to, S 52 The second end of is grounded, C A02 The second end of is respectively connected to C A12 The first end of, C A22 The first end of, C A32 The first end of and S 34 The first end of is connected to, C A12 The second end of is connected to the negative output terminal of A2, C A22 The second end of is respectively connected to S 24 The first end of and S 36 The first end of is connected to, S 36The second end of is grounded, C A32 The second ends of are respectively connected to S 25 The first end of and S 38 The first end of are connected, S 38 The second end of is grounded, S 34 The second end of is connected to the negative input terminal of A3;

[0025] C I41 The first end of is connected to the first end of S 31 The second end of C is connected to the first end of S I41 The second end of is connected to the first end of S 45 The second end of S is connected to the negative output terminal of A3, C 45 The first end of is connected to the first end of S F11 The second end of C is connected to the first end of S 33 The second end of is connected to the first end of S F11 The second end of is respectively connected to the first end of S 47 The first end of, S 49 The first end of and the first input terminal of the comparator are connected, S 47 The second end of is connected to the negative output terminal of A3, S 49 The second end of is grounded, C A41 The first end of is respectively connected to the first end of S 33 The first end of and S 41 The first end of are connected, S 41 The second end of is grounded, C A41 The second end of is respectively connected to the first end of S 43 The first end of and S 45 The first end of are connected, S 43 The second end of is grounded; C I42 The first end of is connected to the first end of S 32 The second end of C is connected to the first end of S I42 The second end of is connected to the first end of S 46 The second end of S is connected to the positive output terminal of A3, C 46 The first end of is connected to the first end of S F12 The second end of C is connected to the first end of S 34 The second end of is respectively connected to the first end of S F12 The first end of, S 48 The first end of, S 50 The first end of and the second input terminal of the comparator are connected, S 48 The second end of is connected to the positive output terminal of A3, S 50 The second end of is grounded, C A42 The first end of is respectively connected to the first end of S 34 The first end of and S 42 The first end of are connected, S 42 The second end of is grounded, C A42 The second end of is respectively connected to the first end of S 44 The first end of and S 46 The first end of are connected, S44 The second end is grounded.

[0026] Furthermore, the ground in the first operational amplifier unit, the second operational amplifier unit, and the third operational amplifier unit is a common-mode level.

[0027] Furthermore, the control timings of switches S1, S2, S9, S 10 , S 37 , S 38 , S 39 and S 40 are the same as the clock Φ1d, and the control timings of switches S3, S4, S 35 , S 36 , S 43 , S 44 , S 51 and S 52 are the same as the clock Φ2d, and the control timings of switches S5, S6, S 13 , S 14 , S 15 , S 16 , S 21 , S 22 , S 23 , S 24 , S 29 , S 30 , S 31 , S 32 , S 41 , S 42 , S 45 , S 46 , S 49 and S 50 are the same as the clock Φ1, and the control timings of switches S7, S8, S 11 , S 12 , S 17 , S 18 , S 19 , S 20 , S 25 , S 26 , S 27 , S 28 , S 33 , S 34 , S 47 and S 48 are the same as the clock Φ2.

[0028] Furthermore, the capacitance value of C S11 is the same as the capacitance value of C S12 , the capacitance value of C S21 is the same as the capacitance value of C S22 , the capacitance value of C S31 is the same as the capacitance value of C S32 , CS41 has the same capacitance value as C S42 has the same capacitance value; C I11 has the same capacitance value as C I12 has the same capacitance value; C I21 has the same capacitance value as C I22 has the same capacitance value; C I31 has the same capacitance value as C I32 has the same capacitance value; C I41 has the same capacitance value as C I42 has the same capacitance value; C A01 has the same capacitance value as C A02 has the same capacitance value; C A11 has the same capacitance value as C A12 has the same capacitance value; C A21 has the same capacitance value as C A22 has the same capacitance value; C A31 has the same capacitance value as C A32 has the same capacitance value; C A41 has the same capacitance value as C A42 has the same capacitance value; C F11 has the same capacitance value as C F12 has the same capacitance value.

[0029] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0030] (1) The Sigma-Delta modulator in the present invention only requires 3 operational amplifiers to achieve the function of a 4th-order SDM, reducing the number of operational amplifiers in the Sigma-Delta modulator with a 4th-order CIFF structure from the traditional 5 to 3, reducing power consumption by about 40% and area by about 40%, meeting the requirements of low power consumption and miniaturization of MEMS sensors;

[0031] (2) In the traditional 4th-order CIFF structure SDM (Sigma-Delta modulator), each integrator needs to sample at clock Φ1 and clock Φ1d. At this time, the operational amplifier of the integrator does not work but consumes current, and integration only occurs at clock Φ2 and clock Φ2d. At this time, the operational amplifier of the integrator starts to work; while in the Sigma-Delta modulator of the present invention, except for the first operational amplifier A1, the second operational amplifier A2 and the third operational amplifier A3 are always working and do not waste current, significantly reducing the power consumption of the circuit;

[0032] (3) In the traditional structure SDM, 3 operational amplifiers can only achieve the effect of 3rd-order noise shaping. The Sigma-Delta modulator in the present invention achieves the effect of 4th-order noise shaping under the sharing of operational amplifiers, improving the accuracy of MEMS sensors and meeting the high-precision requirements of MEMS sensors;

[0033] (4) Compared with the traditional passive summing circuit, the present invention adopts an active summing circuit, utilizes the virtual short characteristic of the operational amplifier, enhances the complete transmission of signals, and at the same time, due to the existence of the feedback network, suppresses the charge injection and clock feedthrough effects, and enhances the anti-interference ability. Description of the Drawings

[0034] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, form a part of this application, and do not constitute a limitation on the embodiments of the present invention. In the drawings:

[0035] Figure 1 It is a structural block diagram of a Sigma-Delta modulator in the present invention;

[0036] Figure 2 It is a circuit schematic diagram of a Sigma-Delta modulator in the present invention;

[0037] Figure 3 It is a working timing diagram of a Sigma-Delta modulator in the present invention;

[0038] Figure 4 It is a circuit schematic diagram of a Sigma-Delta modulator in the Φ1 and Φ1d stages in the present invention;

[0039] Figure 5 It is a circuit schematic diagram of a Sigma-Delta modulator in the Φ2 and Φ2d stages in the present invention. Specific Embodiments

[0040] The technical solution of the present invention will be further described below in conjunction with the drawings and through specific embodiments.

[0041] Among them, the drawings are only used for exemplary illustration, showing only schematic diagrams, rather than physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0042] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and cannot be understood as a limitation of the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0043] In the description of the present invention, unless otherwise clearly specified and limited, if terms such as "connection" are used to indicate the connection relationship between components, this term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] As Figures 1 to 5 shown, this embodiment discloses a low-power Sigma-Delta modulator.

[0045] As Figure 1 shown, a low-power Sigma-Delta modulator includes a first operational amplifier unit, a second operational amplifier unit, a third operational amplifier unit, a comparator Q, and a digital-to-analog converter DAC. The first operational amplifier unit is configured as a first-stage integrator, the second operational amplifier unit is configured as a second-stage integrator and a third-stage integrator, and the third operational amplifier unit is configured as a fourth-stage integrator and an active adder.

[0046] The first operational amplifier unit is configured to sample the differential input signal as a first-stage integrator during the clock phases Φ1 and Φ1d, and integrate the difference between the differential input signal and the feedback signal as a first-stage integrator during the clock phases Φ2 and Φ2d.

[0047] The second operational amplifier unit is configured to integrate the differential output signal output by the first operational amplifier unit as a first-stage integrator as a second-stage integrator during the clock phases Φ1 and Φ1d, and sample the differential output signal after integration as a second-stage integrator as a third-stage integrator, and sample the differential output signal output by the first operational amplifier unit as a first-stage integrator as a second-stage integrator during the clock phases Φ2 and Φ2d, and integrate the differential output signal after sampling as a second-stage integrator as a third-stage integrator.

[0048] The third operational amplifier unit is configured to, during the clock Φ1 and Φ1d phases, act as a fourth-stage integrator to integrate the differential output signal output by the second operational amplifier unit acting as a third-stage integrator, and act as an active adder for reset and sampling, and during the clock Φ2 and Φ2d phases, act as a fourth-stage integrator to sample the differential output signal output by the second operational amplifier unit acting as a third-stage integrator, and act as an active adder for summation.

[0049] The comparator Q is configured to, during the clock Φ2 and Φ2d phases, quantize the summation result of the active adder and output a bitstream result.

[0050] The digital-to-analog converter DAC is configured to, during the clock Φ2 and Φ2d phases, output a reference voltage according to the bitstream result, and feedback the reference voltage as a feedback signal to the first operational amplifier unit.

[0051] The clock Φ1 and the clock Φ2 are two-phase non-overlapping clocks, the clock Φ1d is a delayed-phase clock of the clock Φ1, and the clock Φ2d is a delayed-phase clock of the clock Φ2. The delay amounts of the clock Φ1 and the clock Φ2 are designed and determined according to the actual circuit.

[0052] In some embodiments of this embodiment, as Figure 2 shown, the first operational amplifier unit includes a first operational amplifier A1, an eleventh sampling capacitor C S11 , a twelfth sampling capacitor C S12 , an eleventh integrating capacitor C I11 , a twelfth integrating capacitor C I12 , a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8.

[0053] The first end of the first switch S1 serves as the positive differential signal input terminal VIP, the first end of the third switch S3 serves as the first feedback signal terminal VDAC1, the second end of the first switch S1 is respectively connected to the second end of the third switch S3 and the first end of the eleventh sampling capacitor C S11 , the second end of the eleventh sampling capacitor C S11 is respectively connected to the first end of the fifth switch S5 and the first end of the seventh switch S7, the second end of the fifth switch S5 is grounded, and the second end of the seventh switch S7 is connected to the positive input terminal of the first operational amplifier A1.

[0054] The first end of the second switch S2 serves as the negative differential signal input terminal VIN, the first end of the fourth switch S4 serves as the second feedback signal terminal VDAC2, the second end of the second switch S2 is respectively connected to the second end of the fourth switch S4 and the first end of the twelfth sampling capacitor C S12 and the second end of the twelfth sampling capacitor CS12 The second ends are respectively connected to the first end of the sixth switch S6 and the first end of the eighth switch S8. The second end of the sixth switch S6 is grounded, and the second end of the eighth switch S8 is connected to the negative input terminal of the first operational amplifier A1.

[0055] The eleventh integrating capacitor C I11 The first end is connected to the positive input terminal of the first operational amplifier A1, and the eleventh integrating capacitor C I11 The second end is connected to the negative output terminal of the first operational amplifier A1, and the twelfth integrating capacitor C I12 The first end is connected to the negative input terminal of the first operational amplifier A1, and the twelfth integrating capacitor C I12 The second end is connected to the positive output terminal of the first operational amplifier A1.

[0056] In some embodiments of this embodiment, as Figure 2 shown, the second operational amplifier unit includes a second operational amplifier A2, a twenty-first sampling capacitor C S21 , a twenty-second sampling capacitor C S22 , a thirty-first sampling capacitor C S31 , a thirty-second sampling capacitor C S32 , a twenty-first integrating capacitor C I21 , a twenty-second integrating capacitor C I22 , a thirty-first integrating capacitor C I31 , a thirty-second integrating capacitor C I32 , a ninth switch S9, a tenth switch S 10 , an eleventh switch S 11 , a twelfth switch S 12 , a thirteenth switch S 13 , a fourteenth switch S 14 , a fifteenth switch S 15 , a sixteenth switch S 16 , a seventeenth switch S 17 , an eighteenth switch S 18 , a nineteenth switch S 19 , a twentieth switch S 20 , a twenty-first switch S 21 , a twenty-second switch S 22 , a twenty-third switch S 23 , a twenty-fourth switch S 24 , a twenty-fifth switch S 25 and a twenty-sixth switch S 26 .

[0057] The first end of the twenty-first sampling capacitor C S21 is respectively connected to the negative output terminal of the first operational amplifier A1 and the first end of the ninth switch S9. The second end of the ninth switch S9 is grounded, and the twenty-first sampling capacitor CS21 The second ends are respectively connected to the positive input terminal of the eleventh switch S 11 and the first end of the thirteenth switch S 13 . The second end of the eleventh switch S 11 is grounded. The second end of the thirteenth switch S 13 is connected to the first end of the fifteenth switch S 15 . The second end of the fifteenth switch S 15 is connected to the positive input terminal of the second operational amplifier A2.

[0058] The first ends of the twenty-second sampling capacitors C S22 are respectively connected to the positive output terminal of the first operational amplifier A1 and the first end of the tenth switch S 10 . The second end of the tenth switch S 10 is grounded. The second end of the twenty-second sampling capacitor C S22 is respectively connected to the first end of the twelfth switch S 12 and the first end of the fourteenth switch S 14 . The second end of the twelfth switch S 12 is grounded. The second end of the fourteenth switch S 14 is connected to the first end of the sixteenth switch S 16 . The second end of the sixteenth switch S 16 is connected to the negative input terminal of the second operational amplifier A2.

[0059] The first end of the twenty-first integrating capacitor C I21 is connected to the first end of the fifteenth switch S 15 . The second end of the twenty-first integrating capacitor C I21 is connected to the first end of the twenty-third switch S 23 . The second end of the twenty-third switch S 23 is connected to the negative output terminal of the second operational amplifier A2. The first end of the seventeenth switch S 17 is connected to the positive input terminal of the second operational amplifier A2. The second end of the seventeenth switch S 17 is respectively connected to the first end of the nineteenth switch S 19 and the first end of the thirty-first integrating capacitor C I31 . The second end of the thirty-first integrating capacitor C I31 is connected to the first end of the twenty-fifth switch S 25 . The second end of the twenty-fifth switch S 25 is connected to the negative output terminal of the second operational amplifier A2. The second end of the nineteenth switch S 19 is respectively connected to the first end of the twenty-first switch S 21 and the first end of the thirty-first sampling capacitor C S31 . The second end of the twenty-first switch S 21The second terminal of which is grounded, and the thirty-first sampling capacitor C S31 The second terminal of which is connected to the twenty-third switch S 23 The first terminal of which is connected.

[0060] The first terminal of the twenty-second integrating capacitor C I22 Is connected to the first terminal of the sixteenth switch S 16 The second terminal of the twenty-second integrating capacitor C I22 Is connected to the first terminal of the twenty-fourth switch S 24 The second terminal of which is connected to the positive output terminal of the second operational amplifier A2, and the eighteenth switch S 24 The first terminal of which is connected to the negative input terminal of the second operational amplifier A2, and the eighteenth switch S 18 The second terminal of which is respectively connected to the first terminal of the twentieth switch S 18 And the first terminal of the thirty-second integrating capacitor C 20 The first terminal of which is connected, and the second terminal of the thirty-second integrating capacitor C I32 Is connected to the first terminal of the twenty-sixth switch S I32 The second terminal of which is connected, and the second terminal of the twenty-sixth switch S 26 Is connected to the positive output terminal of the second operational amplifier A2, and the twentieth switch S 26 The second terminal of which is respectively connected to the first terminal of the twenty-second switch S 20 And the first terminal of the thirty-second sampling capacitor C 22 The first terminal of which is connected, and the second terminal of the twenty-second switch S S32 Is grounded, and the second terminal of the thirty-second sampling capacitor C 22 Is connected to the first terminal of the twenty-fourth switch S S32 The first terminal of which is connected. 24

[0061] In some embodiments of this embodiment, as Figure 2 Shown, the third operational amplifier unit includes a third operational amplifier A3, a forty-first sampling capacitor C S41 , A forty-second sampling capacitor C S42 , A forty-first integrating capacitor C I41 , A forty-second integrating capacitor C I42 , A twenty-seventh switch S 27 , A twenty-eighth switch S 28 , A twenty-ninth switch S 29 , A thirtieth switch S 30 , A thirty-first switch S 31 , A thirty-second switch S 32 , A thirty-third switch S 33 , A thirty-fourth switch S 34 , A thirty-fifth switch S 35 , A thirty-sixth switch S 36 , A thirty-seventh switch S​37 , the thirty-eighth switch S 38 , the thirty-ninth switch S 39 , the fortieth switch S 40 , the forty-first switch S 41 , the forty-second switch S 42 , the forty-third switch S 43 , the forty-fourth switch S 44 , the forty-fifth switch S 45 , the forty-sixth switch S 46 , the forty-seventh switch S 47 , the forty-eighth switch S 48 , the forty-ninth switch S 49 , the fiftieth switch S 50 , the fifty-first switch S 51 and the fifty-second switch S 52 , the first feedforward summing capacitor C A01 , the eleventh feedforward summing capacitor C A11 , the twenty-first feedforward summing capacitor C A21 , the thirty-first feedforward summing capacitor C A31 , the forty-first feedforward summing capacitor C A41 , the second feedforward summing capacitor C A02 , the twelfth feedforward summing capacitor C A12 , the twenty-second feedforward summing capacitor C A22 , the thirty-second feedforward summing capacitor C A32 , the forty-second feedforward summing capacitor C A42 , the eleventh feedback capacitor C F11 and the twelfth feedback capacitor C F12 .

[0062] The first terminal of the forty-first sampling capacitor C S41 is connected to the first terminal of S 25 , and the second terminal of the forty-first sampling capacitor C S41 is respectively connected to the first terminal of the twenty-seventh switch S 27 and the first terminal of the twenty-ninth switch S 29 , the second terminal of the twenty-seventh switch S 27 is grounded, and the second terminal of the twenty-ninth switch S 29 is connected to the first terminal of the thirty-first switch S 31 , and the second terminal of the thirty-first switch S 31 is connected to the positive input terminal of the third operational amplifier A3; the first terminal of the forty-second sampling capacitor C S42 is connected to the first terminal of S 26 , and the second terminal of the forty-second sampling capacitor C S42 is respectively connected to the first terminal of the twenty-eighth switch S 28 and the first terminal of the thirtieth switch S30 is connected to the first end, and the twenty-eighth switch S 28 has its second end grounded, and the thirtieth switch S 30 has its second end connected to the second end of the thirty-second switch S 32 is connected to the first end, and the thirty-second switch S 32 has its second end connected to the negative input terminal of the third operational amplifier A3.

[0063] The thirty-ninth switch S 39 has its first end connected to the positive differential signal input terminal VIP, and the thirty-ninth switch S 39 has its second end connected to the first end of the first feedforward summing capacitor C A01 and the first end of the fifty-first switch S 51 is connected to the first end, and the fifty-first switch S 51 has its second end grounded, and the first feedforward summing capacitor C A01 has its second end respectively connected to the first end of the eleventh feedforward summing capacitor C A11 and the first end of the twenty-first feedforward summing capacitor C A21 and the first end of the thirty-first feedforward summing capacitor C A31 and the first end of the thirty-third switch S 33 is connected to the first end, and the eleventh feedforward summing capacitor C A11 has its second end connected to the positive output terminal of the first operational amplifier A1, and the twenty-first feedforward summing capacitor C A21 has its second end respectively connected to the first end of the twenty-third switch S 23 and the first end of the thirty-fifth switch S 35 is connected to the first end, and the thirty-fifth switch S 35 has its second end grounded, and the thirty-first feedforward summing capacitor C A31 has its second end respectively connected to the first end of the twenty-sixth switch S 26 and the first end of the thirty-seventh switch S 37 is connected to the first end, and the thirty-seventh switch S 37 has its second end grounded, and the thirty-third switch S 33 has its second end connected to the positive input terminal of the third operational amplifier A3.

[0064] The fortieth switch S 40 has its first end connected to the negative differential signal input terminal VIN, and the fortieth switch S 40 has its second end connected to the first end of the second feedforward summing capacitor C A02 and the first end of the fifty-second switch S 52 is connected to the first end, and the fifty-second switch S 52 has its second end grounded, and the second feedforward summing capacitor C A02 has its second end respectively connected to the first end of the twelfth feedforward summing capacitor C A12 and the first end of the twenty-second feedforward summing capacitor C A22The first end of, the thirty-second feed-forward summing capacitor C A32 The first end of and the thirty-fourth switch S 34 The first end of is connected to the twelfth feed-forward summing capacitor C A12 The second end of is connected to the negative output terminal of the second operational amplifier A2, and the twenty-second feed-forward summing capacitor C A22 The second end of is respectively connected to the twenty-fourth switch S 24 The first end of and the thirty-sixth switch S 36 The first end of is connected, and the thirty-sixth switch S 36 The second end of is grounded, and the thirty-second feed-forward summing capacitor C A32 The second end of is respectively connected to the twenty-fifth switch S 25 The first end of and the thirty-eighth switch S 38 The first end of is connected, and the thirty-eighth switch S 38 The second end of is grounded, and the thirty-fourth switch S 34 The second end of is connected to the negative input terminal of the third operational amplifier A3.

[0065] The forty-first integrating capacitor C I41 The first end of is connected to the first end of the thirty-first switch S 31 The first end of, the forty-first integrating capacitor C I41 The second end of is connected to the first end of the forty-fifth switch S 45 The first end of, the forty-fifth switch S 45 The second end of is connected to the negative output terminal of the third operational amplifier A3, and the eleventh feedback capacitor C F11 The first end of is connected to the first end of the thirty-third switch S 33 The first end of, the eleventh feedback capacitor C F11 The second end of is respectively connected to the first end of the forty-seventh switch S 47 The first end of, the first end of the forty-ninth switch S 49 The first end of and the first input terminal of the comparator Q, and the forty-seventh switch S 47 The second end of is connected to the negative output terminal of the third operational amplifier A3, and the forty-ninth switch S 49 The second end of is grounded, and the forty-first feed-forward summing capacitor C A41 The first end of is respectively connected to the first end of the thirty-third switch S 33 The first end of and the first end of the forty-first switch S 41 The first end of, the forty-first switch S 41 The second end of is grounded, and the forty-first feed-forward summing capacitor C A41 The second end of is respectively connected to the first end of the forty-third switch S 43 The first end of and the first end of the forty-fifth switch S 45 The first end of, the forty-third switch S 43 The second end of is grounded.

[0066] The forty-second integrating capacitor C I42 has its first terminal connected to the first terminal of the thirty-second switch S 32 , the second terminal of the forty-second integrating capacitor C I42 is connected to the first terminal of the forty-sixth switch S 46 , the second terminal of the forty-sixth switch S 46 is connected to the positive output terminal of the third operational amplifier A3, the first terminal of the twelfth feedback capacitor C F12 is connected to the first terminal of the thirty-fourth switch S 34 , the second terminal of the twelfth feedback capacitor C F12 is respectively connected to the first terminal of the forty-eighth switch S 48 , the first terminal of the fiftieth switch S 50 and the second input terminal of the comparator Q, the second terminal of the forty-eighth switch S 48 is connected to the positive output terminal of the third operational amplifier A3, the second terminal of the fiftieth switch S 50 is grounded, the first terminal of the forty-second feedforward summing capacitor C A42 is respectively connected to the first terminal of the thirty-fourth switch S 34 and the first terminal of the forty-second switch S 42 , the second terminal of the forty-second switch S 42 is grounded, the second terminal of the forty-second feedforward summing capacitor C A42 is respectively connected to the first terminal of the forty-fourth switch S 44 and the first terminal of the forty-sixth switch S 46 , the second terminal of the forty-fourth switch S 44 is grounded.

[0067] In some embodiments of this embodiment, as Figure 2 shown, the grounds in the first operational amplifier unit, the second operational amplifier unit and the third operational amplifier unit are at a common-mode level.

[0068] In some embodiments of this embodiment, as Figure 2 shown, the control timings of the first switch S1, the second switch S2, the ninth switch S9, the tenth switch S 10 , the thirty-seventh switch S 37 , the thirty-eighth switch S 38 , the thirty-ninth switch S 39 and the fortieth switch S 40 are the same as the clock Φ1d, and the control timings of the third switch S3, the fourth switch S4, the thirty-fifth switch S 35 , the thirty-sixth switch S 36 , the forty-third switch S 43 , the forty-fourth switch S 44 , the fifty-first switch S 51 and the fifty-second switch S 52The control timing is the same as the clock Φ2d. The fifth switch S5, the sixth switch S6, the thirteenth switch S 13 , the fourteenth switch S 14 , the fifteenth switch S 15 , the sixteenth switch S 16 , the twenty-first switch S 21 , the twenty-second switch S 22 , the twenty-third switch S 23 , the twenty-fourth switch S 24 , the twenty-ninth switch S 29 , the thirtieth switch S 30 , the thirty-first switch S 31 , the thirty-second switch S 32 , the forty-first switch S 41 , the forty-second switch S 42 , the forty-fifth switch S 45 , the forty-sixth switch S 46 , the forty-ninth switch S 49 and the fiftieth switch S 50 have a control timing that is the same as the clock Φ1. The seventh switch S7, the eighth switch S8, the eleventh switch S 11 , the twelfth switch S 12 , the seventeenth switch S 17 , the eighteenth switch S 18 , the nineteenth switch S 19 , the twentieth switch S 20 , the twenty-fifth switch S 25 , the twenty-sixth switch S 26 , the twenty-seventh switch S 27 , the twenty-eighth switch S 28 , the thirty-third switch S 33 , the thirty-fourth switch S 34 , the forty-seventh switch S 47 and the forty-eighth switch S 48 have a control timing that is the same as the clock Φ2.

[0069] In some embodiments of this embodiment, as Figure 2 shown, the capacitance value of the eleventh sampling capacitor C S11 is the same as the capacitance value of the twelfth sampling capacitor C S12 , the capacitance value of the twenty-first sampling capacitor C S21 is the same as the capacitance value of the twenty-second sampling capacitor C S22 , the capacitance value of the thirty-first sampling capacitor C S31 is the same as the capacitance value of the thirty-second sampling capacitor C S32 , the capacitance value of the forty-first sampling capacitor C S41 is the same as the capacitance value of the forty-second sampling capacitor C S42has the same capacitance value; the eleventh integrating capacitor C I11 has the same capacitance value as the twelfth integrating capacitor C I12 has the same capacitance value; the twenty-first integrating capacitor C I21 has the same capacitance value as the twenty-second integrating capacitor C I22 has the same capacitance value; the thirty-first integrating capacitor C I31 has the same capacitance value as the thirty-second integrating capacitor C I32 has the same capacitance value; the forty-first integrating capacitor C I41 has the same capacitance value as the forty-second integrating capacitor C I42 has the same capacitance value; the first feed-forward summing capacitor C A01 has the same capacitance value as the second feed-forward summing capacitor C A02 has the same capacitance value; the eleventh feed-forward summing capacitor C A11 has the same capacitance value as the twelfth feed-forward summing capacitor C A12 has the same capacitance value; the twenty-first feed-forward summing capacitor C A21 has the same capacitance value as the twenty-second feed-forward summing capacitor C A22 has the same capacitance value; the thirty-first feed-forward summing capacitor C A31 has the same capacitance value as the thirty-second feed-forward summing capacitor C A32 has the same capacitance value; the forty-first feed-forward summing capacitor C A41 has the same capacitance value as the forty-second feed-forward summing capacitor C A42 has the same capacitance value; the eleventh feedback capacitor C F11 has the same capacitance value as the twelfth feedback capacitor C F12 has the same capacitance value.

[0070] The low-power Sigma-Delta modulator of the present invention is at Figure 3Under the shown working timing, at clock Φ1 and clock Φ1d, the first operational amplifier A1 samples as the first-stage integrator; the second operational amplifier A2 integrates as the second-stage integrator and samples as the third-stage integrator at the same time; the third operational amplifier A3 integrates as the fourth-stage integrator and resets and clears as the active adder. At clock Φ2 and clock Φ2d, the first operational amplifier A1 integrates as the first-stage integrator; the second operational amplifier A2 samples as the second-stage integrator and integrates as the third-stage integrator at the same time; the third operational amplifier A3 samples as the fourth-stage integrator and sums as the active adder; the comparator Q quantifies the summation result and outputs the first bitstream result bs and the second bitstream result bs_n; under the control of clock Φ2, the first bitstream result bs and the second bitstream result bs_n, the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFP (the feedback reference high voltage of the DAC) or VREFN (the feedback reference low voltage of the DAC), and the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFN or VREFP (when the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFP, the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFN; or when the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFN, the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFP), and at the same time, the output signals of the first output terminal VDAC1 and the second output terminal VDAC2 of the digital-to-analog converter DAC are fed back to the input terminal of the first operational amplifier A1.

[0071] As Figure 4 shown, at clock Φ1 and clock Φ1d, the first operational amplifier A1 samples the differential input signal (input from the VIP and VIN terminals) to the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 as the first-stage integrator; the second operational amplifier A2 integrates the differential output signal after the first-stage integration through the twenty-first sampling capacitor C S21 , the twenty-first integration capacitor C I21 , the twenty-second sampling capacitor C S22 and the twenty-second integration capacitor C I22 as the second-stage integrator, and the second operational amplifier A2 samples the differential output signal after the second-stage integration to the thirty-first sampling capacitor C S31 and the thirty-second sampling capacitor C S32 as the third-stage integrator at the same time; the third operational amplifier A3 integrates the differential output signal after the third-stage integration through the forty-first sampling capacitor C S41 , the forty-first integration capacitor CI41 , the forty-second sampling capacitor C S42 and the forty-second integrating capacitor C I42 perform integration. The third operational amplifier A3 also acts as an active adder to reset and clear to zero. The eleventh feedback capacitor C F11 , the twelfth feedback capacitor C F12 , the eleventh feedforward summing capacitor C A11 , the twelfth feedforward summing capacitor C A12 , the thirty-first feedforward summing capacitor C A31 and the thirty-second feedforward summing capacitor C A32 are grounded at both ends to release charge. The first feedforward summing capacitor C A01 and the second feedforward summing capacitor C A02 sample the input differential signal. The twenty-first feedforward summing capacitor C A21 and the twenty-second feedforward summing capacitor C A22 sample the second-stage differential output signal. The forty-first feedforward summing capacitor C A41 and the forty-second feedforward summing capacitor C A42 sample the fourth-stage differential output signal; during the clock Φ1 and clock Φ1d phases, the active adder samples the input signal, the second-stage integrator output signal, and the fourth-stage output signal, so as to perform proportional summation on the input signal and all 4-stage output signals during the clock Φ2 and clock Φ2d phases.

[0072] As Figure 5 shown, at the clock Φ2 and clock Φ2d, the first operational amplifier A1 acts as the first-stage integrator to integrate the difference between the input differential signal and the feedback signal; the second operational amplifier A2 acts as the second-stage integrator to sample the differential output signal after the first-stage integration onto the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 , and at the same time acts as the third-stage integrator to integrate the differential output result after the second-stage integration through the thirty-first sampling capacitor C S31 , the thirty-first integrating capacitor C I31 , the thirty-second sampling capacitor C S32 and the thirty-second integrating capacitor C I32 ; the third operational amplifier A3 acts as the fourth-stage integrator to sample the differential output signal after the third-stage integration onto the forty-first sampling capacitor C S41 and the forty-second sampling capacitor C S42 , the third operational amplifier A3 also acts as an active adder to perform a summing operation. The eleventh feedback capacitor C F11 and the twelfth feedback capacitor C F12 are connected across the input and output terminals of the third operational amplifier A3. The third operational amplifier A3 connects the first feedforward summing capacitor C A01, the eleventh feed-forward summing capacitor C A11 , the twenty-first feed-forward summing capacitor C A21 , the thirty-first feed-forward summing capacitor C A31 , the forty-first feed-forward summing capacitor C A41 , the second feed-forward summing capacitor C A02 , the twelfth feed-forward summing capacitor C A12 , the twenty-second feed-forward summing capacitor C A22 , the thirty-second feed-forward summing capacitor C A32 , the forty-second feed-forward summing capacitor C A42 The stored charge is transferred to perform a summation operation; the comparator Q quantizes the summation result to output the first bitstream result bs and the second bitstream result bs_n; under the control of the clock Φ2, the first bitstream result bs and the second bitstream result bs_n, the digital-to-analog converter DAC outputs VREFP or VREFN at the first output terminal VDAC1 of the digital-to-analog converter DAC, and outputs VREFN or VREFP at the second output terminal VDAC2 of the digital-to-analog converter DAC. At the same time, the output signals of the first output terminal VDAC1 of the digital-to-analog converter DAC and the second output terminal VDAC2 of the digital-to-analog converter DAC are fed back to the input terminal of the first operational amplifier A1.

[0073] In this embodiment, in the clock Φ2 and clock Φ2d phases, the "differential output signal after the first-stage integration" is sampled by the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 ; in the clock Φ2 and clock Φ2d phases, the first operational amplifier A1 serves as the first-stage integrator, and the "differential output signal after the first-stage integration" will be directly sampled by the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 . When the operational amplifier is disconnected, the sampling capacitor samples the signal after the previous-stage integration. The signal sampled in the clock Φ1 (clock Φ2) phase will be integrated as the input signal of this stage in the clock Φ2 (clock Φ1) phase. For example: in the clock Φ1 phase, the input terminal of the first operational amplifier A1 (sampling as the first-stage integrator) is disconnected from the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 , and the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 sample the input signal (this signal will be integrated by the first operational amplifier A1 in the clock Φ2 phase). The input terminal of the second operational amplifier A2 (sampling as the third-stage integrator) is disconnected from the thirty-first sampling capacitor C S31 and the thirty-second sampling capacitor C S32 , and the thirty-first sampling capacitor C S31and the thirty-second sampling capacitor C S32 Samples the output signal of the second operational amplifier A2 (integrating as the second-stage integrator) (this signal will be integrated by the second operational amplifier A2 in the clock Φ2 phase); in the clock Φ2 phase, the input terminal of the second operational amplifier A2 (sampling as the second-stage integrator) is connected to the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 is disconnected, and the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 Samples the output signal of A1 (integrating as the first-stage integrator) (this signal will be integrated by A2 in the Φ1 phase), and the input terminal of the third operational amplifier A3 (sampling as the fourth-stage integrator) is connected to the forty-first integrating capacitor C I41 and the forty-second sampling capacitor C S42 is disconnected, and the forty-first integrating capacitor C I41 and the forty-second sampling capacitor C S42 Samples the output signal of the second operational amplifier A2 (integrating as the third-stage integrator) (this signal will be integrated by the third operational amplifier A3 in the clock Φ1 phase). That is: the signal sampled by the sampling capacitor at the input terminal of the current stage in a certain stage (clock Φ1 or clock Φ2) will be integrated as the input signal of the current stage in the next stage (clock Φ2 or clock Φ1).

[0074] In a traditional 4th-order CIFF structure SDM (Sigma-Delta modulator), each integrator needs to be sampled at clock Φ1 and clock Φ1d. At this time, the operational amplifier of the integrator is not working but consumes current, and integration is only performed at clock Φ2 and clock Φ2d. At this time, the operational amplifier of the integrator starts to work, and 4 operational amplifiers are required for the integrator, and one operational amplifier is used as the active summing circuit. In the low-power Sigma-Delta modulator of the present invention, except for the first operational amplifier A1 of the operational amplifier, the second operational amplifier A2 and the third operational amplifier A3 are always working, without wasting current, and only 3 operational amplifiers are required to achieve the function of a 4th-order SDM, greatly saving the circuit power consumption and area. Since SDM has relatively high requirements for the operational amplifier performance of the first-stage operational amplifier, the first operational amplifier A1 in the present invention is only used as the first-stage integrator and does not participate in sharing.

[0075] The above-described specific embodiments further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A low-power Sigma-Delta modulator, characterized in that, Comprising: A first operational amplifier unit configured to sample a differential input signal in clock phases Φ1 and Φ1d, and integrate the difference between the differential input signal and a feedback signal in clock phases Φ2 and Φ2d; A second operational amplifier unit configured to integrate the differential output signal output by the first operational amplifier unit in clock phases Φ1 and Φ1d, sample the integrated differential output signal, integrate the differential output signal output by the first operational amplifier unit in clock phases Φ2 and Φ2d, and sample the sampled differential output signal; A third operational amplifier unit configured to integrate the differential output signal output by the second operational amplifier unit in clock phases Φ1 and Φ1d, reset and sample as an active adder, sample the differential output signal output by the second operational amplifier unit in clock phases Φ2 and Φ2d, and sum as an active adder; A comparator configured to quantize the summation result of the active adder in clock phases Φ2 and Φ2d and output a bitstream result; A digital-to-analog converter configured to output a reference voltage according to the bitstream result in clock phases Φ2 and Φ2d, and feedback the reference voltage as a feedback signal to the first operational amplifier unit; Wherein, clock Φ1 and clock Φ2 are two-phase non-overlapping clocks, clock Φ1d is the delayed phase clock of clock Φ1, and clock Φ2d is the delayed phase clock of clock Φ2.

2. The low-power Sigma-Delta modulator according to claim 1, characterized in that The first operational amplifier unit includes a first operational amplifier A1, sampling capacitors C S11 and C S12 , integrating capacitors C I11 and C I12 , and switches S1 to S8; The first terminal of S1 serves as the positive differential signal input terminal, the first terminal of S3 serves as the first feedback signal terminal, and the second terminal of S1 is respectively connected to the second terminal of S3 and the first terminal of C S11 The second terminal of C S11 is respectively connected to the first terminal of S5 and the first terminal of S7. The second terminal of S5 is grounded, and the second terminal of S7 is connected to the positive input terminal of A1; The first terminal of S2 serves as the negative differential signal input terminal, the first terminal of S4 serves as the second feedback signal terminal, and the second terminal of S2 is respectively connected to the second terminal of S4 and the first terminal of C S12 ; the second terminal of C S12 is respectively connected to the first terminal of S6 and the first terminal of S8. The second terminal of S6 is grounded, and the second terminal of S8 is connected to the negative input terminal of A1; C I11 The first end of C is connected to the positive input terminal of A1, C I11 The second end of C is connected to the negative output terminal of A1, C I12 The first end of C is connected to the negative input terminal of A1, C I12 The second end of C is connected to the positive output terminal of A1.

3. A low-power Sigma-Delta modulator according to claim 2, wherein The second operational amplifier unit includes a second operational amplifier A2, sampling capacitors C S21 and C S22 , sampling capacitors C S31 and C S32 , integrating capacitors C I21 and C I22 , integrating capacitors C I31 and C I32 , switches S9 to S 26 ; C S21 The first end of C is respectively connected to the negative output end of A1 and the first end of S9, and the second end of S9 is grounded. S21 The second end of C is respectively connected to the first end of S 11 and the first end of S 13 . The second end of S 11 is grounded. The second end of S 13 is connected to the first end of S 15 . The second end of S 15 is connected to the positive input end of A2; C S22 The first end of is respectively connected to the positive output end of A1 and S 10 The first end of, S 10 The second end of is grounded, C S22 The second end of is respectively connected to S 12 The first end of and S 14 The first end of, S 12 The second end of is grounded, S 14 The second end of is connected to the first end of S 16 The first end of, S 16 The second end of is connected to the negative input end of A2; C I21 The first end of is connected to S 15 The first end of C I21 The second end of is connected to S 23 The first end of S 23 The second end of is connected to the negative output terminal of A2, S 17 The first end of is connected to the positive input terminal of A2, S 17 The second end of is respectively connected to S 19 The first end of and C I31 The first end of C I31 The second end of is connected to S 25 The first end of S 25 The second end of is connected to the negative output terminal of A2, S 19 The second end of is respectively connected to S 21 The first end of and C S31 The first end of C 21 The second end of is grounded, C S31 The second end of is connected to S 23 The first end of; C I22 The first end of is connected to S 16 The first end of C I22 The second end of is connected to S 24 The first end of S 24 The second end of is connected to the positive output terminal of A2, S 18 The first end of is connected to the negative input terminal of A2, S 18 The second end of is respectively connected to S 20 The first end of and C I32 The first end of C I32 The second end of is connected to S 26 The first end of S 26 The second end of is connected to the positive output terminal of A2, S 20 The second end of is respectively connected to S 22 The first end of and C S32 The first end of C 22 The second end of is grounded, C S32 The second end of is connected to S 24 The first end of.

4. A low-power Sigma-Delta modulator according to claim 3, characterized in that, The third operational amplifier unit includes a third operational amplifier A3, sampling capacitors C S41 and C S42 , integrating capacitors C I41 and C I42 , switches S 27 to S 52 , feedforward summing capacitors C A01 , C A11 , C A21 , C A31 , C A41 , C A02 , C A12 , C A22 , C A32 , C A42 , feedback capacitors C F11 and C F12 ; C S41 's first end is connected to S 25 's first end, and C S41 's second end is respectively connected to S 27 's first end and S 29 's first end, S 27 's second end is grounded, and S 29 's second end is connected to S 31 's first end, and S 31 's second end is connected to the positive input terminal of A3; C S42 's first end is connected to S 26 's first end, and C S42 's second end is respectively connected to S 28 's first end and S 30 's first end, S 28 's second end is grounded, and S 30 's second end is connected to S 32 's first end, S 32 's second end is connected to the negative input terminal of A3; S 39 The first end is connected to the positive differential signal input terminal, S 39 The second end of the C A01 The first end and S 51 The first end of the connection, S 51 The second end of C is grounded. A01 The second end of C A11 The first end, C A21 The first end, C A31 The first end and S 33 The first end of the connection, C A11 The second end is connected to the positive output terminal of A1, C A21 The second end of S 23 The first end and S 35 The first end of the connection, S 35 The second end of C is grounded. A31 The second end of S 26 The first end and S 37 The first end of the connection, S 37 The second end of the ground, S 33 The second end of S is connected to the positive input terminal of A3; 40 The first end is connected to the negative differential signal input terminal, S 40 The second end of the C A02 The first end and S 52 The first end of the connection, S 52 The second end of C is grounded. A02 The second end of C A12 The first end, C A22 The first end, C A32 The first end and S 34 The first end of the connection, C A12 The second end of C is connected to the negative output terminal of A2. A22 The second end of S 24 The first end and S 36 The first end of the connection, S 36 The second end of C is grounded. A32 The second end of S 25 The first end and S 38 The first end of the connection, S 38 The second end of S is grounded. 34 The second end of is connected to the negative input terminal of A3; C I41 The first end of is connected to S 31 The first end of C I41 The second end of is connected to S 45 The first end of S 45 The second end of is connected to the negative output terminal of A3, C F11 The first end of C 33 is connected to the first end of S F11 The second end of C 47 is respectively connected to the first end of S 49 the first end of S 47 and the first input terminal of the comparator, S 49 The second end of is connected to the negative output terminal of A3, S A41 The second end of C 33 is grounded, C 41 The first end of C 41 is respectively connected to the first end of S A41 the first end of S 43 and the first end of S 45 The second end of S 43 is grounded; C I42 The first end of C 32 is connected to the first end of S I42 The second end of C 46 is connected to the first end of S 46 The second end of S F12 is connected to the positive output terminal of A3, C 34 The first end of C F12 is connected to the first end of S 48 The second end of C 50 is respectively connected to the first end of S 48 the first end of S 50 and the second input terminal of the comparator, S A42 The second end of is connected to the positive output terminal of A3, S 34 The second end of C 42 is grounded, C 42 The first end of C A42 is respectively connected to the first end of S 44 the first end of S 46 and the first end of S 44 The second end of is grounded.

5. A low-power Sigma-Delta modulator according to claim 4, characterized in that The grounds in the first operational amplifier unit, the second operational amplifier unit, and the third operational amplifier unit are at a common-mode level.

6. A low-power Sigma-Delta modulator according to claim 4, characterized in that, Switches S1, S2, S9, S 10 , S 37 , S 38 , S 39 and S 40 have a control timing identical to clock Φ1d. Switches S3, S4, S 35 , S 36 , S 43 , S 44 , S 51 and S 52 have a control timing identical to clock Φ2d. Switches S5, S6, S 13 , S 14 , S 15 , S 16 , S 21 , S 22 , S 23 , S 24 , S 29 , S 30 , S 31 , S 32 , S 41 , S 42 , S 45 , S 46 , S 49 and S 50 have a control timing identical to clock Φ1. Switches S7, S8, S 11 , S 12 , S 17 , S 18 , S 19 , S 20 , S 25 , S 26 , S 27 , S 28 , S 33 , S 34 , S 47 and S 48 have a control timing identical to clock Φ2.

7. A low-power Sigma-Delta modulator according to claim 4, characterized in that, C S11 has the same capacitance value as C S12 ; C S21 has the same capacitance value as C S22 ; C S31 has the same capacitance value as C S32 ; C S41 has the same capacitance value as C S42 ; C I11 has the same capacitance value as C I12 ; C I21 has the same capacitance value as C I22 ; C I31 has the same capacitance value as C I32 ; C I41 has the same capacitance value as C I42 ; C A01 has the same capacitance value as C A02 ; C A11 has the same capacitance value as C A12 ; C A21 has the same capacitance value as C A22 ; C A31 has the same capacitance value as C A32 ; C A41 has the same capacitance value as C A42 ; C F11 has the same capacitance value as C F12 ;

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