A low-power Sigma-Delta modulator

Abstract

The present invention discloses a low-power Sigma-Delta modulator, which belongs to the field of analog integrated circuit design. A low-power Sigma-Delta modulator includes a first operational amplifier unit, a second operational amplifier unit, a third operational amplifier unit, a comparator, and a digital-to-analog converter. The first operational amplifier unit is constructed as a first-stage integrator, the second operational amplifier unit is constructed as a second-stage integrator and a third-stage integrator, and the third operational amplifier unit is constructed as a fourth-stage integrator and an active adder. The Sigma-Delta modulator in the present invention only needs three operational amplifiers to realize the function of a fourth-order SDM, reducing the number of operational amplifiers in the fourth-order CIFF structure Sigma-Delta modulator from the traditional five to three, reducing power consumption by about 40%, and reducing area by about 40%, thereby meeting the low power consumption and miniature requirements of MEMS sensors.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design, and in particular relates to a low-power Sigma-Delta modulator. Background Art

[0002] With the rapid development of integrated circuit technology, especially the development of MEMS inertial sensor technology, the power consumption and area requirements of various MEMS inertial sensor interface chips such as MEMS accelerometer sensors, gyroscope sensors and pressure sensors have become more stringent.

[0003] Sigma-Delta modulator (SDM) circuits, the core circuitry of MEMS inertial sensor interface chips, suffer from excessive power consumption, which can lead to temperature rise, increased thermal noise, and parameter drift, resulting in reduced chip lifespan and reduced stability. Traditional 4th-order CIFF SDM structures require separate op amps for each integrator and summing module, resulting in high circuit power consumption and a large physical footprint, making it difficult to meet the miniaturization and low power requirements of MEMS sensors.

[0004] Therefore, it is necessary to optimize and improve the traditional 4th-order CIFF structure SDM circuit to reduce its power consumption and area, and further meet the requirements of high stability and miniaturization of MEMS inertial sensors. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a low-power Sigma-Delta modulator to reduce the power consumption of the Sigma-Delta modulator circuit and reduce the area of ​​the Sigma-Delta modulator circuit.

[0006] The present invention is implemented through the following technical solution: a low-power Sigma-Delta modulator, comprising:

[0007] a first operational amplifier unit configured to sample a differential input signal during clock Φ1 and Φ1d phases, and to integrate the differential input signal after performing a subtraction operation on the differential input signal and a feedback signal during clock Φ2 and Φ2d phases;

[0008] a second operational amplifier unit configured to integrate the differential output signal output by the first operational amplifier unit during clock phases Φ1 and Φ1d and to sample the integrated differential output signal, and to sample the differential output signal output by the first operational amplifier unit during clock phases Φ2 and Φ2d and to integrate the sampled differential output signal;

[0009] a third operational amplifier unit configured to integrate the differential output signal output by the second operational amplifier unit during clock Φ1 and Φ1d phases, and to reset and sample the differential output signal output by the second operational amplifier unit as an active adder, and to sample the differential output signal output by the second operational amplifier unit during clock Φ2 and Φ2d phases, and to sum the differential output signal output by the second operational amplifier unit as an active adder;

[0010] A comparator configured to quantize a summation result of the active adder during clock Φ2 and Φ2d phases and output a bit stream result;

[0011] A digital-to-analog converter, the digital-to-analog converter being configured to output a reference voltage according to a bit stream result in clock phases Φ2 and Φ2d, and to feed the reference voltage back to the first operational amplifier unit as a feedback signal;

[0012] The clock Φ1 and the clock Φ2 are two-phase non-overlapping clocks, the clock Φ1d is the delayed phase clock of the clock Φ1, and the clock Φ2d is the delayed phase clock of the clock Φ2.

[0013] Furthermore, the first operational amplifier unit includes a first operational amplifier A1, a sampling capacitor C S11 and C S12 , integrating capacitor C I11 and C I12 , switches S1~S8;

[0014] The first end of S1 is used as the positive differential signal input end, the first end of S3 is used as the first feedback signal end, and the second end of S1 is connected to the second end of S3 and C S11 The first end of the connection, C S11 The second end of is connected to the first end of S5 and the first end of S7 respectively, the second end of S5 is grounded, and the second end of S7 is connected to the positive input terminal of A1;

[0015] The first end of S2 is used as the negative differential signal input end, the first end of S4 is used as the second feedback signal end, and the second end of S2 is connected to the second end of S4 and C S12 The first end of the connection, C S12 The second end of is connected to the first end of S6 and the first end of S8 respectively, the second end of S6 is grounded, and the second end of S8 is connected to the negative input terminal of A1;

[0016] C I11 The first end is connected to the positive input of A1, C I11 The second end is connected to the negative output terminal of A1, C I12 The first end is connected to the negative input of A1, C I12 The second end of is connected to the positive output terminal of A1.

[0017] Furthermore, the second operational amplifier unit includes a second operational amplifier A2, a sampling capacitor C S21 and C S22 , sampling capacitor C S31 and C S32 , integrating capacitor C I21 and C I22 , integrating capacitor C I31 and C I32 , switch S9~S 26 ;

[0018] C S21 The first end of the S9 is connected to the negative output end of A1 and the first end of S9 respectively, the second end of S9 is grounded, and C S21 The second end of S 11 The first end and S 13 The first end of the connection, S 11 The second end of the ground, S 13 The second end and S 15 The first end of the connection, S 15 The second end of is connected to the positive input terminal of A2;

[0019] C S22 The first end is connected to the positive output of A1 and S 10 The first end of the connection, S 10 The second end of C is grounded. S22 The second end of S 12 The first end and S 14 The first end of the connection, S 12 The second end of the ground, S 14 The second end and S 16 The first end of the connection, S 16 The second end of is connected to the negative input terminal of A2;

[0020] C I21 The first end and S 15 The first end of the connection, C I21 The second end and S 23 The first end of the connection, S 23 The second end is connected to the negative output terminal of A2, S 17 The first end is connected to the positive input of A2, S 17 The second end of S 19 The first end and C I31 The first end of the connection, C I31 The second end and S 25 The first end of the connection, S 25 The second end is connected to the negative output terminal of A2, S 19 The second end of S 21 The first end and C S31The first end of the connection, S 21 The second end of C is grounded. S31 The second end and S 23 The first end of the connection;

[0021] C I22 The first end and S 16 The first end of the connection, C I22 The second end and S 24 The first end of the connection, S 24 The second end is connected to the positive output of A2, S 18 The first end is connected to the negative input of A2, S 18 The second end of S 20 The first end and C I32 The first end of the connection, C I32 The second end and S 26 The first end of the connection, S 26 The second end is connected to the positive output of A2, S 20 The second end of S 22 The first end and C S32 The first end of the connection, S 22 The second end of C is grounded. S32 The second end and S 24 The first end of the connection.

[0022] Furthermore, the third operational amplifier unit includes a third operational amplifier A3, a sampling capacitor C S41 and C S42 , integrating capacitor C I41 and C I42 , switch S 27 ~S 52 , feedforward summing capacitor C A01 、C A11 、C A21 、C A31 、C A41 、C A02 、C A12 、C A22 、C A32 、C A42 , feedback capacitor C F11 and C F12 ;

[0023] C S41 The first end and S 25 The first end of the connection, C S41 The second end of S 27 The first end and S 29 The first end of the connection, S 27 The second end of the ground, S 29 The second end and S31 The first end of the connection, S 31 The second end of C is connected to the positive input of A3; S42 The first end and S 26 The first end of the connection, C S42 The second end of S 28 The first end and S 30 The first end of the connection, S 28 The second end of the ground, S 30 The second end and S 32 The first end of the connection, S 32 The second end of is connected to the negative input terminal of A3;

[0024] S 39 The first end is connected to the positive differential signal input terminal, S 39 The second end of C A01 The first end and S 51 The first end of the connection, S 51 The second end of C is grounded. A01 The second end of C A11 The first end, C A21 The first end, C A31 The first end and S 33 The first end of the connection, C A11 The second end is connected to the positive output of A1, C A21 The second end of S 23 The first end and S 35 The first end of the connection, S 35 The second end of C is grounded. A31 The second end of S 26 The first end and S 37 The first end of the connection, S 37 The second end of the ground, S 33 The second end of S is connected to the positive input terminal of A3; 40 The first end is connected to the negative differential signal input terminal, S 40 The second end of C A02 The first end and S 52 The first end of the connection, S 52 The second end of C is grounded. A02 The second end of C A12 The first end, C A22 The first end, C A32 The first end and S 34 The first end of the connection, C A12 The second end is connected to the negative output terminal of A2, C A22 The second end of S 24 The first end and S 36 The first end of the connection, S 36The second end of C is grounded. A32 The second end of S 25 The first end and S 38 The first end of the connection, S 38 The second end of the ground, S 34 The second end of is connected to the negative input terminal of A3;

[0025] C I41 The first end and S 31 The first end of the connection, C I41 The second end and S 45 The first end of the connection, S 45 The second end is connected to the negative output terminal of A3, C F11 The first end and S 33 The first end of the connection, C F11 The second end of S 47 The first end, S 49 The first terminal is connected to the first input terminal of the comparator, S 47 The second end is connected to the negative output terminal of A3, S 49 The second end of C is grounded. A41 The first end of S 33 The first end and S 41 The first end of the connection, S 41 The second end of C is grounded. A41 The second end of S 43 The first end and S 45 The first end of the connection, S 43 The second end of C is grounded; I42 The first end and S 32 The first end of the connection, C I42 The second end and S 46 The first end of the connection, S 46 The second end is connected to the positive output of A3, C F12 The first end and S 34 The first end of the connection, C F12 The second end of S 48 The first end, S 50 The first terminal is connected to the second input terminal of the comparator, S 48 The second end is connected to the positive output of A3, S 50 The second end of C is grounded. A42 The first end of S 34 The first end and S 42 The first end of the connection, S 42 The second end of C is grounded. A42 The second end of S 44 The first end and S 46 The first end of the connection, S44 The second end is grounded.

[0026] Furthermore, the grounds of the first operational amplifier unit, the second operational amplifier unit and the third operational amplifier unit are at a common mode level.

[0027] Furthermore, switches S1, S2, S9, S 10 、S 37 、S 38 、S 39 and S 40 The control timing of the clock Φ1d is the same as that of the switches S3, S4, S 35 、S 36 、S 43 、S 44 、S 51 and S 52 The control timing of the clock Φ2d is the same as that of the switches S5, S6, S 13 、S 14 、S 15 、S 16 、S 21 、S 22 、S 23 、S 24 、S 29 、S 30 、S 31 、S 32 、S 41 、S 42 、S 45 、S 46 、S 49 and S 50 The control timing of the clock is the same as that of the clock Φ1, switches S7, S8, S 11 、S 12 、S 17 、S 18 、S 19 、S 20 、S 25 、S 26 、S 27 、S 28 、S 33 、S 34 、S 47 and S 48 The control timing is the same as that of clock Φ2.

[0028] Furthermore, C S11 The capacitance value and C S12 The capacitance value is the same, C S21 The capacitance value and C S22 The capacitance value is the same, C S31 The capacitance value and C S32 The capacitance value is the same, CS41 The capacitance value and C S42 The capacitance value is the same; C I11 The capacitance value and C I12 The capacitance value is the same, C I21 The capacitance value and C I22 The capacitance value is the same, C I31 The capacitance value and C I32 The capacitance value is the same, C I41 The capacitance value and C I42 The capacitance value is the same; C A01 The capacitance value and C A02 The capacitance value is the same, C A11 The capacitance value and C A12 The capacitance value is the same, C A21 The capacitance value and C A22 The capacitance value is the same, C A31 The capacitance value and C A32 The capacitance value is the same, C A41 The capacitance value and C A42 The capacitance value is the same; C F11 The capacitance value and C F12 The capacitance value is the same.

[0029] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0030] (1) The Sigma-Delta modulator of the present invention only requires three operational amplifiers to realize the function of the fourth-order SDM, reducing the number of operational amplifiers in the fourth-order CIFF structure Sigma-Delta modulator from the traditional five to three, reducing power consumption by about 40% and area by about 40%, thus meeting the low power consumption and miniaturization requirements of MEMS sensors;

[0031] (2) In the traditional 4th-order CIFF structure SDM (Sigma-Delta modulator), each integrator needs to be sampled at clock Φ1 and clock Φ1d. At this time, the operational amplifier of the integrator is not working but consumes current. Integration is performed at clock Φ2 and clock Φ2d. At this time, the operational amplifier of the integrator starts to work. However, in the Sigma-Delta modulator of the present invention, except for the first operational amplifier A1, the second operational amplifier A2 and the third operational amplifier A3 are all working all the time, and no current is wasted, which greatly reduces the power consumption of the circuit.

[0032] (3) In the traditional SDM structure, three operational amplifiers can only achieve the effect of third-order noise shaping. The Sigma-Delta modulator in the present invention can achieve the effect of fourth-order noise shaping by sharing operational amplifiers, thereby improving the accuracy of the MEMS sensor and meeting the high-precision requirements of the MEMS sensor.

[0033] (4) Compared with the traditional passive summing circuit, the present invention adopts an active summing circuit and utilizes the virtual short characteristics of the operational amplifier to enhance the integrity of the signal transmission. At the same time, due to the existence of the feedback network, the charge injection and clock feedthrough effects are suppressed, thereby enhancing the anti-interference performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0035] Figure 1 A structural block diagram of a Sigma-Delta modulator in the present invention;

[0036] Figure 2 A circuit diagram of a Sigma-Delta modulator in the present invention;

[0037] Figure 3 Sigma-Delta modulator working timing diagram of the present invention;

[0038] Figure 4 Schematic diagram of the circuit of the Sigma-Delta modulator in the Φ1 and Φ1d stages of the present invention;

[0039] Figure 5 This is a circuit schematic diagram of the Sigma-Delta modulator in the Φ2 and Φ2d stages of the present invention. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific implementation methods.

[0041] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0042] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inside", "outside" and the like indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0043] In the description of the present invention, unless otherwise expressly specified or limited, when the term "connection" or the like appears to indicate a connection relationship between components, such term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be internal communication between two components or an interaction between two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0044] like Figures 1 to 5 As shown, this embodiment discloses a low-power Sigma-Delta modulator.

[0045] like Figure 1 As shown, a low-power Sigma-Delta modulator includes a first operational amplifier unit, a second operational amplifier unit, a third operational amplifier unit, a comparator Q, and a digital-to-analog converter DAC. The first operational amplifier unit is configured as a first-stage integrator, the second operational amplifier unit is configured as a second-stage integrator and a third-stage integrator, and the third operational amplifier unit is configured as a fourth-stage integrator and an active adder.

[0046] The first operational amplifier unit is configured to serve as a first-stage integrator to sample the differential input signal during the clock Φ1 and Φ1d phases, and to serve as a first-stage integrator to integrate the differential input signal after performing a difference operation on the feedback signal during the clock Φ2 and Φ2d phases.

[0047] The second operational amplifier unit is configured to serve as a second-stage integrator to integrate the differential output signal output by the first operational amplifier unit as a first-stage integrator during the clock Φ1 and Φ1d stages, and to serve as a third-stage integrator to sample the differential output signal after integration as the second-stage integrator; and to serve as a second-stage integrator to sample the differential output signal output by the first operational amplifier unit as a first-stage integrator during the clock Φ2 and Φ2d stages, and to serve as a third-stage integrator to integrate the differential output signal after sampling as the second-stage integrator.

[0048] The third operational amplifier unit is configured to integrate the differential output signal output by the second operational amplifier unit as the third-stage integrator as a fourth-stage integrator during the clock Φ1 and Φ1d phases, and to reset and sample as an active adder, and to sample the differential output signal output by the second operational amplifier unit as the third-stage integrator as a fourth-stage integrator during the clock Φ2 and Φ2d phases, and to sum the signals as an active adder.

[0049] The comparator Q is configured to quantize the summation result of the active adder in the clock phases Φ2 and Φ2d and output a bit stream result.

[0050] The digital-to-analog converter DAC is configured to output a reference voltage according to a bit stream result in clock phases Φ2 and Φ2d, and feed the reference voltage back to the first operational amplifier unit as a feedback signal.

[0051] The clock Φ1 and the clock Φ2 are two-phase non-overlapping clocks, the clock Φ1d is the delayed phase clock of the clock Φ1, and the clock Φ2d is the delayed phase clock of the clock Φ2. The delay amount of the clock Φ1 and the clock Φ2 is determined according to the actual circuit design.

[0052] In some implementations of this embodiment, Figure 2 As shown, the first operational amplifier unit includes a first operational amplifier A1, an eleventh sampling capacitor C S11 , the twelfth sampling capacitor C S12 、The eleventh integrating capacitor C I11 , the twelfth integrating capacitor C I12 , a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8.

[0053] The first end of the first switch S1 is used as the positive differential signal input terminal VIP, the first end of the third switch S3 is used as the first feedback signal terminal VDAC1, and the second end of the first switch S1 is connected to the second end of the third switch S3 and the eleventh sampling capacitor C respectively. S11 The first end of the eleventh sampling capacitor C S11 The second end of the fifth switch S5 is connected to the first end of the fifth switch S5 and the first end of the seventh switch S7 respectively, the second end of the fifth switch S5 is grounded, and the second end of the seventh switch S7 is connected to the positive input terminal of the first operational amplifier A1.

[0054] The first end of the second switch S2 is used as the negative differential signal input terminal VIN, the first end of the fourth switch S4 is used as the second feedback signal terminal VDAC2, and the second end of the second switch S2 is connected to the second end of the fourth switch S4 and the twelfth sampling capacitor C S12 The first end of the twelfth sampling capacitor CS12 The second end of the sixth switch S6 is connected to the first end of the sixth switch S6 and the first end of the eighth switch S8 respectively, the second end of the sixth switch S6 is grounded, and the second end of the eighth switch S8 is connected to the negative input terminal of the first operational amplifier A1.

[0055] Eleventh integrating capacitor C I11 The first end of the eleventh integrating capacitor C is connected to the positive input terminal of the first operational amplifier A1. I11 The second end of the twelfth integral capacitor C is connected to the negative output terminal of the first operational amplifier A1. I12 The first end of the twelfth integrating capacitor C is connected to the negative input terminal of the first operational amplifier A1. I12 The second end of is connected to the positive output end of the first operational amplifier A1.

[0056] In some implementations of this embodiment, Figure 2 As shown, the second operational amplifier unit includes a second operational amplifier A2, a twenty-first sampling capacitor C S21 , the 22nd sampling capacitor C S22 、The 31st sampling capacitor C S31 、32nd sampling capacitor C S32 、The twenty-first integral capacitor C I21 、22nd integrating capacitor C I22 、The thirty-first integral capacitor C I31 、32nd integrating capacitor C I32 , ninth switch S9, tenth switch S 10 , eleventh switch S 11 , twelfth switch S 12 , 13th switch S 13 , fourteenth switch S 14 , the fifteenth switch S 15 , sixteenth switch S 16 , Seventeenth switch S 17 , Eighteenth switch S 18 , 19th switch S 19 , 20th switch S 20 21st switch S 21 22nd switch S 22 23rd switch S 23 24th switch S 24 25th switch S 25 and the twenty-sixth switch S 26 .

[0057] The 21st sampling capacitor C S21 The first end of the sampling capacitor C is connected to the negative output end of the first operational amplifier A1 and the first end of the ninth switch S9 respectively. The second end of the ninth switch S9 is grounded.S21 The second end of each of the eleventh switch S 11 The first end and the thirteenth switch S 13 The first end of the eleventh switch S 11 The second end of the thirteenth switch S 13 The second end of the fifteenth switch S 15 The first end of the fifteenth switch S 15 The second end of is connected to the positive input terminal of the second operational amplifier A2.

[0058] The 22nd sampling capacitor C S22 The first end is connected to the positive output end of the first operational amplifier A1 and the tenth switch S 10 The first end of the tenth switch S 10 The second end of the twenty-second sampling capacitor C S22 The second end of each of the twelfth switch S 12 The first end and the fourteenth switch S 14 The first end of the twelfth switch S 12 The second end of the fourteenth switch S 14 The second end of the sixteenth switch S 16 The first end of the sixteenth switch S 16 The second end of is connected to the negative input terminal of the second operational amplifier A2.

[0059] The twenty-first integral capacitor C I21 The first end of the fifteenth switch S 15 The first end is connected to the twenty-first integrating capacitor C I21 The second end of the twenty-third switch S 23 The first end of the twenty-third switch S 23 The second end of the seventeenth switch S is connected to the negative output terminal of the second operational amplifier A2. 17 The first end of the seventeenth switch S is connected to the positive input terminal of the second operational amplifier A2. 17 The second end of each of the nineteenth switch S 19 The first terminal and the thirty-first integrating capacitor C I31 The first end is connected to the thirty-first integrating capacitor C I31 The second end of the twenty-fifth switch S 25 The first end of the twenty-fifth switch S 25 The second end of the nineteenth switch S is connected to the negative output terminal of the second operational amplifier A2. 19 The second end of each of the twenty-first switch S 21 The first terminal and the thirty-first sampling capacitor C S31 The first end of the twenty-first switch S 21The second end of the thirty-first sampling capacitor C S31 The second end of the twenty-third switch S 23 The first end of the connection.

[0060] 22nd integrating capacitor C I22 The first end of the sixteenth switch S 16 The first end of the twenty-second integrating capacitor C I22 The second end of the twenty-fourth switch S 24 The first end of the twenty-fourth switch S 24 The second end of the eighteenth switch S is connected to the positive output terminal of the second operational amplifier A2. 18 The first end of the eighteenth switch S is connected to the negative input terminal of the second operational amplifier A2. 18 The second end of each of the twentieth switch S 20 The first terminal and the thirty-second integrating capacitor C I32 The first end of the thirty-second integrating capacitor C I32 The second end of the twenty-sixth switch S 26 The first end of the twenty-sixth switch S 26 The second end of the twentieth switch S is connected to the positive output terminal of the second operational amplifier A2. 20 The second end of the twenty-second switch S 22 The first end and the thirty-second sampling capacitor C S32 The first end of the twenty-second switch S 22 The second end of the thirty-second sampling capacitor C S32 The second end of the twenty-fourth switch S 24 The first end of the connection.

[0061] In some implementations of this embodiment, Figure 2 As shown, the third operational amplifier unit includes a third operational amplifier A3, a forty-first sampling capacitor C S41 , the forty-second sampling capacitor C S42 、41st integrating capacitor C I41 42nd integrating capacitor C I42 27th switch S 27 28th switch S 28 、Twenty-ninth switch S 29 30th switch S 30 、31st switch S 31 32nd switch S 32 33rd switch S 33 34th switch S 34 35th switch S 35 36th switch S 36 37th switch S37 38th switch S 38 、39th switch S 39 40th switch S 40 41st switch S 41 42nd switch S 42 43. Switch S 43 44th switch S 44 45th switch S 45 46th switch S 46 47th switch S 47 48th switch S 48 49th switch S 49 、Fiftieth switch S 50 、51st switch S 51 and the fifty-second switch S 52 , the first feedforward summing capacitor C A01 , the eleventh feedforward summing capacitor C A11 , the twenty-first feedforward summing capacitor C A21 、The thirty-first feedforward summing capacitor C A31 , the forty-first feedforward summing capacitor C A41 , the second feedforward summing capacitor C A02 , the twelfth feedforward summing capacitor C A12 , the twenty-second feedforward summing capacitor C A22 、32nd feedforward summing capacitor C A32 42nd feedforward summing capacitor C A42 , the eleventh feedback capacitor C F11 and the twelfth feedback capacitor C F12 .

[0062] The 41st sampling capacitor C S41 The first end and S 25 The first end is connected to the forty-first sampling capacitor C S41 The second end of the twenty-seventh switch S 27 The first end of the twenty-ninth switch S 29 The first end of the twenty-seventh switch S 27 The second end of the twenty-ninth switch S 29 The second end of the thirty-first switch S 31 The first end of the thirty-first switch S 31 The second end of the forty-second sampling capacitor C is connected to the positive input terminal of the third operational amplifier A3; S42 The first end and S 26 The first end of the forty-second sampling capacitor C S42 The second end of the twenty-eighth switch S 28 The first end and the thirtieth switch S30 The first end of the twenty-eighth switch S 28 The second end of the 30th switch S 30 The second end of the thirty-second switch S 32 The first end of the thirty-second switch S 32 The second end of is connected to the negative input terminal of the third operational amplifier A3.

[0063] Switch S 39 The first end is connected to the positive differential signal input terminal VIP, the thirty-ninth switch S 39 The second end of the first feedforward summing capacitor C A01 The first end and the fifty-first switch S 51 The first end of the fifty-first switch S 51 The second end of the first feedforward summing capacitor C A01 The second end of the eleventh feedforward summing capacitor C A11 The first end of the twenty-first feedforward summing capacitor C A21 The first end of the thirty-first feedforward summing capacitor C A31 The first end and the thirty-third switch S 33 The first end of the eleventh feedforward summing capacitor C A11 The second end of the second operational amplifier A1 is connected to the positive output terminal of the first operational amplifier A1, and the second end of the second operational amplifier A1 is connected to the positive output terminal of the first operational amplifier A1. A21 The second end of the twenty-third switch S 23 The first end and the thirty-fifth switch S 35 The first end of the thirty-fifth switch S 35 The second end of the thirty-first feedforward summing capacitor C A31 The second end of the twenty-sixth switch S 26 The first end and the thirty-seventh switch S 37 The first end of the thirty-seventh switch S 37 The second end of the thirty-third switch S is grounded. 33 The second end of is connected to the positive input terminal of the third operational amplifier A3.

[0064] 40th switch S 40 The first end is connected to the negative differential signal input terminal VIN, the fortieth switch S 40 The second end of the second feedforward summing capacitor C A02 The first end and the fifty-second switch S 52 The first end of the fifty-second switch S 52 The second end of the second feedforward summing capacitor C A02 The second end of the twelfth feedforward summing capacitor C A12 The first end of the twenty-second feedforward summing capacitor C A22The first end of the thirty-second feedforward summing capacitor C A32 The first end and the thirty-fourth switch S 34 The first end of the twelfth feedforward summing capacitor C A12 The second end of the second operational amplifier A2 is connected to the negative output terminal of the second operational amplifier A2, and the twenty-second feedforward summing capacitor C A22 The second end of the twenty-fourth switch S 24 The first end and the thirty-sixth switch S 36 The first end of the thirty-sixth switch S 36 The second end of the thirty-second feedforward summing capacitor C A32 The second end of the twenty-fifth switch S 25 The first end and the thirty-eighth switch S 38 The first end of the thirty-eighth switch S 38 The second end of the thirty-fourth switch S 34 The second end of is connected to the negative input terminal of the third operational amplifier A3.

[0065] Forty-first integrating capacitor C I41 The first end of the thirty-first switch S 31 The first end is connected to the forty-first integrating capacitor C I41 The second end of the forty-fifth switch S 45 The first end of the forty-fifth switch S 45 The second end of the eleventh feedback capacitor C is connected to the negative output terminal of the third operational amplifier A3. F11 The first end of the thirty-third switch S 33 The first end of the eleventh feedback capacitor C F11 The second end of each of the forty-seventh switch S 47 The first end of the forty-ninth switch S 49 The first end of the forty-seventh switch S is connected to the first input end of the comparator Q. 47 The second end of the forty-ninth switch S is connected to the negative output terminal of the third operational amplifier A3. 49 The second end of the forty-first feedforward summing capacitor C A41 The first end of each of the thirty-third switch S 33 The first end and the forty-first switch S 41 The first end of the forty-first switch S 41 The second end of the forty-first feedforward summing capacitor C A41 The second end of each of the forty-third switch S 43 The first end and the forty-fifth switch S 45 The first end of the forty-third switch S 43 The second end is grounded.

[0066] 42nd integrating capacitor C I42 The first end of the thirty-second switch S 32 The first end of the forty-second integrating capacitor C I42 The second end of the forty-sixth switch S 46 The first end of the forty-sixth switch S 46 The second end of the twelfth feedback capacitor C is connected to the positive output terminal of the third operational amplifier A3. F12 The first end of the thirty-fourth switch S 34 The first end of the twelfth feedback capacitor C F12 The second end of the forty-eighth switch S 48 The first end of the 50th switch S 50 The first end of the forty-eighth switch S is connected to the second input end of the comparator Q. 48 The second end of the 50th switch S is connected to the positive output terminal of the third operational amplifier A3. 50 The second end of the forty-second feedforward summing capacitor C A42 The first end of each of the thirty-fourth switches S 34 The first end and the forty-second switch S 42 The first end of the forty-second switch S 42 The second end of the forty-second feedforward summing capacitor C A42 The second end of each of the forty-fourth switch S 44 The first end and the forty-sixth switch S 46 The first end of the forty-fourth switch S 44 The second end is grounded.

[0067] In some implementations of this embodiment, Figure 2 As shown, the grounds of the first operational amplifier unit, the second operational amplifier unit and the third operational amplifier unit are at a common mode level.

[0068] In some implementations of this embodiment, Figure 2 As shown, the first switch S1, the second switch S2, the ninth switch S9, the tenth switch S 10 37th switch S 37 38th switch S 38 、39th switch S 39 and the fortieth switch S 40 The control timing of the third switch S3, the fourth switch S4, and the thirty-fifth switch S 35 36th switch S 36 43. Switch S 43 44th switch S 44 、51st switch S 51 and the fifty-second switch S 52The control timing of the fifth switch S5, the sixth switch S6, and the thirteenth switch S 13 , fourteenth switch S 14 , the fifteenth switch S 15 , sixteenth switch S 16 21st switch S 21 22nd switch S 22 23rd switch S 23 24th switch S 24 、Twenty-ninth switch S 29 30th switch S 30 、31st switch S 31 32nd switch S 32 41st switch S 41 42nd switch S 42 45th switch S 45 46th switch S 46 49th switch S 49 and the 50th switch S 50 The control timing of the seventh switch S7, the eighth switch S8, and the eleventh switch S 11 , twelfth switch S 12 , Seventeenth switch S 17 , Eighteenth switch S 18 , 19th switch S 19 , 20th switch S 20 25th switch S 25 26th switch S 26 27th switch S 27 28th switch S 28 33rd switch S 33 34th switch S 34 47th switch S 47 and the forty-eighth switch S 48 The control timing is the same as that of clock Φ2.

[0069] In some implementations of this embodiment, Figure 2 As shown, the eleventh sampling capacitor C S11 The capacitance value of the twelfth sampling capacitor C S12 The capacitance value of the twenty-first sampling capacitor C S21 The capacitance value of the 22nd sampling capacitor C S22 The capacitance value of the thirty-first sampling capacitor C S31 The capacitance value of the 32nd sampling capacitor C S32 The capacitance value of the forty-first sampling capacitor C S41 The capacitance value of the forty-second sampling capacitor C S42The capacitance value is the same; the eleventh integral capacitor C I11 The capacitance value of the twelfth integral capacitor C I12 The capacitance value of the twenty-first integral capacitor C I21 The capacitance value of the 22nd integral capacitor C I22 The capacitance value is the same as the 31st integral capacitor C I31 The capacitance value of the 32nd integral capacitor C I32 The capacitance value is the same as the forty-first integral capacitor C I41 The capacitance value of the 42nd integral capacitor C I42 The capacitance value of the first feedforward summing capacitor C A01 The capacitance value of the second feedforward summing capacitor C A02 The capacitance value is the same as the eleventh feedforward summing capacitor C A11 The capacitance value of the twelfth feedforward summing capacitor C A12 The capacitance value of the twenty-first feedforward summing capacitor C A21 The capacitance value of the 22nd feedforward summing capacitor C A22 The capacitance value is the same as the 31st feedforward summing capacitor C A31 The capacitance value of the 32nd feedforward summing capacitor C A32 The capacitance value is the same as the forty-first feedforward summing capacitor C A41 The capacitance value of the forty-second feedforward summing capacitor C A42 The capacitance value is the same as the eleventh feedback capacitor C F11 The capacitance value of the twelfth feedback capacitor C F12 The capacitance value is the same.

[0070] The low power consumption Sigma-Delta modulator of the present invention is Figure 3In the working timing shown, at clock Φ1 and clock Φ1d, the first operational amplifier A1 acts as a first-stage integrator for sampling; the second operational amplifier A2 acts as a second-stage integrator for integration and also acts as a third-stage integrator for sampling; the third operational amplifier A3 acts as a fourth-stage integrator for integration and also acts as an active adder for resetting and clearing. At clock Φ2 and clock Φ2d, the first operational amplifier A1 acts as a first-stage integrator for integration; the second operational amplifier A2 acts as a second-stage integrator for sampling and also acts as a third-stage integrator for integration; the third operational amplifier A3 acts as a fourth-stage integrator for sampling and also acts as an active adder for summing; the comparator Q quantizes the summation result and outputs a first bit stream result bs and a second bit stream result bs_n; under the control of clock Φ2, the first bit stream result bs, and the second bit stream result bs_n, the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFP (the DAC's feedback reference high voltage) or VREFN (feedback reference low voltage of DAC), the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFN or VREFP (the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFP, and the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFN; or, the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFN, and the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFP), and the output signals of the first output terminal VDAC1 of the digital-to-analog converter DAC and the second output terminal VDAC2 of the digital-to-analog converter DAC are fed back to the input terminal of the first operational amplifier A1.

[0071] like Figure 4 As shown, at clock Φ1 and clock Φ1d, the first operational amplifier A1 acts as a first-stage integrator to sample the differential input signal (differential input signal is input from VIP and VIN terminals) to the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 The second operational amplifier A2 acts as a second-stage integrator to output the differential output signal after the first-stage integration through the twenty-first sampling capacitor C S21 、The twenty-first integral capacitor C I21 , the 22nd sampling capacitor C S22 and the twenty-second integrating capacitor C I22 The second operational amplifier A2 is used as a third-stage integrator to sample the differential output signal after the second-stage integration to the thirty-first sampling capacitor C S31 and the thirty-second sampling capacitor C S32 The third operational amplifier A3 is used as the fourth stage integrator to output the differential output signal after the third stage integration through the forty-first sampling capacitor C S41 、41st integrating capacitor CI41 , the forty-second sampling capacitor C S42 and the forty-second integrating capacitor C I42 The third operational amplifier A3 is used as an active adder to reset and clear the eleventh feedback capacitor C F11 , the twelfth feedback capacitor C F12 , the eleventh feedforward summing capacitor C A11 , the twelfth feedforward summing capacitor C A12 、The thirty-first feedforward summing capacitor C A31 and the thirty-second feedforward summing capacitor C A32 Both ends are grounded to release the charge, and the first feedforward summing capacitor C A01 and the second feedforward summing capacitor C A02 To sample the input differential signal, the twenty-first feedforward summing capacitor C A21 and the twenty-second feedforward summing capacitor C A22 The second stage differential output signal is sampled, the forty-first feedforward summing capacitor C A41 and ground 42 feedforward summing capacitor C A42 The fourth-stage differential output signal is sampled; in the clock Φ1 and clock Φ1d stages, the active adder samples the input signal, the second-stage integrator output signal, and the fourth-stage output signal, so as to perform proportional summation of the input signal and all the output signals of the 4th stage in the clock Φ2 and clock Φ2d stages.

[0072] like Figure 5 As shown, at clock Φ2 and clock Φ2d, the first operational amplifier A1 acts as a first-stage integrator to integrate the difference between the input differential signal and the feedback signal; the second operational amplifier A2 acts as a second-stage integrator to sample the differential output signal after the first-stage integration to the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 At the same time, it acts as a third-stage integrator and transmits the differential output result after the second-stage integration through the thirty-first sampling capacitor C S31 、The thirty-first integral capacitor C I31 、32nd sampling capacitor C S32 and the thirty-second integrating capacitor C I32 The third operational amplifier A3 is used as the fourth stage integrator to sample the differential output signal after the third stage integration to the forty-first sampling capacitor C S41 and the forty-second sampling capacitor C S42 The third operational amplifier A3 also acts as an active adder to perform summing operation, and the eleventh feedback capacitor C F11 and the twelfth feedback capacitor C F12 The third operational amplifier A3 is connected across the input and output terminals, and the third operational amplifier A3 converts the first feedforward summing capacitor C A01, the eleventh feedforward summing capacitor C A11 , the twenty-first feedforward summing capacitor C A21 、The thirty-first feedforward summing capacitor C A31 , the forty-first feedforward summing capacitor C A41 , the second feedforward summing capacitor C A02 , the twelfth feedforward summing capacitor C A12 , the twenty-second feedforward summing capacitor C A22 、32nd feedforward summing capacitor C A32 42nd feedforward summing capacitor C A42 The charge stored on the digital-to-analog converter is transferred to realize the summation operation; the comparator Q quantizes the summation result and outputs the first bit stream result bs and the second bit stream result bs_n; under the control of the clock Φ2, the first bit stream result bs and the second bit stream result bs_n, the first output terminal VDAC1 of the digital-to-analog converter DAC outputs VREFP or VREFN, and the second output terminal VDAC2 of the digital-to-analog converter DAC outputs VREFN or VREFP, and at the same time, the output signals of the first output terminal VDAC1 of the digital-to-analog converter DAC and the second output terminal VDAC2 of the digital-to-analog converter DAC are fed back to the input terminal of the first operational amplifier A1.

[0073] In this embodiment, at the clock Φ2 and clock Φ2d stages, the “differential output signal after the first stage integration” is input by the twenty-first sampling capacitor C at the clock Φ2 stage. S21 and the twenty-second sampling capacitor C S22 Sampling is obtained; in the clock Φ2 and clock Φ2d stages, the first operational amplifier A1 acts as the first-stage integrator, and the "differential output signal after the first-stage integration" is directly input to the 21st sampling capacitor C S21 and the twenty-second sampling capacitor C S22 Sampling. When the op amp is disconnected, the sampling capacitor samples the signal after integration at the previous stage. The signal sampled at the clock Φ1 (clock Φ2) stage will be integrated as the input signal of this stage at the clock Φ2 (clock Φ1) stage. For example, at the clock Φ1 stage, the input of the first operational amplifier A1 (sampling as the first stage integrator) is connected to the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 Disconnect, the eleventh sampling capacitor C S11 and the twelfth sampling capacitor C S12 The input signal is sampled (the signal will be integrated by the first operational amplifier A1 in the clock Φ2 phase), and the input terminal of the second operational amplifier A2 (sampling as the third stage integrator) is connected to the thirty-first sampling capacitor C S31 and the thirty-second sampling capacitor C S32 Disconnect, the thirty-first sampling capacitor C S31and the thirty-second sampling capacitor C S32 The output signal of the second operational amplifier A2 (integrated as the second stage integrator) is sampled (the signal will be integrated by the second operational amplifier A2 in the clock Φ2 phase); in the clock Φ2 phase, the input terminal of the second operational amplifier A2 (sampling as the second stage integrator) is connected to the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 Disconnect, the twenty-first sampling capacitor C S21 and the twenty-second sampling capacitor C S22 The output signal of A1 (integrated as the first stage integrator) is sampled (the signal will be integrated by A2 in the Φ1 stage), and the input terminal of the third operational amplifier A3 (sampling as the fourth stage integrator) is connected to the forty-first integral capacitor C I41 and the forty-second sampling capacitor C S42 Disconnect the 41st integrating capacitor C I41 and the forty-second sampling capacitor C S42 The output signal of the second operational amplifier A2 (which integrates as the third-stage integrator) is sampled (this signal will be integrated by the third operational amplifier A3 during the clock Φ1 phase). That is, the signal sampled by the sampling capacitor at the input of this stage at a certain phase (clock Φ1 or clock Φ2) will be integrated as the input signal of this stage during the next phase (clock Φ2 or clock Φ1).

[0074] In a traditional fourth-order CIFF SDM (Sigma-Delta Modulator), each integrator needs to sample at clocks Φ1 and Φ1d. During this time, the integrator's operational amplifier is inactive but consumes current. Integration occurs at clocks Φ2 and Φ2d, at which point the integrator's operational amplifier begins operating. Four operational amplifiers are required for the integrators, with one operational amplifier serving as an active summing circuit. However, the low-power Sigma-Delta modulator of the present invention, in addition to the first operational amplifier A1, also has the second operational amplifier A2 and the third operational amplifier A3 operating continuously, eliminating current waste. Only three operational amplifiers are required to implement the fourth-order SDM function, significantly reducing circuit power consumption and area. Because SDM requires high performance from the first-stage operational amplifier, the first operational amplifier A1 in the present invention serves only as a first-stage integrator and is not shared.

[0075] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low power Sigma-Delta modulator, characterized in that: include: a first operational amplifier unit configured to sample a differential input signal during clock Φ1 and Φ1d phases, and to integrate the differential input signal after performing a subtraction operation on the differential input signal and a feedback signal during clock Φ2 and Φ2d phases; a second operational amplifier unit configured to integrate the differential output signal output by the first operational amplifier unit during clock phases Φ1 and Φ1d and to sample the integrated differential output signal, and to sample the differential output signal output by the first operational amplifier unit during clock phases Φ2 and Φ2d and to integrate the sampled differential output signal; a third operational amplifier unit configured to integrate the differential output signal output by the second operational amplifier unit during clock Φ1 and Φ1d phases, and to reset and sample the differential output signal output by the second operational amplifier unit as an active adder, and to sample the differential output signal output by the second operational amplifier unit during clock Φ2 and Φ2d phases, and to sum the differential output signal output by the second operational amplifier unit as an active adder; A comparator configured to quantize a summation result of the active adder during clock Φ2 and Φ2d phases and output a bit stream result; A digital-to-analog converter, the digital-to-analog converter being configured to output a reference voltage according to a bit stream result in clock phases Φ2 and Φ2d, and to feed the reference voltage back to the first operational amplifier unit as a feedback signal; Among them, clock Φ1 and clock Φ2 are two-phase non-overlapping clocks, clock Φ1d is the delayed phase clock of clock Φ1, and clock Φ2d is the delayed phase clock of clock Φ2; in the clock Φ1 and Φ1d phases and the clock Φ2 and Φ2d phases, the operational amplifiers in the second operational amplifier unit and the third operational amplifier unit are always working, and no current is wasted; The first operational amplifier unit includes a first operational amplifier A1, sampling capacitors CS11 and CS12, integrating capacitors CI11 and CI12, and switches S1 to S8; The first end of S1 serves as a positive differential signal input end, the first end of S3 serves as a first feedback signal end, the second end of S1 is connected to the second end of S3 and the first end of CS11 respectively, the second end of CS11 is connected to the first end of S5 and the first end of S7 respectively, the second end of S5 is grounded, and the second end of S7 is connected to the positive input end of A1; The first end of S2 serves as a negative differential signal input end, the first end of S4 serves as a second feedback signal end, the second end of S2 is connected to the second end of S4 and the first end of CS12 respectively, the second end of CS12 is connected to the first end of S6 and the first end of S8 respectively, the second end of S6 is grounded, and the second end of S8 is connected to the negative input end of A1; A first terminal of CI11 is connected to the positive input terminal of A1, a second terminal of CI11 is connected to the negative output terminal of A1, a first terminal of CI12 is connected to the negative input terminal of A1, and a second terminal of CI12 is connected to the positive output terminal of A1; The second operational amplifier unit includes a second operational amplifier A2, sampling capacitors CS21 and CS22, sampling capacitors CS31 and CS32, integrating capacitors CI21 and CI22, integrating capacitors CI31 and CI32, and switches S9 to S26; A first end of CS21 is connected to the negative output terminal of A1 and the first end of S9, respectively. A second end of S9 is grounded. A second end of CS21 is connected to the first end of S11 and the first end of S13, respectively. A second end of S11 is grounded. A second end of S13 is connected to the first end of S15, and a second end of S15 is connected to the positive input terminal of A2. A first end of CS22 is connected to the positive output terminal of A1 and the first end of S10 respectively, a second end of S10 is grounded, a second end of CS22 is connected to the first end of S12 and the first end of S14 respectively, a second end of S12 is grounded, a second end of S14 is connected to the first end of S16, and a second end of S16 is connected to the negative input terminal of A2; A first end of CI21 is connected to a first end of S15, a second end of CI21 is connected to a first end of S23, a second end of S23 is connected to the negative output end of A2, a first end of S17 is connected to the positive input end of A2, a second end of S17 is connected to a first end of S19 and a first end of CI31, a second end of CI31 is connected to a first end of S25, a second end of S25 is connected to the negative output end of A2, a second end of S19 is connected to a first end of S21 and a first end of CS31, a second end of S21 is grounded, and a second end of CS31 is connected to a first end of S23; A first end of CI22 is connected to a first end of S16, a second end of CI22 is connected to a first end of S24, a second end of S24 is connected to the positive output end of A2, a first end of S18 is connected to the negative input end of A2, a second end of S18 is connected to a first end of S20 and a first end of CI32, a second end of CI32 is connected to a first end of S26, a second end of S26 is connected to the positive output end of A2, a second end of S20 is connected to a first end of S22 and a first end of CS32, a second end of S22 is grounded, and a second end of CS32 is connected to a first end of S24; The third operational amplifier unit includes a third operational amplifier A3, sampling capacitors CS41 and CS42, integrating capacitors CI41 and CI42, switches S27 to S52, feedforward summing capacitors CA01, CA11, CA21, CA31, CA41, CA02, CA12, CA22, CA32, and CA42, and feedback capacitors CF11 and CF12; A first end of CS41 is connected to a first end of S25, a second end of CS41 is connected to a first end of S27 and a first end of S29 respectively, a second end of S27 is grounded, a second end of S29 is connected to a first end of S31, a second end of S31 is connected to a positive input end of A3; a first end of CS42 is connected to a first end of S26, a second end of CS42 is connected to a first end of S28 and a first end of S30 respectively, a second end of S28 is grounded, a second end of S30 is connected to a first end of S32, and a second end of S32 is connected to a negative input end of A3; A first end of S39 is connected to the positive differential signal input end, a second end of S39 is connected to the first end of CA01 and the first end of S51, a second end of S51 is grounded, a second end of CA01 is connected to the first end of CA11, the first end of CA21, the first end of CA31 and the first end of S33, a second end of CA11 is connected to the positive output end of A1, a second end of CA21 is connected to the first end of S23 and the first end of S35, a second end of S35 is grounded, a second end of CA31 is connected to the first end of S26 and the first end of S37, a second end of S37 is grounded, and a second end of S33 is connected to the positive input end of A3; A first end of S40 is connected to the negative differential signal input end, a second end of S40 is connected to the first end of CA02 and the first end of S52, a second end of S52 is grounded, a second end of CA02 is respectively connected to the first end of CA12, the first end of CA22, the first end of CA32 and the first end of S34, a second end of CA12 is connected to the negative output end of A2, a second end of CA22 is respectively connected to the first end of S24 and the first end of S36, a second end of S36 is grounded, a second end of CA32 is respectively connected to the first end of S25 and the first end of S38, a second end of S38 is grounded, and a second end of S34 is connected to the negative input end of A3; A first end of CI41 is connected to a first end of S31, a second end of CI41 is connected to a first end of S45, a second end of S45 is connected to the negative output end of A3, a first end of CF11 is connected to a first end of S33, a second end of CF11 is respectively connected to a first end of S47, a first end of S49 and a first input end of the comparator, a second end of S47 is connected to the negative output end of A3, a second end of S49 is grounded, a first end of CA41 is respectively connected to a first end of S33 and a first end of S41, a second end of S41 is grounded, a second end of CA41 is respectively connected to a first end of S43 and a first end of S45, and a second end of S43 is grounded; The first end of CI42 is connected to the first end of S32, the second end of CI42 is connected to the first end of S46, the second end of S46 is connected to the positive output end of A3, the first end of CF12 is connected to the first end of S34, the second end of CF12 is respectively connected to the first end of S48, the first end of S50 and the second input end of the comparator, the second end of S48 is connected to the positive output end of A3, the second end of S50 is grounded, the first end of CA42 is respectively connected to the first end of S34 and the first end of S42, the second end of S42 is grounded, the second end of CA42 is respectively connected to the first end of S44 and the first end of S46, and the second end of S44 is grounded.

2. A low-power Sigma-Delta modulator according to claim 1, characterized in that: The grounds of the first operational amplifier unit, the second operational amplifier unit and the third operational amplifier unit are at a common mode level.

3. A low-power Sigma-Delta modulator according to claim 1, characterized in that: The control timing of switches S1, S2, S9, S10, S37, S38, S39, and S40 is the same as that of clock Φ1d. The control timing of switches S3, S4, S35, S36, S43, S44, S51, and S52 is the same as that of clock Φ2d. The control timing of switches S5, S6, S13, S14, S15, S16, S21, S22, S23, S24, S29, S30, S31, S32, S41, S42, S45, S46, S49, and S50 is the same as that of clock Φ1. The control timing of switches S7, S8, S11, S12, S17, S18, S19, S20, S25, S26, S27, S28, S33, S34, S47, and S48 is the same as that of clock Φ2.

4. A low-power Sigma-Delta modulator according to claim 1, characterized in that: The capacitance value of CS11 is the same as that of CS12, the capacitance value of CS21 is the same as that of CS22, the capacitance value of CS31 is the same as that of CS32, and the capacitance value of CS41 is the same as that of CS42; the capacitance value of CI11 is the same as that of CI12, the capacitance value of CI21 is the same as that of CI22, the capacitance value of CI31 is the same as that of CI32, and the capacitance value of CI41 is the same as that of CI42; the capacitance value of CA01 is the same as that of CA02, the capacitance value of CA11 is the same as that of CA12, the capacitance value of CA21 is the same as that of CA22, the capacitance value of CA31 is the same as that of CA32, and the capacitance value of CA41 is the same as that of CA42; and the capacitance value of CF11 is the same as that of CF12.

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