A multi-layer micro-space power supply board and its manufacturing method

Abstract

The present invention discloses a multi-layer micro-space power supply board and a manufacturing method thereof, which belongs to the technical field of power supply boards. The multi-layer micro-space power supply board includes: a substrate, a dielectric layer, an inner copper layer, a surface copper layer and an inner conductive copper layer. Among them, a through groove is provided on the substrate. The dielectric layer includes a first dielectric layer and a second dielectric layer arranged on opposite sides of the substrate, and at least one through hole is provided on the first dielectric layer. The inner copper layer is stacked between the first dielectric layer and the second dielectric layer and fills the through groove. The surface copper layer includes a first surface copper layer arranged on the side of the first dielectric layer facing away from the inner copper layer and a second surface copper layer arranged on the side of the second dielectric layer facing away from the inner copper layer. The inner conductive copper layer is arranged in the through hole and is electrically connected to the inner copper layer and the first surface copper layer. The present invention maximizes the use of the longitudinal space superposition of the power supply board structure to obtain an ultra-thick copper heat dissipation layer, which significantly improves the heat dissipation capacity of the power supply board structure.

Description

Technical Field

[0001] The present application relates to the technical field of power supply boards, and in particular to a multi-layer micro-space power supply board and a manufacturing method thereof. Background Art

[0002] With the advent of the big data era, market demand for PMICs (power management integrated circuits) is growing. The heat generation associated with high-speed computing is drawing increasing attention. This heat dissipation issue is becoming even more prominent due to the increasing demands for smaller and smaller space. To address this issue, ultra-thick copper is often used for heat dissipation.

[0003] However, when creating ultra-thick copper foil embedded in inner layers to achieve efficient heat dissipation, when the copper foil thickness reaches or exceeds 0.210mm, copper etching efficiency significantly decreases, making the creation of ultra-thick copper patterns extremely difficult. This not only increases processing time but also increases uncertainty and cost. Furthermore, during the lamination process, gaps in the ultra-thick copper inner layer patterns are often poorly filled. This poor filling can prevent cross-layer conductivity, seriously impacting the electrical performance and reliability of the circuit board. Summary of the Invention

[0004] The purpose of the present application is to provide a multi-layer micro-space power supply board and a manufacturing method thereof, so as to solve the problem in the prior art that it is difficult to manufacture an inner layer of ultra-thick copper foil.

[0005] To solve the above technical problems, this application is implemented by adopting the following technical solutions:

[0006] Providing a first copper layer, a substrate, and a second copper layer stacked in sequence;

[0007] A first blind groove is formed on the substrate and the first copper layer, and an opening of the first blind groove is located on the first copper layer;

[0008] providing a third copper layer covering the surface of the second copper layer, the interior of the first blind groove, and the surface of the first copper layer to form an inner copper layer integral with the second copper layer and the first copper layer;

[0009] pattern electroplating the inner copper layer;

[0010] A first dielectric layer and a second dielectric layer are respectively provided on opposite surfaces of the inner copper layer, a fourth copper layer is provided on a side of the first dielectric layer facing away from the inner copper layer, and a fifth copper layer is provided on a side of the second dielectric layer facing away from the inner copper layer;

[0011] A first blind hole is formed on the first dielectric layer and the fourth copper layer, wherein the opening of the first blind hole is located on the fourth copper layer;

[0012] An inner conductive copper layer is provided in the first blind hole, a sixth copper layer is provided on a side of the fourth copper layer facing away from the first dielectric layer, and a seventh copper layer is provided on a side of the fifth copper layer facing away from the second dielectric layer;

[0013] The sixth copper layer and the fourth copper layer are integrally formed into a first surface copper layer, the seventh copper layer and the second copper layer are integrally formed into a second surface copper layer, and the first surface copper layer is electrically connected to the inner copper layer through the inner conductive copper layer;

[0014] The first surface copper layer and the second surface copper layer are patterned.

[0015] Optionally, the step of providing a third copper layer covering the surface of the second copper layer, the interior of the first blind groove, and the surface of the first copper layer includes:

[0016] cleaning the first blind groove;

[0017] Chemical copper deposition in the first blind trench;

[0018] Copper is electroplated to form a third copper layer, and the surface of the third copper layer is polished.

[0019] Optionally, the step of pattern electroplating the inner copper layer includes:

[0020] A dry film is provided in the non-electroplated area of ​​the inner copper layer;

[0021] The inner copper layer is electroplated with copper and tin in sequence;

[0022] Perform film removal, etching, and tin stripping in sequence;

[0023] A resin isolation layer is provided on the exposed surface of the inner copper layer;

[0024] The resin isolation layer on the electroplated side of the inner copper layer is removed by grinding.

[0025] Optionally, after providing a fifth copper layer on a side of the second dielectric layer facing away from the inner copper layer and before providing an inner conductive copper layer in the first blind hole, the method further includes:

[0026] At least one first through hole is formed on the fourth copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer and the fifth copper layer;

[0027] A first insulating layer is provided in the first through hole;

[0028] A second through hole is formed in the first insulating layer.

[0029] Optionally, a cross-layer conductive copper layer is arranged in the second through hole; a cross-layer conductive copper layer is arranged in the second through hole, an inner-layer conductive copper layer is arranged in the first blind hole, a sixth copper layer is arranged on the side of the fourth copper layer facing away from the first dielectric layer, and a seventh copper layer is arranged on the side of the fifth copper layer facing away from the second dielectric layer. The steps include: electroplating copper, and forming a third through hole on the first surface copper layer, the cross-layer conductive copper layer and the second surface copper layer by electroplating copper.

[0030] Optionally, a second insulating layer is provided in the third through hole;

[0031] The first surface copper layer is back-sunk copper on a side facing away from the first dielectric layer, and the second surface copper layer is back-sunk copper on a side facing away from the second dielectric layer.

[0032] On the other hand, the present application provides a multi-layer micro-space power supply board, comprising: a substrate, wherein a through groove is formed on the substrate;

[0033] a dielectric layer comprising a first dielectric layer and a second dielectric layer disposed on opposite sides of the substrate, wherein the first dielectric layer is provided with at least one through hole;

[0034] an inner copper layer, stacked between the first dielectric layer and the second dielectric layer, and filling the through groove;

[0035] The surface copper layer comprises a first surface copper layer provided on a side of the first dielectric layer facing away from the inner copper layer and a second surface copper layer provided on a side of the second dielectric layer facing away from the inner copper layer;

[0036] The inner conductive copper layer is disposed in the through hole and electrically connected to the inner copper layer and the first surface copper layer.

[0037] This solution creates a super-thick copper heat sink between the first and second dielectric layers by providing through-slots in the substrate and filling them with an inner copper layer. This solution maximizes the vertical space of the power board structure, creating a super-thick copper heat sink. This significantly improves the heat dissipation capacity of the power board structure, helping to reduce its operating temperature and enhance its stability and reliability.

[0038] Optionally, at least one buried via is formed on the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer and the second surface copper layer, and both ends of the buried via are respectively located in the first surface copper layer and the second surface copper layer, and the first insulating layer, the cross-layer conductive copper layer and the second insulating layer are nested in sequence in the buried via, and the cross-layer conductive copper layer is electrically connected to the first surface copper layer and the second surface copper layer.

[0039] This solution forms a conductive channel through the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the second surface copper layer by providing buried vias. A first insulating layer is placed within the buried via to isolate the inner copper layer, and a cross-layer conductive copper layer is provided within the first insulating layer to achieve conductivity between the first surface copper layer and the second surface copper layer, thereby achieving conductivity across the inner copper layer. The cross-layer conductive copper layer design provides greater flexibility in the layout and routing of the power board, meeting the design requirements of complex circuits and effectively reducing the overall unit graphic size of the power board structure.

[0040] Optionally, a resin isolation layer is provided between the first dielectric layer and the second dielectric layer, and the resin isolation layer covers both sides of the inner copper layer. The resin isolation layer improves the electrical isolation performance and structural stability of the power board, reducing the risk of failure due to short circuits, signal interference, or structural looseness.

[0041] Optionally, unit graphic cutting paths are provided on the substrate.

[0042] Beneficial effects

[0043] The present application forms a first blind groove on the substrate and the first copper layer, and then fills the first blind groove with copper. Then, on this basis, graphic selective copper plating is further used to perform targeted thickening to obtain an inner copper layer with ultra-thick copper characteristics. The surface flatness of the inner copper layer obtained by the above method (the difference between the inner copper layer and the substrate) can be reduced by 2 / 3 compared with the existing process. It makes it more convenient to fill the resin at the unit graphic cutting position before lamination of the inner copper layer, avoiding the occurrence of bubbles, voids and other undesirable conditions caused by the resin filling of the ultra-thick copper gap before lamination in the existing technology. And the use of graphic selective copper plating for thickening saves the cost of copper plating compared to electroplating ultra-thick copper on the entire board.

[0044] This application forms a conductive channel in the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the second surface copper layer by providing buried vias. By providing a first insulating layer within the buried vias to isolate the inner copper layer, and by providing a cross-layer conductive copper layer within the first insulating layer to achieve conductivity between the first surface copper layer and the second surface copper layer, surface wiring space is conserved to the greatest extent possible, while utilizing the inner layer's extra-thick copper space for heat dissipation to the greatest extent possible. This allows for a reduction of more than 20% in unit pattern size while maintaining the same heat dissipation, ultimately achieving an overall cost reduction advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 This is a schematic diagram of the overall structure of the multi-layer micro-space power supply board provided by this application;

[0047] Figure 2 This is a flow chart of a method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0048] Figure 3 This is a flow chart of a method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0049] Figure 4 This is a schematic structural diagram of the first copper layer, substrate, and second copper layer in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0050] Figure 5 This is a structural schematic diagram of forming a first blind groove in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0051] Figure 6 This is a schematic structural diagram of forming a third copper layer in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0052] Figure 7 This is a schematic diagram of the grinding structure of the third copper layer in the method for manufacturing the multi-layer micro-space power board of Example 1 provided in this application;

[0053] Figure 8 This is a schematic structural diagram of a dry film provided by pattern electroplating in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0054] Figure 9 This is a schematic diagram of the structure of patterned copper and tin electroplating in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0055] Figure 10 This is a structural diagram of pattern electroplating film removal, etching, and tin stripping in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0056] Figure 11 This is a structural schematic diagram of providing a resin isolation layer in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0057] Figure 12 This is a schematic structural diagram of the step of grinding and removing the resin isolation layer on the electroplated side of the inner copper layer in the method for manufacturing the multi-layer micro-space power board according to Example 1 of the present application;

[0058] Figure 13 This is a schematic structural diagram of the first dielectric layer, the second dielectric layer, the fourth copper layer, and the fifth copper layer in the method for manufacturing the multi-layer micro-space power board according to Example 1 of the present application;

[0059] Figure 14 This is a structural schematic diagram of forming a first through hole in the method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0060] Figure 15 This is a structural schematic diagram of providing a first insulating layer in the method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0061] Figure 16 This is a structural schematic diagram of forming a second through hole in the method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0062] Figure 17 This is a schematic structural diagram of forming a first blind hole in the method for manufacturing a multi-layer micro-space power board according to Example 1 of the present application;

[0063] Figure 18 This is a schematic structural diagram of forming a cross-layer conductive copper layer, an inner layer conductive copper layer, a sixth copper layer, a seventh copper layer, and a third through hole in the manufacturing method of the multi-layer micro-space power board of Example 1 provided by the present application;

[0064] Figure 19 This is a structural schematic diagram of providing a second insulating layer in the method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0065] Figure 20 This is a schematic structural diagram of the reverse copper deposition method in the method for manufacturing a multi-layer micro-space power board according to Example 2 of the present application;

[0066] Figure 21 It is a structural schematic diagram of forming an outer layer circuit in the manufacturing method of the multi-layer micro-space power board of Example 1 provided in this application.

[0067] Explanation of the reference numerals: 100-substrate; 110-through groove; 120-unit graphic cutting road; 210-first dielectric layer; 220-second dielectric layer; 300-inner copper layer; 310-first copper layer; 320-second copper layer; 330-third copper layer; 331-dry film; 332-tin; 410-first surface copper layer; 411-fourth copper layer; 412-sixth copper layer; 420-second surface copper layer; 421-fifth copper layer; 422-seventh copper layer; 500-inner conductive copper layer; 610-first insulating layer; 620-cross-layer conductive copper layer; 630-second insulating layer; 640-first through hole; 650-second through hole; 660-third through hole; 700-resin isolation layer; 800-first blind groove; 900-first blind hole. DETAILED DESCRIPTION

[0068] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present disclosure / application, and not all embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application, its application, or use.

[0069] Example 1

[0070] This embodiment introduces a method for manufacturing a multi-layer micro-space power supply board. Figure 2 The manufacturing method of the multi-layer micro-space power board in this embodiment includes:

[0071] S100 : providing a first copper layer 310 , a substrate 100 , and a second copper layer 320 stacked in sequence.

[0072] refer to Figure 4 A first copper layer 310, a substrate 100, and a second copper layer 320 are provided, stacked in sequence. The substrate 100 is located between the first copper layer 310 and the second copper layer 320. The thickness of the substrate 100 is ≤ 0.1 mm. Furthermore, a unit pattern cutting path is provided on the substrate 100. S200: A first blind groove 800 is formed on the substrate 100 and the first copper layer 310. The opening of the first blind groove 800 is located on the first copper layer 310.

[0073] refer to Figure 5, a first blind groove 800 is formed on the substrate 100 and the first copper layer 310, and the opening of the first blind groove 800 is located on the first copper layer 310. Specifically, first, a window is laser opened on the first copper layer 310. Then, a laser groove is basically performed along the window opening position of the first copper layer 310, so as to obtain the first blind groove 800 with the opening located on the first copper layer 310. It should be noted that the first blind groove 800 should avoid the unit graphic cutting path setting, so that when the unit graphic is subsequently cut, there is no need to add an additional etching process to remove the copper on the unit graphic cutting path. By reserving the grooves at the unit graphic cutting path position, the problem of low efficiency caused by directly etching the ultra-thick copper layer is avoided, and the problems of low etching factor and low graphic accuracy in the ultra-thick copper etching process are also avoided.

[0074] S300 : providing a third copper layer 330 covering the surface of the second copper layer 320 , the interior of the first blind groove 800 and the surface of the first copper layer 310 to form an inner copper layer 300 integrated with the second copper layer 320 and the first copper layer 310 .

[0075] refer to Figure 6 A third copper layer 330 is provided to cover the surface of the second copper layer 320, the interior of the first blind groove 800, and the surface of the first copper layer 310. The third copper layer 330 can be combined with the second copper layer 320 and the first copper layer 310 by electroplating, chemical deposition, or other methods to form an integrated inner copper layer 300.

[0076] As an optional embodiment, the step of providing the third copper layer 330 covering the surface of the second copper layer 320, the interior of the first blind groove 800 and the surface of the first copper layer 310 includes:

[0077] S301: Cleaning the first blind groove 800;

[0078] Remove the glue residue in the first blind groove 800 to ensure that the interior of the first blind groove is clean and free of impurities.

[0079] S302: Electroless copper deposition in the first blind trench 800;

[0080] Using chemical deposition technology, a thin layer of chemical copper is deposited on the inner wall of the first blind trench 800. This layer of chemical copper is often called a "seed layer." Chemical copper deposition provides a uniform conductive base for electroplated copper, enhancing the bonding between copper layers.

[0081] S303 : electroplating copper to form a third copper layer 330 , and polishing the surface of the third copper layer 330 .

[0082] The third copper layer 330 is formed by electroplating copper to cover the surface of the second copper layer 320, the interior of the blind groove and the surface of the first copper layer 310. Figure 7After the electroplating is completed, the surface of the third copper layer 330 is ground to remove burrs, protrusions and uneven parts on the surface so that the surface of the copper layer reaches the required flatness and smoothness.

[0083] S400: Graphically electroplating the inner copper layer 300 to increase the copper thickness.

[0084] refer to Figures 8 to 12 In this embodiment, the step of pattern electroplating the inner copper layer 300 includes:

[0085] S401: a dry film 331 is provided in the non-electroplating area of ​​the inner copper layer 300.

[0086] Before electroplating, a dry film 331 is applied to the non-electroplating areas of the inner copper layer 300. Dry film 331 is a photosensitive resin material that forms a pattern through exposure and development processes, protecting the underlying copper layer from corrosion by the electroplating solution. The thickness of dry film 331 is selected based on actual needs. It is important to note that the maximum thickness of dry film 331 should not exceed 0.200 mm.

[0087] S402: The inner copper layer 300 is electroplated with copper and tin 332 in sequence.

[0088] After the dry film 331 is formed, copper electroplating is first performed in an electroplating solution to increase the thickness of the copper layer, followed by tin electroplating 332 .

[0089] S403: performing film removal, etching, and tin stripping 332 in sequence.

[0090] After the electroplating is complete, the dry film 331 needs to be removed. Next, an etching process is performed, using chemical or physical methods to remove the copper layer not protected by the electroplating, forming the desired circuit pattern. Finally, the tin layer 332 is stripped off, leaving behind the copper layer that has been electroplated and etched.

[0091] S404 : a resin isolation layer 700 is provided on the exposed surface of the inner copper layer 300 .

[0092] S405 : Grinding and removing the resin isolation layer 700 on the electroplating side of the inner copper layer 300 .

[0093] Through the above steps, the resin isolation layer 700 covers both sides of the inner copper layer 300, thereby improving the electrical isolation performance of the inner copper layer 300.

[0094] The inner copper layer 300 is thickened by pattern electroplating. While increasing the thickness of the inner copper layer 300, the structural robustness of the inner copper layer 300 is maintained, ensuring that the inner copper layer 300 functions as a whole and avoiding problems such as poor conductivity. In this embodiment, the inner copper layer 300 obtained through the above steps has a thickness greater than 0.34 mm, and the resulting inner copper layer 300 has a concavity (the difference between the inner copper layer and the substrate) less than 0.005 mm.

[0095] This embodiment achieves a thicker inner copper layer 300 by electroplating the first blind slot 800 and then grinding it after electroplating, followed by pattern-selective copper plating to thicken the copper. This solves the problem of resin difficulty filling gaps between ultra-thick copper and avoids the waste of thick copper plating across the entire board. Furthermore, in the manufacturing process of ultra-thick copper PCBs, due to the thick copper layer, direct etching makes it difficult to ensure line precision and surface quality. This embodiment uses blind slot plating and pattern-selective copper plating to precisely control the location and thickness of the copper layer, thereby reducing the difficulty of etching and improving line precision and surface quality.

[0096] S500: A first dielectric layer 210 and a second dielectric layer 220 are respectively disposed on opposite surfaces of the inner copper layer 300. A fourth copper layer 411 is disposed on a surface of the first dielectric layer 210 facing away from the inner copper layer 300. A fifth copper layer 421 is disposed on a surface of the second dielectric layer 220 facing away from the inner copper layer 300.

[0097] refer to Figure 13 First, a first dielectric layer 210 and a second dielectric layer 220 are laminated onto opposite surfaces of the inner copper layer 300. Next, a fourth copper layer 411 is laminated onto the surface of the first dielectric layer 210 facing away from the inner copper layer 300, and a fifth copper layer 421 is laminated onto the surface of the second dielectric layer 220 facing away from the inner copper layer 300. The isolation between the first dielectric layer 210 and the second dielectric layer 220 ensures electrical insulation between the fourth and fifth copper layers 411 and 421 and the inner copper layer 300.

[0098] S600 : forming a first blind via 900 on the first dielectric layer 210 and the fourth copper layer 411 , wherein the opening of the first blind via 900 is located on the fourth copper layer 411 .

[0099] refer to Figure 17 A first blind via 900 is formed on the first dielectric layer 210 and the fourth copper layer 411, with the opening of the first blind via 900 located on the fourth copper layer 411. Specifically, a window is firstly laser-cut on the fourth copper layer 411. Next, a hole is laser-drilled at the location where the window was cut, thereby forming the first blind via 900 with the opening located on the fourth copper layer 411.

[0100] S700 : an inner conductive copper layer 500 is disposed in the first blind via 900 , a sixth copper layer 412 is disposed on a surface of the fourth copper layer 411 facing away from the first dielectric layer 210 , and a seventh copper layer 422 is disposed on a surface of the fifth copper layer 421 facing away from the second dielectric layer 220 .

[0101] The sixth copper layer 412 and the fourth copper layer 411 are integrally formed into a first surface copper layer 410 , the seventh copper layer 422 and the second copper layer 320 are integrally formed into a second surface copper layer 420 , and the first surface copper layer 410 is conductively connected to the inner copper layer 300 through the inner conductive copper layer 500 .

[0102] refer to Figure 18 In this embodiment, copper electroplating is used to form an inner conductive copper layer 500 within the first blind via 900, a sixth copper layer 412 on the surface of the fourth copper layer 411 facing away from the first dielectric layer 210, and a seventh copper layer 422 on the surface of the fifth copper layer 421 facing away from the second dielectric layer 220. The first surface copper layer 410 is electrically connected to the inner copper layer 300 via the inner conductive copper layer 500, achieving electrical connection between the multiple layers. The inner copper layer 300, the inner conductive copper layer 500, and the first surface copper layer 410 form an ultra-thick copper heat dissipation layer, significantly improving the heat dissipation capability of the power board structure, helping to reduce the operating temperature of the power board and enhance its stability and reliability.

[0103] S800 : patterning the first surface copper layer 410 and the second surface copper layer 420 .

[0104] refer to Figure 21 The first and second surface copper layers 410 and 420 are patterned according to actual needs to form the outer circuitry of the multi-layer micro-space power supply board. The following is an optional patterning method. First, a layer of photoresist is evenly coated on the surfaces of the first and second surface copper layers 410 and 420. Using a photolithography machine or a stepper, the photoresist-coated copper layer is exposed through a mask. The pattern on the mask determines the final circuit layout of the circuit board. During the exposure process, light passes through the transparent portion of the mask and strikes the photoresist, causing a chemical reaction. After exposure, the circuit board is placed in a developer, which dissolves the exposed areas of the photoresist, forming the desired pattern on the copper surface. A chemical etchant or plasma etching method is used to remove the copper layer not covered by the photoresist. The etchant reacts with the copper not covered by the photoresist while not attacking the copper layer protected by the photoresist. After etching, only the areas covered by the photoresist remain on the copper layer, forming the outer circuitry of the multi-layer micro-space power supply board. After etching is complete, the remaining photoresist is removed using a stripping solution or plasma stripping method to expose the complete outer layer circuit. Finally, the circuit board is cleaned to remove residual impurities such as the etching solution and stripping solution.

[0105] S900: Solder-proof treatment for outer circuits.

[0106] Apply solder mask to the outer circuit layers to protect them from environmental corrosion and the risk of short circuits. The following is an optional solder mask treatment method. First, remove the oxide layer, oil stains, and other impurities from the outer circuit surface to ensure that the solder mask ink adheres firmly to the copper layer. Common cleaning methods include chemical cleaning agents and ultrasonic cleaning. Next, select an appropriate solder mask ink based on the specific application scenario and requirements. Apply the solder mask ink evenly to the outer circuit surface using methods such as screen printing, electrostatic spraying, curtain printing, or roller printing. The solder mask-coated outer circuit layers are pre-baked in an oven to evaporate the solvent in the ink, creating a smooth, non-sticky coating. A photolithography machine or exposure machine then transfers the image to the solder mask ink using film (or laser direct imaging). During exposure, ultraviolet light strikes the ink, causing a photochemical reaction that hardens and firmly bonds it to the copper layer. The exposed PCB is then placed in a developer to rinse away any unhardened ink. Developers typically use weak alkaline solutions such as sodium carbonate. Finally, the developed PCB is placed in an oven for post-baking. The purpose of post-baking is to completely cure the ink and enhance its solder resistance, wear resistance, and chemical corrosion resistance.

[0107] Example 2

[0108] Based on the same inventive concept as that of Example 1, Figure 3 This embodiment is used to achieve cross-layer conduction between the first surface copper layer 410 and the second surface copper layer 420 based on the manufacturing method of Example 1. It is specifically achieved in the following manner.

[0109] First, after the fifth copper layer 421 is formed on the surface of the second dielectric layer 220 facing away from the inner copper layer 300 and before the inner conductive copper layer 500 is formed in the blind hole, the present embodiment further includes:

[0110] S510 : forming at least one first through hole 640 on the fourth copper layer 411 , the first dielectric layer 210 , the inner copper layer 300 , the second dielectric layer 220 and the fifth copper layer 421 .

[0111] refer to Figure 14 In this embodiment, at least one first through-hole 640 is formed by mechanical drilling in the fourth copper layer 411, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the fifth copper layer 421. The first through-hole 640 penetrates the fourth copper layer 411, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the fifth copper layer 421, providing a physical path across the inner copper layer 300.

[0112] S520 : a first insulating layer 610 is disposed in the first through hole 640 .

[0113] refer to Figure 15 , the first through hole 640 is plugged with resin to form a first insulating layer 610 , and the first insulating layer 610 at both ends of the first through hole 640 is polished and flat.

[0114] S530 : forming a second through hole 650 in the first insulating layer 610 .

[0115] refer to Figure 16 A second through hole 650 is formed by mechanical drilling in the first insulating layer 610 , thereby forming a conductive channel in the first insulating layer 610 , which is connected to the inner first insulating layer 610 and can isolate the inner copper layer 300 .

[0116] S710 : Disposing a cross-layer conductive copper layer 620 in the second through hole 650 .

[0117] refer to Figure 18 During the process of forming the inner conductive copper layer 500 in the blind via via copper electroplating, forming the sixth copper layer 412 on the surface of the fourth copper layer 411 facing away from the first dielectric layer 210, and forming the seventh copper layer 422 on the surface of the fifth copper layer 421 facing away from the second dielectric layer 220, a cross-layer conductive copper layer 620 can be formed in the second through-hole 650. Furthermore, through the high-aspect-ratio through-hole copper electroplating process, a third through-hole 660 can be formed on the first surface copper layer 410, the cross-layer conductive copper layer 620, and the second surface copper layer 420. In this embodiment, both the isolation of the inner copper layer 300 and the conduction between the first surface copper layer 410 and the second surface copper layer 420 are achieved in the first through-hole 640, effectively reducing the size of the overall unit pattern.

[0118] S720: The second insulating layer 630 is disposed in the third through hole 660, and copper is deposited on the first surface copper layer 410 facing away from the first dielectric layer 210 and the second surface copper layer 420 facing away from the second dielectric layer 220. Figure 19 and Figure 20 The reverse copper deposition not only covers the third through hole 660 , but also further increases the copper thickness of the first surface copper layer 410 and the second surface copper layer 420 .

[0119] Example 3

[0120] This embodiment introduces a multi-layer micro-space power supply board. Figure 1The multilayer micro-space power board in this embodiment includes: a substrate 100, a dielectric layer, an inner copper layer 300, a surface copper layer, and an inner conductive copper layer 500. The substrate 100 is provided with a through-slot 110, which is formed by laser lithography. The dielectric layer includes a first dielectric layer 210 and a second dielectric layer 220, which are disposed on opposite sides of the substrate 100. The first dielectric layer 210 is provided with at least one through-hole. The inner copper layer 300 is stacked between the first dielectric layer 210 and the second dielectric layer 220 and fills the through-slot 110. Furthermore, a resin isolation layer 700 is provided between the first dielectric layer 210 and the second dielectric layer 220, covering both sides of the inner copper layer 300. The resin isolation layer 700 improves the electrical isolation performance and structural stability of the power board, reducing the risk of failure due to short circuits, signal interference, or structural looseness. The surface copper layer is solder mask-treated and includes a first surface copper layer 410 disposed on the side of the first dielectric layer 210 facing away from the inner copper layer 300, and a second surface copper layer 420 disposed on the side of the second dielectric layer 220 facing away from the inner copper layer 300. An inner conductive copper layer 500 is disposed within the through-hole and electrically connected to the inner copper layer 300 and the first surface copper layer 410. In this embodiment, the inner copper layer 300 is greater than 0.34 mm thick.

[0121] In this embodiment, through-slots 110 are provided on the substrate 100 and filled with the inner copper layer 300, forming a relatively thick copper heat dissipation layer between the first dielectric layer 210 and the second dielectric layer 220. By providing through-holes in the first dielectric layer 210 and positioning the inner conductive copper layer 500 within the through-holes, an ultra-thick copper heat dissipation layer is formed, consisting of the inner copper layer 300, the inner conductive copper layer 500, and the first surface copper layer 410. This ultra-thick copper heat dissipation layer is achieved by maximizing the longitudinal spatial stacking of the power board structure, significantly improving the heat dissipation capacity of the power board structure, helping to reduce the operating temperature of the power board and enhance its stability and reliability.

[0122] In this embodiment, unit pattern cutting streets 120 are provided on the substrate 100 .

[0123] Example 4

[0124] Based on the same inventive concept as described in Example 3, refer to Figure 1This embodiment is used to achieve cross-layer conduction in a multi-layer micro-space power board to meet the design requirements of complex circuits. Specifically, in this embodiment, at least one buried via is formed in the first surface copper layer 410, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the second surface copper layer 420. The ends of the buried via are located in the first surface copper layer 410 and the second surface copper layer 420, respectively. The first insulating layer 610, the cross-layer conductive copper layer 620, and the second insulating layer 630 are sequentially nested within the buried via. The cross-layer conductive copper layer 620 is electrically connected to the first surface copper layer 410 and the second surface copper layer 420.

[0125] In this embodiment, buried vias are provided to form conductive channels in the first surface copper layer 410, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the second surface copper layer 420. The inner copper layer 300 is isolated by providing a first insulating layer 610 within the buried vias, and the first surface copper layer and the second surface copper layer 420 are connected by providing a cross-layer conductive copper layer 620 within the first insulating layer 610, thereby achieving the conductive requirement across the inner copper layer 300. The design of the cross-layer conductive copper layer 620 makes the power board more flexible in layout and routing, meets the design requirements of complex circuits, and can maximize the savings in surface wiring space and maximize the use of the inner layer heat dissipation ultra-thick copper space. Under the premise of the same heat dissipation, the unit graphic size can be reduced by more than 20%, ultimately achieving an overall cost reduction advantage.

[0126] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present disclosure / application. These improvements and modifications should also be regarded as the scope of protection of the present disclosure / application.

Claims

1. A method for manufacturing a multi-layer micro-space power board, characterized in that: The following steps are involved: Providing a first copper layer, a substrate, and a second copper layer stacked in sequence; A first blind groove is formed on the substrate and the first copper layer, and an opening of the first blind groove is located on the first copper layer; providing a third copper layer covering the surface of the second copper layer, the interior of the first blind groove, and the surface of the first copper layer to form an inner copper layer integral with the second copper layer and the first copper layer; pattern electroplating the inner copper layer; The step of pattern electroplating the inner copper layer comprises: A dry film is provided in the non-electroplated area of ​​the inner copper layer; The inner copper layer is electroplated with copper and tin in sequence; Perform film removal, etching, and tin stripping in sequence; A resin isolation layer is provided on the exposed surface of the inner copper layer; Grinding and removing the resin isolation layer on the electroplated side of the inner copper layer; A first dielectric layer and a second dielectric layer are respectively provided on opposite surfaces of the inner copper layer, a fourth copper layer is provided on a side of the first dielectric layer facing away from the inner copper layer, and a fifth copper layer is provided on a side of the second dielectric layer facing away from the inner copper layer; A first blind hole is formed on the first dielectric layer and the fourth copper layer, wherein the opening of the first blind hole is located on the fourth copper layer; An inner conductive copper layer is provided in the first blind hole, a sixth copper layer is provided on a side of the fourth copper layer facing away from the first dielectric layer, and a seventh copper layer is provided on a side of the fifth copper layer facing away from the second dielectric layer; The sixth copper layer and the fourth copper layer are integrally formed into a first surface copper layer, the seventh copper layer and the second copper layer are integrally formed into a second surface copper layer, and the first surface copper layer is electrically connected to the inner copper layer through the inner conductive copper layer; The first surface copper layer and the second surface copper layer are patterned.

2. The method for manufacturing a multi-layer micro-space power board according to claim 1, characterized in that: The step of providing a third copper layer covering the surface of the second copper layer, the interior of the first blind groove and the surface of the first copper layer includes: cleaning the first blind groove; Chemical copper deposition in the first blind trench; Copper is electroplated to form a third copper layer, and the surface of the third copper layer is polished.

3. The method for manufacturing a multi-layer micro-space power board according to claim 1, characterized in that: After the fifth copper layer is provided on the side of the second dielectric layer facing away from the inner copper layer and before the inner conductive copper layer is provided in the first blind hole, the method further includes: At least one first through hole is formed on the fourth copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer and the fifth copper layer; A first insulating layer is provided in the first through hole; A second through hole is formed in the first insulating layer.

4. The method for manufacturing a multi-layer micro-space power board according to claim 3, characterized in that: The steps of arranging a cross-layer conductive copper layer in the second through hole, arranging a cross-layer conductive copper layer in the second through hole, arranging an inner layer conductive copper layer in the first blind hole, arranging a sixth copper layer on a side of the fourth copper layer facing away from the first dielectric layer, and arranging a seventh copper layer on a side of the fifth copper layer facing away from the second dielectric layer include: electroplating copper to form a third through hole on the first surface copper layer, the cross-layer conductive copper layer, and the second surface copper layer by electroplating copper.

5. The method for manufacturing a multi-layer micro-space power board according to claim 4, characterized in that: A second insulating layer is provided in the third through hole; The first surface copper layer is back-sunk copper on a side facing away from the first dielectric layer, and the second surface copper layer is back-sunk copper on a side facing away from the second dielectric layer.

6. A multi-layer micro-space power board, characterized in that: include: A base plate, wherein a through groove is formed on the base plate; a dielectric layer comprising a first dielectric layer and a second dielectric layer disposed on opposite sides of the substrate, wherein the first dielectric layer is provided with at least one through hole; an inner copper layer, stacked between the first dielectric layer and the second dielectric layer, and filling the through groove; The surface copper layer comprises a first surface copper layer provided on a side of the first dielectric layer facing away from the inner copper layer and a second surface copper layer provided on a side of the second dielectric layer facing away from the inner copper layer; an inner conductive copper layer, disposed in the through hole and electrically connected to the inner copper layer and the first surface copper layer; At least one buried via is formed on the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer and the second surface copper layer, the two ends of the buried via are respectively located in the first surface copper layer and the second surface copper layer, the first insulating layer, the cross-layer conductive copper layer and the second insulating layer are nested in sequence in the buried via, the cross-layer conductive copper layer is electrically connected to the first surface copper layer and the second surface copper layer; a resin isolation layer is provided between the first dielectric layer and the second dielectric layer, and the resin isolation layer covers both side surfaces of the inner copper layer.

7. The multi-layer micro-space power board according to claim 6, characterized in that: Unit graphic cutting paths are provided on the substrate.

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