Memory cell based on ferroelectric topological domain and preparation method thereof

Abstract

The invention relates to a memory cell based on a ferroelectric topological domain and a preparation method of the memory cell. The memory cell comprises a ferroelectric nano island array and electrodes, and the electrode is positioned in the center of the ferroelectric nano island array. The preparation method of the memory cell based on the ferroelectric topological domain comprises the following steps: preparing a ferroelectric nano island array on a substrate through a pulse laser deposition method and an argon ion beam etching method, and depositing a circular electrode at the central position of the ferroelectric nano island array through a focused ion beam assisted deposition method, and obtaining the memory cell based on the ferroelectric topological domain. According to the method, a new method is provided for constructing a novel low-dimensional topological electronics device, and compared with a traditional storage unit, the prepared ferroelectric topological storage unit array device is improved in integration level and density.

Description

Technical Field

[0001] The present invention relates to the field of information storage technology, and particularly to a storage unit based on ferroelectric topological domains and a preparation method thereof. Background Art

[0002] Traditional storage unit technologies cover from early mechanical memories, such as punched cards and magnetic tapes, to modern semiconductor memories, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc. The early mechanical memories had slow read / write speeds, small capacities, and were vulnerable to external interference. With the development of computer technology, in the 1950s, RAM gradually replaced the mechanical memories. It had fast read / write speeds and large capacities and became the mainstream storage medium. Among them, DRAM consists of a capacitor and a transistor, with a large capacity but relatively slow read / write speeds; while SRAM consists of a bistable circuit, with fast read / write speeds but small capacities. To meet the growing demands for storage capacity and read / write speeds, storage technologies have been continuously innovated. For example, flash memory is a non-volatile memory, divided into NAND flash and NOR flash, which can retain data after power-off and is suitable for mobile devices and computer memory expansion. Another new memory technology, phase change memory (PCM), uses the phase change characteristics of materials to store data, with advantages such as high-speed writing and reading, low power consumption, and long lifespan. In addition, to increase the storage capacity, 3D stacked memory technology stacks multiple layers of memories together, achieving a larger storage capacity while reducing the physical size of the memory. Similarly, topological domains in ferroelectric materials have great application potential in the research field of new information electronic devices. For example, by regulating the flipping of the central-type topological domain structure, the conductive domain walls embedded therein can achieve reversible switching between high-resistance states and low-resistance states, promising to build a new generation of high-performance non-volatile information storage devices.

[0003] At present, traditional storage units have the problem of poor horizontal scalability. Traditional storage architectures, especially SAN storage devices, generally adopt a dual-controller architecture, where the two controllers back up each other, and two switches are configured to connect to the front-end servers. The horizontal expansion ability of this architecture is limited, restricted by the external service ability of the front-end controller. Vertically expanding the number of disks cannot effectively improve the service ability of the storage device to the outside. At the same time, the front-end controller becomes the bottleneck of the entire storage performance, affecting the scalability and performance of the storage system. At the same time, the stability of traditional storage units also has problems. Although the traditional storage architecture is relatively reliable in terms of stability, once a controller fails, the performance of the system will drop significantly, affecting the normal use of storage. In addition, traditional storage generally uses a dedicated SAN or IP network, which has a relatively high stability but also a relatively high maintenance cost. More importantly, although DRAM has a fast read and write speed, it requires continuous power supply to maintain information and has a high power consumption. While flash memory is non-volatile and suitable for long-term large-capacity storage, its read and write speed is relatively slow. Ferroelectric memory is in between the two, but existing ferroelectric random access memory (FeRAM) has the problem that reading the polarization value is a destructive operation, requires extremely high durability, and has a high write voltage, which affects its popularization in practical applications.

[0004] In addition, there are also many limitations and difficulties in the research on electronic devices based on ferroelectric topological domain structures, including incompatibility with the current industrial high-integration device fabrication process, complex resistive switching behavior regulation process, imperfect functional characteristics, etc. In addition, the topological domain storage device units proposed in current research are all based on bare nano-islands or nano-sheet structures without a fixed top electrode, which also limits the possibility of their further practical application. And when a conductive electrode is grown on its surface to form a complete "sandwich" device structure, the ferroelectric nanostructures covered by the top electrode will be affected by the interface effect and other effects, resulting in possible changes in their domain structure, and whether the resulting high-performance resistive switching behavior can be maintained will become an unknown. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a storage unit based on ferroelectric topological domains and its preparation method, constructing a storage unit with high integration and density.

[0006] The purpose of the present invention is achieved by the following technical solutions:

[0007] In the first aspect, the present invention provides a storage unit based on ferroelectric topological domains, including a ferroelectric nano-island array and an electrode; the electrode is located at the center of the ferroelectric nano-island array.

[0008] Compared with the prior art, the storage unit based on ferroelectric topological domains provided by the present invention is designed based on four-quadrant topological domains, and has improved integration and density compared with traditional storage units. Each of these device units is nanoscale in size (about 400 nm) and is arranged in a large area in an orderly and close manner on a device substrate. Compared with the existing device structure (where the ferroelectric layer is a whole thin film), this greatly improves the storage density of the device. At the same time, the device unit structure can stably form topological domains (central domains). Compared with existing storage devices (non-topological domains), due to the topological protection characteristics of this device structure, its performance is more stable. Therefore, the storage unit based on ferroelectric topological domains provided by the present invention can utilize the high conductivity of domain walls and the fast response characteristics driven by an electric field to achieve low-power and high-speed read and write operations, not only reducing the power consumption of the storage unit, but also helping to improve the read and write speed of the storage unit.

[0009] In a preferred embodiment, the ferroelectric nanoisland array is a ferroelectric layer / bottom electrode nanoisland array.

[0010] In a preferred embodiment, the bottom electrode is a SrRuO3 conductive layer, and a ferroelectric layer is stacked on its upper surface, and the two together form a ferroelectric nanoisland array with a ferroelectric layer / bottom electrode structure.

[0011] In a preferred embodiment, the ferroelectric layer is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, a HfO2 layer, or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode.

[0012] In a second aspect, the present invention also provides a method for preparing a storage unit based on ferroelectric topological domains, including the following steps: preparing a ferroelectric nanoisland array on a substrate by pulsed laser deposition and argon ion beam etching, and then depositing a circular electrode at the center position of the ferroelectric nanoisland array by focused ion beam assisted deposition to obtain a storage unit based on ferroelectric topological domains.

[0013] Compared with the prior art, the ferroelectric topological storage unit array device prepared by using the preparation method of the present invention has improved integration and density compared with traditional storage units. Among them, the focused ion beam assisted deposition method has the advantages of high precision and controllability in preparing electrodes, can accurately position and grow and process nano-scale electrodes on nano-scale BFO nanoislands, avoiding the micron-scale limitations and randomness of traditional photolithography methods, and does not require a mask template required by traditional photolithography methods, greatly shortening the process cycle and reducing costs.

[0014] In a preferred embodiment, the ferroelectric nanoisland array is prepared by the following steps: First, an epitaxial bottom electrode is grown on a substrate by pulsed laser deposition technology. Second, a monolayer of polystyrene spheres is evenly spread on the epitaxial bottom electrode as a mask template, and then the bottom electrode is etched into a nanoisland array by argon ion beam etching. Finally, a ferroelectric layer is self-assembled and grown on the cleaned nanoisland array by pulsed laser deposition technology, thus obtaining the ferroelectric nanoisland array.

[0015] In a preferred embodiment, the substrate is a (001)-oriented SrTiO3 single crystal substrate; the bottom electrode is a SrRuO3 conductive layer with a thickness of 130 nm, and its preparation conditions are: the pulse energy is 74 - 87 mJ, the pulse frequency is 8 Hz, the epitaxial temperature is 660 - 730 °C, and the oxygen pressure is 15 Pa.

[0016] In a preferred embodiment, the ferroelectric layer is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, a HfO2 layer, or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode; and the circular electrode is any one of a Pt, Au, or Co electrode.

[0017] In a preferred embodiment, the ferroelectric layer is a BiFeO3 layer with a thickness of 60 nm, and its preparation conditions are: the pulse energy is 64 - 70 mJ, the pulse frequency is 8 Hz, the temperature is 660 - 720 °C, and the oxygen pressure is 20 Pa.

[0018] In a preferred embodiment, the circular electrode is prepared by focused ion beam assisted deposition.

[0019] The preparation method of the memory cell based on ferroelectric topological domains provided by the present invention prepares a BFO / SRO nanoisland array on a substrate by pulsed laser deposition technology and Ar ion beam etching technology, and deposits and grows a circular Pt electrode at the center of the ferroelectric nanoisland by using focused ion beam assisted deposition technology, providing a new method for constructing a novel low-dimensional topological electronics device. The ferroelectric topological memory cell array device prepared by the present invention has improved integration and density compared with traditional memory cells. This design method of the memory cell based on ferroelectric topological domains can utilize the high conductivity of the domain wall and the fast response characteristics driven by the electric field to achieve low-power and high-speed read and write operations, not only reducing the power consumption of the memory cell, but also helping to improve the read and write speed of the memory cell. At the same time, this preparation method is applicable to a variety of ferroelectric materials, which has great practical significance.

[0020] For better understanding and implementation, the present invention will be described in detail below with reference to the accompanying drawings. Brief Description of the Drawings

[0021] Figure 1Schematic structural diagram of the Pt / BFO / SRO nano - island memory cell array device prepared in Example 1 of the present invention

[0022] Figure 2 Schematic structural diagram of the Pt / BFO / SRO nano - island memory cell prepared in Example 1 of the present invention

[0023] Figure 3 Scanning electron microscope morphology image of the Pt / BFO / SRO nano - island memory cell array device prepared in Example 1 of the present invention and AFM morphology image in the upper right corner (a), out - of - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 0° (b), in - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 0° (c)

[0024] Figure 4 AFM morphology image (a), out - of - plane PFM phase image (b), in - plane PFM phase image (c) and in - plane PFM amplitude image (d) obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 0°, in - plane PFM phase image (e) and in - plane PFM amplitude image (f) obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 90° prepared in Example 1 of the present invention

[0025] Figure 5 Domain structure flipping of the Pt / BFO / SRO nano - island memory cell under the regulation of an external electric field and the corresponding conductance intensity diagrams in Example 1 of the present invention are respectively: (a) CAFM image of the initial state of the Pt / BFO / SRO nano - island memory cell; (b) in - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 0° in the initial state; (c) in - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 90° in the initial state; (d) schematic diagram of the corresponding domain structure of the Pt / BFO / SRO nano - island memory cell in the initial state; (e) CAFM image of the Pt / BFO / SRO nano - island memory cell after domain flipping with a - 5V scanning voltage applied by the tip; (f) in - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 0° after domain flipping with a - 5V scanning voltage applied by the tip; (g) in - plane PFM phase image obtained by testing the Pt / BFO / SRO nano - island memory cell placed at 90° after domain flipping with a - 5V scanning voltage applied by the tip; (h) schematic diagram of the corresponding domain structure of the Pt / BFO / SRO nano - island memory cell after domain flipping with a - 5V scanning voltage applied by the tip Detailed implementation manners

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. For those not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. For reagents or instruments not indicated with the manufacturer, they are all conventional products that can be obtained through commercial purchase.

[0027] The storage unit based on ferroelectric topological domains provided by the present invention, its preparation method, and applications will be specifically described below.

[0028] The present invention provides a storage unit based on ferroelectric topological domains, including a ferroelectric nanoisland array and an electrode; the electrode is located at the center of the ferroelectric nanoisland array. Each of these storage unit devices is nanoscale, about 400 nm, and is arranged in a large area in an orderly and closely packed manner on the substrate, greatly improving the storage density of the device. At the same time, the device unit structure can stably form a central topological domain. Compared with existing storage devices (non-topological domains), due to the topological protection characteristics of this device structure, its performance is more stable.

[0029] Furthermore, the storage unit devices of the present invention can be arranged in a large area in an orderly and closely packed manner on a SrTiO3 single crystal substrate in the (001) direction, that is, an STO single crystal substrate is selected. The dielectric constant of STO at room temperature is as high as about 300, which can significantly enhance the electric field control ability of the bottom electrode on BFO, reduce the device power consumption, and increase the switching ratio. At the same time, the cubic lattice structure of STO has a high degree of compatibility with many functional materials (such as superconducting thin film REBCO, perovskite oxides), which is beneficial to the epitaxial growth of high-quality single crystal thin films. From the perspective of preparation, STO shows good chemical inertness in high-temperature and oxidation / reduction atmospheres and is suitable for complex process environments (such as pulsed laser deposition or chemical vapor deposition). In addition, the thermal conductivity of the STO substrate is better than that of traditional substrates such as sapphire, which helps the device dissipate heat and extend its lifespan.

[0030] Furthermore, the ferroelectric nanoisland array of the present invention is a ferroelectric layer / bottom electrode nanoisland array. The ferroelectric layer is formed on the bottom electrode to form a ferroelectric nanoisland array that constitutes the ferroelectric layer / bottom electrode structure.

[0031] As a reference ground, the ferroelectric layer of the present invention is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, a HfO2 layer, or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode. Any of the above ferroelectric thin film materials or metal oxide thin film materials can be used to prepare the ferroelectric nanoisland array of the present invention. Among them, the BiFeO3 ferroelectric thin film material is more commonly used and will be described in detail using this material in the embodiments. This does not mean that the ferroelectric layer of the present invention can only be a BiFeO3 layer. SRO (SrRuO3), as a perovskite oxide electrode, has a highly matched lattice structure with BFO (BiFeO3), reduces interface defects, and can regulate the polarization direction of BFO through charge coupling. Moreover, when BFO grows epitaxially on SRO, the lattice mismatch rate is low, reducing interface stress and promoting the growth of BFO with high crystal quality, thereby reducing leakage current and further improving the storage performance.

[0032] Correspondingly, the present invention also provides a preparation method for the above storage unit based on ferroelectric topological domains, including the following steps:

[0033] A ferroelectric nanoisland array is prepared on a substrate by pulsed laser deposition and argon ion beam etching, and then a circular electrode is deposited at the center position of the ferroelectric nanoisland array by focused ion beam assisted deposition, thus obtaining a storage unit based on ferroelectric topological domains. This method provides a new method for constructing novel low-dimensional topological electronic devices. Among them, the focused ion beam assisted deposition method has the advantages of high precision and controllability in preparing electrodes, can accurately position and grow and process nano-scale electrodes on nano-scale BFO nanoislands, avoiding the micron-scale limitations and randomness of traditional photolithography methods, and does not require a mask template required by traditional photolithography methods, greatly shortening the process cycle and reducing costs. The ferroelectric topological storage unit array device prepared by the present invention has improved integration and density compared with traditional storage units.

[0034] Specifically, the ferroelectric nanoisland array of the present invention is prepared through the following steps: First, a bottom electrode is epitaxially grown on a substrate by pulsed laser deposition technology. Secondly, a monolayer of polystyrene spheres is evenly spread on the epitaxial bottom electrode as a mask template. Then, the bottom electrode is etched into a nanoisland array by argon ion beam etching. Finally, a ferroelectric layer is self-assembled and grown on the cleaned nanoisland array by pulsed laser deposition technology, thus obtaining the ferroelectric nanoisland array. Traditional preparation processes (such as sol-gel methods) can cause some elements to be easily volatilized or the reaction to be uneven, resulting in a deviation in the stoichiometric ratio. However, pulsed laser deposition can almost completely reproduce the chemical composition of the target material. At the same time, pulsed laser deposition can flexibly adjust the growth atmosphere and gas pressure, control the oxygen vacancy concentration of BFO by regulating the oxygen pressure, and thus optimize its ferroelectric properties. In addition, the BFO prepared by pulsed laser deposition is better than traditional processes (such as magnetron sputtering) in terms of density and interface optimization, and the leakage current density can also be reduced by 1-2 orders of magnitude.

[0035] As a reference ground, in the preparation process of the ferroelectric nanoisland array, a polystyrene (PS) microsphere solution with a diameter of 500 nm is selected. After dilution according to the ratio of PS microsphere solution: absolute ethanol of 2:3, a closely arranged single layer of PS microspheres is evenly spread on deionized water. Then, the SRO (SrRuO3) electrode obtained in step 1 is treated with oxygen plasma for 3 minutes, and then the treated SRO (SrRuO3) electrode is clamped with tweezers to pick up the single layer of polystyrene (PS) microspheres in deionized water. After the water naturally evaporates, a closely arranged layer of PS microspheres is obtained on the surface of the SRO (SrRuO3) electrode. The SRO (SrRuO3) electrode covered with the PS microsphere mask plate is placed in an oxygen plasma machine and treated for 50 - 70 minutes under the condition of a power of 1.2 KW - 1.4 KW, so as to reduce the diameter of the PS microspheres and separate the closely arranged microspheres. Subsequently, the treated SRO (SrRuO3) electrode sample is placed in an Ar ion etching machine and etched for 90 seconds under the conditions of a vacuum degree of 8.0×10-4, room temperature, a cathode current of 15.8 A, an anode voltage of 50 V, a screen grid voltage of 300 V, an acceleration voltage of 250 V, a neutralization current of 13 A, and a bias voltage of 1.2 V. The model of the Ar ion etching machine used is MIBE-150C. Finally, the etched SRO (SrRuO3) electrode sample is ultrasonically cleaned with chloroform, acetone, absolute ethanol, and deionized water for 10 - 15 minutes, taken out and dried with a nitrogen gun, and then the surface is cleaned with oxygen plasma with a power of 1 KW - 1.2 KW for 4 - 6 minutes, and an ordered and clean SRO (SrRuO3) nanoisland array can be obtained. Exemplarily, the oxygen plasma treatment power can be 1.2 KW, 1.3 KW or 1.4 KW, or any other value within the range of 1.2 KW - 1.4 KW; the treatment time can be 50 minutes, 60 minutes or 70 minutes, or any other value within the range of 50 - 70 minutes. The ultrasonic cleaning time can be 10 minutes, 12 minutes or 15 minutes, or any other value within the range of 10 - 15 minutes. The power of the oxygen plasma cleaning can be 1 KW, 1.1 KW or 1.2 KW, or any other value within the range of 1 KW - 1.2 KW; the oxygen plasma cleaning time can be 4 minutes, 5 minutes or 6 minutes, or any other value within the range of 4 - 6 minutes.

[0036] For reference, the bottom electrode of the present invention is a SrRuO3 conductive layer with a thickness of 130 nm, and its preparation conditions are as follows: the pulse energy is 74 - 87 mJ, the pulse frequency is 8 Hz, the epitaxial temperature is 660 - 730 °C, and the oxygen pressure is 15 Pa. Exemplarily, the pulse energy is 74 mJ, 75 mJ, 76 mJ, 77 mJ, 78 mJ, 79 mJ, 80 mJ, 81 mJ, 82 mJ, 83 mJ, 84 mJ, 85 mJ, 86 mJ or 87 mJ, or any other arbitrary value within the range of 74 - 87 mJ. The epitaxial temperature is 660 °C, 670 °C, 680 °C, 690 °C, 700 °C, 710 °C, 720 °C or 730 °C, or any other arbitrary value within the range of 660 - 730 °C.

[0037] For reference, the ferroelectric layer of the present invention is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, an HfO2 layer or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode; the circular electrode is any one of a Pt, Au or Co electrode. Any of the above ferroelectric thin film materials or metal oxide thin film materials can be used to prepare the ferroelectric nano - island array of the present invention. The circular electrode is the top electrode, and a conductive metal material can be selected. Pt, Au or Co electrodes can all be used as the top electrode to prepare a ferroelectric topological storage unit array device with a topological structure.

[0038] For reference, the ferroelectric layer of the present invention is a BiFeO3 layer with a thickness of 60 nm, and its preparation conditions are as follows: the pulse energy is 64 - 70 mJ, the pulse frequency is 8 Hz, the temperature is 660 - 720 °C, and the oxygen pressure is 20 Pa. In the embodiments, the relatively common ferroelectric material BiFeO3 is selected as the ferroelectric layer material, and the ferroelectric topological storage unit array device prepared when its thickness is 60 nm has the best performance. Exemplarily, the pulse energy is 64 mJ, 65 mJ, 66 mJ, 67 mJ, 68 mJ, 69 mJ or 70 mJ, or any other arbitrary value within the range of 64 - 70 mJ. The temperature is 660 °C, 670 °C, 680 °C, 690 °C, 700 °C, 710 °C or 720 °C, or any other arbitrary value within the range of 660 - 720 °C. Within the parameter range of the above - mentioned preparation conditions, it can ensure that a ferroelectric topological storage unit array device with relatively ideal performance is obtained. Compared with the existing ferroelectric storage unit devices, the integration degree and density are both improved, and at the same time, the power consumption is lower and the reading and writing speed is faster.

[0039] As a reference ground, the circular electrode of the present invention is prepared by focused ion beam assisted deposition. This method has the advantages of high precision and controllability in preparing electrodes, and can accurately position and grow and process nanoscale electrodes at the center of nanoscale BFO nanoislands, avoiding the micron-scale limitations and randomness of traditional lithography methods, and eliminating the need for a mask required by traditional lithography methods, greatly shortening the process cycle and reducing costs. At the same time, this process combines a scanning electron microscope or a secondary electron detector, and can observe the electrode morphology in real time during the processing, and adjust the parameters in a timely manner, so that the prepared electrode morphology and interface contact quality are relatively high. In addition, this process prepares electrodes at a relatively low temperature, which can reduce the damage to BFO nanoislands and the impact on their performance.

[0040] The following are the best embodiments of the present invention. It should be noted that each parameter value adopted in the embodiments is a relatively good parameter value within the parameter range limited by the claims. In other embodiments, as long as the parameter values adopted are within the scope of the claims, the invention purpose of the present invention can be achieved.

[0041] Example 1

[0042] This embodiment provides a storage unit based on ferroelectric topological domains and a preparation method thereof. The preparation method of the storage unit includes the following steps:

[0043] S1: Prepare the bottom electrode of the storage unit device by pulsed laser deposition:

[0044] Pulsed laser deposition is a method of depositing a film on a substrate by using a high-energy laser pulse generated by a laser to evaporate the target material. The present invention uses (001)-oriented STO (SrTiO3) as the substrate, and uses pulsed laser deposition technology to grow a 130-nm-thick SRO (SrRuO3) conductive layer as the bottom electrode under the experimental conditions of a pulse energy of 81 mJ, a pulse frequency of 8 Hz, an epitaxial temperature of 680 °C, and an oxygen pressure of 15 Pa.

[0045] S2: Prepare the nanoisland array required for the growth of the ferroelectric layer of the storage unit by Ar ion etching technology:

[0046] Select a polystyrene (PS) microsphere solution with a diameter of 500 nm. After diluting it according to the ratio of PS microsphere solution to absolute ethanol of 2:3, spread it evenly into a closely packed monolayer of PS microspheres in deionized water. Then, treat the SRO (SrRuO3) electrode obtained in S1 with oxygen plasma for 3 minutes. Next, use tweezers to pick up the monolayer of polystyrene (PS) microspheres in deionized water with the treated SRO (SrRuO3) electrode. After the water evaporates naturally, a closely packed layer of PS microspheres is obtained on the surface of the SRO (SrRuO3) electrode. Place the SRO (SrRuO3) electrode covered with the PS microsphere mask plate in an oxygen plasma machine and treat it for 60 minutes under the condition of a power of 1.2 KW to reduce the diameter of the PS microspheres and separate the closely packed microspheres. Subsequently, place the treated SRO (SrRuO3) electrode sample in an Ar ion etching machine and etch it for 90 seconds under the conditions of a vacuum degree of 8.0×10 -4 -6 Pa, room temperature, a cathode current of 15.8 A, an anode voltage of 50 V, a screen grid voltage of 300 V, an acceleration voltage of 250 V, a neutralization current of 13 A, and a bias voltage of 1.2 V. The model of the Ar ion etching machine used is MIBE-150C. Finally, ultrasonically clean the etched SRO (SrRuO3) electrode sample with chloroform, acetone, absolute ethanol, and deionized water for 12 minutes respectively. After taking it out, dry it with a nitrogen gun, and then clean the surface with oxygen plasma with a power of 1 KW for 4 minutes to obtain an ordered and clean SRO (SrRuO3) nanoisland array.

[0047] S3: Prepare the ferroelectric layer of the memory cell device by pulsed laser deposition method:

[0048] Select a BFO (BiFeO3) target. Use pulsed laser deposition technology to deposit a 60-nm-thick BFO (BiFeO3) as the ferroelectric layer on the ordered and clean SRO (SrRuO3) nanoisland array under the experimental conditions of a pulse energy of 67 mJ, a pulse frequency of 8 Hz, a temperature of 680 °C, and an oxygen pressure of 20 Pa to obtain an ordered BFO / SRO nanoisland array.

[0049] S4: Prepare the top electrode of the memory cell by focused ion beam assisted deposition method:

[0050] The focused ion beam technology can achieve microscale topography etching, deposition, etc. of materials with its nanoscale ion beam. Its working principle is to excite ions through an ion source, and then accelerate them through an electric field and focus them through an electrostatic lens to form a high-speed and high-energy ion beam, so as to realize detection and characterization on the material surface and maskless direct writing processing. The present invention mainly uses the assisted deposition function of the focused ion beam. Its working principle is to introduce the precursor source of the material Pt to be deposited into the focused ion beam system. During the processing, the precursor Pt will be sprayed near the processing area, that is, on the top of the BFO / SRO nanoisland. Since there is precursor Pt on the sample surface, when the ion beam bombards, the precursor Pt will contact the ion beam and undergo a chemical reaction, being decomposed into volatile parts and non-volatile parts. The volatile parts will be pumped away by the vacuum system, and the non-volatile parts will grow and deposit on the surface of the BFO / SRO nanoisland top. Finally, a circular Pt electrode with a diameter of 150 nm is obtained at the center position of the BFO / SRO nanoisland. After this step, a complete Pt / BFO / SRO nanoisland storage unit can be obtained.

[0051] Please also refer to Figure 1 and 2 , the Pt / BFO / SRO nanoisland storage unit structure from bottom to top includes a stacked SRO bottom electrode, a BFO ferroelectric layer, and a top electrode Pt. Among them, the SRO bottom electrode and the BFO ferroelectric layer form a BFO / SRO ferroelectric nanoisland array, and the top electrode Pt is located at the center position of the BFO / SRO ferroelectric nanoisland array; the four different color modules in the figure respectively correspond to different polarization directions in the four quadrants of the topological domain, and the red dividing line represents the domain wall of the four-quadrant domain.

[0052] Test Example 1 Atomic Force Microscopy Characterization

[0053] The atomic force microscope (AFM) test system mainly includes: a cantilever and probe system, a laser system, a feedback system, and a data processing system, etc. The atomic force microscope maps the surface morphology of an object based on the tiny bending change of the probe cantilever caused by the interaction force between the sample surface and the probe. A probe (nanoscale) is installed below the end of the elastic cantilever of the instrument. During the test, the probe will move on the sample surface. Due to the undulation of the topography, the interaction force generated between the tip and the sample surface will cause the elastic cantilever to bend slightly. This tiny bending causes a change in the reflected light, which is further amplified by an optical lever, and finally read by a sensitive optical detector, and then the topography map of the sample can be obtained through the processing of the data processing system. In this test example, the atomic force microscope is used to characterize the morphology of the Pt / BFO / SRO nanoisland storage unit prepared in Example 1.

[0054] Test Example 2 Piezoelectric Response Force Microscopy Characterization

[0055] Piezoresponse Force Microscopy (PFM) is a microscope developed on the basis of contact-mode atomic force microscopy for detecting the electro-induced deformation of a sample surface at the microscale. This mode is mainly used to characterize the domain structure of ferroelectric materials and detect the mechanical deformation of a sample due to the inverse piezoelectric effect under an applied electric field. By applying an alternating voltage to the conductive tip, a periodic deformation is generated in the local sample under the tip, which causes the cantilever connected to the tip to twist, thus affecting the optical signal reflected by it. This signal is collected by a photodiode and subsequently analyzed by a lock-in amplifier to achieve detection. At the same time, a DC bias voltage can also be applied to the tip during the contact scanning with the sample to reverse the polarization of the ferroelectric material. In this test example, piezoresponse force microscopy was used to characterize the domain structure of the Pt / BFO / SRO nanoscale island memory cell prepared in Example 1. The results show that the initial polarization state of the Pt / BFO / SRO nanoscale island memory cell is a central-converging topological domain structure, and after voltage writing is applied, the polarization state of the Pt / BFO / SRO nanoscale island memory cell flips to a central-diverging topological domain structure.

[0056] Please also refer to Figure 3 and Figure 4 From Figure 3 it can be seen that the preparation method of the present invention can prepare a memory cell array with ordered arrangement, consistent shape and size, and stable performance. Even after adding the top electrode Pt, the central-type domain in the initial state of the BFO / SRO nanoscale island memory cell can still remain unaffected. And from Figure 4 it can be further verified that the initial polarization state of the BFO / SRO nanoscale island memory cell is still a central-converging topological domain structure after growing the Pt electrode on the top.

[0057] Test Example 3 Conductive Atomic Force Microscopy Characterization

[0058] Conductive Atomic Force Microscope (CAFM) is a mode for measuring the microscopic electrical properties of materials by directly contacting a conductive probe with a sample. Compared with AFM, the probe used in CAFM is coated with a layer of conductive material, so the current distribution of the sample can be obtained while measuring the sample topography in the CAFM mode. CAFM is a powerful tool for studying the microscopic conductive properties of materials. It can not only read the current distribution information of a region of the sample under a constant voltage, but also fix the conductive probe at a point and read the current response of the sample at this point by applying different magnitudes of voltage. In the present invention, conductive atomic force microscopy was used to test the conductive properties of the domain structure of the Pt / BFO / SRO nanoscale island memory cell. AsFigure 5 As shown, the test results indicate that the current of the Pt / BFO / SRO nanoisland memory cell in the initial state is almost zero. After applying a voltage of -5V, its polarization state flips to a topological domain with central divergence and out-of-plane polarization upward, and the conductivity reaches the nA level at this time.

[0059] In summary, compared with the prior art, the present invention proposes a ferroelectric topological memory cell designed based on four-quadrant topological domains and its preparation method. The fabricated ferroelectric topological memory cell array device improves the integration and density of the memory cells compared with traditional memory cells. This memory cell design method based on ferroelectric topological domains can achieve low-power and high-speed read and write operations by utilizing the high conductivity of domain walls and the fast response characteristics driven by an electric field. It not only reduces the power consumption of the memory cells but also helps to improve the read and write speed of the memory cells. This method is applicable to various ferroelectric materials and has great practical significance.

[0060] The above-described embodiments merely represent one implementation mode of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. A storage cell based on ferroelectric topological domains, characterized in that: It includes a ferroelectric nano - island array and an electrode; the electrode is located at the center of the ferroelectric nano - island array.

2. The storage cell based on ferroelectric topological domains according to claim 1, wherein: The ferroelectric nano - island array is a ferroelectric layer / bottom - electrode nano - island array.

3. The storage cell based on ferroelectric topological domains according to claim 2, wherein: The bottom electrode is a SrRuO3 conductive layer, and the ferroelectric layer is laminated on its upper surface, and the two together form a ferroelectric nano - island array with a ferroelectric layer / bottom - electrode structure.

4. The storage cell based on ferroelectric topological domains according to claim 3, characterized in that: The ferroelectric layer is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, a HfO2 layer or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode.

5. A method for preparing a storage unit based on ferroelectric topological domains according to any one of claims 1 to 4, characterized in that: It includes the following steps: Prepare a ferroelectric nano - island array on a substrate by pulsed laser deposition and argon ion beam etching, and then deposit a circular electrode at the center position of the ferroelectric nano - island array by focused ion beam assisted deposition to obtain a storage unit based on ferroelectric topological domains.

6. The preparation method according to claim 5, wherein: The ferroelectric nano - island array is prepared through the following steps: First, epitaxially grow a bottom electrode on a substrate by pulsed laser deposition technology. Secondly, evenly spread a monolayer of polystyrene spheres on the epitaxial bottom electrode as a mask template. Then, use argon ion beam etching to etch the bottom electrode into a nano - island array. Finally, self - assemble and grow a ferroelectric layer on the cleaned nano - island array by pulsed laser deposition technology to obtain the ferroelectric nano - island array.

7. The preparation method according to claim 6, wherein: The substrate is a (001) - oriented SrTiO3 single - crystal substrate; the bottom electrode is a SrRuO3 conductive layer with a thickness of 130 nm, and its preparation conditions are: pulsed energy is 74 - 87 mJ, pulsed frequency is 8 Hz, epitaxial temperature is 660 - 730 °C, and oxygen pressure is 15 Pa.

8. The preparation method according to claim 6, characterized in that: The ferroelectric layer is any one of a BiFeO3 layer, a BaTiO3 layer, a PbTiO3 layer, a HfO2 layer or a ZrO2 layer; the bottom electrode is a SrRuO3 electrode; the circular electrode is any one of a Pt, Au or Co electrode.

9. The preparation method according to claim 8, characterized in that: The ferroelectric layer is a BiFeO3 layer with a thickness of 60 nm, and its preparation conditions are: pulsed energy is 64 - 70 mJ, pulsed frequency is 8 Hz, temperature is 660 - 720 °C, and oxygen pressure is 20 Pa.

10. The preparation method according to claim 5, characterized in that: The circular electrode is prepared by focused ion beam assisted deposition.

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