MOSFET device and manufacturing method thereof

Abstract

The invention relates to the field of semiconductor power devices, in particular to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, which comprises the following steps of: etching on a substrate to form a groove, the groove is provided with a side wall and a bottom wall, and the side wall is connected with the bottom wall and forms a corner; arranging a Schottky metal layer in the groove, wherein the Schottky metal layer covers the side wall, the bottom wall and the corners of the groove; a silicon oxide layer is arranged on the surface of the Schottky metal layer, the silicon oxide layer is located in the groove, and the junction depth of the upper surface of the silicon oxide layer is lower than that of a preset P well region; and removing the Schottky metal layer which is not covered by the silicon oxide layer. Therefore, the problem that the gate oxide layer of the MOSFET device at the corner of the bottom of the groove is easy to break down and lose efficacy can be effectively improved, and the MOSFET device has the characteristics of high voltage resistance, low turn-on voltage and low switching loss, and can be used as a fly-wheel diode to replace an additional diode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and particularly relates to a MOSFET device and a manufacturing method thereof. Background Art

[0002] A silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is a MOSFET fabricated using silicon carbide (SiC) semiconductor material. Compared with traditional silicon (Si) MOSFETs, SiC MOSFETs have lower on-resistance, lower switching losses, and better high-temperature performance. Therefore, SiC MOSFETs are becoming increasingly prominent in high-temperature, high-frequency, and high-voltage applications.

[0003] Existing SiC MOSFETs are of two types: planar and trench. The trench type has smaller cell sizes, so it has the advantage of saving area. However, the electric field is relatively concentrated at the bottom corner of the trench in trench-type SiC MOSFETs, resulting in easy breakdown and failure of the gate oxide layer at the corner. Moreover, in practical applications, SiC MOSFETs need an anti-parallel diode for freewheeling. The built-in body diode of SiC MOSFETs has a relatively high turn-on voltage and high switching losses, which affect the switching frequency of the device. Therefore, SiC MOSFETs require an additional diode for freewheeling to maintain a high-frequency and low-loss application environment, leading to an increase in cost.

[0004] It should be noted that the information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0005] To solve the problems of the prior art, the present invention provides a new manufacturing method for a MOSFET device, which includes the following steps: Etch a trench in a substrate. The trench has sidewalls and a bottom wall, and the sidewalls connect to the bottom wall to form a corner. Dispose a Schottky metal layer in the trench. The Schottky metal layer covers the sidewalls, the bottom wall, and the corner of the trench. Dispose a silicon oxide layer on the surface of the Schottky metal layer. The silicon oxide layer is located in the trench, and the upper surface of the silicon oxide layer is lower than the junction depth of a preset P-well region. Remove the Schottky metal layer not covered by the silicon oxide layer.

[0006] Further, the manufacturing method of the MOSFET device further includes the following steps: disposing a gate oxide layer and a polysilicon layer in the trench, the gate oxide layer being connected to the substrate, and the polysilicon layer being connected to the gate oxide layer; forming the P-well region and the N-source region in the substrate by ion implantation, the P-well region being connected to the N-source region, and the P-well region being higher than the Schottky metal layer.

[0007] Further, the manufacturing method of the MOSFET device further includes the following steps: disposing an interlayer dielectric layer, a contact hole, a front metal layer, and a back metal layer, the interlayer dielectric layer covering the gate oxide layer, the contact hole penetrating from the upper surface of the interlayer dielectric layer downward to the P-well region, the front metal layer being disposed on the interlayer dielectric layer and connected to the contact hole, and the back metal layer being disposed on the lower surface of the substrate.

[0008] Further, the material of the substrate includes silicon carbide.

[0009] Further, the depth range of the trench is 2 - 3 μm.

[0010] Further, the etching depth range of the silicon oxide layer is 1.5 - 2.5 μm.

[0011] Further, the silicon oxide layer is grown by chemical vapor deposition.

[0012] Further, the Schottky metal layer not covered by the silicon oxide layer is removed by wet etching.

[0013] Further, the Schottky metal layer is disposed by metal sputtering.

[0014] The present invention also provides a MOSFET device, which is prepared by using the manufacturing method of the MOSFET device described in any one of the foregoing.

[0015] A MOSFET device and its manufacturing method provided by the present invention, by disposing a completely covered Schottky metal layer at the bottom corner of the trench, enables the Schottky metal layer and the substrate to form a Schottky barrier diode (SBD), which can effectively improve the problem that the gate oxide layer at the bottom corner of the trench of the MOSFET device is prone to breakdown failure, and has the characteristics of high breakdown voltage, low turn-on voltage, and low switching loss, and can be used as a freewheeling diode to replace an additional diode.

[0016] Other features and beneficial effects of the present invention will be described in the subsequent specification, and some of the technical features and beneficial effects can be obviously obtained from the specification, or can be understood by implementing the present invention. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, some of the drawings described below are embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic flow chart of a manufacturing method of a MOSFET device provided by an embodiment of the present invention; Figures 2 to 9 It is a schematic structural diagram of each stage during the manufacturing process of a MOSFET device provided by an embodiment of the present invention.

[0019] Reference numerals: 100 - Substrate; 110 - Trench; 111 - Sidewall; 112 - Bottom wall; 120 - Schottky metal layer; 130 - Silicon oxide layer; 140 - Gate oxide layer; 150 - Polysilicon layer; 160 - P-well region; 170 - N-source region; 180 - Interlayer dielectric layer; 190 - Contact hole; 200 - Front metal layer; 210 - Back metal layer. Detailed implementation manners

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, rather than all, of the embodiments of the present invention; the technical features designed in different implementation manners of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0021] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. Additionally, the term "comprising" and any variations thereof mean "including at least".

[0022] Please refer to Figures 1 to 9 。 Figure 1 FIG. is a schematic flow chart of a method for manufacturing a MOSFET device provided by an embodiment of the present invention, Figures 2 to 9 and FIG. is a schematic structural diagram of each stage during the manufacturing process of a MOSFET device provided by an embodiment of the present invention.

[0023] As shown in the figure, a method for manufacturing a MOSFET device provided by an embodiment of the present invention includes the following steps: S100: Etch a trench 110 on a substrate 100. The trench 110 has sidewalls 111 and a bottom wall 112, and the sidewalls 111 are connected to the bottom wall 112 to form a corner. The material of the substrate 100 may include silicon carbide.

[0024] S200: Dispose a Schottky metal layer 120 in the trench 110. The Schottky metal layer 120 covers the sidewalls 111, the bottom wall 112, and the corner of the trench 110. The material of the Schottky metal layer 120 may include platinum (Pt), gold (Au), palladium (Pd), etc.

[0025] S300: Dispose a silicon oxide layer 130 on the surface of the Schottky metal layer 120. The silicon oxide layer 130 is located in the trench 110, and the silicon oxide layer 130 is etched. The upper surface of the etched silicon oxide layer 130 is lower than the junction depth of a preset P-well region 160. The preset P-well region 160 refers to the P-well region 160 formed subsequently. The thickness of the etched silicon oxide layer 130 corresponds to the height of the Schottky metal layer 120. The Schottky metal layer 120 cannot exceed the junction depth of the P-well region 160, otherwise an inversion layer cannot be formed, a conductive channel cannot be formed, and the device cannot be switched.

[0026] S400: Remove the Schottky metal layer 120 that is not covered by the silicon oxide layer 130.

[0027] Further, the manufacturing method of the MOSFET device may further include the following steps: S500: A gate oxide layer 140 and a polysilicon layer 150 are disposed in the trench 110. The gate oxide layer 140 is connected to the substrate 100, and the polysilicon layer 150 is connected to the gate oxide layer 140; S600: By means of ion implantation, a P-well region 160 and an N-source region 170 are formed in the substrate 100. The P-well region 160 is connected to the N-source region 170. The P-well region 160 is higher than the Schottky metal layer 120. That is to say, the Schottky metal layer 120 cannot cover the sidewall more than the depth of the P-well region 160. Otherwise, it will affect the formation of an inversion layer in the P-well region 160, and a conductive channel cannot be formed, resulting in the device being unable to switch.

[0028] S700: An interlayer dielectric layer 180, a contact hole 190, a front metal layer 200, and a back metal layer 210 are provided. The interlayer dielectric layer 180 covers the gate oxide layer 140. The contact hole 190 penetrates from the upper surface of the interlayer dielectric layer 180 downward to the P-well region 160. The front metal layer 200 is disposed on the interlayer dielectric layer 180 and is connected to the contact hole 190. The back metal layer 210 is disposed on the lower surface of the substrate 100.

[0029] Combined Figures 2 to 9 looking at it, first as Figure 2 shown, a silicon carbide substrate 100 is provided, and a trench 110 is formed on the substrate 100. The depth range of the trench 110 can be 2 - 3 μm.

[0030] As Figure 3 shown, a Schottky metal layer 120 is formed in the trench 110 by means of metal sputtering. The Schottky metal layer 120 covers the sidewall 111, the bottom wall 112, and the corner of the trench 110, so that the Schottky metal layer 120 and the substrate 100 form a Schottky barrier diode (SBD), which can effectively improve the problem that the gate oxide layer 140 at the bottom corner of the trench 110 of the MOSFET device is prone to breakdown failure, and has the characteristics of high breakdown voltage, low turn-on voltage, and low switching loss, and can be used as a freewheeling diode to replace an additional diode. On the contrary, if the Schottky metal layer 120 is only formed on the bottom of the trench (i.e., only covering the bottom wall 112), the concentrated electric field at the corner will break down the exposed gate oxide layer 140 at the corner. If the Schottky metal layer 120 is only formed on the sidewall 111, the exposed gate oxide layer 140 at the bottom of the trench 110 will also be broken down by the concentrated electric field, and the device cannot be effectively protected.

[0031] As Figure 4 shown, a silicon oxide layer 130 is grown on the surface of the Schottky metal layer 120 by chemical vapor deposition.

[0032] As shown Figure 5 etch the silicon oxide layer 130. The etching depth range of the silicon oxide layer 130 is 1.5 - 2.5 μm. After etching, the thickness of the silicon oxide layer 130 can be reserved at about 0.5 μm.

[0033] As shown Figure 6 using the etched silicon oxide layer 130 as a barrier layer, remove the Schottky metal layer 120 that is not covered by the silicon oxide layer 130 by wet etching.

[0034] As shown Figure 7 set a gate oxide layer 140 and a polysilicon layer 150 in the trench 110, and then perform back-etching on the polysilicon layer 150.

[0035] As shown Figure 8 form a P-well region 160 and an N-source region 170 in the substrate 100 by ion implantation.

[0036] As shown Figure 9 form an interlayer dielectric layer 180, a contact hole 190, a front metal layer 200, and a back metal layer 210. The interlayer dielectric layer 180 covers the gate oxide layer 140, the contact hole 190 penetrates from the upper surface of the interlayer dielectric layer 180 downward to the P-well region 160, the front metal layer 200 is disposed on the interlayer dielectric layer 180 and connected to the contact hole 190, and the back metal layer 210 is disposed on the lower surface of the substrate 100.

[0037] Finally, the Schottky metal layer 120 and the front metal layer 200 are connected to the source electrode, the polysilicon layer 150 is connected to the gate electrode, and the back metal layer 210 is connected to the drain electrode.

[0038] The present invention also provides a MOSFET device, which is prepared by using the manufacturing method of the MOSFET device in any one of the foregoing.

[0039] In summary, a MOSFET device and a manufacturing method thereof provided by the present invention, by setting a completely covered Schottky metal layer 120 at the bottom corner of the trench 110, enable the Schottky metal layer 120 and the substrate 100 to form a Schottky barrier diode (SBD), which can effectively improve the problem that the gate oxide layer 140 at the bottom corner of the trench 110 of the MOSFET device is prone to breakdown failure, and has the characteristics of high breakdown voltage, low turn-on voltage, and low switching loss, and can be used as a freewheeling diode to replace an additional diode.

[0040] In addition, those skilled in the art should understand that although there are many problems in the prior art, each embodiment or technical solution of the present invention can be improved in only one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or the background art at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be regarded as a limitation to that claim.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing method of a MOSFET device, characterized in that: The manufacturing method of the MOSFET device includes the following steps: Etch a trench in the substrate, the trench having sidewalls and a bottom wall, the sidewalls connecting the bottom wall and forming corners; Dispose a Schottky metal layer in the trench, the Schottky metal layer covering the sidewalls, the bottom wall and the corners of the trench; Dispose a silicon oxide layer on the surface of the Schottky metal layer, the silicon oxide layer being located in the trench, and the upper surface of the silicon oxide layer being lower than the junction depth of a preset P-well region; Remove the Schottky metal layer not covered by the silicon oxide layer.

2. The manufacturing method of the MOSFET device according to claim 1, wherein: The manufacturing method of the MOSFET device further includes the following steps: Dispose a gate oxide layer and a polysilicon layer in the trench, the gate oxide layer connecting to the substrate, and the polysilicon layer connecting to the gate oxide layer; Form the P-well region and the N-source region in the substrate by ion implantation, the P-well region connecting to the N-source region, and the P-well region being higher than the Schottky metal layer.

3. The manufacturing method of the MOSFET device according to claim 2, characterized in that: The manufacturing method of the MOSFET device further includes the following steps: dispose an interlayer dielectric layer, a contact hole, a front metal layer and a back metal layer, the interlayer dielectric layer covering the gate oxide layer, the contact hole penetrating from the upper surface of the interlayer dielectric layer downward to the P-well region, the front metal layer being disposed on the interlayer dielectric layer and connecting to the contact hole, and the back metal layer being disposed on the lower surface of the substrate.

4. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The material of the substrate includes silicon carbide.

5. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The depth range of the trench is 2 - 3 μm.

6. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The etching depth range of the silicon oxide layer is 1.5 - 2.5 μm.

7. The manufacturing method of the MOSFET device according to claim 1, characterized in that: Grow the silicon oxide layer by chemical vapor deposition.

8. The manufacturing method of the MOSFET device according to claim 1, characterized in that: Remove the Schottky metal layer not covered by the silicon oxide layer by wet etching.

9. The manufacturing method of the MOSFET device according to claim 1, wherein: Dispose the Schottky metal layer by metal sputtering.

10. A MOSFET device, characterized in that: The MOSFET device is prepared by using the manufacturing method of the MOSFET device according to any one of claims 1 - 9.

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