Semiconductor device structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device structure and a manufacturing method thereof. The structure includes a gate electrode layer disposed over a substrate, a first source / drain region disposed over the substrate, a conductive contact disposed over the first source / drain region, a first dielectric layer disposed over the gate electrode layer and the conductive contact, a first conductive feature disposed in the first dielectric layer, and a second conductive feature disposed in the second dielectric layer. A second conductive feature disposed in the first dielectric layer; and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer is in contact with a portion of the side surface of the second conductive feature.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor device structures and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each having smaller and more complex circuits than the previous generation. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling process generally provides benefits by increasing production efficiency and reducing related costs. This scaling also increases the complexity of processing and manufacturing ICs. Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device structure, comprising:

[0004] a gate electrode layer disposed over a substrate;

[0005] a first source / drain region disposed over the substrate;

[0006] a conductive contact disposed over the first source / drain region;

[0007] a first dielectric layer disposed over the gate electrode layer and the conductive contact;

[0008] a first conductive component disposed in the first dielectric layer;

[0009] a second conductive component disposed in the first dielectric layer; and

[0010] a second dielectric layer disposed over the first dielectric layer, wherein the second dielectric layer contacts a portion of a side surface of the second conductive component.

[0011] Another embodiment of the present disclosure provides a semiconductor device structure, comprising:

[0012] a gate electrode layer disposed over a substrate;

[0013] a source / drain region disposed over the substrate;

[0014] a conductive contact disposed over the source / drain region;

[0015] a first dielectric layer disposed over the gate electrode layer and the conductive contact;

[0016] a first conductive component disposed in the first dielectric layer;

[0017] A second conductive component, disposed in the first dielectric layer;

[0018] A third conductive component, disposed on and in contact with the first conductive component;

[0019] A fourth conductive component, disposed on and in contact with the second conductive component;

[0020] A second dielectric layer, disposed on the first dielectric layer, wherein the second dielectric layer is in contact with a portion of a side surface of the second conductive component and a first portion of a side surface of the third conductive component; and

[0021] A third dielectric layer, disposed on the second dielectric layer, wherein the third dielectric layer is in contact with a portion of a side surface of the fourth conductive component and a second portion of the side surface of the third conductive component.

[0022] Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device structure, including:

[0023] Forming a first dielectric layer over a substrate, wherein the substrate includes a gate electrode layer, source / drain regions, and a conductive contact disposed over the source / drain regions;

[0024] Forming a first conductive component in the first dielectric layer;

[0025] Depositing a second dielectric layer over the first conductive component and the first dielectric layer;

[0026] Depositing a third dielectric layer over the second dielectric layer;

[0027] Forming a second conductive component in the first dielectric layer, the second dielectric layer, and the third dielectric layer; and

[0028] Performing a chemical mechanical polishing process to expose the second dielectric layer and the second conductive component, wherein the first conductive component is covered by the second dielectric layer during the chemical mechanical polishing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be increased or reduced arbitrarily for clarity of discussion.

[0030] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure in accordance with some embodiments.

[0031] Figures 7A to 12A is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to some embodiments. Figure 6

[0032] Figures 7B to 12B is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line B-B according to some embodiments. Figure 6

[0033] Figures 7C to 12C is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line C-C according to some embodiments. Figure 6

[0034] Figures 13A to 13I is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to some embodiments. Figure 6

[0035] Figures 14A to 14B is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to alternative embodiments. Figure 6

[0036] Figures 15A to 15G is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to alternative embodiments. Figure 6

[0037] Figures 16A to 16B is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to alternative embodiments. Figure 6

[0038] Figures 17A to 17E is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A according to alternative embodiments. Figure 6

[0039] Figure 18 is a cross-sectional side view of one of the various stages of fabricating a semiconductor device structure taken along line A-A according to alternative embodiments. Figure 6 DETAILED DESCRIPTION

[0040] Numerous different embodiments or examples are provided below for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the embodiments and / or configurations being discussed.

[0041] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0042] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs, such as all-around gate (GAA) FETs, e.g., horizontal all-around gate (HGAA) FETs or vertical all-around gate (VGAA) FETs, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. Those of ordinary skill in the art will readily understand other modifications that may be made within the scope of the present disclosure. In the case of adapting an all-around gate (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, one or more lithography processes may be used to pattern the structure, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0043] Figures 1 to 13I An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure is shown. It should be understood that Figures 1 to 13IProvide additional operations before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of the operations / processes is not restricted and may be interchangeable.

[0044] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As Figure 1 shown, the semiconductor device structure 100 includes a stack 104 of semiconductor layers formed over a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate that has an insulating layer (not shown) for enhancement disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing layer.

[0045] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0046] The stack 104 of semiconductor layers includes alternating semiconductor layers made of different materials to facilitate the formation of a nanostructure channel in a multi-gate device such as a nanostructure channel FET. In some embodiments, the stack 104 of semiconductor layers includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack 104 of semiconductor layers includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Optionally, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0047] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the layers of the stack 104 of semiconductor layers can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0048] In a later manufacturing stage, the first semiconductor layer 106 or a portion thereof can form a nanostructured channel of the semiconductor device structure 100. The term nanostructure is used herein to denote any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term denotes elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or bar-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channel of the semiconductor device structure 100 can be surrounded by a gate electrode. The semiconductor device structure 100 can include nanostructured transistors. Nanostructured transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0049] Each first semiconductor layer 106 can have a thickness in the range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 can be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range between about 2 nm and about 50 nm. As Figure 1 shown, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged, which is for illustrative purposes and is not intended to limit what is specifically recited in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the stack 104 of semiconductor layers, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0050] In Figure 2In [the structure], the fin structure 112 is formed from a stack 104 of semiconductor layers. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the stack 104 of semiconductor layers using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer into a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process can be used to pattern the photoresist layer to form the masking element. The etching process forms trenches 114 through the hard mask layer, through the stack 104 of semiconductor layers, and into the substrate 101 in unprotected regions, leaving multiple extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0051] In Figure 3 [the structure], after forming the fin structures 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or a back etching method, is performed such that the tops of the fin structures 112 are exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0052] In Figure 4 [the structure], the insulating material 118 is recessed to form isolation regions 120. The recessing of the insulating material 118 exposes portions of the fin structures 112, such as the stack 104 of semiconductor layers. The recessing of the insulating material 118 exposes the trenches 114 between adjacent fin structures 112. The isolation regions 120 can be formed using suitable processes, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0053] In Figure 5In [the structure], one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning those layers into the sacrificial gate structure 130. Then, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the spacers 138 may be formed by conformally depositing one or more layers for the spacers 138 and anisotropically etching the one or more layers. In some embodiments, the spacers 138 are also formed on the sidewalls of the exposed portions of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction. In some embodiments, the contact poly pitch (CPP) (which is the minimum center-to-center distance between adjacent sacrificial gate electrode layers 134) is in the range from about 35 nm to about 100 nm.

[0054] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The spacers 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbon oxide, SiOCN, and / or combinations thereof.

[0055] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100.

[0056] In Figure 6 [the structure], the portions of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacers 138 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of the portions of the fin structure 112 may be accomplished by an etching process (isotropic or anisotropic etching process), and the etching process may be selective with respect to one or more crystal planes of the substrate 101. The etching process may be dry etching (such as RIE, NBE, etc.) or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0057] Figure 7A 、 Figure 7B and Figure 7C are respectively along Figure 61 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC.

[0058] Figure 8A , Figure 8B and Figure 8C According to some embodiments, Figure 6 FIG. 1 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along lines AA, BB, and CC. Figure 8A As shown, the edge portion of each second semiconductor layer 108 of the stack of semiconductor layers 104 is horizontally removed along the X direction. The edge portion of the second semiconductor layer 108 is removed to form a cavity. In some embodiments, the portion of the second semiconductor layer 108 is removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP) or potassium hydroxide (KOH) solution.

[0059] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), and then performing anisotropic etching to remove the portion of the conformal dielectric layer except the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the dielectric spacers 144 along the X direction.

[0060] Figure 9A , Figure 9B and Figure 9C According to some embodiments, Figure 6 FIG. 1 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along lines AA, BB, and CC. Figure 9A and Figure 9CAs shown, the source / drain (S / D) region 146 is formed from the substrate portion 116. The S / D region 146 can grow vertically and horizontally to form facets that can correspond to the crystal planes of the material used for the substrate portion 116. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are substantially the same. Additionally, depending on the context, the source / drain region can refer to the source or the drain individually or collectively. The S / D region 146 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, a p-type dopant (such as boron (B)) can also be included in the S / D region 146. The S / D region 146 can be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0061] Figure 10A , Figure 10B and Figure 10C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along Figure 6 lines A-A, B-B, and C-C, respectively, according to some embodiments. In Figure 10A , Figure 10B and Figure 10C , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. The CESL 162 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc. or a combination thereof, and can be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 includes SiC, SiN, SiOCN, SiOC, SiCN, SiO, AlO, AlON, or AlN. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material for the ILD layer 164 can include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. An organic material (such as a polymer) can also be used for the ILD layer 164. The ILD layer 164 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 164, the semiconductor device structure 100 can be subjected to a thermal process to anneal the ILD layer 164.

[0062] As Figure 10A and Figure 10B shown, after forming the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0063] Figure 11A and Figure 11B and Figure 11C are cross-sectional side views of one of the respective stages of fabricating the semiconductor device structure 100 taken along line A-A, line B-B, and line C-C according to some embodiments. As shown in Figure 6 and Figure 11A and Figure 11B , the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D regions 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (such as dry etching, wet etching, or a combination thereof), and subsequently the sacrificial gate dielectric layer 132 can be removed, which can also be performed by any suitable process (such as dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the ILD layer 164, and the CESL 162.

[0064] The second semiconductor layer 108 can be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the Si, the dielectric material of the gate spacers 138, and the dielectric spacers 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant (such as but not limited to hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4)), a dry etchant (such as a fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0065] After forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 108, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the exposed surface of the gate dielectric layer 170 and the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more dielectric materials, such as silicon oxide, silicon nitride, or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HbZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can also be deposited above the upper surface of the ILD layer 164. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed above the ILD layer 164 are removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0066] Figure 12A , Figure 12B and Figure 12C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 according to some embodiments. As Figure 12B and Figure 12CAs shown, conductive contact 180 is formed in ILD layer 164 and CESL 162. Conductive contact 180 is electrically connected to corresponding S / D regions 146 via silicide layer 182. Conductive contact 180 can be conductive and can include a material having one or more of Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, or TaN. Conductive contact 180 can be formed by any suitable method, such as electroless plating (ECP) or PVD. Silicide layer 182 can be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on semiconductor device structure 100. The metal layer can include Ti, Ni, Ru, Co, W, or other suitable metal. The metal layer can be deposited by any suitable process, such as ALD, CVD, or PVD. After the metal layer is deposited, an annealing process is performed to react S / D regions 146 with the metal layer, thereby forming silicide layer 182. Silicide layer 192 can include any suitable material, such as NiSi, TiSi, CoSi, RuSi, or WSi. As Figure 12A shown, a planarization process, such as a CMP process, can be performed to make the top surface of gate electrode layer 172 and the top surface of conductive contact 180 substantially coplanar. In some embodiments, conductive contact 180 has a critical dimension in the range from about 5 nm to about 50 nm.

[0067] Figures 13A to 13H is a cross-sectional side view of various stages of manufacturing semiconductor device structure 100 taken along line A-A of Figure 6 . For clarity, Figures 13A to 13H various components on substrate 101 are omitted in Figure 13A shown. In some embodiments, conductive contact 180 is formed between liners 202. The liners can include any suitable dielectric material, such as SiN. In some embodiments, liner 202 includes Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable material. In some embodiments, there is no liner 202, and conductive contact 180 contacts ILD layer 164. Next, as Figure 13BAs shown, an etch stop layer 204 and another ILD layer 206 are formed over the ILD layer 164, the gate structure 174, and the conductive contact 180. The etch stop layer 204 may include the same material as the CESL 162, and the ILD layer 206 may include the same material as the ILD layer 164. A conductive component 208 is formed in the ILD layer 206 and the etch stop layer 204. The conductive component 208 may include a conductive material such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, or a combination thereof or other suitable materials. The conductive component 208 may be formed by any suitable process such as PVD or ECP. In some embodiments, the conductive component 208 is electrically connected to the gate electrode layer 172. As Figure 13B shown, in some embodiments, the conductive component 208 is electrically connected to the gate electrode layer 172 and the conductive contact 180 adjacent to one or more gate electrode layers 172. In some embodiments, the conductive component 208 is in direct contact with the gate electrode layer 172.

[0068] As Figure 13C shown, a planarization process such as a CMP process is performed, and the top surface of the conductive component 208 and the top surface of the ILD layer 206 are substantially coplanar. The conductive component 208 is electrically connected to the gate electrode layer 172 (and in some embodiments the adjacent conductive contact 180). The conductive component 208 that is electrically connected to the gate electrode layer 172 and the conductive contact 180 may be referred to as a butt contact. In some embodiments, the conductive component 208 has a critical dimension in the range from about 5 nm to about 50 nm. Next, as Figure 13D shown, a CMP stop layer 210 and another ILD layer 212 are formed over the ILD layer 206 and the conductive component 208. The CMP stop layer 210 may include any suitable material such as SiC, SiN, SiOCN, SiOC, SiCN, SiO, AlO, AlON, or AlN. The CMP stop layer 210 may be formed by any suitable process such as ALD, CVD, or PVD. The ILD layer 212 may include the same material as the ILD layer 206 and may be deposited by the same process as the ILD layer 216. Next, as Figure 13EAs shown, conductive component 214 is formed in ILD layer 212, CMP stop layer 210, ILD layer 206, and etch stop layer 204. Conductive component 214 may include a conductive material such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, or a combination thereof or other suitable materials. In some embodiments, conductive component 214 includes a material different from that of conductive component 208. For example, in some embodiments, conductive component 208 is used to provide a signal or power supply to gate electrode layer 172, and conductive component 208 includes Ti or W, which may result in a higher yield. Conductive component 214 is used to provide a signal or power supply to S / D region 146, and conductive component 214 includes Ru, Mo, or Ir, which may result in a reduced resistance. Conductive component 214 may be formed by any suitable process such as PVD or ECP. In some embodiments, conductive component 214 is in direct contact with conductive contact 180, and conductive contact 180 is electrically connected to S / D region 146 via silicide layer 182( Figure 12A , Figure 12C ).

[0069] As Figure 13F shown, a CMP process is performed to remove a portion of conductive component 214 and ILD layer 212. The CMP process stops when CMP stop layer 210 is exposed. As described above, in some embodiments, conductive component 208 and conductive component 214 are made of different materials, such as different metals. Therefore, both conductive component 208 and conductive component 214 are exposed to the slurry of the CMP process, which may cause galvanic corrosion. Galvanic corrosion refers to the corrosion damage caused when two different materials (i.e., conductive components 208, 214) are coupled in a corrosive electrolyte (i.e., the slurry of the CMP process). To prevent galvanic corrosion, CMP stop layer 210 is used to cover conductive component 208, while conductive component 214 is exposed during the CMP process. In some embodiments, CMP stop layer 210 has a thickness in the range from about 1 nm to about 10 nm. As Figure 13F shown, compared with the height of conductive component 208, the thickness of CMP stop layer 210 defines an additional height of conductive component 214 along the Z direction. If the thickness of CMP stop layer 210 is less than about 1 nm, CMP stop layer 210 may not sufficiently cover conductive component 208 during the CMP process. On the other hand, if the thickness of CMP stop layer 210 is greater than about 10 nm, conductive component 214 may be too close to the conductive components in the layer located above the adjacent conductive components. As a result, the parasitic capacitance may increase. As Figure 13F shown, after the CMP process, the top surface of CMP stop layer 210 and the top surface of conductive component 214 are substantially coplanar. In some embodiments, conductive component 214 has a critical dimension in the range from about 5 nm to about 50 nm.

[0070] As shown Figure 13G in some embodiments, after the CMP process, the CMP stop layer 210 is removed. The CMP stop layer 210 can be removed by any suitable process, such as an etching process. The etching process can be a selective etching process that substantially does not affect the conductive component 214. After removing the CMP stop layer 210, the conductive component 214 extends to a level above the top surfaces of the conductive component 208 and the ILD layer 206. As shown Figure 13G in some embodiments, a portion of the side surface of each conductive component 214 is exposed. As shown Figure 13G in some embodiments, the bottom surface of the conductive component 208 and the bottom surface of the conductive component 214 are substantially coplanar, and the top surface of the conductive component 214 extends above the level of the top surface of the conductive component 208.

[0071] Next, as shown Figure 13H in some embodiments, another etch stop layer 216 is deposited on the top surfaces of the conductive component 208, the ILD layer 206, and the conductive component 214, and the etch stop layer 216 is also deposited on the exposed portions of the side surfaces of each conductive component 214. An inter-metal dielectric (IMD) layer 218 is deposited on the etch stop layer 216. The etch stop layer 216 can include the same material as the etch stop layer 204 and can be formed by the same process as the etch stop layer 204. The IMD layer 218 is made of a dielectric material, such as SiO x 、SiO x C y H z or SiO x C y where x, y, and z are integers or non-integers. In some embodiments, the IMD layer 218 includes a dielectric material having a k value in the range from about 1 to about 5. As shown Figure 13IAs shown, the conductive component 220 is formed in the IMD layer 218 and the etch stop layer 216. In some embodiments, each conductive component 220 includes a barrier layer 222 and a conductive material 224. The barrier layer 222 may include Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable materials, and the conductive material 224 may include Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable materials. In some embodiments, the conductive material 224 includes a metal that is prone to diffusion, such as Cu, and the barrier layer 222 may include Ti, TiN, or TaN, which can prevent the metal from diffusing from the conductive material 224 into the IMD layer 218. In some embodiments, the conductive material 224 is not prone to diffusion, and there is no barrier layer 222. In some embodiments, the thickness of the barrier layer 222 may be in the range from about 0.5 nm to about 10 nm. In some embodiments, a planarization process, such as a CMP process, is performed so that the top surfaces of the conductive component 220 and the IMD layer 218 are substantially coplanar. In some embodiments, as Figure 13I shown, the etch stop layer 216 contacts a portion of the side surface of each conductive component 220 and a portion of the side surface of each conductive component 214.

[0072] Figures 14A to 14B is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along line A-A according to an alternative embodiment. As Figure 6 shown, a CMP process is performed to expose the CMP stop layer 210 and the conductive component 214, which is the same manufacturing stage as Figure 14A shown. Next, as Figure 13F shown, an etch stop layer 216 is deposited on the CMP stop layer 210 and the conductive component 214, rather than removing the CMP stop layer 210. The ILD layer 218 is deposited on the etch stop layer 216, and the conductive component 220 is formed in the ILD layer 218 and the etch stop layer 216. As Figure 14B shown, the conductive component 220 disposed above the conductive component 208 is also formed in the CMP stop layer 210. In some embodiments, as Figure 14B shown, the CMP stop layer 210 contacts a portion of the side surface of each conductive component 220 disposed above the gate electrode layer 172 and a portion of the side surface of each conductive component 214. As Figure 14B shown, the etch stop layer 216 contacts a portion of the side surface of each conductive component 220. Figure 14B shown, the etch stop layer 216 contacts a portion of the side surface of each conductive component 220.

[0073] Figures 15A to 15G is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along line A-A according to an alternative embodiment. In some embodiments, as Figure 6 shown,Figures 13A to 13H and Figures 14A to 14B As shown, conductive component 208 is formed before forming conductive component 214. In some embodiments, conductive component 214 is formed before forming conductive component 208. As Figure 15A shown, after forming conductive contact 180, etch stop layer 204 and ILD layer 206 are deposited on semiconductor device structure 100. Next, conductive component 214 is formed in ILD layer 206 and etch stop layer 204. As Figure 15B shown, a planarization process, such as a CMP process, is performed on semiconductor device structure 100.

[0074] As Figure 15C shown, CMP stop layer 210 is deposited on ILD layer 206 and conductive component 214, and ILD layer 212 is deposited on CMP stop layer 21. Next, as Figure 15D shown, conductive component 208 is formed in ILD layer 212, CMP stop layer 210, ILD layer 206, and etch stop layer 204. As Figure 15E shown, a CMP process is performed to expose CMP stop layer 210. CMP stop layer 210 covers conductive component 214 during the CMP process. Thus, conductive component 208 is exposed to the slurry of the CMP process, while conductive component 214 is protected by CMP stop layer 210. As a result, galvanic corrosion is prevented. In some embodiments, as Figure 15F shown, CMP stop layer 210 is removed. After removing CMP stop layer 210, the top surface of conductive component 214 and the top surface of ILD layer 206 are substantially coplanar, and the top surface of conductive component 208 extends to a level above the top surfaces of conductive component 214 and ILD layer 206. As Figure 15F shown, a portion of the side surface of each conductive component 208 is exposed. In some embodiments, as Figure 15F shown, the bottom surface of conductive component 208 and the bottom surface of conductive component 214 are substantially coplanar, and the top surface of conductive component 208 extends above the level of the top surface of conductive component 214.

[0075] Next, as Figure 15GAs shown, an etch stop layer 216 is deposited on the top surfaces of the conductive component 208, the ILD layer 206, and the conductive component 214, and the etch stop layer 216 is deposited on the exposed portions of the side surfaces of each conductive component 208. The IMD layer 218 is deposited on the etch stop layer 216, and the conductive component 220 is formed in the IMD layer 218 and the etch stop layer 216. In some embodiments, a planarization process, such as a CMP process, is performed, so that the top surfaces of the conductive component 220 and the IMD layer 218 are substantially coplanar. In some embodiments, the etch stop layer 216 contacts portions of the side surfaces of each conductive component 208 and portions of the side surfaces of each conductive component 220 disposed above the conductive component 214.

[0076] Figures 16A to 16B is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along line A-A according to an alternative embodiment. As Figure 6 shown, a CMP process is performed to expose the CMP stop layer 210 and the conductive component 208, which is the same manufacturing stage as Figure 16A shown. Next, as Figure 15E shown, an etch stop layer 216 is deposited on the CMP stop layer 210 and the conductive component 208, rather than removing the CMP stop layer 210. The ILD layer 218 is deposited on the etch stop layer 216, and the conductive component 220 is formed in the ILD layer 218 and the etch stop layer 216. As Figure 16B shown, the conductive component 220 disposed above the conductive component 214 is also formed in the CMP stop layer 210. In some embodiments, as Figure 16B shown, the CMP stop layer 210 contacts portions of the side surfaces of each conductive component 208 and portions of the side surfaces of each conductive component 220 disposed above the conductive component 214. As Figure 16B shown, the etch stop layer 216 contacts portions of the side surfaces of each conductive component 220. Figure 16B shown.

[0077] Figures 17A to 17E is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along line A-A according to an alternative embodiment. In some embodiments, the gate electrode layer 172 and the conductive contact 180 ( Figure 6 ) include different materials. Therefore, in some embodiments, the CMP process performed after forming the conductive contact 180 may cause galvanic corrosion. The CMP stop layer can be used to cover the gate electrode layer 172 during the CMP process. As Figure 12A ) shown, the gate electrode layer 172 is formed, which is the same manufacturing stage as Figure 17A shown, Figure 11A 、 Figure 11B 、 Figure 11C shown. Next, asFigure 17B As shown, a CMP stop layer 250 is deposited on the gate electrode layer 172 and the ILD layer 164. The CMP stop layer 250 is also deposited on the spacers 138, the gate dielectric layer 170, and the CESL 162. The CMP stop layer 250 may include the same material as the CMP stop layer 210 and may be formed by the same process as the CMP stop layer 210. The CMP stop layer 250 may have the same thickness as the CMP stop layer 210.

[0078] As Figure 17C shown, an ILD layer 206 is deposited on the CMP stop layer 250, and liners 202 and conductive contacts 180 are formed in the ILD layer 206. The liners 202 and the conductive contacts 180 are formed to pass through the ILD layer 206, the CMP stop layer 250, the ILD layer 164, and the CESL 162. Next, a CMP process is performed to remove portions of the conductive contacts 180, the ILD layer 206, and the liners 202 until the CMP stop layer 250 is exposed. During the CMP process, the gate electrode layer 172 (which may be made of a metal different from that of the conductive contacts 180) is covered by the CMP stop layer 250. As a result, galvanic corrosion is prevented. As Figure 17D shown, the top surface of the CMP stop layer 250 and the top surface of the conductive contacts 180 may be substantially coplanar.

[0079] Next, as Figure 17E shown, an ILD layer 206 is deposited on the CMP stop layer 250. As Figure 17E shown, the processes described in Figures 13B to 13H or Figures 13B to 13F and Figure 14B may be performed to form the conductive components 208, 214, the CMP stop layer 210, the etch stop layer 216, the IMD layer 218, and the conductive component 220. In some embodiments, the CMP stop layer 210 remains in the semiconductor device structure 100. In some embodiments, the CMP stop layer 210 is removed. In some embodiments, the conductive component 214 is formed before the conductive component 208. Thus, as Figure 17E shown, the height of the conductive component 208 is significantly greater than the height of the conductive component 214.

[0080] Figure 18 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100 taken along line A-A of Figure 6 . In some embodiments, the CMP stop layer 210 is removed, and the conductive component 208 is formed before the conductive component 214.

[0081] Embodiments of the present disclosure provide a semiconductor device structure 100 that includes a first conductive component 208 disposed on and in contact with a gate electrode layer 172 and a second conductive component 214 disposed on and in contact with a conductive contact 180. Since a CMP stop layer 210 is formed on the first conductive component 208 or the second conductive component 214, the height of the first conductive component 208 is different from the height of the second conductive component 214. Some embodiments can achieve advantages. For example, during a CMP process, the CMP stop layer 210 is formed on the first conductive component 208 or the second conductive component 214, and one of the first conductive component 208 and the second conductive component 214 is exposed during the CMP process, which can prevent galvanic corrosion.

[0082] An embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed above a substrate, a first source / drain region disposed above the substrate, a conductive contact disposed above the first source / drain region, a first dielectric layer disposed above the gate electrode layer and the conductive contact, a first conductive component disposed in the first dielectric layer, a second conductive component disposed in the first dielectric layer, and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer contacts a portion of the side surface of the second conductive component.

[0083] In some embodiments, the semiconductor device structure further includes spacers disposed on opposite sides of the gate electrode layer and a third dielectric layer disposed on the spacers, wherein the first dielectric layer is disposed on the third dielectric layer.

[0084] In some embodiments, the first conductive component and the second conductive component are disposed in the third dielectric layer.

[0085] In some embodiments, the top surface of the third dielectric layer and the top surface of the conductive contact are substantially coplanar.

[0086] In some embodiments, the semiconductor device structure further includes a fourth dielectric layer disposed on the second dielectric layer.

[0087] In some embodiments, the semiconductor device structure further includes: a third conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein the third conductive component is disposed on and in contact with the first conductive component.

[0088] In some embodiments, the semiconductor device structure further includes: a fourth conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein the fourth conductive component is disposed on and in contact with the second conductive component, and the top surface of the third conductive component and the top surface of the fourth conductive component are substantially coplanar.

[0089] In some embodiments, the first conductive component is disposed on and in contact with the gate electrode layer, and the second conductive component is disposed on and in contact with the conductive contact.

[0090] In some embodiments, the first conductive component is disposed on and in contact with the conductive contact, and the second conductive component is disposed on and in contact with the gate electrode layer.

[0091] Another embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed above a substrate, source / drain regions disposed above the substrate, a conductive contact disposed above the source / drain regions, a first dielectric layer disposed above the gate electrode layer and the conductive contact, a first conductive component disposed in the first dielectric layer, a second conductive component disposed in the first dielectric layer, a third conductive component disposed on and in contact with the first conductive component, a fourth conductive component disposed on and in contact with the second conductive component, and a second dielectric layer disposed above the first dielectric layer. The second dielectric layer contacts a portion of the side surface of the second conductive component and a first portion of the side surface of the third conductive component. The structure further includes a third dielectric layer disposed above the second dielectric layer, and the third dielectric layer contacts a portion of the side surface of the fourth conductive component and a second portion of the side surface of the third conductive component.

[0092] In some embodiments, the semiconductor device structure further includes a fourth dielectric layer disposed above the third dielectric layer, wherein the third conductive component and the fourth conductive component are disposed in the third dielectric layer and the fourth dielectric layer.

[0093] In some embodiments, the top surfaces of the third conductive component and the fourth conductive component are substantially coplanar.

[0094] In some embodiments, the semiconductor device structure further includes spacers disposed on opposite sides of the gate electrode layer and a fifth dielectric layer disposed on the spacers, wherein the first dielectric layer is disposed above the fifth dielectric layer.

[0095] In some embodiments, the first conductive component and the second conductive component are disposed in the fifth dielectric layer.

[0096] In some embodiments, the top surface of the fifth dielectric layer and the top surface of the conductive contact are substantially coplanar.

[0097] Another embodiment is a method. The method includes forming a first dielectric layer over a substrate, and the substrate includes a gate electrode layer, source / drain regions, and a conductive contact disposed over the source / drain regions. The method further includes forming a first conductive component in the first dielectric layer, depositing a second dielectric layer over the first conductive component and the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, forming a second conductive component in the first dielectric layer, the second dielectric layer, and the third dielectric layer, and performing a chemical mechanical polishing process to expose the second dielectric layer and the second conductive component. During the chemical mechanical polishing, the first conductive component is covered by the second dielectric layer.

[0098] In some embodiments, the method further includes: removing the second dielectric layer to expose the top surfaces of the first conductive component and the second conductive component and a portion of the side surface of the second conductive structure; and depositing a fourth dielectric layer over the first dielectric layer, the first conductive component, and the second conductive component, wherein the fourth dielectric layer is deposited over the exposed portion of the side surface of the second conductive structure.

[0099] In some embodiments, the method further includes: depositing a fourth dielectric layer over the second dielectric layer and the second conductive component.

[0100] In some embodiments, the first conductive component is formed over the gate electrode layer, and the second conductive component is formed over the conductive contact.

[0101] In some embodiments, the first conductive component is formed over the conductive contact, and the second conductive component is formed over the gate electrode layer.

[0102] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A gate electrode layer disposed above a substrate; A first source / drain region disposed above the substrate; A conductive contact disposed above the first source / drain region; A first dielectric layer disposed above the gate electrode layer and the conductive contact; A first conductive component disposed in the first dielectric layer; A second conductive component disposed in the first dielectric layer; And A second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is in contact with a portion of the side surface of the second conductive component.

2. The semiconductor device structure according to claim 1 further includes spacers disposed on opposite sides of the gate electrode layer and a third dielectric layer disposed on the spacers, wherein, The first dielectric layer is disposed on a third dielectric layer.

3. The semiconductor device structure according to claim 2, wherein, The first conductive component and the second conductive component are disposed in the third dielectric layer.

4. The semiconductor device structure according to claim 2, wherein, The top surface of the third dielectric layer and the top surface of the conductive contact are substantially coplanar.

5. The semiconductor device structure according to claim 1, further comprising a fourth dielectric layer disposed on the second dielectric layer.

6. The semiconductor device structure according to claim 5 further includes a third conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein, The third conductive component is disposed on the first conductive component and in contact with the first conductive component.

7. The semiconductor device structure according to claim 6 further includes a fourth conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein, The fourth conductive component is disposed on the second conductive component and in contact with the second conductive component, and the top surface of the third conductive component and the top surface of the fourth conductive component are substantially coplanar.

8. The semiconductor device structure according to claim 1, wherein, The first conductive component is disposed on the gate electrode layer and in contact with the gate electrode layer, and the second conductive component is disposed on the conductive contact and in contact with the conductive contact.

9. A semiconductor device structure, comprising: A gate electrode layer disposed above a substrate; A source / drain region disposed above the substrate; A conductive contact disposed above the source / drain region; A first dielectric layer disposed above the gate electrode layer and the conductive contact; A first conductive component disposed in the first dielectric layer; A second conductive component disposed in the first dielectric layer; A third conductive component disposed on the first conductive component and in contact with the first conductive component; A fourth conductive component disposed on the second conductive component and in contact with the second conductive component; A second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is in contact with a portion of the side surface of the second conductive component and a first portion of the side surface of the third conductive component; and A third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer is in contact with a portion of the side surface of the fourth conductive component and a second portion of the side surface of the third conductive component.

10. A method of manufacturing a semiconductor device structure, comprising: Forming a first dielectric layer above a substrate, wherein the substrate includes a gate electrode layer, a source / drain region, and a conductive contact disposed above the source / drain region; Forming a first conductive component in the first dielectric layer; Depositing a second dielectric layer on the first conductive component and the first dielectric layer; Depositing a third dielectric layer on the second dielectric layer; Forming a second conductive component in the first dielectric layer, the second dielectric layer, and the third dielectric layer; and A chemical mechanical polishing process is performed to expose the second dielectric layer and the second conductive component, wherein during the chemical mechanical polishing process, the first conductive component is covered by the second dielectric layer.

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