Gallium nitride device and preparation method thereof

Abstract

The invention provides a gallium nitride device and a preparation method of the gallium nitride device, relates to the technical field of semiconductor devices, and can improve the voltage withstanding level of a buffer layer of the gallium nitride device and improve the dynamic electrical property of the gallium nitride device. The gallium nitride device comprises a silicon substrate, an insulating layer and a buffer layer which are stacked in the first direction, the insulating layer is located between the silicon substrate and the buffer layer, the silicon substrate and the buffer layer are separated by the insulating layer, the insulating layer and the buffer layer are in contact connection, the insulating layer comprises a first part and a second part, and the first part and the second part are adjacently arranged in the second direction. In the first direction, the thickness of the first part is smaller than that of the second part, the second direction is perpendicular to the first direction, the insulating layer is introduced between the silicon substrate and the buffer layer and used for separating the silicon substrate from the buffer layer, background electrons are prevented from being captured by defects of the buffer layer, and therefore the on-resistance of the buffer layer is improved; the voltage withstanding level of the buffer layer is improved, and the dynamic electrical property of the gallium nitride device is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular, to a gallium nitride device and a method for manufacturing a gallium nitride device. Background Art

[0002] Gallium nitride (GaN) material is a new type of semiconductor material for developing microelectronic devices and optoelectronic devices, and together with semiconductor materials such as silicon carbide (SiC) and diamond, it is known as the third-generation semiconductor material. Due to the lack of large-size gallium nitride substrates, gallium nitride materials are generally grown by heteroepitaxy on sapphire, silicon carbide, and silicon substrates. Among them, silicon substrates are widely used as the epitaxial materials for gallium nitride microelectronic devices and gallium nitride optoelectronic devices to fabricate silicon-based gallium nitride devices due to their advantages such as large size, low cost, and adjustable conductivity.

[0003] In order to improve the vertical breakdown voltage of silicon-based gallium nitride devices, it is generally achieved by forming a high-resistance buffer layer above the silicon substrate. For example, growing a buffer layer with a high aluminum (Al) component to increase the breakdown voltage per unit thickness; growing a thicker gallium nitride buffer layer, etc. However, during the process of epitaxially growing gallium nitride materials on silicon substrates, a relatively large number of background electrons are easily generated, reducing the on-resistance of the buffer layer, thereby affecting the dynamic electrical properties of silicon-based gallium nitride devices. Summary of the Invention

[0004] Embodiments of the present disclosure provide a gallium nitride device and a method for manufacturing a gallium nitride device, which can improve the breakdown voltage level of the buffer layer of the gallium nitride device and enhance the dynamic electrical properties of the gallium nitride device.

[0005] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a gallium nitride device is provided. The gallium nitride device includes: a silicon substrate, an insulating layer, and a buffer layer stacked in a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact connection; the insulating layer includes a first part and a second part, and the first part and the second part are arranged adjacent to each other in a second direction; along the first direction, the thickness of the first part is less than the thickness of the second part, and the second direction is perpendicular to the first direction.

[0006] The gallium nitride device provided by the embodiments of the present disclosure introduces an insulating layer between the silicon substrate and the buffer layer, which is used to separate the silicon substrate and the buffer layer, play an electrical isolation role, block the electrical coupling between the silicon substrate and the buffer layer, avoid background electrons from being injected into the buffer layer and captured by buffer layer defects, thereby increasing the on-resistance of the buffer layer, improving the breakdown voltage level of the buffer layer, reducing the off-state leakage current, and further enhancing the dynamic on-resistance stability of the gallium nitride device, as well as enhancing the dynamic electrical properties and reliability of the gallium nitride device.

[0007] In the gallium nitride device provided by the embodiments of the present disclosure, the insulating layer includes a first part and a second part arranged adjacent to each other in the second direction. Along the first direction, the thickness of the first part is less than that of the second part, forming a structure with alternating thin and thick parts. This structure with alternating thin and thick parts is achieved by the process of secondary epitaxial growth of the insulating layer. By secondary epitaxial growth of the insulating layer, the crystal continuity of the insulating layer is ensured, the defects of the insulating layer are reduced, and a coherent insulating layer is formed to stably separate the silicon substrate and the buffer layer.

[0008] In some embodiments, a plurality of first parts and a plurality of second parts together form the first surface of the insulating layer. The first surface is in contact connection with the buffer layer, and the first surface has first protrusions and first depressions arranged alternately in the second direction.

[0009] In some embodiments, the number of the first parts is plural, and the number of the second parts is plural; along the second direction, the plurality of first parts and the plurality of second parts are arranged alternately.

[0010] In some embodiments, along the first direction, the range of the thickness difference between the first part and the second part is from 100 nm to 1000 nm.

[0011] In some embodiments, along the second direction, the length of each first part is from 200 nm to 10000 nm.

[0012] In some embodiments, along the second direction, the length of the plurality of second parts accounts for 30% to 70% of the length of the insulating layer.

[0013] In some embodiments, the thickness of the insulating layer is from 50 nm to 1500 nm.

[0014] In some embodiments, the thermal expansion coefficient of the insulating layer is less than ; and / or, the difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the silicon substrate is less than .

[0015] In some embodiments, the material of the insulating layer includes one or a combination of more of silicon nitride, silicon oxide, and silicon oxynitride.

[0016] In some embodiments, the buffer layer includes a first buffer layer and a second buffer layer stacked along the first direction, and the second buffer layer is located between the first buffer layer and the insulating layer.

[0017] In some embodiments, the second buffer layer includes a third part and a fourth part arranged along the first direction. The third part is located between the fourth part and the first part, and the third part is arranged in the second direction with the second part.

[0018] In some embodiments, the gallium nitride device further includes a nucleation layer located between the silicon substrate and the insulating layer, and the insulating layer is located between the nucleation layer and the buffer layer, and the insulating layer separates the nucleation layer and the buffer layer.

[0019] In some embodiments, the gallium nitride device further includes a channel layer, a barrier layer, and a cap layer stacked along a first direction. The buffer layer is located between the channel layer and the insulating layer, and the barrier layer is located between the channel layer and the cap layer.

[0020] In another aspect, a method for manufacturing a gallium nitride device is provided, including: providing a silicon substrate; forming an insulating layer and a buffer layer; wherein, the silicon substrate, the insulating layer, and the buffer layer are stacked along a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact connection; the insulating layer includes a first part and a second part, and the first part and the second part are arranged adjacent to each other in a second direction; along the first direction, the thickness of the first part is less than the thickness of the second part, and the second direction is perpendicular to the first direction.

[0021] In some embodiments, forming the insulating layer and the buffer layer includes: forming an insulating dielectric layer, and the silicon substrate and the insulating dielectric layer are stacked along the first direction; removing a part of the insulating dielectric layer to form a first hole, and the remaining insulating dielectric layer includes the first part of the insulating layer; forming the second part of the insulating layer in the first hole; forming the buffer layer.

[0022] In some embodiments, forming the second part of the insulating layer in the first hole includes: forming a third part of a second buffer layer, the third part and the first part are stacked along the first direction, the first part is located between the third part and the silicon substrate, and there is a second hole facing the first hole between adjacent third parts; filling an insulating material so that the insulating material covers the first hole, the second hole, and the third part; grinding the insulating material to expose the third part.

[0023] In some embodiments, forming the buffer layer includes: forming a fourth part of a second buffer layer, the fourth part covers the third part and the second part; forming a first buffer layer, and the second buffer layer is located between the first buffer layer and the insulating layer.

[0024] It can be understood that for the method for manufacturing a gallium nitride device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the gallium nitride device in the above text, and will not be elaborated here. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required to be used in some embodiments of the present disclosure will be briefly introduced below.

[0026] Figure 1 It is a schematic structural diagram of a gallium nitride device provided in an embodiment of the present application; Figure 2 Schematic structural diagram of a gallium nitride device provided by another embodiment of the present application; Figure 3 Schematic structural diagram of a gallium nitride device provided by another embodiment of the present application; Figure 4 Schematic structural diagram of a gallium nitride device provided by yet another embodiment of the present application; Figure 5 Schematic flow diagram of a method for fabricating a gallium nitride device provided by an embodiment of the present application; Figure 6 Schematic structural diagram of a silicon substrate provided by an embodiment of the present application; Figure 7 Schematic flow diagram of forming an insulating layer and a buffer layer provided by an embodiment of the present application; Figure 8 Schematic structural diagram of forming a first part of an insulating layer on a silicon substrate provided by an embodiment of the present application; Figure 9 Schematic structural diagram of forming a nucleation layer on a silicon substrate provided by an embodiment of the present application; Figure 10 Schematic structural diagram of forming a first part of an insulating layer on a nucleation layer provided by an embodiment of the present application; Figure 11 Schematic flow diagram of forming a second part of an insulating layer in a first hole provided by an embodiment of the present application; Figure 12 Schematic structural diagram of forming a first nitride layer and a second nitride layer provided by an embodiment of the present application; Figure 13 Schematic structural diagram of forming a third part of a second buffer layer provided by an embodiment of the present application; Figure 14 Schematic structural diagram of forming a third nitride layer provided by an embodiment of the present application; Figure 15 Schematic structural diagram of forming a third part of a second buffer layer provided by another embodiment of the present application; Figure 16 Schematic structural diagram of filling an insulating material provided by an embodiment of the present application; Figure 17 Schematic structural diagram of filling an insulating material provided by another embodiment of the present application; Figure 18 Schematic structural diagram of forming an insulating layer provided by an embodiment of the present application; Figure 19 Schematic structural diagram of forming an insulating layer provided by another embodiment of the present application; Figure 20Schematic flowchart of forming a buffer layer provided by an embodiment of the present application; Figure 21 Schematic structural diagram of the fourth part of forming a second buffer layer provided by an embodiment of the present application; Figure 22 Schematic structural diagram of the fourth part of forming a second buffer layer provided by another embodiment of the present application; Figure 23 Schematic structural diagram of forming a first buffer layer provided by an embodiment of the present application; Figure 24 Schematic structural diagram of forming a first buffer layer provided by another embodiment of the present application; Figure 25 Schematic structural diagram of forming a channel layer provided by an embodiment of the present application; Figure 26 Schematic structural diagram of forming a barrier layer and a cap layer provided by an embodiment of the present application; Figure 27 Schematic structural diagram of forming a channel layer provided by another embodiment of the present application. Detailed implementation manners

[0027] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0028] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0029] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0030] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0031] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0032] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0033] Gallium nitride (GaN) material is a new type of semiconductor material for developing microelectronic devices and optoelectronic devices. Together with semiconductor materials such as silicon carbide (SiC) and diamond, it is known as the third-generation semiconductor material. Due to the lack of large-size gallium nitride substrates, gallium nitride materials are generally grown heteroepitaxially on sapphire, silicon carbide, and silicon substrates. Among them, silicon (Si) substrates are widely used as the epitaxial materials for gallium nitride microelectronic devices and gallium nitride optoelectronic devices due to their advantages such as large size, low cost, and adjustable conductivity.

[0034] However, when growing gallium nitride thin film materials epitaxially on silicon substrates, it is limited by the large thermal mismatch and lattice mismatch between the silicon substrate and the gallium nitride material. The large thermal mismatch between the silicon substrate and the gallium nitride material means that the thermal expansion coefficients of GaN and silicon are extremely different. When cooling, GaN shrinks faster than silicon, resulting in the GaN epitaxial layer being subjected to tensile stress, which easily causes cracks or warping. The lattice mismatch between the silicon substrate and the gallium nitride material means that the lattice constants of GaN and silicon do not match, resulting in a high dislocation density in the GaN epitaxial layer, affecting the electrical properties of the fabricated gallium nitride devices (such as leakage current, reduction of breakdown voltage, etc.). To solve the above problems, the performance of gallium nitride devices can be improved by optimizing the gallium nitride epitaxial structure and substrate parameters (such as thickness, resistivity).

[0035] For example, a low-resistivity silicon substrate with a resistance less than 1 Ω·cm (ohm·centimeter) is used as the substrate for gallium nitride device epitaxy to reduce the on-resistance of the substrate. Alternatively, by increasing the substrate thickness, the overall resistivity of the substrate can be reduced, and the warping caused by thermal stress can be reduced. However, low-resistance silicon itself cannot withstand high voltages. The high breakdown voltage of silicon-based gallium nitride devices in the vertical direction (refer to the first direction in the following embodiments) is mainly achieved by a high-resistance buffer layer above the silicon substrate. Exemplarily, the breakdown voltage per unit thickness can be increased by growing a buffer layer with a high aluminum (Al) component (Al>50%) above the silicon substrate. For example, an AlN (aluminum nitride) or AlGaN (aluminum gallium nitride) superlattice buffer layer with a high Al component can be used, the thickness of the AlGaN buffer layer can be increased, and the Al component in AlGaN can be increased, etc.; alternatively, a thicker gallium nitride buffer layer can be grown to disperse stress using the thick buffer layer, reduce cracks, and simultaneously improve the breakdown voltage level in the vertical direction.

[0036] During the epitaxial growth of gallium nitride on a silicon substrate, that is, before epitaxially growing a buffer layer on the silicon substrate, aluminum nitride is usually used as a nucleation layer to relieve the lattice mismatch between GaN and silicon and provide a starting template for heteroepitaxy. However, a large number of dislocation defects (such as threading dislocations) are easily generated at the interface between silicon and AlN due to lattice mismatch and thermal mismatch. In addition, background electrons are easily generated at the AlN / Si interface, forming an unintentionally doped conductive channel, resulting in unstable leakage current or dynamic resistance. If the background electrons are captured by buffer layer defects, the on-resistance of the buffer layer will be reduced, thereby affecting the dynamic electrical properties of the fabricated silicon-based gallium nitride devices.

[0037] Figure 1 The structural schematic diagram of a gallium nitride device provided by an embodiment of the present application. To solve the above problems, in some embodiments, in combination with Figure 1 As shown, the present application provides a gallium nitride device 1, including a silicon substrate 10, an insulating layer 30, and a buffer layer 40 stacked in the first direction. The insulating layer 30 is located between the silicon substrate 10 and the buffer layer 40. The insulating layer 30 separates the silicon substrate 10 and the buffer layer 40, and the insulating layer 30 and the buffer layer 40 are in contact connection.

[0038] In this embodiment, an insulating layer 30 is introduced between the silicon substrate 10 and the buffer layer 40 to separate the silicon substrate 10 and the buffer layer 40, playing an electrical isolation role, blocking the electrical coupling between the silicon substrate 10 and the buffer layer 40, preventing background electrons from being injected into the buffer layer 40 and captured by buffer layer 40 defects, thereby improving the on-resistance of the buffer layer 40, improving the breakdown voltage level of the buffer layer 40, reducing the off-state leakage current, and further improving the dynamic on-resistance stability of the gallium nitride device 1, and improving the dynamic electrical properties and reliability of the gallium nitride device 1.

[0039] In some embodiments, along the first direction, the thickness of the insulating layer 30 is from 50 nm (nanometers) to 1500 nm. Exemplarily, the thickness of the insulating layer 30 is 50 nm, 300 nm, 650 nm, 800 nm, 1000 nm, 1250 nm or 1500 nm.

[0040] Among them, when the thickness of the insulating layer 30 approaches 50 nm along the first direction, it is beneficial to reduce the size of the gallium nitride device 1 along the first direction. When the thickness of the insulating layer 30 approaches 1500 nm along the first direction, it is beneficial to improve the electrical isolation effect of the insulating layer 30 and further enhance the dynamic on-resistance stability of the gallium nitride device 1.

[0041] In some embodiments, the thermal expansion coefficient of the insulating layer 30 is less than (per Kelvin); and / or, the difference between the thermal expansion coefficient of the insulating layer 30 and the thermal expansion coefficient of the silicon substrate 10 is less than .

[0042] In this embodiment, it is defined that the thermal expansion coefficient of the insulating layer 30 is less than Or, the difference between the thermal expansion coefficient of the insulating layer 30 and the thermal expansion coefficient of the silicon substrate 10 is less than , so that the thermal expansion coefficient of the insulating layer 30 is closer to that of the silicon substrate 10 than AlN (the thermal expansion coefficient of the silicon substrate 10 is about ), and the shrinkage behavior is more synchronized with that of silicon during cooling. In this embodiment, the insulating layer 30 acts as a "stress transition layer" to gradually absorb the sudden change in the thermal expansion coefficient between the silicon and the buffer layer 40 and avoid stress concentration in the thermal expansion coefficient.

[0043] In some embodiments, the material of the insulating layer 30 includes one or a combination of silicon nitride, silicon oxide and silicon oxynitride.

[0044] Among them, the thermal expansion coefficient of silicon nitride is , the thermal expansion coefficient of silicon oxide is , and the thermal expansion coefficient of silicon oxynitride generally ranges from to , and the specific value depends on its chemical ratio of nitrogen (N) and oxygen (O) and the preparation process. In this embodiment, the thermal expansion coefficients of silicon nitride, silicon oxide and silicon oxynitride are all less than , and the difference from the thermal expansion coefficient of the silicon substrate 10 is less than . When the insulating layer 30 is prepared from one or more of silicon nitride, silicon oxide and silicon oxynitride, the insulating layer 30 can play an electrical isolation role and, as a "stress transition layer", relieve the thermal mismatch between the silicon substrate 10 and the gallium nitride material.

[0045] Figure 2Schematic diagram of the structure of a gallium nitride device provided by another embodiment of this application. In some embodiments, in combination with Figure 2 As shown, the insulating layer 30 includes a first part 301 and a second part 302. The first part 301 and the second part 302 are arranged adjacent to each other in the second direction. Along the first direction, the thickness of the first part 301 is less than the thickness of the second part 302, and the second direction is perpendicular to the first direction.

[0046] In this embodiment, the first part 301 and the second part 302 are in contact with each other in the second direction, so that the first part 301 and the second part 302 together form a coherent insulating layer 30, thereby separating the silicon substrate 10 from the buffer layer 40. Among them, along the first direction, the thickness of the first part 301 is less than the thickness of the second part 302, forming a structure with alternating thin and thick parts. This structure with alternating thin and thick parts is realized by the process of secondary epitaxial growth of the insulating layer 30. By secondary epitaxial growth of the insulating layer 30, the crystal continuity of the insulating layer 30 is ensured, the defects of the insulating layer 30 are reduced, and a coherent insulating layer 30 is formed to stably separate the silicon substrate 10 from the buffer layer 40.

[0047] In some embodiments, in combination with Figure 2 As shown, the number of the first parts 301 is multiple, and the number of the second parts 302 is multiple. Along the second direction, the multiple first parts 301 and the multiple second parts 302 are arranged alternately.

[0048] In this embodiment, the insulating layer 30 includes a first part 301 and a second part 302 arranged adjacent to each other in the second direction. Along the first direction, the thickness of the first part 301 is less than the thickness of the second part 302. The number of the first parts 301 and the second parts 302 can be multiple, and the multiple first parts 301 and the multiple second parts 302 are arranged alternately to form a periodic alternating structure. This periodic alternating structure is realized by the process of secondary epitaxial growth of the insulating layer 30. The first epitaxial growth first grows a uniform thin insulating layer, and then openings are made in the areas that need to be thickened (i.e., the second part 302) through photolithography, and the mask in the area of the first part 301 is retained to form the first part 301 of the insulating layer 30. The second epitaxial growth selectively grows a thicker insulating layer in the opening area by secondary epitaxial growth to form the second part 302 of the insulating layer 30. By secondary epitaxial growth of the insulating layer 30, the crystal continuity of the insulating layer 30 is ensured, the defects of the insulating layer 30 are reduced, and a coherent insulating layer 30 is formed to stably separate the silicon substrate 10 from the buffer layer 40.

[0049] In some embodiments, in combination with Figure 2As shown, a plurality of first parts 301 and a plurality of second parts 302 together form the first surface 303 of the insulating layer 30. The first surface 303 is in contact connection with the buffer layer 40, and the first surface 303 has first protrusions 304 and first depressions 305 alternately arranged in the second direction.

[0050] In this embodiment, the periodic alternating structure formed by the alternating arrangement of the plurality of first parts 301 and the plurality of second parts 302 results in the first surface 303 of the insulating layer 30 having first protrusions 304 and first depressions 305 alternately arranged in the second direction. The first protrusions 304 and the first depressions 305 are realized by the process of secondary epitaxial growth of the insulating layer 30. By secondary epitaxial growth of the insulating layer 30, the crystal continuity of the insulating layer 30 is ensured, so as to stably separate the silicon substrate 10 and the buffer layer 40.

[0051] In some embodiments, along the first direction, the range of the thickness difference between the first part 301 and the second part 302 is 100 nm to 1000 nm. Exemplarily, as Figure 2 shown, along the first direction, if the thickness difference between the first part 301 and the second part 302 is h, then the value of h can be 100 nm, 300 nm, 500 nm, 700 nm, 900 nm or 1000 nm.

[0052] Among them, when the thickness difference between the first part 301 and the second part 302 along the first direction approaches 100 nm, it is beneficial to reduce the size of the gallium nitride device 1 in the first direction. When the thickness difference between the first part 301 and the second part 302 along the first direction approaches 1000 nm, it is beneficial to increase the thickness of the buffer layer 40, so as to further disperse stress, reduce cracks, and improve the breakdown voltage level of the gallium nitride device 1 in the first direction.

[0053] In some embodiments, along the second direction, the value range of the length of each first part 301 is 200 nm to 10000 nm. Exemplarily, as Figure 2 shown, along the second direction, if the length of a first part 301 is y, then the value of y can be 200 nm, 1500 nm, 2800 nm, 4000 nm, 5100 nm, 6300 nm, 7500 nm, 8800 nm or 10000 nm.

[0054] Among them, when the length of the first part 301 along the second direction approaches 200 nm, it is convenient for gallium nitride epitaxial growth and improves the crystal quality of gallium nitride epitaxial growth. When the length of the first part 301 along the second direction approaches 10000 nm, the preparation process is simple and is beneficial to the preparation of the gallium nitride device 1.

[0055] In some embodiments, along the second direction, the length of the plurality of second portions 302 accounts for 30% to 70% of the length of the insulating layer 30. Exemplarily, as Figure 2 shown, along the second direction, the length of one second portion 302 is f, and the length of the plurality of second portions 302 is f×m, where m represents the number of second portions 302. Let the ratio of the length of the plurality of second portions 302 to the length of the insulating layer 30 be K, then K = (f×m) / r, where r represents the length of the insulating layer 30, and the value of K can be 30%, 40%, 50%, 60% or 70%.

[0056] Among them, when the length of the plurality of second portions 302 along the second direction accounts for nearly 30% of the length of the insulating layer 30, the manufacturing process is simple, which is beneficial to the fabrication of the gallium nitride device 1. When the length of the plurality of second portions 302 along the second direction accounts for nearly 70% of the length of the insulating layer 30, it is convenient for gallium nitride epitaxial growth and can improve the crystal quality of gallium nitride epitaxial growth.

[0057] In the above embodiments, the thickness difference between the first portion 301 and the second portion 302 in the first direction, and the specific values of the length of each first portion 301 and the length of the plurality of second portions 302 in the second direction need to be set according to the actual requirements of the gallium nitride device 1 and the manufacturing process requirements, and are not specifically limited in this application.

[0058] In some embodiments, as shown in Figure 2 shown, the buffer layer 40 includes a first buffer layer 400 and a second buffer layer 410 stacked along the first direction, and the second buffer layer 410 is located between the first buffer layer 400 and the insulating layer 30. The first buffer layer 400 includes a high-resistance buffer layer, and the second buffer layer 410 includes a nitride buffer layer.

[0059] In this embodiment, the second buffer layer 410 is located between the first buffer layer 400 and the insulating layer 30, and the second buffer layer 410 is in contact connection with the insulating layer 30. The second buffer layer 410 includes a nitride buffer layer, and the material of the nitride buffer layer includes GaN and / or AlGaN. The first buffer layer 400 includes a high-resistance buffer layer, and the material of the high-resistance buffer layer includes iron (Fe) / carbon (C) doped GaN, and / or, high-Al-component AlGaN, and the resistivity of the high-resistance buffer layer is greater than Ω·cm.

[0060] In this embodiment, the second buffer layer 410 is used to provide a high-quality epitaxial template to improve the crystal quality of subsequent epitaxial growth, and at the same time provide a low-resistance lateral path to achieve lateral current spreading. The first buffer layer 400 uses its high-resistance characteristic to expand the depletion region laterally, reduce the longitudinal electric field strength, and at the same time block the leakage path caused by substrate defects, thereby improving the breakdown voltage of the gallium nitride device 1 in the vertical direction.

[0061] In some embodiments, along the first direction, the thickness of the second buffer layer 410 ranges from 300 nm to 1500 nm. Exemplarily, the thickness of the second buffer layer 410 is 300 nm, 600 nm, 900 nm, 1200 nm, or 1500 nm.

[0062] Among them, when along the first direction, the thickness of the second buffer layer 410 approaches 300 nm, it is beneficial to reduce the size of the gallium nitride device 1 in the first direction. When along the first direction, the thickness of the second buffer layer 410 approaches 1500 nm, in order to further disperse stress, reduce cracks, and improve the breakdown voltage level of the gallium nitride device 1 in the first direction.

[0063] In some embodiments, along the first direction, the thickness of the first buffer layer 400 ranges from 1000 nm to 5000 nm. Exemplarily, the thickness of the first buffer layer 400 is 1000 nm, 2000 nm, 3000 nm, 4000 nm, or 5000 nm.

[0064] Among them, when along the first direction, the thickness of the first buffer layer 400 approaches 1000 nm, it is beneficial to reduce the size of the gallium nitride device 1 in the first direction. When along the first direction, the thickness of the first buffer layer 400 approaches 5000 nm, in order to further disperse stress, reduce cracks, and improve the breakdown voltage level of the gallium nitride device 1 in the first direction.

[0065] In the above embodiments, the thickness values of the first buffer layer 400 and the second buffer layer 410 in the first direction need to be set according to the actual requirements of the gallium nitride device 1 and the requirements of the manufacturing process, and are not specifically limited in this application.

[0066] In some embodiments, as shown in Figure 2 the second buffer layer 410 includes a third portion 411 and a fourth portion 412 arranged along the first direction. The third portion 411 is located between the fourth portion 412 and the first portion 301, and the third portion 411 and the second portion 302 are arranged in the second direction.

[0067] In this embodiment, the third portion 411 and the fourth portion 412 are in contact with each other in the second direction, so that the third portion 411 and the fourth portion 412 jointly form a coherent second buffer layer 410, reducing internal defects of the second buffer layer 410.

[0068] In some embodiments, as shown in Figure 2As shown, the number of the third parts 411 is multiple, and the multiple third parts 411 are arranged at intervals along the second direction. Along the first direction, one third part 411 is in contact connection with one first part 301. Along the second direction, the multiple third parts 411 and the multiple second parts 302 are arranged alternately.

[0069] In this embodiment, the second buffer layer 410 includes a third part 411 and a fourth part 412 arranged along the first direction. Among them, the number of the third parts 411 can be multiple, and the multiple third parts 411 are arranged at intervals along the second direction to form a periodic structure. This periodic structure is realized by the process of secondary epitaxial growth of the second buffer layer 410. By secondary epitaxial growth of the second buffer layer 410, the crystal continuity of the second buffer layer 410 is ensured, and the crystal quality of the second buffer layer 410 is improved.

[0070] In some embodiments, combined with Figure 2 As shown, the fourth part 412 and the multiple third parts 411 together constitute the second surface 413 of the second buffer layer 410. The second surface 413 is in contact connection with the insulating layer 30, and the second surface 413 has second protrusions 414 and second depressions 415 arranged alternately along the second direction.

[0071] In this embodiment, the periodic structure formed by the multiple third parts 411 arranged at intervals along the second direction causes the second surface 413 of the second buffer layer 410 to have second protrusions 414 and second depressions 415 arranged alternately along the second direction. The second protrusions 414 and the second depressions 415 are realized by the process of secondary epitaxial growth of the second buffer layer 410. By secondary epitaxial growth of the second buffer layer 410, the crystal continuity of the second buffer layer 410 is ensured, and the crystal quality of the second buffer layer 410 is improved.

[0072] In the above embodiment, the second surface 413 of the second buffer layer 410 is in contact connection with the first surface 303 of the insulating layer 30, the first protrusion 304 is in contact connection with the second depression 415, and the first depression 305 is in contact connection with the second protrusion 414.

[0073] Figure 3 The structural schematic diagram of a gallium nitride device provided for another embodiment of the present application. In some embodiments, combined with Figure 3 As shown, the gallium nitride device 1 further includes a nucleation layer 20. Along the first direction, the nucleation layer 20 is located between the silicon substrate 10 and the insulating layer 30, the insulating layer 30 is located between the nucleation layer 20 and the buffer layer 40, and the insulating layer 30 separates the nucleation layer 20 and the buffer layer 40. The material of the nucleation layer 20 includes AlN, or AlN and GaN.

[0074] In this embodiment, a nucleation layer 20 is disposed between the silicon substrate 10 and the insulating layer 30 to alleviate the lattice mismatch and thermal stress between the silicon substrate 10 and GaN. The lattice constants of silicon and GaN differ significantly, and direct growth would result in a high density of dislocations (greater than ). By providing an intermediate transition layer, the nucleation layer 20 can partially compensate for the lattice mismatch and reduce the dislocation density. The thermal expansion coefficients of silicon and GaN also differ significantly. During the cooling process after growth, the nucleation layer 20 absorbs thermal stress through elastic or plastic deformation, which can reduce cracks or film peeling caused by thermal mismatch. In addition, the nucleation layer 20 forms nanoscale nuclei (such as island structures of AlN) on the silicon surface, and these nanoscale nuclei are combined into a continuous mask by controlling the growth conditions (such as temperature and pressure). During lateral epitaxial overgrowth, the design of the nucleation layer 20 (such as an AlN mask) can guide the lateral growth of GaN, further reducing threading dislocations and improving crystal quality.

[0075] Figure 4 FIG. is a schematic structural diagram of a gallium nitride device provided in another embodiment of the present application. In some embodiments, as shown in combination with Figure 4 , the gallium nitride device 1 further includes a channel layer 500, a barrier layer 510, and a cap layer 520 stacked along a first direction. Along the first direction, a buffer layer 40 is located between the channel layer 500 and the insulating layer 30, and the barrier layer 510 is located between the channel layer 500 and the cap layer 520.

[0076] In this embodiment, as shown in combination with Figure 4 , the channel layer 500, the barrier layer 510, and the cap layer 520 together constitute the device layer 50 of the gallium nitride device 1, which determines the performance of the gallium nitride device 1. Among them, the channel layer 500 is the main path for current to pass through, and electrons can move quickly in the channel layer 500 to achieve high-speed electron transport. The barrier layer 510 induces a two-dimensional electron gas in the channel layer 500 through the polarization effect. The barrier layer 510 also serves as a barrier to prevent electrons from leaking from the channel layer 500 to other regions. The cap layer 520 is used to protect the structure of the gallium nitride device 1, improve the surface characteristics, and adjust the electrical properties.

[0077] In some embodiments, the material of the channel layer 500 includes GaN. The material of the barrier layer 510 includes AlGaN. The material of the cap layer 520 includes one or a combination of GaN, SiN, and p-type GaN (p-GaN).

[0078] In some embodiments, along the first direction, the thickness of the channel layer 500 ranges from 50 nm to 500 nm. Exemplarily, the thickness of the channel layer 500 is 50 nm, 150 nm, 275 nm, 375 nm, or 500 nm.

[0079] In some embodiments, along the first direction, the thickness of the barrier layer 510 ranges from 10 nm to 30 nm. Exemplarily, the thickness of the barrier layer 510 is 10 nm, 20 nm, or 30 nm.

[0080] In some embodiments, the material of the cap layer 520 is GaN and / or SiN, and along the first direction, the thickness of the cap layer 520 ranges from 1 nm to 5 nm. Exemplarily, the thickness of the cap layer 520 is 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0081] In some embodiments, the material of the cap layer 520 is p-GaN, and along the first direction, the thickness of the cap layer 520 ranges from 50 nm to 100 nm. Exemplarily, the thickness of the cap layer 520 is 50 nm, 67 nm, 75 nm, 87 nm, or 100 nm.

[0082] In some embodiments, the present application provides a method for manufacturing a gallium nitride device for manufacturing the gallium nitride device described in the above embodiments. Figure 5 It is a schematic flow chart of a method for manufacturing a gallium nitride device provided by an embodiment of the present application. As Figure 5 shown, the method for manufacturing a gallium nitride device includes: S51, providing a silicon substrate.

[0083] In this step, the provided silicon substrate is as Figure 6 shown, Figure 6 which is a schematic structural diagram of a silicon substrate provided by an embodiment of the present application.

[0084] S52, forming an insulating layer and a buffer layer, wherein the silicon substrate, the insulating layer, and the buffer layer are stacked along the first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, the insulating layer and the buffer layer are in contact connection, the insulating layer includes a first part and a second part, the first part and the second part are arranged adjacent to each other in the second direction, and along the first direction, the thickness of the first part is less than the thickness of the second part, and the second direction is perpendicular to the first direction.

[0085] In this embodiment, by forming the stacked insulating layer 30 and buffer layer 40 on the provided silicon substrate 10 along the first direction, the gallium nitride device 1 described in the above embodiments can be formed. Therefore, for the method for manufacturing a gallium nitride device provided in this embodiment, the beneficial effects that can be achieved can refer to the beneficial effects of the gallium nitride device 1 in the above text, which will not be elaborated here.

[0086] In some embodiments, as Figure 7 shown, Figure 7 which is a schematic flow chart of forming an insulating layer and a buffer layer provided by an embodiment of the present application. Step S52, forming an insulating layer and a buffer layer, includes: S521, form an insulating dielectric layer, and the silicon substrate and the insulating dielectric layer are stacked along a first direction.

[0087] Figure 8 This is a schematic structural diagram of the first part of the insulating layer formed on the silicon substrate provided by an embodiment of the present application. In this step, in combination with Figure 8 as shown, a layer of silicon nitride, silicon oxide or silicon oxynitride with a thickness ranging from 50 nm to 2000 nm can be deposited on the silicon substrate 10 by PECVD (Plasma Enhance Chemical Vapor Deposition) process to form the insulating dielectric layer 306, so as to achieve the first epitaxy of the insulating layer 30 in the above embodiment (see Figures 1 to 4 the insulating layer 30 therein).

[0088] In one example, in combination with Figure 8 as shown, a 250-nm-thick silicon oxide film can be grown above the silicon substrate 10 by PECVD process to form the insulating dielectric layer 306.

[0089] In some embodiments, the gallium nitride device 1 includes a nucleation layer 20. For the specific position of the nucleation layer 20 in the gallium nitride device 1, refer to the above embodiment. In order to form the gallium nitride device 1 including the nucleation layer 20, before step S21 of forming the insulating dielectric layer, the manufacturing method of the gallium nitride device further includes: forming a nucleation layer, the silicon substrate, the nucleation layer and the insulating dielectric layer are stacked along a first direction, and the nucleation layer is located between the silicon substrate and the insulating dielectric layer.

[0090] Figure 9 This is a schematic structural diagram of the nucleation layer formed on the silicon substrate provided by an embodiment of the present application. In this embodiment, in combination with Figure 9 as shown, a nitride film (such as aluminum nitride film, or, aluminum nitride and gallium nitride film) can be deposited above the silicon substrate 10 by MOCVD (Metal-organic Chemical Vapor Deposition) process to form the nucleation layer 20. Among them, the deposition temperature range of the nucleation layer 20 is 800 °C to 1200 °C. Then, the temperature is lowered to room temperature to obtain an epitaxial wafer with the silicon substrate 10 and the nucleation layer 20 stacked along the first direction.

[0091] In one example, in combination with Figure 9 as shown, by MOCVD process, after the temperature is raised to 1150 °C, a 200-nm AlN film and a 100-nm GaN film can be grown above the silicon substrate 10 to form the nucleation layer 20, and then the temperature is lowered to room temperature to obtain an epitaxial wafer with the silicon substrate 10 and the nucleation layer 20 stacked along the first direction.

[0092] Figure 10 This is a schematic structural diagram of forming a first part of an insulating layer on a nucleation layer provided by an embodiment of the present application. In combination with Figure 10 as shown, in this embodiment, a silicon nitride, silicon oxide, or silicon oxynitride layer can be deposited on the epitaxial wafer shown in Figure 9 by PECVD process to form an insulating dielectric layer 306.

[0093] In one example, in combination with Figure 10 as shown, a first silicon nitride layer with a thickness of 300 nm can be deposited on the epitaxial wafer shown in Figure 9 by PECVD process to form an insulating dielectric layer 306.

[0094] S522, Remove part of the insulating dielectric layer to form a first hole, and the remaining insulating dielectric layer includes the first part of the insulating layer.

[0095] In this step, in combination with Figure 8 and Figure 10 as shown, part of the insulating dielectric layer 306 can be removed by photolithography and etching methods to expose the surface of the silicon substrate 10 or the surface of the nucleation layer 20 below the insulating dielectric layer 306. Among them, as Figure 8 shown, when the nucleation layer 20 is not included, after removing part of the insulating dielectric layer 306, the surface of the silicon substrate 10 below the insulating dielectric layer 306 is exposed; as Figure 10 shown, when the nucleation layer 20 is included, after removing part of the insulating dielectric layer 306, the surface of the nucleation layer 20 below the insulating dielectric layer 306 is exposed. Alternatively, part of the insulating dielectric can be removed by CMP (Chemical Mechanical Polishing) of the insulating dielectric layer 306 until the underlying silicon substrate 10 or nucleation layer 20 is exposed to form a first hole 307, and the remaining insulating dielectric layer 306 includes the first part 301 of the insulating layer 30, thereby forming a periodic pattern mask layer.

[0096] In the periodic pattern mask layer, the period length of the pattern mask (i.e., the length of each first part 301 in the above embodiment) is 200 nm to 10,000 nm, and the pattern opening ratio range (i.e., the ratio K of the length of multiple second parts 302 to the length of the insulating layer 30 in the above embodiment) is 30% to 70%. After forming the periodic pattern mask layer, the epitaxial wafer with the periodic pattern mask layer is cleaned and spun dry for use.

[0097] In one example, the gallium nitride device 1 does not include the nucleation layer 20. In combination with Figure 8As shown, part of the insulating dielectric layer 306 is etched to expose the surface of the silicon substrate 10. The period of the etched pattern (i.e., the length of each first part 301 in the above embodiment) is 800 nm, and the opening ratio of the pattern mask (i.e., along the second direction in the above embodiment, the length of multiple first holes 307 accounts for the total length of the periodic patterned mask layer) is 50%, forming a periodic patterned mask layer. Then, the epitaxial wafer with the pattern mask is cleaned and spun dry.

[0098] In another example, the gallium nitride device 1 includes a nucleation layer 20. As Figure 10 shown, part of the insulating dielectric layer 306 can be removed by photolithography and etching methods to expose the underlying nucleation layer 20, forming a periodic patterned mask layer. The period length of the pattern mask (i.e., the length of each first part 301 in the above embodiment) is 1000 nm, and the opening ratio of the pattern mask (i.e., the ratio K of the length of multiple second parts 302 to the length of the insulating layer 30 in the above embodiment) is 60%. Then, the epitaxial wafer with the pattern mask is cleaned and spun dry.

[0099] S523, form the second part of the insulating layer in the first hole.

[0100] S524, form a buffer layer.

[0101] In some embodiments, Figure 11 is a schematic flowchart of forming the second part of the insulating layer in the first hole provided by an embodiment of the present application. As Figure 11 shown, step S523, forming the second part of the insulating layer in the first hole, includes: S5231, form the third part of the second buffer layer. The third part and the first part are stacked along the first direction. The first part is located between the third part and the silicon substrate, and there are second holes facing the first hole between adjacent third parts.

[0102] Figure 12 is a schematic structural diagram of forming the first nitride and second nitride layers provided by an embodiment of the present application. Figure 13 is a schematic structural diagram of forming the third part of the second buffer layer provided by an embodiment of the present application. Combining Figure 8 、 Figure 12 and Figure 13As shown, in some embodiments, when the nucleation layer 20 is not included, step S5231 of forming the third part of the second buffer layer includes: forming a first nitride layer 416 in the first hole 307, the material of the first nitride layer 416 including aluminum nitride; forming a second nitride layer 417 that covers the first nitride layer 416 and the first part 301, the material of the second nitride layer 417 including gallium nitride; removing a part of the second nitride layer 417 and the first nitride layer 416 facing the first hole 307 to form a second hole 418 facing the first hole 307 in the second nitride layer 417, and the remaining second nitride layer 417 includes the third part 411 of the second buffer layer 410.

[0103] In this embodiment, in combination with Figure 12 as shown, the first nitride layer 416 (the first nitride layer 416 includes an aluminum nitride thin film) can be grown first on the epitaxial wafer with a periodic pattern mask layer as shown in Figure 8 by the MOCVD process, and then the second nitride layer 417 (the second nitride layer 417 includes a gallium nitride thin film) is grown. The growth temperature of the first nitride layer 416 and the second nitride layer 417 is 800°C to 1200°C. Among them, along the first direction, the total thickness of the first nitride layer 416 and the second nitride layer 417 is 300 nm to 1500 nm, and the second nitride layer 417 merges above the periodic pattern mask layer to form a continuous thin film, realizing that the second nitride layer 417 covers both the first nitride layer 416 and the first part 301 at the same time, achieving the first epitaxy of the second buffer layer 410 (refer to the second buffer layer 410 in Figures 2 to 4 ).

[0104] Furthermore, in combination with Figure 13 as shown, the first nitride layer 416 in the window area (i.e., within the first hole 307) of the periodic pattern mask layer in the epitaxial wafer as shown in Figure 12 and a part of the second nitride layer 417 facing the first hole 307 can be removed by photolithography and etching to expose the silicon substrate 10 under the insulating dielectric layer 306. At this time, the second nitride layer 417 forms a second hole 418 facing the first hole 307, and the remaining second nitride layer 417 forms the third part 411 of the second buffer layer 410.

[0105] In one example, as Figure 12 shown, the temperature is raised to 1100°C, and a 200-nm AlN layer is grown in sequence above the epitaxial wafer with a periodic pattern mask layer as shown in Figure 8 by the MOCVD process to form the first nitride layer 416, and a 500-nm GaN layer is formed to form the second nitride layer 417. The GaN layer merges above the first nitride layer 416 and the first part 301 by lateral epitaxy to form a continuous thin film. AsFigure 13 As shown, by photolithography and etching, remove Figure 12 In the epitaxial wafer shown, the first nitride layer 416 grown in the first hole 307 faces the second nitride layer 417 of the part opposite to the first hole 307, exposing the silicon substrate 10, and only the part of the second nitride layer 417 above the first part 301 is retained to form the third part 411 of the second buffer layer 410.

[0106] Figure 14 It is a schematic structural diagram of forming a third nitride layer provided by an embodiment of the present application. Figure 15 It is a schematic structural diagram of forming the third part of the second buffer layer provided by another embodiment of the present application. Combining Figure 10 、 Figure 14 and Figure 15 As shown, in some embodiments, when the nucleation layer 20 is included, step S5231 of forming the third part of the second buffer layer includes: forming a third nitride layer 420 in the first hole 307, the material of the third nitride layer 420 includes gallium nitride, and the third nitride layer 420 covers the first part 301; removing the part of the third nitride layer 420 located in the first hole 307 and opposite to the first hole 307 to form a second hole 418 opposite to the first hole 307, and the remaining third nitride layer 420 includes the third part 411 of the second buffer layer 410.

[0107] In this embodiment, combining Figure 14 As shown, the third nitride layer 420 can be grown on the epitaxial wafer with a periodic pattern mask layer shown by MOCVD process. The growth temperature of the third nitride layer 420 is 800 °C to 1200 °C. Among them, along the first direction, the third nitride layer 420 is 300 nm to 1500 nm, and the third nitride layer 420 merges above the periodic pattern mask layer to form a continuous thin film, realizing that the third nitride layer 420 covers the first part 301, and realizing the first epitaxy of the second buffer layer 410 (refer to the second buffer layer 410 in Figure 10 ). Figures 2 to 4 ).

[0108] Furthermore, combining Figure 15 As shown, the part of the third nitride layer 420 in the window area (located in the first hole 307 and opposite to the first hole 307) of the periodic pattern mask layer in the epitaxial wafer shown can be removed by photolithography and etching to expose the nucleation layer 20 below the insulating dielectric layer 306. At this time, the second hole 418 opposite to the first hole 307 is formed, and the remaining third nitride layer 420 forms the third part 411 of the second buffer layer 410. Figure 14 ).

[0109] In one example, as Figure 14As shown, heat up to 1000 °C and grow a 600-nm GaN thin film on the epitaxial wafer with a periodic pattern mask layer shown in Figure 8 to form the third nitride layer 420. The third nitride layer 420 merges above the first part 301 to form a continuous thin film. As shown in Figure 15 , remove, through photolithography and etching, the third nitride layer 420 that grows inside the first hole 307 and the part opposite to the first hole 307 shown in Figure 14 to expose the nucleation layer 20, and only retain the part of the third nitride layer 420 above the first part 301 to form the third part 411 of the second buffer layer 410.

[0110] S5232, fill with an insulating material so that the insulating material covers the first hole, the second hole, and the third part.

[0111] Figure 16 is a schematic structural diagram of the insulating material filling provided by an embodiment of the present application. Figure 17 is a schematic structural diagram of the insulating material filling provided by another embodiment of the present application. Combining Figure 16 and Figure 17 shown, in this step, an insulating material 419 (such as silicon nitride, silicon oxide, or silicon oxynitride) can be deposited in the epitaxial wafer formed in step S5231 through the PECVD process to fill the insulating material 419. Among them, the deposition thickness of the insulating material 419 is 50 nm to 2000 nm, and the insulating material 419 covers the first hole 307, the second hole 418, and the third part 411, forming a continuous mask in the second direction to achieve the second epitaxy of the insulating layer 30 (refer to the insulating layer 30 in Figures 1 to 4 ).

[0112] In one example, the second hole 418 is formed by removing part of the second nitride layer 417. Combining Figure 16 shown, silicon oxide can be deposited in the epitaxial wafer shown in Figure 13 through the PECVD process. The deposition thickness of the silicon oxide is 800 nm, so that the silicon oxide communicates with the remaining insulating dielectric layer 306 in the second direction to form a laterally penetrating thin film. The obtained thin film covers the first hole 307, the second hole 418, and the remaining second nitride layer 417, achieving coverage of the first hole 307, the second hole 418, and the third part 411.

[0113] In another example, the second hole 418 is formed by removing part of the third nitride layer 420. Combining Figure 17 shown, silicon oxide can be deposited in the epitaxial wafer shown in Figure 15Deposit silicon nitride on the epitaxial wafer shown. The deposition thickness of the silicon nitride is 600 nm, such that the silicon nitride and the remaining insulating dielectric layer 306 are connected in the second direction to form a laterally penetrating thin film. The obtained thin film covers the first hole 307, the second hole 418, and the remaining third nitride layer 420, achieving coverage of the first hole 307, the second hole 418, and the third part 411.

[0114] S5233, Remove part of the insulating material to expose the third part.

[0115] Figure 18 Schematic diagram of the structure for forming an insulating layer provided by an embodiment of the present application. Figure 19 Schematic diagram of the structure for forming an insulating layer provided by another embodiment of the present application. In this step, in combination with Figure 18 and Figure 19 As shown, the insulating material 419 can be partially etched by photolithography and etching methods, or CMP can be performed on the insulating material 419 to remove part of the insulating material 419 to expose the third part 411. After exposing the third part 411, the epitaxial wafer with the exposed third part 411 is cleaned and spin-dried for use. At this time, the remaining insulating material 419 includes the insulating material 419 located in the first hole 307 and the second hole 418, forming the second part 302. The first part 301 and the second part 302 together constitute the insulating layer 30, achieving the formation of the insulating layer 30 through secondary epitaxial growth.

[0116] In one example, the third part 411 is formed by the remaining second nitride layer 417. As Figure 18 shown, CMP can be performed on the insulating material 419 to remove the insulating material 419 above the remaining second nitride layer 417, thereby exposing the third part 411, and then the obtained epitaxial wafer is cleaned and spin-dried.

[0117] In another example, the third part 411 is formed by the remaining third nitride layer 420. As Figure 19 shown, CMP can be performed on the insulating material 419 to remove the insulating material 419 above the remaining third nitride layer 420, thereby exposing the third part 411, and then the obtained epitaxial wafer is cleaned and spin-dried.

[0118] Figure 20 Schematic diagram of the process for forming a buffer layer provided by an embodiment of the present application. In some embodiments, as Figure 20 shown, S524, Form a buffer layer, including: S5241, Form the fourth part of the second buffer layer, and the fourth part covers the third part and the second part.

[0119] Figure 21Schematic diagram of the fourth part for forming the second buffer layer provided by an embodiment of the present application. Figure 22 Schematic diagram of the fourth part for forming the second buffer layer provided by another embodiment of the present application. In this step, in combination with Figure 21 and Figure 22 As shown, a fourth nitride layer can be continuously grown on the epitaxial wafer formed in step S23, that is, the epitaxial wafer with the third part 411 exposed, by MOCVD process. The growth temperature range of the fourth nitride layer is 800 °C to 1200 °C, the thickness value range of the fourth nitride layer is 300 nm to 1500 nm, and the material of the fourth nitride layer includes gallium nitride. The fourth nitride layer merges above the third part 411 and the second part 302 to form a continuous thin film, forming the fourth part 412 of the second buffer layer 410, and realizing the second epitaxy of the second buffer layer 410. The fourth part 412 covers the third part 411 and the second part 302, and the fourth part 412 and the third part 411 together constitute the second buffer layer 410, realizing the growth of the second buffer layer 410 by secondary epitaxy.

[0120] In one example, the third part 411 is formed by the remaining second nitride layer 417. As Figure 21 shown, the temperature can be raised to 1000 °C, and a GaN thin film can be continuously grown on the epitaxial wafer as Figure 16 shown by MOCVD process. The thickness of the GaN thin film is 500 nm, so that the GaN thin film merges above the third part 411 and the second part 302, thereby forming the fourth part 412 of the second buffer layer 410.

[0121] In another example, the third part 411 is formed by the remaining third nitride layer 420. As Figure 22 shown, the temperature can be raised to 1050 °C, and a GaN thin film can be continuously grown on the epitaxial wafer as Figure 17 shown by MOCVD process. The thickness of the GaN thin film is 800 nm, so that the GaN thin film merges above the third part 411 and the second part 302, thereby forming the fourth part 412 of the second buffer layer 410.

[0122] S5242, form the first buffer layer, and the second buffer layer is located between the first buffer layer and the insulating layer.

[0123] Figure 23 Schematic diagram of the structure for forming the first buffer layer provided by an embodiment of the present application. Figure 24 Schematic diagram of the structure for forming the first buffer layer provided by another embodiment of the present application. In this step, in combination with Figure 23 and Figure 24As shown, a high-resistance buffer layer can be continuously grown above the second buffer layer 410 to form the first buffer layer 400. The temperature range for forming the first buffer layer 400 is 800°C to 1200°C, the thickness range of the first buffer layer 400 is 1000 nm to 5000 nm, and the material of the first buffer layer 400 includes Fe / C-doped GaN and / or high-Al-component AlGaN.

[0124] In one example, in combination with Figure 23 as shown, when the temperature of the reaction chamber is reduced to 900°C, a 50-nm AlN layer can be continuously grown on the surface of the epitaxial wafer shown in Figure 21 and then the temperature is raised to 1020°C to grow a 2000-nm AlGaN layer and a 1000-nm carbon-doped GaN layer to form a 3050-nm high-resistance buffer layer, thereby forming the first buffer layer 400.

[0125] In another example, in combination with Figure 24 as shown, when the temperature of the reaction chamber is 1000°C, an AlN layer, an AlGaN layer, and a carbon-doped GaN layer can be sequentially grown on the surface of the epitaxial wafer shown in Figure 22 to form a 2500-nm high-resistance buffer layer, thereby forming the first buffer layer 400.

[0126] In step S524, after the buffer layer is formed, the method for manufacturing a gallium nitride device further includes: forming a channel layer; forming a barrier layer; forming a cap layer. Among them, along the first direction, the buffer layer is located between the channel layer and the insulating layer, and the barrier layer is located between the channel layer and the cap layer.

[0127] Figure 25 It is a schematic structural diagram of forming a channel layer provided by an embodiment of the present application. Figure 26 It is a schematic structural diagram of forming a barrier layer and a cap layer provided by an embodiment of the present application. Figure 27 It is a schematic structural diagram of forming a channel layer provided by another embodiment of the present application. In this embodiment, in combination with Figure 4 and Figures 25 to 27As shown, a channel layer 500 can be further grown above the epitaxial wafer formed in step S24, i.e., the epitaxial wafer formed with a buffer layer 40. The material of the channel layer 500 includes GaN. The growth temperature range of the channel layer 500 is 1000°C to 1200°C. Along the first direction, the thickness of the channel layer 500 is 50 nm to 500 nm. Then, a barrier layer 510 is grown above the channel layer 500. The material of the barrier layer 510 includes AlGaN. The growth temperature range of the barrier layer 510 is 1000°C to 1200°C. Along the first direction, the thickness of the barrier layer 510 is 10 nm to 30 nm. Next, a cap layer 520 is grown above the barrier layer 510. The growth temperature range of the cap layer 520 is 900°C to 1200°C. Along the first direction, the cap layer 520 can be a GaN layer / SiN layer with a thickness of 1 nm to 5 nm, or a p-GaN layer with a thickness of 50 nm to 100 nm. In this embodiment, the channel layer 500, the barrier layer 510, and the cap layer 520 together constitute the device layer 50 of the gallium nitride device 1.

[0128] In one example, as Figure 25 shown, a GaN layer can be continuously grown above the first buffer layer 400 of the epitaxial wafer shown in Figure 23 to form a channel layer 500. The growth temperature of the channel layer 500 is 1080°C, and the thickness of the channel layer 500 is 200 nm. Further, as Figure 26 shown, an AlGaN layer is continuously grown above the channel layer 500 of the epitaxial wafer shown in Figure 25 to form a barrier layer 510. The growth temperature of the barrier layer 510 is 1060°C, and the thickness of the barrier layer 510 is 20 nm. As Figure 26 shown, a GaN layer is continuously grown above the barrier layer 510 to form a cap layer 520. The growth temperature of the cap layer 520 is 1060°C, and the thickness of the cap layer 520 is 3 nm.

[0129] In another example, as Figure 27 shown, a GaN layer can be continuously grown above the first buffer layer 400 of the epitaxial wafer shown in Figure 24 to form a channel layer 500. The growth temperature of the channel layer 500 is 1100°C, and the thickness of the channel layer 500 is 150 nm. Further, an AlGaN layer is continuously grown above the channel layer 500 of the epitaxial wafer shown in Figure 27 to form a barrier layer 510, as Figure 4 shown. The growth temperature of the barrier layer 510 is 1100°C, and the thickness of the barrier layer 510 is 20 nm. As Figure 4 shown, a p-GaN layer is continuously grown on the barrier layer 510 to form a cap layer 520. The growth temperature of the cap layer 520 is 980°C, and the thickness of the cap layer 520 is 100 nm.

[0130] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claimed rights.

Claims

1. A gallium nitride device, characterized in that, Comprising: A silicon substrate, an insulating layer, and a buffer layer stacked in a first direction, wherein the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact connection; The insulating layer includes a first portion and a second portion, and the first portion and the second portion are arranged adjacent to each other in a second direction; Along the first direction, the thickness of the first portion is less than the thickness of the second portion, and the second direction is perpendicular to the first direction.

2. The gallium nitride device according to claim 1, wherein A plurality of the first portions and a plurality of the second portions together constitute a first surface of the insulating layer, the first surface is in contact connection with the buffer layer, and the first surface has first protrusions and first depressions alternately arranged in the second direction.

3. The gallium nitride device according to claim 1 or 2, characterized in that, The number of the first portions is plural, and the number of the second portions is plural; Along the second direction, a plurality of the first portions and a plurality of the second portions are arranged alternately.

4. The gallium nitride device according to claim 3, wherein Along the first direction, the range of the thickness difference between the first portion and the second portion is 100 nm to 1000 nm; and / or, Along the second direction, the length of each first portion is 200 nm to 10000 nm; and / or, Along the second direction, the length of a plurality of the second portions accounts for 30% to 70% of the length of the insulating layer; and / or, The thickness of the insulating layer is 50 nm to 1500 nm.

5. The gallium nitride device according to claim 1 or 2, characterized in that, The material of the insulating layer includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

6. The gallium nitride device according to claim 1 or 2, characterized in that The buffer layer includes a first buffer layer and a second buffer layer stacked in the first direction, and the second buffer layer is located between the first buffer layer and the insulating layer.

7. The gallium nitride device according to claim 6, characterized in that, The second buffer layer includes a third portion and a fourth portion arranged in the first direction, the third portion is located between the fourth portion and the first portion, and the third portion and the second portion are arranged in the second direction.

8. The gallium nitride device according to claim 1 or 2, characterized in that, The gallium nitride device further includes a nucleation layer, the nucleation layer is located between the silicon substrate and the insulating layer, the insulating layer is located between the nucleation layer and the buffer layer, and the insulating layer separates the nucleation layer and the buffer layer.

9. A method for preparing a gallium nitride device, characterized in that, Comprising: Providing a silicon substrate; Forming an insulating layer and a buffer layer; Wherein, the silicon substrate, the insulating layer, and the buffer layer are stacked in a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact connection; the insulating layer includes a first portion and a second portion, and the first portion and the second portion are arranged adjacent to each other in a second direction; Along the first direction, the thickness of the first portion is less than the thickness of the second portion, and the second direction is perpendicular to the first direction.

10. The preparation method according to claim 9, characterized in that, The forming of the insulating layer and the buffer layer includes: Forming an insulating dielectric layer, and the silicon substrate and the insulating dielectric layer are stacked in the first direction; Removing a part of the insulating dielectric layer to form a first hole, and the remaining insulating dielectric layer includes the first portion of the insulating layer; Form the second part of the insulating layer within the first hole; Form a buffer layer.

11. The preparation method according to claim 10, characterized in that, The forming of the second part of the insulating layer within the first hole includes: Form a third part of a second buffer layer, the third part and the first part being stacked along the first direction, the first part being located between the third part and the silicon substrate, and there being a second hole facing the first hole between adjacent third parts; Fill the insulating material so that the insulating material covers the first hole, the second hole, and the third part; Grind the insulating material to expose the third part.

12. The preparation method according to claim 11, characterized in that, The forming of the buffer layer includes: Form a fourth part of a second buffer layer, the fourth part covering the third part and the second part; Form a first buffer layer, with the second buffer layer being located between the first buffer layer and the insulating layer.

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