Semiconductor material and method of making the same

Abstract

The embodiment of the present disclosure provides a semiconductor material and a preparation method thereof, wherein the semiconductor material comprises a first silicon carbide layer; the first silicon carbide layer comprises a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; a projection of a growth direction of the twin structure on a thickness extension direction of the first silicon carbide layer is greater than zero; and a size of the twin structure is greater than a grain size of the non-twin structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a semiconductor material and a preparation method thereof. BACKGROUND

[0002] As an important third-generation semiconductor material, silicon carbide (SiC) has the characteristics of wide band gap, high critical electric field, high thermal conductivity, high carrier saturation drift speed, etc., and has broad application prospects in the fields of semiconductor lighting, new-generation mobile communication, smart grid, high-speed rail transportation, new energy vehicles, and consumer electronics, and is a key new material supporting the development of information, energy, transportation, and national defense industries.

[0003] In practical applications, the performance of silicon carbide, such as etch resistance, directly affects the service life of semiconductor devices. Therefore, how to improve the etch resistance of silicon carbide has become a problem to be solved at present. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor material and a preparation method thereof. The semiconductor material provided by the embodiments of the present disclosure comprises: a first silicon carbide layer; the first silicon carbide layer comprises a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure on the thickness extension direction of the first silicon carbide layer is greater than zero; and the size of the twin structure is greater than the grain size of the non-twin structure.

[0005] In some embodiments, the twin structure comprises a plurality of twin crystals; and adjacent twin crystals contact each other.

[0006] In some embodiments, the plurality of twin crystals are symmetrically arranged in a direction perpendicular to the thickness extension direction.

[0007] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between a plurality of grains in the non-twin structure.

[0008] In some embodiments, the atomic density of the twin structure is greater than the atomic density of the non-twin structure.

[0009] In some embodiments, the first silicon carbide layer comprises a plurality of substructure layers stacked along the thickness extension direction; and the plurality of twin structures in each substructure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

[0010] In some embodiments, the first silicon carbide layer comprises a plurality of substructure layers stacked along the thickness extension direction; and the plurality of twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0011] In some embodiments, in the plurality of substructure layers, part of the twin structures extend from one substructure layer to another substructure layer along the thickness extension direction.

[0012] In some embodiments, in the plurality of twin structures in each of the substructure layers, sizes of at least part of the twin structures are different.

[0013] In some embodiments, in the plurality of substructure layers, sizes of the plurality of twin structures in each of the substructure layers are randomly distributed.

[0014] In some embodiments, the semiconductor material further comprises: a second silicon carbide layer; the second silicon carbide layer is composed of the non-twin structure; and the second silicon carbide layer and the first silicon carbide layer are alternately arranged along the thickness extension direction.

[0015] The method for preparing a semiconductor material provided by the embodiments of the present disclosure includes: forming a first silicon carbide layer by a chemical vapor deposition process to form the semiconductor material; wherein the first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; a projection of a growth direction of the twin structure on a thickness extension direction of the first silicon carbide layer is greater than zero; and a size of the twin structure is greater than a grain size of the non-twin structure.

[0016] The semiconductor material and the method for preparing the same provided by the embodiments of the present disclosure include: a first silicon carbide layer; the first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; a projection of a growth direction of the twin structure on a thickness extension direction of the first silicon carbide layer is greater than zero; and a size of the twin structure is greater than a grain size of the non-twin structure. In the embodiments of the present disclosure, on one hand, by increasing the twin structure with high etching resistance in the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Furthermore, the twin structure can make the first silicon carbide layer more uniformly distribute stress during deformation, so as to avoid stress concentration and improve the overall deformation ability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent with or intersects (not including perpendicular) the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder the movement of dislocations, so as to improve the strength of the first silicon carbide layer and prolong the service life of the device. On the other hand, when the growth direction of the twin structure is consistent with or intersects (not including perpendicular) the thickness direction of the first silicon carbide layer, the size of the twin structure in the thickness extension direction can be accurately controlled, so as to make the strength and toughness of the twin structure optimal, so that the high strength and high plasticity characteristics of the first silicon carbide layer can be simultaneously improved, so as to improve the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An exemplary cross-sectional schematic diagram of a semiconductor material provided in an embodiment of the present disclosure;

[0018] Figure 2 A schematic cross-sectional view of a semiconductor material provided in an embodiment of the present disclosure;

[0019] Figure 3 for Figure 2 Schematic diagram of the enlarged local area in the figure;

[0020] Figure 4 A schematic diagram of a process flow for forming a semiconductor material provided in an embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of the principle of forming a silicon carbide semiconductor material provided in an embodiment of the present disclosure.

[0022] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0024] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0025] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0026] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0027] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be proposed in the following description in order to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementations.

[0030] Silicon carbide is a wide bandgap semiconductor material with high voltage resistance, high thermal conductivity and high electric saturation mobility, making it suitable for harsh environments such as high temperature, high pressure and high frequency. Silicon carbide exists in various crystal direction structures, such as hexagonal structure (α-SiC), cubic structure (β-SiC), rhombohedral structure, etc. Silicon carbide with different crystal direction structures has different physical and chemical properties, making it suitable for different fields. Among them, cubic structure (such as 3C-SiC) has the characteristics of high temperature resistance, high pressure resistance, high electron mobility, etc., and is suitable for high frequency, high power, high temperature resistance, corrosion resistance, etc. Power electronic devices. Hexagonal structure (such as 4H-SiC and 6H-SiC) has high hardness and high thermal conductivity, and is widely used in the field of semiconductors, such as high-power electronic devices and optoelectronic devices. Rhombohedral structure (such as 15R-SiC) has good thermal stability and mechanical properties, and is suitable for aerospace, nuclear energy development and other fields.

[0031] In some embodiments, silicon carbide can also be divided into single crystal silicon carbide and polycrystalline silicon carbide. Single crystal silicon carbide can be applied to mechanical structure materials, semiconductor devices, power and optoelectronic devices in high temperature environment; polycrystalline silicon carbide can be applied to semiconductor devices, thin film coatings, magnetic materials and other fields. In some possible embodiments, polycrystalline silicon carbide can have a larger application in the parts of the plasma etching machine, for example, polycrystalline silicon carbide is used to prepare focusing rings, upper electrodes (also as a shower for multiple etching gas access holes) and other parts in the plasma etching machine.

[0032] In practical applications, the etching resistance of polycrystalline silicon carbide directly affects the service life of these parts, and the higher the etching resistance of polycrystalline silicon carbide, the longer the service life of the parts. The more uniform the etching resistance of polycrystalline silicon carbide, the better the etching stability of the parts. Therefore, how to improve the etching resistance and etching uniformity of polycrystalline silicon carbide has become a problem to be solved.

[0033] In view of this, in order to solve one or more of the above problems, a semiconductor material is proposed in the embodiments of the present disclosure, which can improve the etching resistance and etching uniformity of polycrystalline silicon carbide. Among them, referring to Figure 1 and Figure 2 , Figure 1 an exemplary cross-sectional schematic view of a semiconductor material provided by the present disclosure; Figure 2A schematic diagram of a physical cross-section of a semiconductor material according to the present disclosure; the semiconductor material comprises a first silicon carbide layer 102; the first silicon carbide layer 102 comprises a twin structure 100, a projection of a growth direction of the twin structure 100 on a thickness extension direction of the first silicon carbide layer is greater than zero.

[0034] It should be noted that the twin structure has higher etching resistance due to its high strength, high toughness, high stability and other characteristics. Therefore, in the embodiments of the present disclosure, on the one hand, by increasing the twin structure with high etching resistance in the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. In addition, the twin structure can make the first silicon carbide layer more uniformly distribute stress during deformation, avoid stress concentration, and thus improve the overall deformation ability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent or intersects (not including perpendicular) with the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and prolonging the service life of the device. On the other hand, when the growth direction of the twin structure is consistent or intersects (not including perpendicular) with the thickness direction of the first silicon carbide layer, the size of the twin structure in the thickness extension direction can be precisely controlled, thereby making the strength and toughness of the twin structure optimal, and thus the high strength and high plasticity characteristics of the first silicon carbide layer can be simultaneously improved, and the stability of the device can be improved.

[0035] In the embodiments of the present disclosure, the projection of the growth direction of the twin structure 100 on the thickness extension direction of the first silicon carbide layer is greater than zero, that is, the growth direction of the twin structure 100 can be the same / consistent with the thickness extension direction of the first silicon carbide layer 102, or can intersect with the thickness extension direction of the first silicon carbide layer 102. It should be emphasized that the intersection here does not include perpendicular. In other words, in some embodiments, the growth direction of the twin structure 100 can be parallel to the thickness extension direction of the first silicon carbide layer 102, so that the twin structure can guide the dislocations to extend in a certain direction, avoid lateral expansion, and improve the reliability of the semiconductor material. In other embodiments, the growth direction of the twin structure 100 forms an acute angle with the thickness extension direction of the first silicon carbide layer 102, rather than being completely perpendicular, that is, the twin structure grows obliquely; wherein the grain boundary in the oblique twin structure can effectively intercept the threading dislocations (such as screw dislocations and edge dislocations), reduce the defect density, and improve the reliability of the semiconductor material. In addition, the oblique twin structure can release lattice mismatch stress through shear component, that is, release epitaxial stress, reduce cracks and stacking faults of the first silicon carbide layer, and improve the quality of the semiconductor material.

[0036] The semiconductor material and the twin structure provided in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Here, the twin structure 100 can be a silicon carbide twin, for example.

[0037] In some embodiments, referring to Figure 3 , Figure 3 is a zoomed-in schematic view of a local region in Figure 2 . In this way, the twin structure 100 can include a plurality of twin crystals; adjacent twin crystals contact each other. In this way, the migration of grain boundaries and the propagation of cracks can be inhibited, the strength and hardness of the twin structure can be enhanced, and the stability of the twin structure can be improved.

[0038] In some embodiments, referring to Figure 3 , the plurality of twin crystals are symmetrically arranged in a direction perpendicular to a thickness extension direction. It should be understood that the symmetric arrangement helps to improve the stability of the twin structure. Here, the thickness extension direction of the first silicon carbide layer is, for example, the Z-axis direction, and the direction perpendicular to the thickness extension direction is, for example, the X-axis direction or the Y-axis direction. In some possible embodiments, the plurality of twin crystals can have a mirror-symmetric orientation relationship along a common twin boundary in the arrangement direction (X-axis direction or Y-axis direction). In this way, on the one hand, the strength and hardness of the twin structure can be significantly improved without losing the ductility of the material by introducing a high density of twin boundaries. On the other hand, the twin boundary has a lower interfacial energy, so that the plurality of twin crystals are very stable, and thus the twin structure can also maintain good stability performance in a high-temperature or high-stress environment.

[0039] In some embodiments, referring to Figure 1 and Figure 2 , the first silicon carbide layer 102 further includes a non-twin structure 200; the twin structure 100 is embedded in the non-twin structure 200; here, the area of the non-twin structure 200 is greater than the area of the twin structure 100. The non-twin structure 200 is, for example, polycrystalline silicon carbide. The polycrystalline silicon carbide can include a plurality of crystal orientations, such as <111> crystal orientation, <100> crystal orientation, etc., and the specific crystal orientation of the polycrystalline silicon carbide is not limited in the embodiments of the present disclosure.

[0040] In some possible embodiments, the size of the twin structure 100 is greater than the grain size of the non-twin structure 200. In this way, when the first silicon carbide layer is subjected to stress, the propagation of cracks can be limited, and the toughness and crack resistance of the first silicon carbide layer can be improved.

[0041] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between the plurality of grains in the non-twin structure. In other words, the plurality of twin crystals are more closely arranged, so that the twin structure has a higher density, and in this way, the mechanical properties, durability, and corrosion resistance of the twin structure can be improved, and the thermal stability of the twin structure can be enhanced.

[0042] In some embodiments, the atomic density of the twin structure 100 is greater than the atomic density of the non-twin structure 200. In this way, the defect density of the twin structure can be reduced, and the stability and etch resistance of the twin structure and the first silicon carbide layer can be improved.

[0043] In some embodiments, the plurality of twin structures are uniformly distributed in the first silicon carbide layer. In this way, the etch resistance uniformity of the first silicon carbide layer can be improved. Further, in the embodiments of the present disclosure, the etch resistance uniformity of the first silicon carbide layer can be improved by adjusting the distribution position of the twin structures in the first silicon carbide layer.

[0044] In some embodiments, the first silicon carbide layer can include a plurality of sub-structure layers stacked along a thickness extension direction; wherein the plurality of twin structures in each sub-structure layer are uniformly arranged along a direction perpendicular to the thickness extension direction. In this way, the etch resistance and etch resistance uniformity of each sub-structure layer can be improved.

[0045] In some possible embodiments, referring to Figure 1 , the first silicon carbide layer 102 can include a first sub-structure layer 1021, a second sub-structure layer 1022, and a third sub-structure layer 1023 stacked along the Z-axis direction. The first sub-structure layer 1021, the second sub-structure layer 1022, and the third sub-structure layer 1023 each include a plurality of twin structures. The plurality of twin structures in each sub-structure layer are uniformly arranged along the X-axis direction / Y-axis direction, so that the etch resistance and etch resistance uniformity of each sub-structure layer can be improved.

[0046] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along a thickness extension direction; wherein the plurality of twin structures in each sub-structure layer are randomly arranged in a direction perpendicular to the thickness extension direction. Here, the randomly arranged twin structures can impede dislocation movement in multiple directions, achieve a more uniform strengthening effect, avoid the mechanical performance short board of a single orientation, and improve the overall strength, toughness, and stability of the semiconductor material.

[0047] In some embodiments, among the plurality of sub-structure layers, part of the twin structures extend from one sub-structure layer to another sub-structure layer along the thickness extension direction. In this way, the adhesion between the two sub-structure layers can be improved, and the stability of the first silicon carbide layer in the thickness extension direction can be improved.

[0048] In some possible embodiments, referring to Figure 1 , the twin structure (such as the twin structure labeled as 100a) extends from the first sub-structure layer 1021 to the second sub-structure layer 1022 along the Z-axis direction, so that the adhesion between the first sub-structure layer 1021 and the second sub-structure layer 1022 can be improved, and the stability of the first silicon carbide layer in the Z-axis direction can be improved.

[0049] In some embodiments, the sizes of at least part of the plurality of twin structures in each sub-structure layer are different. In this way, the etch resistance uniformity of the first silicon carbide layer can be further improved.

[0050] In some possible embodiments, referring to Figure 1 The plurality of twin structures in the third sub-structure layer 1023 include a first twin structure 100b, a second twin structure 100c, and a third twin structure 100d, and the sizes of the first twin structure 100b, the second twin structure 100c, and the third twin structure 100d are all different. In this way, the stress can be dispersed within the third sub-structure layer 1023 to form a gradient distribution or a non-uniform distribution, thereby improving the strength and toughness of the third sub-structure layer 1023 as a whole.

[0051] In some possible embodiments, the size of the second twin structure 100c in the third sub-structure layer 1023 can be the same as that of the fourth twin structure 100e in the first sub-structure layer 1021. In this way, the damage distribution on different sub-structure layers can be made more uniform, and the rapid expansion of local damage can be avoided. In other words, the sizes of part of the plurality of twin structures in the first silicon carbide layer are the same, and the sizes of another part of the plurality of twin structures are different. In this way, the stress concentration of the first silicon carbide layer can be reduced, and the etch resistance uniformity of the first silicon carbide layer can be further improved.

[0052] In some embodiments, in the plurality of sub-structure layers, the sizes of the plurality of twin structures in each sub-structure layer are randomly distributed. In other words, the sizes of the plurality of twin structures in the first silicon carbide layer are randomly distributed. In this way, the generation of internal defects can be reduced, thereby improving the fatigue resistance of the first silicon carbide layer, reducing the concentration of local stress in the first silicon carbide layer, and enhancing the crack resistance and etch resistance uniformity of the first silicon carbide layer.

[0053] In some possible embodiments, in the plurality of twin structures in each sub-structure layer, the larger twin structures are uniformly distributed, and the smaller twin structures are randomly arranged. In this way, the etch resistance uniformity of the sub-structure layer and the semiconductor material can be further improved, and the generation of particles can be reduced.

[0054] In some embodiments, the semiconductor material further includes a second silicon carbide layer; the second silicon carbide layer is composed of non-twin structures; and the second silicon carbide layer and the first silicon carbide layer are alternately and stacked arranged along the thickness extension direction. In this way, the crack probability of the semiconductor material in the thickness extension direction can be reduced, and the etch resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) can be enhanced.

[0055] In some possible embodiments, referring to Figure 1The semiconductor material may include two second silicon carbide layers, namely a bottom second silicon carbide layer 101 and a top second silicon carbide layer 103, and the first silicon carbide layer 102 is located between the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103. The constituent materials of the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 may be the same, such as both being composed of a non-twin structure, that is, the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 are both polycrystalline silicon carbide.

[0056] It should be noted that during later processing of semiconductor materials, processes such as grinding and polishing may be used, which can easily form cracks in the growth direction (i.e., the thickness extension direction). In this case, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can reduce the elastic degradation of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) and improve the semiconductor material's etching resistance in the growth direction. In other words, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can both improve the semiconductor material's etching resistance in the growth direction and prevent the formation of cracks extending along the growth direction during processing.

[0057] In other embodiments, the semiconductor material may also include only a second silicon carbide layer, and the second silicon carbide layer and the first silicon carbide layer are stacked and arranged along the Z-axis direction. Specifically, the second silicon carbide layer may be Figure 1 The bottom second silicon carbide layer 101 in Figure 1 In this way, the probability of longitudinal cracks caused by the excessive size of the twin structure in the Z-axis direction can be reduced, thereby improving the quality and reliability of the semiconductor material.

[0058] Based on this, in the embodiment of the present disclosure, on the one hand, by adding a twin structure with high etching resistance in the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Furthermore, the twin structure can make the first silicon carbide layer distribute stress more evenly during deformation, avoid stress concentration, and thus improve the overall deformation capacity of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and extending the service life of the device. Furthermore, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the size of the twin structure in the thickness extension direction can be precisely controlled, and then the strength and toughness of the twin structure can be optimized. In this way, the high strength and high plasticity characteristics of the first silicon carbide layer can be simultaneously improved, thereby improving the stability of the device. On the other hand, the etching resistance uniformity of the first silicon carbide layer can be improved by adjusting the distribution position of the twin structure in the first silicon carbide layer. In this way, the service life of the device can be extended and the stability of the device can be improved.

[0059] Based on the above semiconductor material, the embodiment of the present disclosure provides a preparation method of a semiconductor material, referring to Figure 4 , Figure 4 A process flow diagram for forming a semiconductor material is provided in the embodiment of the present disclosure; wherein the method comprises the following steps:

[0060] Step S401: forming a first silicon carbide layer by a chemical vapor deposition process to form a semiconductor material; wherein the first silicon carbide layer comprises a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure. Here, the twin structure includes silicon carbide twin.

[0061] It should be noted that the preparation process of the semiconductor material may, for example, include a solid phase method, such as carbothermal reduction method, silicon-carbon direct reaction method, etc. Liquid phase method (LPE, Liquid Phase Epitaxy), such as sol-gel method, polymer thermal decomposition method, etc. Gas phase method, such as chemical vapor deposition method (CVD, Chemical Vapor Deposition), physical vapor transport method (PVT, Physical Vapor Transport), and high temperature chemical vapor deposition method (HTCVD, High Temperature Chemical Vapor Deposition), thermal decomposition method, plasma method, laser-induced gas phase method, etc., which are not limited by the present disclosure.

[0062] In the embodiment of the present disclosure, the formation of the semiconductor material by the chemical vapor deposition method (CVD) and the semiconductor material as a silicon carbide structure is taken as an example for illustration. Among them, the process of depositing the silicon carbide structure can include the following steps: providing a substrate and a CVD reaction device; placing the substrate on the susceptor in the CVD reaction chamber. Among them, the substrate can include but is not limited to graphite substrate.

[0063] A specific reaction pressure and a specific reaction temperature are set for a CVD reaction chamber, and a main reaction gas and a carrier gas are mixed and injected into the reaction chamber (Chamber) for deposition while maintaining the specific reaction pressure and the specific reaction temperature. The main reaction gas can include a monomeric reaction gas and a binary reaction gas, such as methyltrichlorosilane (MTS), dimethyldichlorosilane (DDS), trimethylchlorosilane (TCS), and the like. The binary reaction gas can include, for example, silane and carbon. The carrier gas can be, for example, hydrogen and argon, and the like.

[0064] For the sake of clear understanding, the main reaction gas is taken as methyltrichlorosilane (MTS) as an example for illustration hereinafter, and it should be understood that the description of the reaction gas hereinafter is only for illustration of the present disclosure and does not limit the scope of the present disclosure.

[0065] In some possible embodiments, in the process of forming a silicon carbide structure on a graphite substrate using a system with MTS as the main reaction gas and hydrogen as the carrier gas, a series of complex chain reactions between the diluted gaseous MTS and the excess hydrogen near the surface of the substrate and the gradual condensation and growth of the gas-phase particles on the surface of the substrate are involved, which mainly include multi-element and multi-phase radical-based intermediate phase reactions, decomposition, surface adsorption, and catalysis. In the deposition process, too high or too low values of the deposition temperature and the partial pressure of each gas-phase reactant will cause different changes in the reaction rate of each intermediate reaction, which can change the slowest step of the reaction process, resulting in changes in the reaction product and different deposition structures. Therefore, different semiconductor materials can be obtained by adjusting the specific reaction pressure and the specific reaction temperature.

[0066] In the deposition process of preparing a silicon carbide structure from MTS, reference is made to Formula 1, which provides a reaction formula of the overall deposition reaction. The overall deposition reaction can include three steps. In the first step, MTS is sequentially thermally decomposed into groups containing silicon elements, carbon elements, and chlorine elements, as shown in Formula 2 and Formula 3. In the second step, the groups SiCl2 / CH2formed by the first thermal decomposition are adsorbed onto the substrate and subjected to secondary thermal decomposition, as shown in Formula 4 and Formula 5. In the third step, the groups adsorbed on the substrate react with each other, as shown in Formula 6. Of course, the silicon elements and the carbon elements can react with each other to form silicon carbide, or silicon carbide and silicon elements, or silicon carbide and carbon elements.

[0067] (Formula 1)

[0068] (Formula 2)

[0069] (Formula 3)

[0070] (Formula 4)

[0071] (Formula 5)

[0072] (Formula 6)

[0073] Specifically, as shown in Figure 5 the step of forming the silicon carbide structure can include: (1) transport of reactants, i.e., transporting the gaseous reactants into a chemical vapor deposition reactor (i.e., a reaction chamber); (2) precursor reaction, i.e., the first thermal decomposition reaction of the reaction gas to form groups containing silicon elements, carbon elements, and chlorine elements; (3) gas molecule diffusion, i.e., diffusion of the groups formed by the first thermal decomposition reaction; (4) precursor adsorption, i.e., adsorption of the groups formed by the first thermal decomposition reaction onto the substrate; (5) precursor diffusion into the substrate; (6) surface reaction, i.e., mutual reaction between the groups adsorbed by the substrate to form a continuous silicon carbide structure; (7) desorption of by-products, i.e., desorption of by-products adsorbed onto the substrate; (8) by-product removal, i.e., removal of by-products from the outlet of the reaction chamber.

[0074] Here, the silicon carbide structure can include a first silicon carbide layer, in other words, the first silicon carbide layer can be formed by the above method.

[0075] In some embodiments, the type of crystal orientation of the semiconductor material can be adjusted by controlling different reaction parameters (such as a specific reaction pressure and a specific reaction temperature).

[0076] In some embodiments, the twin structure can include a plurality of twin crystals; adjacent ones of the twin crystals contact each other.

[0077] In some embodiments, the plurality of twin crystals are symmetrically arranged in a direction perpendicular to the thickness extension direction.

[0078] In some possible embodiments, the non-twin structure includes polycrystalline silicon carbide.

[0079] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between a plurality of grains in the non-twin structure.

[0080] In some embodiments, the twin structure has an atomic density greater than that of the non-twin structure.

[0081] In some embodiments, the first silicon carbide layer comprises a plurality of substructure layers stacked along a thickness extension direction; wherein the plurality of twin structures in each substructure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

[0082] In some embodiments, the first silicon carbide layer comprises a plurality of substructure layers stacked along a thickness extension direction; wherein the plurality of twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0083] In some embodiments, in the plurality of substructure layers, part of the twin structures extend from one substructure layer to another substructure layer along the thickness extension direction.

[0084] In some embodiments, in the plurality of twin structures in each substructure layer, at least part of the twin structures have different sizes.

[0085] In some embodiments, in the plurality of substructure layers, the sizes of the plurality of twin structures in each substructure layer are randomly distributed. In this way, the etching uniformity of the first silicon carbide layer can be enhanced, and the generation of particles can be reduced.

[0086] In some embodiments, the method further comprises: forming a second silicon carbide layer on at least one side of the first silicon carbide layer along the thickness extension direction. The second silicon carbide layer is composed of non-twin structures.

[0087] In some possible embodiments, the second silicon carbide layer can be located on only one side of the first silicon carbide layer along the thickness extension direction, or can be located on opposite sides of the first silicon carbide layer along the thickness extension direction, respectively. In this way, the probability of cracks of the semiconductor material in the thickness extension direction can be reduced, and the etching resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) can be enhanced.

[0088] In some possible embodiments, the method can specifically comprise: forming a bottom second silicon carbide layer on the substrate, forming the first silicon carbide layer on the bottom second silicon carbide layer, and forming a top second silicon carbide layer on the first silicon carbide layer. In this way, a second silicon carbide layer can be formed on each of the opposite sides of the first silicon carbide layer along the growth direction, so as to further improve the quality and reliability of the semiconductor material.

[0089] It should be understood that the term "in one embodiment" or "in an embodiment" as used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Therefore, appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-mentioned processes does not mean the execution order, and the execution order of the processes should be determined according to the functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence of the above-mentioned embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0090] The preferred embodiments of the disclosure are described above, and the patent scope of the disclosure is not limited by the above description. Any equivalent structure transformation made according to the disclosure, or direct / indirect application in other related technical fields within the concept of the disclosure is included in the patent protection scope of the disclosure.

Claims

1. A semiconductor material, characterized in that include: a first silicon carbide layer; The first silicon carbide layer includes a twin structure and a non-twin structure; The twinned structure is embedded in the non-twinned structure; The projection of the growth direction of the twin structure on the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure; wherein the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; among the plurality of substructure layers, part of the twin structures extends from one substructure layer to another substructure layer along the thickness extension direction; as well as, A second silicon carbide layer; the second silicon carbide layer is composed of the non-twin structure; the second silicon carbide layer and the first silicon carbide layer are alternately stacked and arranged along the thickness extension direction.

2. The semiconductor material according to claim 1, characterized in that The twin structure includes a plurality of twin crystals; adjacent twin crystals are in contact with each other.

3. The semiconductor material according to claim 2, characterized in that The plurality of twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction.

4. The semiconductor material according to claim 2, characterized in that The porosity between the plurality of twinned crystals is smaller than the porosity between the plurality of grains in the non-twinned structure.

5. The semiconductor material according to claim 1, characterized in that The atomic density of the twin structure is greater than the atomic density of the non-twin structure.

6. The semiconductor material according to claim 1, characterized in that The multiple twin structures in each substructure layer are evenly arranged in a direction perpendicular to the thickness extension direction.

7. The semiconductor material according to claim 1, characterized in that The multiple twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

8. The semiconductor material according to claim 6 or 7, characterized in that Among the multiple twin structures in each substructure layer, at least some of the twin structures have different sizes.

9. The semiconductor material according to claim 6 or 7, characterized in that In the plurality of substructure layers, sizes of the plurality of twin structures in each substructure layer are randomly distributed.

10. A method for preparing a semiconductor material, characterized in that: The method comprises: The semiconductor material is formed by alternately stacking a first silicon carbide layer and a second silicon carbide layer along a thickness extension direction through a chemical vapor deposition process; wherein, The first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure on the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure; the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; among the plurality of substructure layers, part of the twin structures extend from one substructure layer to another substructure layer along the thickness extension direction; the second silicon carbide layer is composed of the non-twin structure.

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