Integrated passive device and manufacturing method thereof

Abstract

The invention discloses an integrated passive device and a manufacturing method thereof. Relates to the technical field of semiconductors. The integrated passive device comprises a substrate; the first type of passive elements and the second type of passive elements are located on one side of the substrate and arranged in the first direction; wherein the first type of passive elements are connected with the second type of passive elements, and the first direction is parallel to the direction of the surface of the substrate. Passive elements deposited on a substrate in the integrated passive device are changed from vertical stacking to horizontal arrangement (in the first direction parallel to the surface of the substrate), at least one dielectric layer is reduced, interlayer parasitic capacitance and loss of dielectric materials are reduced, and therefore the inductance Q value and the self-resonant frequency are improved, and the performance of the integrated passive device is improved. And the device performance is finally improved. Therefore, the technical problem of poor performance stability of the device caused by interlayer parasitic capacitance and high-frequency loss introduced by a plurality of dielectric layers due to the fact that various passive elements are arranged by adopting a vertical stacking framework in the integrated passive device in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to an integrated passive device and a manufacturing method thereof. Background Art

[0002] In recent years, due to the growing demand for miniaturization of electronic devices and the progress of the semiconductor industry, the market for integrated passive devices (IPDs) has experienced significant growth. By integrating discrete passive components (resistors, capacitors, inductors) into a single chip-level package, integrated passive devices significantly improve circuit density and system reliability.

[0003] In existing integrated passive devices, a technical path of vertically stacking passive components on one side surface of a substrate is generally adopted. Taking a typical structure including a capacitor and a double-layer inductor as an example, its manufacturing process is as follows: First, a MIM (metal-insulator-metal) capacitor structure (composed of a first electrode, a first dielectric layer, and a second electrode) is constructed on the substrate surface; then, a second dielectric layer, a first inductor layer (conducted with the capacitor through a via), a third dielectric layer, and a second inductor layer (conducted with the first inductor layer through a via) are sequentially deposited, and finally a vertically stacked capacitor-double inductor layout is formed.

[0004] However, this vertical stacking architecture has the following technical bottlenecks: (1) The introduction of multiple dielectric layers inevitably generates interlayer parasitic capacitance, whose value is proportional to the dielectric constant of the dielectric layer and the overlapping area of the electrodes, resulting in a significant downward shift of the inductance self-resonant frequency and a reduction in the quality factor (Q value), affecting the performance stability of the device; (2) In high-frequency scenarios such as millimeter waves, the polarization loss (caused by dipole rotation hysteresis) and leakage conductance loss (caused by the conductivity of the material) of the dielectric material increase sharply, resulting in device temperature rise, which may cause risks of inductance metal migration and capacitor dielectric breakdown, further affecting the performance stability of the device.

[0005] Therefore, there is an urgent need for an innovative integrated passive device architecture to fundamentally reduce parasitic effects and high-frequency losses and improve device performance by reducing the usage amount of dielectric layers. Summary of the Invention

[0006] Embodiments of the present disclosure provide an integrated passive device and a manufacturing method thereof. At least solve the problem that in the prior art, an integrated passive device adopts a vertical stacking architecture to arrange various passive components, and due to the introduction of interlayer parasitic capacitance and high-frequency losses by multiple dielectric layers, the performance stability of the device is poor.

[0007] According to one aspect of the embodiments of the present disclosure, an integrated passive device is provided, including: a substrate; and a first type of passive element and a second type of passive element located on one side of the substrate and arranged in a first direction; wherein, the first type of passive element and the second type of passive element are connected, and the first direction is a direction parallel to the surface of the substrate.

[0008] Optionally, the first type of passive element includes: a first electrode located in a first area on one side of the substrate; a first dielectric layer located on the side of the first electrode away from the substrate; and a second electrode located on the side of the first dielectric layer away from the substrate.

[0009] Optionally, the second type of passive element includes: a first inductor layer located in a second area on one side of the substrate; wherein, the first inductor layer includes at least two inductor areas spaced apart in the first direction, and at least one inductor area is connected to the first type of passive element; a first metal support structure, the first metal support structure includes a plurality of support units spaced apart in the first direction; wherein, at least one support unit is located between adjacent inductor areas in a non-contact manner and covers a partial surface of the substrate, and at least part of the support units are respectively located on the side of each inductor area away from the substrate; a second dielectric layer located on the side of the first metal support structure away from the substrate, the second dielectric layer exposes a partial surface of at least part of the support units; and a second inductor layer located on the side of the second dielectric layer away from the substrate, the second inductor layer covers the exposed surfaces of the plurality of support units.

[0010] Optionally, the first inductor layer includes a first inductor area and a second inductor area spaced apart in the first direction, and the first inductor area is connected to the first type of passive element; the first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart in the first direction; wherein, the first support unit is located on the side of the first inductor area away from the substrate, the second support unit is located between the first inductor area and the second inductor area in a non-contact manner and covers a partial surface of the substrate, the third support unit is located on the side of the second inductor area away from the substrate; and the second dielectric layer exposes a partial surface of the first support unit and a partial surface of the third support unit.

[0011] Optionally, the integrated passive device further includes: a second metal support structure located on one side of the substrate, the second metal support structure is connected to the first type of passive element and the second type of passive element; and a conductive connection structure located on the side of the second metal support structure away from the substrate.

[0012] Optionally, the second metal support structure includes: a fourth support unit located in a third region on one side of the substrate, the fourth support unit being connected to the first type of passive component; and a fifth support unit located in a fourth region on one side of the substrate, the fifth support unit being connected to the second type of passive component.

[0013] Optionally, the first type of passive component includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on a side of the first electrode away from the substrate; and a second electrode located on a side of the first dielectric layer away from the substrate; and in the first direction, the fourth support unit is isolated from the first type of passive component by an air dielectric; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode.

[0014] Optionally, the second type of passive component includes at least two layers of inductors, and the fifth support unit is only connected to the inductor disposed on the surface of the substrate in the second type of passive component.

[0015] Optionally, the conductive connection structure includes: a first conductive connector located on a side of the fourth support unit away from the substrate; and a second conductive connector located on a side of the fifth support unit away from the substrate.

[0016] Optionally, the second type of passive component further includes: a third dielectric layer located on a side of the second inductor layer away from the substrate and exposing a partial surface of the second inductor layer; and a third inductor layer located on a side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

[0017] According to another aspect of the embodiments of the present disclosure, there is also provided a method for manufacturing an integrated passive device, including: manufacturing a substrate; and manufacturing a first type of passive component and a second type of passive component arranged along a first direction on one side of the substrate; wherein, the first type of passive component and the second type of passive component are connected, and the first direction is a direction parallel to the surface of the substrate.

[0018] Optionally, the process of fabricating the first type of passive component includes: fabricating a first electrode, a first dielectric layer, and a second electrode; wherein, the first electrode is located in a first region on one side of the substrate, the first dielectric layer is located on the side of the first electrode away from the substrate, and the second electrode is located on the side of the first dielectric layer away from the substrate; and the process of fabricating the second type of passive component includes: fabricating a first inductive layer, a first metal support structure, a second dielectric layer, and a second inductive layer; wherein, the first inductive layer is located in a second region on one side of the substrate, the first inductive layer includes at least two inductive regions spaced apart along the first direction, and at least one inductive region is connected to the first type of passive component; the first metal support structure includes a plurality of support units spaced apart along the first direction; wherein, at least one support unit is located between adjacent inductive regions in a non-contact manner and covers a partial surface of the substrate, and at least part of the support units are respectively located on the side of each inductive region away from the substrate; the second dielectric layer is located on the side of the first metal support structure away from the substrate and exposes a partial surface of at least part of the support units; and the second inductive layer is located on the side of the second dielectric layer away from the substrate, and the second inductive layer covers the exposed surfaces of the plurality of support units.

[0019] Optionally, the process of fabricating the first inductive layer includes: fabricating a first inductive region and a second inductive region spaced apart along the first direction, and the first inductive region is connected to the first type of passive component; the process of fabricating the first metal support structure includes: fabricating a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein, the first support unit is located on the side of the first inductive region away from the substrate, the second support unit is located between the first inductive region and the second inductive region in a non-contact manner and covers a partial surface of the substrate, and the third support unit is located on the side of the second inductive region away from the substrate; and the second dielectric layer exposes a partial surface of the first support unit and a partial surface of the third support unit.

[0020] Optionally, the manufacturing method further includes: fabricating a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive component and the second type of passive component; and fabricating a conductive connection structure located on the side of the second metal support structure away from the substrate; the process of fabricating the second metal support structure includes: fabricating a fourth support unit in a third region on one side of the substrate, the fourth support unit being connected to the first type of passive component; and fabricating a fifth support unit in a fourth region on one side of the substrate, the fifth support unit being connected to the second type of passive component.

[0021] Optionally, the process of fabricating the first type of passive component includes: fabricating a first electrode in a first region on one side of the substrate; fabricating a first dielectric layer on a side of the first electrode away from the substrate; and fabricating a second electrode on a side of the first dielectric layer away from the substrate; and in the first direction, the fourth support unit and the first type of passive component are isolated by an air medium; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode; the second type of passive component includes at least two layers of inductors, and the fifth support unit is only connected to the inductor disposed on the substrate surface in the second type of passive component; the process of fabricating the conductive connection structure includes: fabricating a first conductive connector on a side of the fourth support unit away from the substrate; and fabricating a second conductive connector on a side of the fifth support unit away from the substrate.

[0022] Optionally, the process of fabricating the second type of passive component further includes: fabricating a third dielectric layer on a side of the second inductor layer away from the substrate and exposing a partial surface of the second inductor layer; and fabricating a third inductor layer on a side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

[0023] In the integrated passive device and its manufacturing method proposed in this application, by changing the vertical stacking of passive components deposited on the substrate in the integrated passive device to a horizontal arrangement layout (arranged in a first direction parallel to the substrate surface), innovation at the architecture level is achieved. Specifically, by horizontally arranging various passive components on the substrate surface, at least one dielectric layer is reduced in use (i.e., the dielectric layer between passive components is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of the dielectric material are reduced, thereby improving the inductance Q value and the self-resonant frequency, and ultimately improving the device performance. Furthermore, the technical problem in the prior art that the integrated passive device uses a vertical stacking architecture to arrange various passive components, resulting in poor device performance stability due to the introduction of interlayer parasitic capacitance and high-frequency loss by multiple dielectric layers, is solved. Description of the Drawings

[0024] The drawings described herein are used to provide a further understanding of the present disclosure, and constitute a part of this application. The schematic embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure. In the drawings: Figure 1 It is a schematic structural diagram in the manufacturing process of the integrated passive device provided by the first embodiment of this application; Figure 2 It is another schematic structural diagram in the manufacturing process of the integrated passive device provided by the first embodiment of this application; Figure 3 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 4 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 5 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 6 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 7 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 8 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 9 Another structural schematic diagram in the manufacturing process of the integrated passive device provided by the first embodiment of the present application; Figure 10 Structural schematic diagram of the integrated passive device provided by the second embodiment of the present application; Figure 11 Structural schematic diagram of the integrated passive device provided by the third embodiment of the present application; Figure 12 Structural schematic diagram of the integrated passive device provided by the fourth embodiment of the present application. Detailed implementation manners

[0025] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0026] It should be noted that the terms "first", "second", etc. in the description, claims and the above drawings of the present disclosure are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] Secondly, the present application will be described in detail with reference to schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0028] As described in the background art section, the existing integrated passive devices generally adopt the technical path of vertically stacking passive components on one side surface of the substrate. However, this vertical stacking architecture has the following technical bottlenecks: (1) The introduction of multiple dielectric layers inevitably generates interlayer parasitic capacitance, the value of which is proportional to the dielectric constant of the dielectric layer and the overlapping area of the electrodes, resulting in a significant downward shift of the inductance self-resonant frequency and a reduction in the quality factor (Q value), affecting the performance stability of the device; (2) In high-frequency scenarios such as millimeter waves, the polarization loss (caused by dipole rotation lag) and leakage conductance loss (caused by the conductivity of the material) of the dielectric material increase sharply, resulting in device temperature rise, which may cause risks such as inductive metal migration and dielectric breakdown of the capacitor, further affecting the performance stability of the device.

[0029] In view of this, the embodiments of the present application provide an integrated passive device and a manufacturing method thereof. By changing the vertical stacking of the passive components deposited on the substrate in the integrated passive device to a horizontal arrangement layout (arranged in a first direction parallel to the substrate surface), innovation at the architecture level is achieved. Specifically, by horizontally arranging various passive components on the substrate surface, at least one dielectric layer is reduced (i.e., the dielectric layer between the passive components is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of the dielectric material are reduced, thereby improving the inductance Q value and the self-resonant frequency, and ultimately improving the device performance. Furthermore, it solves the technical problem that the integrated passive device in the prior art uses a vertical stacking architecture to arrange various passive components, resulting in poor device performance stability due to the introduction of interlayer parasitic capacitance and high-frequency loss by multiple dielectric layers.

[0030] The following describes the integrated passive device and its manufacturing method provided by the embodiments of the present application in combination with specific embodiments.

[0031] Embodiment 1 For ease of understanding, the manufacturing method of the integrated passive device is first described in the present application. The manufacturing method of the integrated passive device provided by the embodiments of the present application includes: As Figure 1 shown, a sacrificial layer 110 is formed on one side of a substrate 100 used as a carrier, and the sacrificial layer exposes the surfaces of multiple regions of the substrate 100. Optionally, the material of the sacrificial layer 110 can be SiO2, PSG, USG, a-Si, photoresist, etc.; the forming process of the sacrificial layer 110 can be PVD, CVD, spin coating, etc.

[0032] Optionally, taking the material of the sacrificial layer 110 as photoresist as an example, the process of manufacturing the sacrificial layer 110 is as follows: Photoresist is coated on one side of the substrate 100, that is, the photoresist is coated on the surface of one side of the substrate 100 to form a photosensitive film. Then, the photoresist is exposed, specifically, selectively irradiated with ultraviolet light or other light sources to initiate a photochemical reaction. After that, a chemical solvent (such as a developer) is used to dissolve the exposed part of the photoresist to form the required physical pattern, and the sacrificial layer 110 is obtained.

[0033] Optionally, in an embodiment of the present application, the substrate 100 is a silicon substrate, a silicon-on-insulator substrate, a glass substrate, a silicon carbide substrate, a gallium arsenide (GaAs) substrate, etc.

[0034] As Figure 2 shown, a first metal layer 120 is deposited on the area of the substrate 100 where no photoresist is coated, and chemical mechanical planarization is performed on the surface of the first metal layer 120. Among them, the first metal layer 120 is used for the first electrode in the subsequent manufacturing of the capacitor structure, the first inductance layer in the double-layer inductance structure, and a part of the support structure.

[0035] Optionally, in an embodiment of the present application, the first metal layer 120 can be an Al layer, a Cu layer, a Mo layer, an Au layer, or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process.

[0036] As Figure 3As shown, the first region of the first metal layer 120 is made into the first electrode 122, and the second region of the first metal layer 120 is made into the first inductor layer. Among them, the first inductor layer includes at least two inductor regions (such as the first inductor region 123 and the second inductor region 125) that are spaced apart along the first direction, and at least one inductor region (such as the first inductor region 123) is connected to the first electrode 122. The first direction is the direction parallel to the surface of the substrate 100. The remaining region of the first metal layer 120 serves as part of the metal support structure (that is, part of a plurality of support units spaced apart along the first direction), for example, including part of the fourth support unit (the first support part 121, the third region on one side of the substrate 100), part of the second support unit (the second support part 124), and part of the fifth support unit (the third support part 126, the fourth region on one side of the substrate 100). Among them, at least one support unit (such as the second support unit) is located between adjacent inductor regions (that is, the first inductor region 123 and the second inductor region 125) in a non-contact manner and covers part of the surface of the substrate 100.

[0037] Optionally, the process of making the first region of the first metal layer 120 into the first electrode 122 includes the following steps: On the surface of the first region of the first metal layer 120, a layer of photoresist is evenly coated, and then ultraviolet light or other suitable light sources are used to selectively irradiate the photoresist through a pre-made mask. The pattern of the first electrode 122 is defined on the mask. During the exposure process, the pattern on the mask is accurately projected onto the photoresist, triggering a photochemical reaction.

[0038] After exposure, the exposed photoresist is processed using a chemical solvent (such as a developer). The developer can dissolve the exposed part of the photoresist, while the unexposed part of the photoresist remains, thus forming a photoresist pattern corresponding to the mask pattern, that is, the pattern of the first electrode 122.

[0039] After development, a chemical etchant or a physical etching method (such as plasma etching) is used to etch the first region of the first metal layer 120. During the etching process, the unprotected part of the metal layer is removed, while the part protected by the photoresist remains, forming the pattern of the first electrode 122.

[0040] After etching is completed, a specific solvent or method is used to remove the residual photoresist, exposing the patterned first electrode 122.

[0041] Through the above steps, the first region of the first metal layer 120 is accurately made into the first electrode 122, laying the foundation for subsequent semiconductor device manufacturing.

[0042] Optionally, the process of fabricating the second region of the first metal layer 120 into the first inductive layer is substantially the same as that of fabricating the first electrode 122, except that the pattern of the first inductive layer is defined on the mask.

[0043] As Figure 4 shown, a first dielectric layer 130 is formed on the side of the first electrode 122 away from the substrate 100. Optionally, the forming process of the first dielectric layer 130 is a deposition process, specifically, it can be PVD or CVD, etc. The material of the first dielectric layer 130 can be SiO2, SiNx or AlN, etc. This application does not make a limitation on this, and it depends on the specific situation.

[0044] It should be noted that in the embodiment of this application, the first dielectric layer 130 is a protective layer of the first electrode 122 to prevent the first electrode 122 from being oxidized. Optionally, the first dielectric layer 130 also serves as the dielectric layer of the capacitor formed subsequently.

[0045] Continuing as Figure 4 shown, a second electrode 140 is fabricated on the surface of the first dielectric layer 130 away from the substrate 100. The first electrode 122, the first dielectric layer 130 and the second electrode 140 form a capacitor (i.e., the first type of passive component). Optionally, the material of the second electrode 140 can be Al, Cu, Mo, Au or Pt, etc. This application does not make a limitation on this, and it depends on the specific situation.

[0046] As Figure 5 shown, a second metal layer 150 is deposited on the first metal layer 120 and the second electrode 140. The second metal layer 150 serves as a metal support structure. Specifically, metal is deposited on the first support part 121, on the second electrode 140, on the first inductive region 123, on the second support part 124, on the second inductive region 125 and on the third support part 126, so as to form the second metal layer 150. Among them, the region of the second metal layer 150 located on the first inductive region 123 forms a first support unit, the region of the second metal layer 150 located on the second support part 124 and the second support part 124 form a second support unit, and the region of the second metal layer 150 located on the second inductive region 125 forms a third support unit. And the first support unit, the second support unit and the third support unit form a first metal support structure.

[0047] Optionally, the second metal layer 150 can be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process.

[0048] Optionally, there is a gap in the first direction between the region of the second metal layer 150 located on the second inductance region 125 and the region located on the third support portion 126, laying a foundation for the subsequent fifth support unit to be only connected to the inductance disposed on the surface of the substrate 100 in the second type of passive component, that is, the fifth support unit is only connected to the second inductance region 125 in the second type of passive component, rather than the second inductance layer 170 in the second type of passive component. This way of only connecting to the second inductance region 125 makes the inductance trace longer compared to the way that the fifth support unit is connected to both the second inductance region 125 and the second inductance layer 170, improving the inductance value of the second type of passive component.

[0049] Continue as Figure 5 shown, continue to deposit a sacrificial material on the basis of the sacrificial layer 110 so that the sacrificial layer 110 fills the voids between the structures.

[0050] As Figure 6 shown, a second dielectric layer 160 is formed on the side of the first support unit, the second support unit, and the third support unit away from the substrate 100, and the second dielectric layer 160 exposes part of the surfaces of the first support unit and the third support unit.

[0051] Optionally, the formation process of the second dielectric layer 160 is a deposition process, specifically, it can be PVD or CVD, etc., and the material of the second dielectric layer 160 can be SiO2, SiNx, or AlN, etc. The present application does not limit this, and it depends on the specific situation.

[0052] Optionally, there is a difference between the material of the second dielectric layer 160 and the material of the first dielectric layer 130. For example, when the material of the first dielectric layer 130 is SiO2, the material of the second dielectric layer 160 can be SiNx.

[0053] It should be noted that in the embodiment of the present application, the second dielectric layer 160 serves as the dielectric layer of the subsequent formed double-layer inductance structure (that is, the second type of passive component).

[0054] As Figure 7 shown, a second inductance layer 170 is deposited on the side of the second dielectric layer 160 away from the substrate 100, and the second inductance layer 170 covers the exposed surfaces of the first support unit and the third support unit.

[0055] Continue as Figure 7As shown, a metal material is continuously deposited in the region of the second metal layer 150 located on the first support portion 121, and a metal material is continuously deposited in the region of the second metal layer 150 located on the third support portion 126, thereby forming a third metal layer 180. Among them, the region of the third metal layer 180 that overlaps with the first support portion 121 in the direction perpendicular to the surface of the substrate 100 (corresponding to the second direction) covers the support structure located on the second electrode 140 (i.e., the region of the second metal layer 150 located on the second electrode 140).

[0056] The region of the third metal layer 180 that overlaps with the first support portion 121 in the direction perpendicular to the surface of the substrate, the region of the second metal layer 150 located on the first support portion 121, the first support portion 121, and the support structure located on the second electrode 140 constitute a fourth support unit. The region of the third metal layer 180 that overlaps with the third support portion 126 in the direction perpendicular to the surface of the substrate, the region of the second metal layer 150 located on the third support portion 126, and the third support portion 126 constitute a fifth support unit. The fourth support unit and the fifth support unit constitute a second metal support structure.

[0057] Optionally, the third metal layer 180 can be an Al layer, a Cu layer, a Mo layer, an Au layer, or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process.

[0058] Continue as Figure 7 As shown, a sacrificial material is continuously deposited on the currently formed sacrificial layer 110, so that the sacrificial layer 110 fills the voids between the various structures.

[0059] As Figure 8 As shown, a first conductive connector 191 is fabricated on the side of the fourth support unit away from the substrate 100, and a second conductive connector 192 is fabricated on the side of the fifth support unit away from the substrate 100. The first conductive connector 191 and the second conductive connector 192 constitute a conductive connection structure. Optionally, the first conductive connector 191 and the second conductive connector 192 are solder or pad pins.

[0060] As Figure 9As shown, the sacrificial layer 110 is released to form a first air cavity, a second air cavity, and a third air cavity. Among them, the first air cavity is the area defined by the third support unit, the substrate 100, the first electrode 122, the first dielectric layer 130, the second electrode 140, and the support structure located on the second electrode 140. The second air cavity is the area defined by the substrate 100, the first inductance region 123, the first support unit, the second dielectric layer 160, and the second support unit. The third air cavity is the area defined by the substrate 100, the second support unit, the second dielectric layer 160, the third support unit, and the second inductance region 125.

[0061] Optionally, the sacrificial layer 110 is released by using a liquid-phase etching or gas-phase etching method, including: etching the sacrificial layer 110 by using a liquid-phase etching solution such as hydrofluoric acid solution (HF) or buffered oxide etchant (BOE); or, etching the sacrificial layer 110 by using gases such as gaseous hydrogen fluoride (HF) or xenon difluoride (XeF2).

[0062] In addition, the embodiments of the present application also provide an integrated passive device manufactured by using the manufacturing method provided in any of the above embodiments.

[0063] As Figure 9 shown, the integrated passive device provided by the embodiments of the present application includes: a substrate 100; and a first type of passive element and a second type of passive element arranged along a first direction on one side of the substrate 100; wherein, the first type of passive element is connected to the second type of passive element, and the first direction is a direction parallel to the surface of the substrate 100.

[0064] Optionally, the first type of passive element includes: a first electrode 122 located in a first area on one side of the substrate 100; a first dielectric layer 130 located on the side of the first electrode 122 away from the substrate; and a second electrode 140 located on the side of the first dielectric layer 130 away from the substrate 100.

[0065] Optionally, the second type of passive element includes: a first inductive layer located in a second region on one side of the substrate 100; wherein the first inductive layer includes at least two inductive regions spaced apart along the first direction, and at least one inductive region is connected to the first electrode 122; a first metal support structure, the first metal support structure including a plurality of support units spaced apart along the first direction; wherein at least one support unit is located between adjacent inductive regions in a non-contact manner and covers a partial surface of the substrate, and at least some of the support units are respectively located on one side of each inductive region away from the substrate; a second dielectric layer 160 located on one side of the first metal support structure away from the substrate 100, the second dielectric layer 160 exposing a partial surface of at least some of the support units; and a second inductive layer 170 located on one side of the second dielectric layer 160 away from the substrate 100, the second inductive layer 170 covering the exposed surfaces of the plurality of support units.

[0066] Optionally, the first inductive layer includes a first inductive region 123 and a second inductive region 125 spaced apart along the first direction, and the first inductive region 123 is connected to the first electrode 122; the first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein the first support unit is located on one side of the first inductive region 123 away from the substrate 100, the second support unit is located between the first inductive region 123 and the second inductive region 125 in a non-contact manner and covers a partial surface of the substrate 100, and the third support unit is located on one side of the second inductive region 125 away from the substrate 100; and the second dielectric layer 160 exposes a partial surface of the first support unit and a partial surface of the third support unit.

[0067] Optionally, the integrated passive device further includes: a second metal support structure located on one side of the substrate 100, the second metal support structure being connected to the first type of passive element and the second type of passive element; and a conductive connection structure located on one side of the second metal support structure away from the substrate.

[0068] Optionally, the second metal support structure includes: a fourth support unit located in a third region on one side of the substrate 100, the fourth support unit being connected to the first type of passive element; and a fifth support unit located in a fourth region on one side of the substrate 100, the fifth support unit being connected to the second type of passive element.

[0069] Optionally, the first type of passive component includes: a first electrode 122 located in a first region on one side of the substrate 100; a first dielectric layer 130 located on a side of the first electrode 122 away from the substrate 100; and a second electrode 140 located on a side of the first dielectric layer 130 away from the substrate 100; and in the first direction, the fourth support unit and the first type of passive component are isolated by an air dielectric; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode 140.

[0070] Optionally, the second type of passive component includes at least two layers of inductors, and the fifth support unit is only connected to the inductor disposed on the surface of the substrate 100 in the second type of passive component.

[0071] Optionally, the conductive connection structure includes: a first conductive connector 191, the first conductive connector 191 is located on a side of the fourth support unit away from the substrate 100; and a second conductive connector 192, the second conductive connector 192 is located on a side of the fifth support unit away from the substrate 100.

[0072] It should be noted that since the detailed structure of the integrated passive device has been described in detail in the manufacturing method of the integrated passive device, it will not be elaborated here.

[0073] In summary, in the integrated passive device and its manufacturing method proposed in this application, by changing the passive components deposited on the substrate in the integrated passive device from vertical stacking to horizontal arrangement (arranged in a first direction parallel to the surface of the substrate), innovation at the architecture level is achieved. Specifically, by horizontally arranging various passive components on the surface of the substrate, at least one dielectric layer is reduced in use (i.e., the dielectric layer between passive components is reduced), and by reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of the dielectric material are reduced, thereby improving the inductance Q value and the self-resonant frequency, and ultimately improving the device performance. Furthermore, the technical problem that the integrated passive device in the prior art uses a vertical stacking architecture to arrange various passive components, resulting in poor device performance stability due to the introduction of interlayer parasitic capacitance and high-frequency loss by multiple dielectric layers is solved.

[0074] Embodiment 2 The inventive concept in this embodiment is basically the same as that in Embodiment 1, except that in this inventive concept, as Figure 10 shown, the first conductive connector 191 and the second conductive connector 192 are bonding wires.

[0075] Embodiment 3 The inventive concept in this embodiment is basically the same as that in Embodiment 1, except that in this inventive concept, as Figure 11As shown, the second type of passive component further includes: a third dielectric layer 200, which is located on the side of the second inductor layer 170 away from the substrate 100 and exposes a part of the surface of the second inductor layer 170; and a third inductor layer 210, which is located on the side of the third dielectric layer 200 away from the substrate 100 and covers the exposed surface of the second inductor layer 170. The integrated passive device further includes a fourth metal layer 220, which includes three parts. The first part is located between the fourth support unit and the first conductive connection 191, the second part is the third inductor layer 210, and the third part is located between the fifth support unit and the second conductive connection 192.

[0076] Specifically, on the basis of Embodiment 1 Figure 7 a third dielectric layer 200 is fabricated on the side of the second inductor layer 170 away from the substrate 100. Optionally, the forming process of the third dielectric layer 200 is a deposition process, specifically, it can be PVD or CVD, etc. The material of the third dielectric layer 200 can be SiO2, SiNx, or AlN, etc. This application does not make a limitation on this, and it depends on the specific situation.

[0077] Optionally, the material of the third dielectric layer 200 is different from that of the first dielectric layer 130, and the material of the third dielectric layer 200 can be the same as that of the second dielectric layer 160. For example, when the material of the first dielectric layer 130 is SiO2, the materials of the second dielectric layer 160 and the third dielectric layer 200 are SiNx.

[0078] Then, a metal material is continuously deposited on the fourth support unit, the third dielectric layer 200, and the fifth support unit, so as to form the fourth metal layer 220. Among them, the fourth metal layer 220 includes three parts. The first part covers the fourth support unit and is used as a support structure. The second part is located on the side of the third dielectric layer 200 away from the substrate 100 and covers the exposed surface of the second inductor layer 170, and the second part is fabricated into the third inductor layer 210. The third part covers the fifth support unit and is used as a support structure.

[0079] Optionally, the fourth metal layer 220 can be an Al layer, a Cu layer, a Mo layer, an Au layer, or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process.

[0080] Next, on the basis of the currently formed sacrificial layer 110, a sacrificial material is continuously deposited so that the sacrificial layer 110 fills the gaps between the structures.

[0081] Subsequently, a first conductive connector 191 is fabricated on a side of a first portion of the fourth metal layer 220 away from the substrate 100, and a second conductive connector 192 is fabricated on a side of a third portion of the fourth metal layer 220 away from the substrate 100.

[0082] Finally, the sacrificial layer 110 is released, thereby obtaining the Figure 11 integrated passive device as described above.

[0083] Embodiment 4 The inventive solution in this embodiment is basically the same as that in Embodiment 3, except that in the inventive solution, as Figure 12 shown, the first conductive connector 191 and the second conductive connector 192 are bonding wires.

[0084] In summary, in the integrated passive device and its manufacturing method proposed in this application, the integrated passive device includes a substrate; and a first type of passive element and a second type of passive element located on one side of the substrate and arranged along a first direction; wherein, the first type of passive element and the second type of passive element are connected, and the first direction is a direction parallel to the surface of the substrate. By changing the passive elements deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement layout (arranged along a first direction parallel to the surface of the substrate), an innovation at the architecture level is achieved. Specifically, by horizontally arranging various passive elements on the surface of the substrate, at least one dielectric layer is reduced in use (i.e., the dielectric layer between passive elements is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of the dielectric material are reduced, thereby improving the inductance Q value and the self-resonant frequency, and ultimately improving the device performance. Furthermore, the technical problem in the prior art that the integrated passive device uses a vertical stack architecture to arrange various passive elements, resulting in poor device performance stability due to the introduction of interlayer parasitic capacitance and high-frequency loss by multiple dielectric layers is solved.

[0085] Each part in this specification is described in a progressive manner. The key points of each part are the differences from other parts. For the same and similar parts among each part, reference can be made to each other.

[0086] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated passive device, characterized in that, Comprising: A substrate; And a first type of passive element and a second type of passive element located on one side of the substrate and arranged along a first direction; wherein, the first type of passive element and the second type of passive element are connected, and the first direction is a direction parallel to the surface of the substrate.

2. The integrated passive device according to claim 1, wherein The first type of passive element includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on the side of the first electrode away from the substrate; and a second electrode located on the side of the first dielectric layer away from the substrate.

3. The integrated passive device according to claim 1, characterized in that The second type of passive element includes: A first inductance layer located in a second region on one side of the substrate; wherein, the first inductance layer includes at least two inductance regions spaced apart along the first direction, and at least one inductance region is connected to the first type of passive element; A first metal support structure, the first metal support structure includes a plurality of support units spaced apart along the first direction; wherein, at least one support unit is located between adjacent inductance regions in a non-contact manner and covers a partial surface of the substrate, and at least part of the support units are respectively located on the side of each inductance region away from the substrate; A second dielectric layer located on the side of the first metal support structure away from the substrate, the second dielectric layer exposes a partial surface of at least part of the support units; and A second inductance layer located on the side of the second dielectric layer away from the substrate, the second inductance layer covers the exposed surfaces of the plurality of support units.

4. The integrated passive device according to claim 3, characterized in that, The first inductance layer includes a first inductance region and a second inductance region spaced apart along the first direction, and the first inductance region is connected to the first type of passive element; The first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein, the first support unit is located on the side of the first inductance region away from the substrate, the second support unit is located between the first inductance region and the second inductance region in a non-contact manner and covers a partial surface of the substrate, and the third support unit is located on the side of the second inductance region away from the substrate; and The second dielectric layer exposes a partial surface of the first support unit and a partial surface of the third support unit.

5. The integrated passive device according to claim 1, wherein Further comprising: A second metal support structure located on one side of the substrate, the second metal support structure is connected to the first type of passive element and the second type of passive element; And A conductive connection structure located on the side of the second metal support structure away from the substrate.

6. The integrated passive device according to claim 5, characterized in that, The second metal support structure includes: A fourth support unit located in a third region on one side of the substrate, the fourth support unit is connected to the first type of passive element; and A fifth support unit located in a fourth region on one side of the substrate, the fifth support unit is connected to the second type of passive element.

7. The integrated passive device according to claim 6, wherein, The first type of passive element includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on the side of the first electrode away from the substrate; and a second electrode located on the side of the first dielectric layer away from the substrate; and In the first direction, the fourth support unit and the first type of passive element are isolated by an air medium; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode.

8. The integrated passive device according to claim 6, wherein The second type of passive element includes at least two layers of inductors, and the fifth support unit is only connected to the inductor disposed on the substrate surface in the second type of passive element.

9. The integrated passive device according to claim 6, wherein, The conductive connection structure includes: A first conductive connector, the first conductive connector being located on a side of the fourth support unit away from the substrate; and A second conductive connector, the second conductive connector being located on a side of the fifth support unit away from the substrate.

10. The integrated passive device according to claim 3, characterized in that, The second type of passive element further includes: A third dielectric layer, the third dielectric layer being located on a side of the second inductor layer away from the substrate and exposing a partial surface of the second inductor layer; and A third inductor layer, the third inductor layer being located on a side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

11. A manufacturing method of an integrated passive device, characterized in that Comprising: Fabricating a substrate; and fabricating a first type of passive element and a second type of passive element arranged along a first direction on one side of the substrate; wherein, the first type of passive element and the second type of passive element are connected, and the first direction is a direction parallel to the substrate surface.

12. The manufacturing method according to claim 11, wherein The process of fabricating the first type of passive element includes: fabricating a first electrode, a first dielectric layer, and a second electrode; wherein, the first electrode is located in a first region on one side of the substrate, the first dielectric layer is located on a side of the first electrode away from the substrate, and the second electrode is located on a side of the first dielectric layer away from the substrate; and The process of fabricating the second type of passive element includes: fabricating a first inductor layer, a first metal support structure, a second dielectric layer, and a second inductor layer; wherein, the first inductor layer is located in a second region on one side of the substrate, the first inductor layer includes at least two inductor regions spaced apart along the first direction, and at least one inductor region is connected to the first type of passive element; the first metal support structure includes a plurality of support units spaced apart along the first direction; wherein, at least one support unit is located between adjacent inductor regions in a non-contact manner and covers a partial surface of the substrate, and at least some of the support units are respectively located on a side of each inductor region away from the substrate; the second dielectric layer is located on a side of the first metal support structure away from the substrate and exposes a partial surface of at least some of the support units; and the second inductor layer is located on a side of the second dielectric layer away from the substrate, and the second inductor layer covers the exposed surfaces of the plurality of support units.

13. The manufacturing method according to claim 12, characterized in that, The process of fabricating the first inductor layer includes: fabricating a first inductor region and a second inductor region spaced apart along the first direction, the first inductor region being connected to the first type of passive element; The process of fabricating the first metal support structure includes: fabricating a first support unit, a second support unit, and a third support unit that are spaced apart along the first direction; wherein, the first support unit is located on the side of the first inductance region away from the substrate, the second support unit is located between the first inductance region and the second inductance region in a non-contact manner and covers a partial surface of the substrate, and the third support unit is located on the side of the second inductance region away from the substrate; and the second dielectric layer exposes a partial surface of the first support unit and a partial surface of the third support unit.

14. The manufacturing method according to claim 11, characterized in that, This fabrication method further includes: fabricating a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive component and the second type of passive component; and fabricating a conductive connection structure located on the side of the second metal support structure away from the substrate; The process of fabricating the second metal support structure includes: fabricating a fourth support unit in a third region located on one side of the substrate, the fourth support unit being connected to the first type of passive component; and fabricating a fifth support unit in a fourth region located on one side of the substrate, the fifth support unit being connected to the second type of passive component.

15. The manufacturing method according to claim 14, wherein, The process of fabricating the first type of passive component includes: fabricating a first electrode in a first region located on one side of the substrate; fabricating a first dielectric layer on the side of the first electrode away from the substrate; and fabricating a second electrode on the side of the first dielectric layer away from the substrate; and In the first direction, the fourth support unit is isolated from the first type of passive component by an air medium; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode; The second type of passive component includes at least two layers of inductors, and the fifth support unit is only connected to the inductor provided on the substrate surface in the second type of passive component; The process of fabricating the conductive connection structure includes: fabricating a first conductive connector located on the side of the fourth support unit away from the substrate; and fabricating a second conductive connector located on the side of the fifth support unit away from the substrate.

16. The manufacturing method according to claim 13, characterized in that, The process of fabricating the second type of passive component further includes: fabricating a third dielectric layer located on the side of the second inductor layer away from the substrate and exposing a partial surface of the second inductor layer; and fabricating a third inductor layer located on the side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

Images