Manufacturing method and device of ER193 type dual differential comparator circuit

Abstract

The present invention provides a method and device for manufacturing an ER193 dual differential comparator circuit, belonging to the field of semiconductor manufacturing technology. The method for manufacturing the ER193 dual differential comparator circuit in an embodiment of the present invention ensures that epitaxial layer drift is corrected during the upper isolation photolithography process by adjusting the isolation photolithography position of the wafer. Even if the epitaxial layer drifts, the photolithography pattern can still be accurately formed on the wafer, avoiding poor circuit function or inconsistent electrical performance due to alignment errors.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method and device of an ER193 type dual differential comparator circuit. Background Art

[0002] The ER193 dual differential comparator circuit utilizes a bipolar process, primarily referring to its use of bipolar transistors as its basic components. This process offers high switching speed and gain, making it suitable for high-frequency and high-precision applications. Dual differential comparators compare two input signals and output a signal representing the relationship between them, commonly used in signal processing and conversion. Compared to other processes, bipolar processes offer superior signal amplification and response speed, making them suitable for high-speed signal processing. Due to these characteristics, the ER193 circuit is widely used in fields such as analog-to-digital conversion, data acquisition, and high-frequency communications.

[0003] The ER193 dual-differential comparator circuit typically utilizes a bipolar process. Unidirectional isolation requires a long, high-temperature process, which reduces the lifespan of the furnace tube. Furthermore, the growth characteristics of the epitaxial structure cause the buried layer pattern to drift within the epitaxial layer, which can compromise the process, resulting in zero breakdown voltage between islands and unsuccessful isolation. Summary of the Invention

[0004] The present invention provides a method and device for manufacturing an ER193 dual differential comparator circuit, which is used to solve the defect in the prior art that the electrical isolation of the ER193 dual differential comparator circuit is easily invalidated, and achieve the effect of normal circuit function.

[0005] The present invention provides a method for manufacturing an ER193 dual differential comparator circuit, comprising:

[0006] After the wafer is subjected to lower isolation processing, it is determined that the surface oxide layer of the wafer is removed;

[0007] Determining that an epitaxial layer is formed on the wafer and performing upper isolation oxidation on the wafer;

[0008] When performing upper isolation lithography, determining and adjusting the isolation lithography position of the wafer to correct epitaxial layer drift;

[0009] It is determined to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0010] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, adjusting the isolation photolithography position of the wafer to correct the epitaxial layer drift includes:

[0011] When the alignment parameters of the lithography machine for performing upper isolation lithography are in an adjustable state, the alignment parameters of the lithography machine are adjusted based on the drift direction and size of the epitaxial layer on the wafer.

[0012] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, adjusting the alignment parameters of a lithography machine based on the drift direction and size of the epitaxial layer on the wafer includes:

[0013] The alignment parameters of the lithography machine are adjusted to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by the length of the thickness of the epitaxial layer.

[0014] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, adjusting the isolation photolithography position of the wafer to correct the epitaxial layer drift includes:

[0015] When the alignment parameters of the lithography machine performing upper isolation lithography are in an unadjustable state, based on the drift direction and size of the epitaxial layer on the wafer, the etch mark of the etched isolation area in the layout used for upper isolation lithography is determined to deviate from the target offset direction by the target offset amount.

[0016] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, the target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the thickness of the epitaxial layer.

[0017] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, after the wafer is subjected to lower isolation processing and before determining to remove the surface oxide layer of the wafer, the method further includes:

[0018] Determining to perform buried layer oxidation on the wafer;

[0019] After the buried layer is oxidized, it is determined that the wafer is subjected to arsenic implantation and arsenic annealing respectively;

[0020] It is determined to perform lower isolation oxidation, lower isolation photolithography, lower isolation implantation and lower isolation annealing on the wafer respectively.

[0021] According to a method for manufacturing an ER193 dual differential comparator circuit provided by the present invention, after determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift, the method includes:

[0022] Determining to perform base oxidation, base pre-expansion, borosilicate glass removal, and base re-diffusion on the wafer;

[0023] Determining to perform emitter region photolithography, emitter region pre-diffusion, phosphosilicate glass removal, and emitter region re-diffusion on the wafer;

[0024] Determine to perform lead hole photolithography and metal sputtering on the wafer.

[0025] The present invention also provides a manufacturing device for an ER193 dual differential comparator circuit, comprising:

[0026] The first processing module is used to determine whether to remove the surface oxide layer of the wafer after the wafer undergoes lower isolation processing;

[0027] A second processing module is used for determining that an epitaxial layer is formed on the wafer and performing upper isolation oxidation on the wafer;

[0028] A third processing module is used to determine and adjust the isolation lithography position of the wafer to correct the epitaxial layer drift when performing upper isolation lithography;

[0029] The fourth processing module is used to determine whether to perform pre-diffusion and re-diffusion on the wafer after the epitaxial layer drift is corrected, so as to obtain a target circuit on the wafer.

[0030] The present invention further provides an ER193 type dual differential comparator circuit, wherein the ER193 type dual differential comparator circuit is manufactured by adopting any of the manufacturing methods of the ER193 type dual differential comparator circuit.

[0031] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for manufacturing the ER193 type dual differential comparator circuit described above is implemented.

[0032] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for manufacturing the ER193 dual differential comparator circuit as described above is implemented.

[0033] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for manufacturing any one of the above-mentioned ER193 dual differential comparator circuits is implemented.

[0034] The manufacturing method and device of the ER193 dual differential comparator circuit provided by the present invention ensure that epitaxial layer drift is corrected during the upper isolation photolithography process by adjusting the isolation photolithography position of the wafer. Even if the epitaxial layer drifts, the photolithography pattern can still be accurately formed on the wafer, avoiding poor circuit function or inconsistent electrical performance due to positioning errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 This is one of the flow charts of the manufacturing method of the ER193 type dual differential comparator circuit provided by the present invention;

[0037] Figure 2 This is the second flow chart of the manufacturing method of the ER193 dual differential comparator circuit provided by the present invention;

[0038] Figure 3 It is a structural schematic diagram of a manufacturing device for the ER193 dual differential comparator circuit provided by the present invention;

[0039] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0041] The following combination Figure 1-Figure 4 The invention describes a method and device for manufacturing the ER193 dual differential comparator circuit.

[0042] The manufacturing method of the ER193 dual differential comparator circuit according to the embodiment of the present invention mainly includes step 110 , step 120 , step 130 and step 140 .

[0043] Step 110, after the wafer is subjected to lower isolation processing, determining to remove the surface oxide layer of the wafer;

[0044] Step 120 , determining whether an epitaxial layer is formed on the wafer and performing upper isolation oxidation on the wafer;

[0045] Step 130 , when performing upper isolation lithography, determining and adjusting the isolation lithography position of the wafer to correct epitaxial layer drift;

[0046] Step 140 , determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift, so as to obtain a target circuit on the wafer.

[0047] In this embodiment, the above steps are a series of process steps related to wafer processing during the semiconductor manufacturing process.

[0048] Wafer surface oxide removal is a process performed on the surface of a wafer, typically to remove the oxide layer (formed during previous process steps) to facilitate subsequent processing. Oxide removal is typically performed to ensure that subsequent processes (such as epitaxial growth and circuit design) are more precise and efficient.

[0049] In semiconductor manufacturing, oxide layers are often used for protection or electrical isolation, but they need to be removed in certain steps to allow for finer processing. For example, removing the oxide layer allows for other types of surface treatment or epitaxial growth.

[0050] The epitaxial layer formation and top isolation oxidation step on the wafer involves growing an epitaxial layer on the wafer surface. This epitaxial layer is typically formed through an epitaxial growth process and can be made of materials such as single crystal silicon. The epitaxial layer is formed to enhance the wafer's properties, such as improving electrical performance.

[0051] Epitaxial growth involves the regular arrangement and directional growth of atoms (or molecules) of a substance on a microfabricated crystal surface (generally referred to as a substrate) under certain conditions. The resulting epitaxial layer is a continuous, smooth, single-crystal layer that corresponds to the substrate's lattice structure. However, in the bipolar process used in integrated circuit manufacturing, growing epitaxial layers on single wafers introduces buried layer drift.

[0052] After epitaxial growth, a layer of oxidation treatment (upper isolation oxidation) is performed on the surface. This oxide layer can act as an isolation layer to prevent electrical interference between different regions, or be used in subsequent photolithography processes.

[0053] During epitaxial layer growth, factors such as temperature, material differences, and equipment deviations may cause the epitaxial layer to "drift" or become unevenly distributed. In these cases, photolithography position adjustments are necessary to ensure that the pattern placement during the photolithography process matches the actual distribution of the epitaxial layer to avoid errors.

[0054] For example, in the LM193 standard process, N-epitaxial growth is required on a P single crystal substrate. During the N-epitaxial growth, the pattern will drift, which is caused by the growth characteristics of the epitaxial layer.

[0055] Diffusion is the process of introducing dopants (such as boron and phosphorus) into the wafer. Pre-diffusion and re-diffusion are typically used to control the doping depth and concentration to ensure that the circuit characteristics meet the design requirements.

[0056] Typically, after epitaxial layer processing, a diffusion step is performed, perhaps to establish specific electrical properties on the wafer surface. Subsequent steps involve further diffusion or adjustments to dopant concentrations to ensure the final circuit's performance meets design requirements. Ultimately, these diffusion steps result in a target circuit with precise electrical characteristics.

[0057] The above steps refer to the process of precisely controlling the characteristics of the wafer surface through a series of process steps such as oxide layer removal, epitaxial growth, photolithography correction, and diffusion during the semiconductor manufacturing process, ultimately obtaining the target circuit that meets the design requirements.

[0058] In some embodiments, after performing the bottom isolation process on the wafer and before removing the surface oxide layer of the wafer, the manufacturing method of the ER193 dual differential comparator circuit further includes the following process.

[0059] It can be determined first to perform buried layer oxidation on the wafer; after the buried layer oxidation, it can be determined to perform arsenic implantation and arsenic annealing on the wafer; and it can be determined to perform lower isolation oxidation, lower isolation photolithography, lower isolation implantation and lower isolation annealing on the wafer.

[0060] The entire buried layer oxidation process has a total of 16 steps, and the process is as follows.

[0061] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0062] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0063] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0064] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0065] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0066] Step 6: Heat up for 64 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 64 minutes, the temperature required for the process, 1120°C, is reached.

[0067] Step 7: Dry oxygen for 5 minutes, temperature: 1120℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface and thus improve the barrier ability to impurities.

[0068] Step 8: DCE for 5 minutes at 1120°C and an oxygen flow rate of 8 L / min. A small amount of nitrogen is used to carry trichloroethylene (DCE) at a flow rate of 0.05 L / min. Chlorine-doped oxidation involves adding a certain amount of chlorine-containing gas, such as HCl or C2HCl3, to the oxidizing atmosphere. Chlorine-doped oxidation is a commonly used oxidation method that reduces sodium ion contamination in silica, inhibits oxide stacking faults, and improves the quality of the oxide film.

[0069] Step 9: Dry oxygen for 5 minutes, temperature: 1120℃, oxygen flow rate 8L / min, most heavy metal atoms react with chlorine to generate volatile gaseous chlorides which are discharged out of the furnace tube to ensure the purity of the oxide layer.

[0070] Step 10: Wet oxygen for 85 minutes at 1120°C, with an oxygen flow rate of 7 L / min and a hydrogen flow rate of 10 L / min. Wet oxygen is mainly used to form the required silicon dioxide film thickness to improve production efficiency. If used as a mask for impurity diffusion, its thickness is mainly determined by the junction depth formed by the diffusion and the diffusion temperature. In other words, the time required for diffusion must be determined first, and then the thickness of the oxide film required to block the diffusion of impurities in the silicon dioxide within this diffusion time must be determined.

[0071] Step 11: Dry oxygen for 5 minutes, temperature: 1120℃, oxygen flow rate 8L / min, most heavy metal atoms react with chlorine to generate volatile gaseous chlorides which are discharged out of the furnace tube to ensure the purity of the oxide layer.

[0072] Step 12: Cool down for 104 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0073] Step 13: After 15 minutes of unloading, when the temperature drops to the standby temperature, the equipment starts to unload.

[0074] Step 14: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the temperature is still high after leaving the boat, so the chip needs to be cooled down to a certain temperature before it can be removed.

[0075] Step 15: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0076] Step 16: The entire process is completed and the equipment is on standby.

[0077] The buried layer lithography process mainly includes HMDS, coating (negative photoresist with a thickness of 19000±2000Å), pre-baking (30 minutes), alignment, development, hardening (30 minutes), wet etching (oxide layer etching: using BOE solution for 10 minutes) and debonding (debonding solution for 10 minutes).

[0078] The implantation dose of arsenic As is 5E+15, and the detected sheet resistance value is 15±3Ω / sq.

[0079] The arsenic annealing process consists of the following 13 steps.

[0080] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0081] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0082] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0083] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0084] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0085] Step 6: Heating for 80 minutes. The temperature of the diffusion furnace increases by 5°C every 1 minute. After 80 minutes, the temperature required for the process, 1200°C, is reached.

[0086] Step 7: Dry oxygen for 60 minutes, temperature: 1200℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface, thereby improving the barrier ability to impurities.

[0087] Step 8: Push the junction with nitrogen for 300 minutes at 1200°C and a nitrogen flow rate of 8L / min for impurity diffusion. This time can achieve the required junction depth.

[0088] Step 9: Cool down for 114 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0089] Step 10: After 15 minutes of unloading, the temperature drops to the standby temperature and the device starts to unload.

[0090] Step 11: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled to a certain temperature before it can be removed.

[0091] Step 12: After 17 minutes in the boat, when the equipment is in standby mode, place the quartz boat in the furnace tube to keep it clean.

[0092] Step 13: The entire process is completed and the equipment is on standby.

[0093] After this, the isolation oxidation process is carried out, and the whole process has a total of 16 steps.

[0094] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0095] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0096] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0097] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0098] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0099] Step 6: Heat up for 58 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 58 minutes, the temperature required for the process, 1090°C, is reached.

[0100] Step 7: Dry oxygen for 5 minutes, temperature: 1090℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface, thereby improving the barrier ability to impurities.

[0101] Step 8: DCE for 5 minutes at 1090°C, with an oxygen flow rate of 8 L / min. A small amount of nitrogen was used to carry trichloroethylene (DCE) at a flow rate of 0.05 L / min. Chlorine-doped oxidation involves adding a certain amount of chlorine-containing gas, such as HCl or C2HCl3, to the oxidizing atmosphere. Chlorine-doped oxidation is a commonly used oxidation method that reduces sodium ion contamination in silica, inhibits oxide stacking faults, and improves the quality of the oxide film.

[0102] Step 9: Dry oxygen for 5 minutes, temperature: 1090℃, oxygen flow rate 8L / min, most heavy metal atoms react with chlorine to generate volatile gaseous chlorides which are discharged out of the furnace tube to ensure the purity of the oxide layer.

[0103] Step 10: Wet oxygen for 88 minutes at 1090°C, with an oxygen flow rate of 7 L / min and a hydrogen flow rate of 10 L / min. Wet oxygen is mainly used to form the required silicon dioxide film thickness to improve production efficiency. If used as a mask for impurity diffusion, its thickness is mainly determined by the junction depth formed by the diffusion and the diffusion temperature. In other words, the time required for diffusion must be determined first, and then the thickness of the oxide film required to block the diffusion of impurities in the silicon dioxide within this diffusion time must be determined.

[0104] Step 11: Dry oxygen for 5 minutes, temperature: 1090℃, oxygen flow rate 8L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the interface between silicon dioxide and silicon, and at the same time dry the silicon dioxide surface and improve the adhesion between silicon dioxide and photoresist.

[0105] Step 12: Cool down for 94 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0106] Step 13: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0107] Step 14: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the temperature is still high after leaving the boat, so the chip needs to be cooled down to a certain temperature before it can be removed.

[0108] Step 15: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0109] Step 16: The entire process is completed and the equipment is on standby.

[0110] The process of lower isolation lithography is HMDS, coating (negative photoresist is used, with a thickness of 19000±2000Å), pre-baking (30min), alignment, development, hardening (30min), wet etching (oxide layer etching: using BOE solution for 10min) and stripping (solvent for 10min).

[0111] The implantation dose of the lower isolation implant is 8E+14, and the sheet resistance detection value is 140±20Ω / sq.

[0112] The lower isolation annealing mainly includes the following steps.

[0113] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0114] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0115] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0116] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0117] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0118] Step 6: Heat up for 56 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 56 minutes, the temperature required for the process, 1080°C, is reached.

[0119] Step 7: Push the knot for 60 minutes. The depth of the knot formed by diffusion is determined by the diffusion temperature and time.

[0120] Step 8: Cool down for 94 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0121] Step 9: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0122] Step 10: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled to a certain temperature before it can be removed.

[0123] Step 11: After 17 minutes in the boat, when the equipment is in standby mode, place the quartz boat in the furnace tube to keep it clean.

[0124] Step 16: The entire process is completed and the equipment is on standby.

[0125] After this step, the surface oxide layer is removed and then epitaxial growth is carried out. The requirements of epitaxial growth are determined by the specific product characteristics, such as a width of 12±0.2μm.

[0126] The upper isolation oxidation process can be compared to the lower isolation oxidation process. The upper isolation lithography process includes: HMDS, photoresist coating (using negative photoresist with a thickness of 19000±2000Å), pre-baking (30 minutes), alignment, development, hardening (30 minutes), wet etching (oxidation layer etching: using BOE solution etching for 10 minutes), and stripping (debonding solution for 10 minutes).

[0127] During the photolithography process, ultraviolet light is irradiated through a mask onto the photoresist on the wafer. Through steps such as exposure and development, the pattern is transferred to the wafer surface. This pattern creates the circuit structure on the wafer.

[0128] When the epitaxial layer drifts, it may cause the position of the wafer surface to be misaligned with the designed pattern. To correct this, it is crucial to adjust the lithography position.

[0129] In some embodiments, in order to correct the offset caused by the drift of the epitaxial layer, it is necessary to align the positioning of the photolithographic pattern with the actual position of the epitaxial layer by fine-tuning the position of the mask.

[0130] In some embodiments, alignment marks are often used during the photolithography process to ensure that the photolithographic pattern is correctly aligned. If the epitaxial layer drifts, the positions of these alignment marks need to be recalibrated.

[0131] In some embodiments, the exposure time, exposure intensity or other process parameters may be adjusted to compensate for the effect of epitaxial layer drift on pattern positioning.

[0132] Correcting epitaxial layer drift by adjusting the photolithography position ensures accurate transfer of the photolithographic pattern to the wafer surface, avoiding pattern shift due to epitaxial layer drift, which could ultimately impact circuit functionality and performance. Upper isolation photolithography not only defines the circuit structure but also involves the precise positioning of electrical isolation regions. Uncorrected drift can compromise the integrity of these isolation regions, impacting proper circuit operation. Semiconductor manufacturing processes require extremely high precision and consistency. This position correction ensures high accuracy and stability throughout the manufacturing process, guaranteeing that the final product meets design specifications.

[0133] According to the manufacturing method of the ER193 dual differential comparator circuit provided by an embodiment of the present invention, by adjusting the isolation lithography position of the wafer, it is ensured that the drift of the epitaxial layer is corrected during the upper isolation lithography process. Even if the epitaxial layer drifts, the lithography pattern can still be accurately formed on the wafer, avoiding poor circuit function or inconsistent electrical performance due to positioning errors.

[0134] After photolithography, upper isolation pre-diffusion can be performed, which mainly includes the following steps.

[0135] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0136] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0137] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0138] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0139] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0140] Step 6: Heating for 44 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 56 minutes, the temperature required for the process, 1020°C, is reached.

[0141] Step 7: Diffusion for 14 minutes to diffuse the impurity source on the boron source sheet to the shallow junction formed on the wafer surface.

[0142] Step 8: Cool down for 74 minutes. The process is completed and the temperature should be reduced to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0143] Step 9: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0144] Step 10: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled to a certain temperature before it can be removed.

[0145] Step 11: After 17 minutes in the boat, when the equipment is in standby mode, place the quartz boat in the furnace tube to keep it clean.

[0146] Step 12: The entire process is completed and the equipment is on standby.

[0147] On this basis, isolation and re-diffusion can be carried out, which mainly includes the following processes.

[0148] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0149] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0150] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0151] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0152] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0153] Step 6: Heat up for 76 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 76 minutes, the temperature required for the process, 1180°C, is reached.

[0154] Step 7: Dry nitrogen for 200 minutes, temperature: 1180℃, nitrogen flow rate 8L / min. After a large number of tests, it takes 200 minutes to achieve complete isolation.

[0155] Step 8: Cool down for 34 minutes, isolation is completed, high temperature bonding is followed by low temperature production of silicon dioxide. Generally, the cooling rate is 3°C / min.

[0156] Step 9: Dry oxygen for 5 minutes, temperature: 1050℃, oxygen flow rate 8L / min, and pass oxygen into the furnace tube for 5 minutes before hydrogen and oxygen synthesis to ensure the gas atmosphere in the furnace tube and the safety of hydrogen and oxygen synthesis.

[0157] Step 10: Wet oxygen for 45 minutes, temperature 1050°C, oxygen flow rate 7L / min, hydrogen flow rate 10L / min. Wet oxygen is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency.

[0158] Step 11: Dry oxygen for 5 minutes, temperature: 1050℃, oxygen flow rate 8L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the interface between silicon dioxide and silicon, and at the same time dry the silicon dioxide surface, thereby improving the adhesion between silicon dioxide and photoresist.

[0159] Step 12: Cool down for 84 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0160] Step 13: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0161] Step 14: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the temperature is still high after leaving the boat, so the chip needs to be cooled down to a certain temperature before it can be removed.

[0162] Step 15: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0163] Step 16: The entire process is completed and the equipment is on standby.

[0164] In some embodiments, the isolation lithography position of the wafer is adjusted to correct the drift of the epitaxial layer, including: when the alignment parameters of the lithography machine performing the upper isolation lithography are in an adjustable state, adjusting the alignment parameters of the lithography machine based on the drift direction and size of the epitaxial layer on the wafer.

[0165] During the exposure process, a lithography machine must precisely align the designed pattern with existing structures on the wafer surface (such as epitaxial layers, oxide layers, and metal layers). This alignment is achieved through the alignment system within the lithography machine. Typically, a set of alignment marks is used to ensure the precise placement of the pattern on the wafer.

[0166] Alignment parameters refer to the settings and parameters used to control and adjust the alignment process in the lithography machine, mainly including position offset, rotation angle, and scaling factor.

[0167] The offset is the relative position between the alignment mark on the wafer and the photolithography mask pattern. The rotation angle is the relative rotation between the photolithography mask and the wafer. The scale factor is the degree to which the photolithography pattern is scaled on the wafer. These parameters determine whether the photolithography pattern can be accurately aligned with the existing structure on the wafer.

[0168] In some cases, the epitaxial layer may have drifted (e.g., shifted in a certain direction or had uneven thickness). This can cause misalignment between the lithographic pattern and the epitaxial layer. To correct this error, the alignment parameters of the lithography machine must be adjusted based on the direction and magnitude of the epitaxial layer drift.

[0169] In this embodiment, by measuring or estimating the direction and extent of epitaxial layer drift, it is possible to determine how to adjust alignment during the lithography process. For example, if the epitaxial layer shifts in a specific direction, the alignment system of the lithography machine can adjust the position of the alignment mark accordingly, realigning the lithographic pattern with the existing structure on the wafer.

[0170] The alignment system of a lithography machine is usually adjustable, meaning that the alignment parameters of the lithography machine can be adjusted manually or automatically to compensate for this deviation. For example, the offset in the X and Y directions or the rotation angle can be adjusted to correct the drift of the epitaxial layer.

[0171] On lithography machines with adjustable alignment parameters, the correction scheme is to compensate for drift by adjusting the machine's alignment parameters. Specifically, the direction and magnitude of the epitaxial layer's drift are known, so the drift of the epitaxial pattern can be corrected by adjusting the lithography machine's alignment (usually by shifting it left and right). This adjustment directly affects the lithography machine's alignment system, compensating for drift and ensuring that the pattern during the lithography process is aligned with the desired position. Since the amount of drift is typically the same as the thickness of the epitaxial layer, the drift effect can be eliminated by shifting the alignment to the left by a certain amount.

[0172] For example, the i9C lithography machine adjusts the alignment parameters during isolation lithography alignment, and offsets the data equivalent to the thickness of the epitaxial layer to the left, which can correct the buried layer drift effect.

[0173] When the epitaxial layer drifts, the alignment parameters of the lithography machine (such as position offset and rotation angle) must be adjusted to compensate for the drift in order to ensure that the pattern generated by the upper isolation lithography is accurately transferred to the wafer surface. This adjustment is based on the direction and magnitude of the epitaxial layer drift and aims to ensure pattern alignment accuracy during the lithography process, thereby guaranteeing the performance and quality of the final semiconductor device.

[0174] In some embodiments, the alignment parameters of the lithography machine are adjusted based on the drift direction and size of the epitaxial layer on the wafer, including: adjusting the alignment parameters of the lithography machine to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by the length of the epitaxial layer thickness.

[0175] In other words, according to the drift direction and size of the epitaxial layer, the alignment parameters of the lithography machine are adjusted so that the alignment position of the lithography machine is offset in the opposite direction of the epitaxial layer drift, corresponding to the drift amount of the epitaxial layer, thereby compensating for the drift of the epitaxial layer.

[0176] In some embodiments, the isolation lithography position of the wafer is adjusted to correct the drift of the epitaxial layer, including determining that the etching mark of the etched isolation area in the layout used for the upper isolation lithography deviates from the target offset direction by the target offset amount based on the drift direction and size of the epitaxial layer on the wafer when the alignment parameters of the lithography machine performing the upper isolation lithography are in an unadjustable state.

[0177] When performing upper isolation lithography, if the alignment parameters of the lithography machine are not adjustable (that is, the drift of the epitaxial layer cannot be compensated directly by adjusting the alignment of the lithography machine), it is necessary to indirectly compensate for the drift of the epitaxial layer by adjusting the etching marks in the layout design.

[0178] The lithography machine's alignment parameters are not adjustable, which means the lithography machine's alignment system cannot be manually adjusted or dynamically adjusted during the lithography process. Therefore, it is impossible to correct epitaxial layer drift by directly adjusting the lithography machine's alignment position.

[0179] Since the alignment of the lithography machine cannot be adjusted, drift can be indirectly compensated by adjusting the layout design. Specifically, when designing the layout for top isolation lithography, the etch marks (the graphic features used to identify the isolation area) will be adjusted according to the drift of the epitaxial layer.

[0180] Based on the drift direction and size of the epitaxial layer, the etching marks in the layout are shifted in the target offset direction. This is done to align the etching marks with the actual position of the epitaxial layer during the etching process, thus ensuring that the isolation area is finally etched in the correct position.

[0181] This offset is determined by the size of the epitaxial layer drift. For example, if the epitaxial layer drifts by 0.5 microns, the etch marks in the layout also need to be offset by 0.5 microns in the drift direction to compensate for the drift.

[0182] For some lithography machines that don't have adjustable alignment parameters, drift compensation can't be performed on the lithography machine itself. Therefore, in these cases, the solution is to modify the layout design itself to correct the drift. Specifically, during the layout design, the etch marks for the isolation areas are shifted to the left by the same amount as the thickness of the epitaxial layer.

[0183] In this way, although the lithography machine cannot dynamically adjust the alignment, it can compensate for the drift effect through design-level compensation. In this case, the offset of the etched area during design is equivalent to reserving drift in the design, ensuring that drift will not adversely affect the final pattern position during the actual manufacturing process.

[0184] In some embodiments, according to actual offset conditions, the target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the thickness of the epitaxial layer.

[0185] like Figure 2 As shown, after determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift, the manufacturing method of the ER193 type dual differential comparator circuit further includes step 210 , step 220 and step 230 .

[0186] Step 210 , determining to perform base oxidation, base pre-expansion, borosilicate glass removal, and base re-diffusion on the wafer.

[0187] Step 220 , determining to perform emitter region photolithography, emitter region pre-diffusion, phosphosilicate glass removal, and emitter region re-diffusion on the wafer;

[0188] Step 230 , determining to perform lead hole photolithography and metal sputtering on the wafer.

[0189] The base oxidation step forms a thin layer of silicon oxide (SiO2) on the base region of the wafer (usually the silicon substrate). The oxide layer isolates different semiconductor regions, prevents impurity diffusion, and provides a protective layer for subsequent processes.

[0190] Base prediffusion is a process performed beneath the base oxide layer. This process typically involves diffusing dopants (such as boron) into the base region to form a P-type or N-type semiconductor region. This step prepares for the subsequent formation of a PN junction (e.g., the junction between the base and emitter regions).

[0191] Borosilicate glass removal occurs during the diffusion process, where boron silicate glass (BSG) may be used as a diffusion source or isolation material. The purpose of removing the borosilicate glass is to remove unwanted material to ensure that subsequent processes do not interfere with the crystal structure or circuit functionality.

[0192] The base re-diffusion step refers to the re-diffusion of dopants (e.g., boron) after the initial diffusion has been completed to further adjust the conductivity characteristics of the semiconductor region and ensure that the correct electrical region is formed in the wafer.

[0193] During the emitter lithography phase, the location of the emitter region is defined on the wafer surface through a photolithography process. The photolithography process uses a mask and ultraviolet light to transfer the desired pattern onto the wafer's photoresist. This step precisely defines the location of the emitter region on the wafer for subsequent doping and diffusion.

[0194] Emitter pre-diffusion This step involves diffusing dopants (such as phosphorus) into the emitter region to form an N-type semiconductor region (in the case of an NPN transistor). Pre-diffusion is done to ensure that the doping concentration and electrical properties of the emitter region meet the design requirements.

[0195] Phosphosilicate glass is often used as a diffusion source or protective layer. After diffusion, the phosphosilicate glass needs to be removed to avoid affecting subsequent processes or causing uneven wafer surface.

[0196] Similar to base region rediffusion, emitter region rediffusion is to diffuse dopants into the emitter region again to ensure that the dopant concentration in the emitter region reaches the required level and forms an efficient PN junction.

[0197] Via lithography is the process of defining the locations of lead holes on the wafer through a photolithography process. Lead holes are used to connect the metal layers on the wafer to external circuits or leads in the package. This step prepares for subsequent electrical connections.

[0198] Metal sputtering is a physical vapor deposition technique used to deposit thin metal films, such as aluminum or copper, onto wafer surfaces. These metal layers are often used for interconnects in circuits. After metal sputtering, subsequent processing, such as etching, is required to form the metal connections within the circuit.

[0199] Through the above steps, it can be ensured that each area and circuit connection are accurately formed on the wafer, ultimately achieving the expected circuit function.

[0200] Base region oxidation mainly includes the following steps.

[0201] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0202] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0203] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0204] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0205] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0206] Step 6: Heat up for 50 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 50 minutes, the temperature required for the process, 1050°C, is reached.

[0207] Step 7: Dry oxygen for 10 minutes, temperature: 1050℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface, thereby improving the barrier ability to impurities.

[0208] Step 8: Wet oxygen for 45 minutes at 1050°C, with an oxygen flow rate of 7 L / min and a hydrogen flow rate of 10 L / min. Wet oxygen is mainly used to form the required silicon dioxide film thickness to improve production efficiency. If used as a mask for impurity diffusion, its thickness is mainly determined by the junction depth formed by the diffusion and the diffusion temperature. In other words, the time required for diffusion must be determined first, and then the thickness of the oxide film required to block the diffusion of impurities in the silicon dioxide must be determined within this diffusion time.

[0209] Step 9: Dry oxygen for 10 minutes, temperature: 1050℃, oxygen flow rate 8L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the interface between silicon dioxide and silicon, and at the same time dry the silicon dioxide surface and improve the adhesion between silicon dioxide and photoresist.

[0210] Step 10: DCE for 10 minutes at 1050°C, with an oxygen flow rate of 8 L / min. A small amount of nitrogen was used to carry trichloroethylene (DCE) at a flow rate of 0.1 L / min. Chlorine-doped oxidation involves adding a certain amount of chlorine-containing gas, such as HCl or C2HCl3, to the oxidizing atmosphere. Chlorine-doped oxidation is a commonly used oxidation method that reduces sodium ion contamination in silica, inhibits oxide stacking faults, and improves the quality of the oxide film.

[0211] Step 11: Dry oxygen for 10 minutes, temperature: 1050℃, oxygen flow rate 8L / min, most heavy metal atoms react with chlorine to generate volatile gaseous chlorides which are discharged out of the furnace tube to ensure the purity of the oxide layer.

[0212] Step 12: Cool down for 83 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0213] Step 13: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0214] Step 14: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the temperature is still high after leaving the boat, so the chip needs to be cooled down to a certain temperature before it can be removed.

[0215] Step 15: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0216] Step 16: The entire process is completed and the equipment is on standby.

[0217] The base area pre-expansion mainly includes the following steps.

[0218] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0219] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0220] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0221] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0222] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0223] Step 6: Heat up for 27 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 27 minutes, the temperature required for the process reaches 935°C.

[0224] Step 7: Diffusion for 21 minutes to diffuse the impurity source on the boron source sheet to the shallow junction formed on the wafer surface.

[0225] Step 8: Cool down for 45 minutes. After the process is completed, the temperature should be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0226] Step 9: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0227] Step 10: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled to a certain temperature before it can be removed.

[0228] Step 11: After 17 minutes in the boat, when the equipment is in standby mode, place the quartz boat in the furnace tube to keep it clean.

[0229] Step 12: The entire process is completed and the equipment is on standby.

[0230] Borosilicate glass removal: The borosilicate glass film will block diffusion, resulting in the base junction depth being unable to reach, so it needs to be removed here.

[0231] Base region re-diffusion mainly includes the following steps.

[0232] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0233] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0234] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0235] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0236] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0237] Step 6: Heating for 66 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 66 minutes, the temperature required for the process, 1130°C, is reached.

[0238] Step 7: Dry nitrogen for 90 minutes, temperature: 1130℃, nitrogen flow rate 8L / min, 90 minutes to reach the required junction depth of the base area.

[0239] Step 8: Dry oxygen for 5 minutes, temperature: 1130℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface and thus improve the barrier ability to impurities.

[0240] Step 9: Wet oxygen for 10 minutes at 1130°C, with an oxygen flow rate of 7 L / min and a hydrogen flow rate of 10 L / min. Wet oxygen is mainly used to form the required silicon dioxide film thickness to improve production efficiency. If used as a mask for impurity diffusion, its thickness is mainly determined by the junction depth formed by the diffusion and the diffusion temperature. In other words, the time required for diffusion must be determined first, and then the thickness of the oxide film required to block the diffusion of impurities in the silicon dioxide within this diffusion time must be determined.

[0241] Step 10: Dry oxygen for 5 minutes, temperature: 1130℃, oxygen flow rate 8L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the interface between silicon dioxide and silicon, and at the same time dry the silicon dioxide surface and improve the adhesion between silicon dioxide and photoresist.

[0242] Step 12: Cool down for 110 minutes. After the oxidation process is completed, the temperature should be lowered to the equipment standby temperature. Generally, the cooling rate is 3°C / min.

[0243] Step 13: After 15 minutes of unloading, when the temperature drops to the standby temperature, the device starts to unload.

[0244] Step 14: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the temperature is still high after leaving the boat, so the chip needs to be cooled down to a certain temperature before it can be removed.

[0245] Step 15: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0246] Step 16: The entire process is completed and the equipment is on standby.

[0247] The photolithography process of the emission area is HMDS, coating (negative photoresist is used, with a thickness of 19000±2000Å), pre-baking (30min), alignment, development, hardening (30min), wet etching (oxide layer etching: using BOE solution for 10min) and stripping (solvent for 10min).

[0248] The steps of pre-diffusion in the emission region are mainly the following processes.

[0249] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0250] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0251] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0252] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0253] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0254] Step 6: Heating for 46 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 50 minutes, the temperature required for the process, 1030°C, is reached.

[0255] Step 7: Nitrogen and oxygen for 3 minutes, temperature: 1030℃, nitrogen flow rate 6L / min, oxygen flow rate 2L / min.

[0256] Step 8: Open the source for 20 minutes, temperature 1030℃, nitrogen flow rate 6L / min, oxygen flow rate 2L / min, and a small amount of nitrogen carrying phosphorus oxychloride 0.4L / min.

[0257] Step 9: Nitrogen and oxygen for 3 minutes, temperature: 1030℃, nitrogen flow rate 6L / min, oxygen flow rate 2L / min.

[0258] Step 10: Cool down for 77 minutes. The oxidation process is completed and the temperature needs to be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0259] Step 11: After 15 minutes of unloading, the temperature drops to the standby temperature and the equipment starts to unload.

[0260] Step 12: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled down to a certain temperature before it can be removed.

[0261] Step 13: After 17 minutes in the boat, when the equipment is in standby mode, place the quartz boat in the furnace tube to keep it clean.

[0262] Step 14: The entire process is completed and the equipment is on standby.

[0263] Phosphosilicate glass removal: The water absorption of phosphosilicate glass film can cause device failure, so it needs to be removed here.

[0264] The redistribution of the emission area mainly includes the following processes.

[0265] Step 1: Take the quartz boat out of the boat for 15 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube and take it out when it is needed to make slices.

[0266] Step 2: Cool down for 10 minutes. Since the furnace temperature is 800℃, the temperature is still high after leaving the boat. Therefore, the temperature needs to be lowered to a certain level before loading the wafer.

[0267] Step 3: Load the wafer for 10 minutes and load the wafer that needs to be oxidized onto the quartz boat.

[0268] Step 4: Enter the boat for 17 minutes. After loading the wafers, the quartz boat is sent into the furnace tube for processing.

[0269] Step 5: Maintain for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after entering the boat.

[0270] Step 6: Heating for 44 minutes. The temperature of the diffusion furnace increases by 5°C for 1 minute. After 44 minutes, the temperature required for the process, 1020°C, is reached.

[0271] Step 7: Dry oxygen for 5 minutes, temperature: 1020℃, oxygen flow rate 8L / min, in order to obtain a dense silicon dioxide surface, thereby improving the barrier ability to impurities.

[0272] Step 8: Wet oxygen for 11 minutes at 1130°C, with an oxygen flow rate of 7 L / min and a hydrogen flow rate of 10 L / min. Wet oxygen is mainly used to form the required silicon dioxide film thickness to improve production efficiency. If used as a mask for impurity diffusion, its thickness is mainly determined by the junction depth formed by the diffusion and the diffusion temperature. In other words, the time required for diffusion must be determined first, and then the thickness of the oxide film required to block the diffusion of impurities in the silicon dioxide must be determined within this diffusion time.

[0273] Step 9: Dry oxygen for 5 minutes, temperature: 1020℃, oxygen flow rate 8L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the interface between silicon dioxide and silicon, and at the same time dry the silicon dioxide surface and improve the adhesion between silicon dioxide and photoresist.

[0274] Step 10: Cool down for 74 minutes. The oxidation process is completed and the temperature should be lowered to the equipment standby temperature. Generally, the cooling rate is 3℃ / min.

[0275] Step 11: After 15 minutes of unloading, the temperature drops to the standby temperature and the equipment starts to unload.

[0276] Step 12: Cool down for 10 minutes. Since the temperature of the furnace tube is 800℃, the wafer is still in a high temperature state after leaving the boat. Therefore, the wafer needs to be cooled down to a certain temperature before it can be removed.

[0277] Step 13: Put the quartz boat into the furnace tube for 17 minutes. When the equipment is in standby mode, in order to keep it clean, place the quartz boat in the furnace tube.

[0278] Step 14: The entire process is completed and the equipment is on standby.

[0279] The process of lead hole lithography is HMDS, coating (negative photoresist is used, the thickness of the photoresist is 19000±2000Å), pre-baking (30min), alignment, development, hardening (30min), wet etching (oxide layer etching: using BOE solution etching for 10min) and stripping (solvent for 10min).

[0280] During the metal sputtering process, the front metal evaporation parameters are Ti: 1500A, Al: 20000A, and the sheet resistance is 8.95Ω / sq, where Ti plays a bonding role and Al plays a metal lead role.

[0281] The process of front metal reverse etching is HMDS, coating (using negative photoresist with a thickness of 28000±2000Å), pre-baking (30 minutes), alignment, development, hardening (30 minutes), wet etching (metal layer etching: using solution stripping solution for 30 minutes) and plasma stripping (30 minutes).

[0282] The Al alloy process parameters are 400°C, 30 min, gas flow rate nitrogen: 8 L / min, hydrogen 1 L / min, the purpose is to ensure good ohmic contact between the front metal and the silicon wafer surface.

[0283] The passivation layer lithography process is HMDS, coating (using negative photoresist with a thickness of 28000±2000Å), pre-baking (30min), alignment, development, hardening (30min), dry etching (passivation layer etching) and plasma stripping (30min).

[0284] The following describes a manufacturing device for the ER193 dual differential comparator circuit provided by the present invention. The manufacturing device for the ER193 dual differential comparator circuit described below and the manufacturing method for the ER193 dual differential comparator circuit described above can refer to each other.

[0285] An apparatus for manufacturing an ER193 dual differential comparator circuit according to an embodiment of the present invention mainly includes a first processing module 310 , a second processing module 320 , a third processing module 330 and a fourth processing module 340 .

[0286] The first processing module 310 is used to determine whether to remove the surface oxide layer of the wafer after the wafer undergoes the bottom isolation process;

[0287] The second processing module 320 is used to determine whether the wafer forms an epitaxial layer and perform upper isolation oxidation on the wafer;

[0288] The third processing module 330 is used to determine and adjust the isolation lithography position of the wafer to correct the epitaxial layer drift when performing upper isolation lithography;

[0289] The fourth processing module 340 is used to determine whether to perform pre-diffusion and re-diffusion on the wafer after the epitaxial layer drift is corrected, so as to obtain a target circuit on the wafer.

[0290] According to the manufacturing device of the ER193 dual differential comparator circuit of the embodiment of the present invention, by adjusting the isolation lithography position of the wafer, it is ensured that the drift of the epitaxial layer is corrected during the upper isolation lithography process. Even if the epitaxial layer drifts, the lithography pattern can still be accurately formed on the wafer, avoiding poor circuit function or inconsistent electrical performance due to alignment errors.

[0291] An embodiment of the present invention further provides an ER193 dual differential comparator circuit. The ER193 dual differential comparator circuit is manufactured using the manufacturing method of the ER193 dual differential comparator circuit described above.

[0292] Figure 4 An example of a physical structure diagram of an electronic device is shown below. Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other via the communications bus 440. The processor 410 may call logic instructions in the memory 430 to execute a method for manufacturing an ER193 dual differential comparator circuit, which includes: after a wafer undergoes lower isolation processing, determining to remove a surface oxide layer from the wafer; determining to form an epitaxial layer on the wafer and perform upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct for epitaxial layer drift; and determining to perform pre-diffusion and re-diffusion on the wafer after correcting for epitaxial layer drift to obtain a target circuit on the wafer.

[0293] Furthermore, the logic instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0294] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the manufacturing method of the ER193 type dual differential comparator circuit provided by the above methods, the method including: after the wafer is subjected to lower isolation processing, determining to remove the surface oxide layer of the wafer; determining to form an epitaxial layer on the wafer and perform upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; determining to pre-diffusion and re-diffusion of the wafer after the epitaxial layer drift is corrected to obtain the target circuit on the wafer.

[0295] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the manufacturing method of the ER193 type dual differential comparator circuit provided by the above-mentioned methods, the method comprising: after the wafer undergoes lower isolation processing, determining to remove the surface oxide layer of the wafer; determining to form an epitaxial layer on the wafer and perform upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; determining to pre-diffusion and re-diffusion of the wafer after the epitaxial layer drift is corrected to obtain the target circuit on the wafer.

[0296] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0297] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0298] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for manufacturing an ER193 dual differential comparator circuit, characterized in that: include: After the wafer is subjected to lower isolation processing, it is determined that the surface oxide layer of the wafer is removed; Determining that an epitaxial layer is formed on the wafer and performing upper isolation oxidation on the wafer; When performing upper isolation lithography, determining and adjusting the isolation lithography position of the wafer to correct epitaxial layer drift, including: when the alignment parameters of the lithography machine performing the upper isolation lithography are in an adjustable state, adjusting the alignment parameters of the lithography machine based on the drift direction and size of the epitaxial layer on the wafer, and the alignment system of the lithography machine correspondingly adjusting the position of the alignment mark so that the lithography pattern is realigned with the existing structure on the wafer; when the alignment parameters of the lithography machine performing the upper isolation lithography are in an unadjustable state, determining, based on the drift direction and size of the epitaxial layer on the wafer, that the etching mark for etching the isolation area in the layout used for the upper isolation lithography deviates in a target offset direction by a target offset amount, so that during the etching process, the etching mark can be aligned with the actual position of the epitaxial layer, thereby ensuring that the position of the isolation area finally etched is correct; It is determined to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

2. The manufacturing method of the ER193 dual differential comparator circuit according to claim 1, characterized in that: The adjusting the alignment parameters of the lithography machine based on the drift direction and size of the epitaxial layer on the wafer includes: The alignment parameters of the lithography machine are adjusted to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by the length of the thickness of the epitaxial layer.

3. The manufacturing method of the ER193 dual differential comparator circuit according to claim 1, characterized in that: The target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the thickness of the epitaxial layer.

4. The manufacturing method of the ER193 dual differential comparator circuit according to claim 1, characterized in that: After the wafer is subjected to the lower isolation process and before the surface oxide layer of the wafer is removed, the method further includes: Determining to perform buried layer oxidation on the wafer; After the buried layer is oxidized, it is determined that the wafer is subjected to arsenic implantation and arsenic annealing respectively; It is determined to perform lower isolation oxidation, lower isolation photolithography, lower isolation implantation and lower isolation annealing on the wafer respectively.

5. The manufacturing method of the ER193 dual differential comparator circuit according to claim 1, characterized in that: After determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift, the method includes: Determining to perform base oxidation, base pre-expansion, borosilicate glass removal, and base re-diffusion on the wafer; Determining to perform emitter region photolithography, emitter region pre-diffusion, phosphosilicate glass removal, and emitter region re-diffusion on the wafer; Determine to perform lead hole photolithography and metal sputtering on the wafer.

6. A manufacturing device suitable for the manufacturing method of the ER193 type dual differential comparator circuit according to any one of claims 1 to 5, characterized in that: include: The first processing module is used to determine whether to remove the surface oxide layer of the wafer after the wafer undergoes lower isolation processing; A second processing module is used for determining that an epitaxial layer is formed on the wafer and performing upper isolation oxidation on the wafer; a third processing module, configured to determine, when performing upper isolation lithography, to adjust an isolation lithography position of the wafer to correct for drift of the epitaxial layer, the module comprising: when the alignment parameters of the lithography machine performing the upper isolation lithography are in an adjustable state, adjusting the alignment parameters of the lithography machine based on the drift direction and size of the epitaxial layer on the wafer, and causing the alignment system of the lithography machine to correspondingly adjust the position of the alignment mark so that the lithography pattern is realigned with the existing structure on the wafer; and when the alignment parameters of the lithography machine performing the upper isolation lithography are in an unadjustable state, determining, based on the drift direction and size of the epitaxial layer on the wafer, that an etching mark for etching an isolation region in a layout for the upper isolation lithography deviates in a target offset direction by a target offset amount, so that during the etching process, the etching mark can be aligned with the actual position of the epitaxial layer, thereby ensuring that the position of the isolation region finally etched is correct; The fourth processing module is used to determine whether to perform pre-diffusion and re-diffusion on the wafer after the epitaxial layer drift is corrected, so as to obtain a target circuit on the wafer.

7. An ER193 type dual differential comparator circuit, characterized in that: The ER193 dual differential comparator circuit is manufactured using the manufacturing method of the ER193 dual differential comparator circuit according to any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that: When the processor executes the program, the method for manufacturing the ER193 dual differential comparator circuit according to any one of claims 1 to 5 is implemented.

Images