A reverse polarity LED epitaxial wafer with improved leakage current and its preparation method

Abstract

The present invention relates to the field of LED technology, and more specifically to a reverse polarity LED epitaxial wafer with improved leakage and a method for preparing the same. The LED epitaxial wafer comprises, from bottom to top, a GaAs substrate, a buffer layer, a growth corrosion stop layer, an N-type ohmic contact layer, a growth electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-face waveguide layer, a multi-quantum well light-emitting layer, a P-face waveguide layer, a third Zener cladding layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer. The present invention introduces a Zener protection layer between epitaxial functional layers with a high potential barrier difference, which can suppress concentration drift under high current injection, improve reverse voltage withstand capability at high temperatures, and enhance the anti-leakage performance of the reverse polarity LED.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and in particular to a reverse polarity LED epitaxial wafer with improved leakage and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs), with their advantages of low operating voltage, long lifespan, and high luminous efficiency, have been widely used in display screens, general lighting, automotive ambient lighting, plant growth lamps, and other fields. High-brightness red LEDs are manufactured using quaternary AlGaInP materials and employ a reverse-polarity chip structure, achieving very high luminous efficiency. These LEDs play a crucial role in products such as outdoor lighting, automotive headlights, and plant lighting. However, with the diversification of application scenarios and the expansion of operating conditions, existing reverse-polarity LEDs are prone to leakage in high-temperature, high-current environments, severely impacting LED manufacturing yield and the reliability of the final product.

[0003] Conventional quaternary AlGaInP reverse polarity LED, the epitaxial wafer structure diagram is as follows Figure 1 As shown, from bottom to top, it includes a GaAs substrate 100, a buffer layer 101, an etching stop layer 102, an N-type ohmic contact layer 103, an electrode protection layer 104, a roughening layer 105, an N-type confinement layer 106, an N-side waveguide layer 107, a multi-quantum well light-emitting layer 108, a P-side waveguide layer 109, a P-type confinement layer 110, a transition layer 111, and a P-type window layer 112. However, when operating at high temperatures and high currents, conventional quaternary AlGaInP reverse-polarity LEDs experience a gradual decrease in the Zener voltage (VZ) of the PN junction within the LED over time, leading to a decrease in the LED's withstand voltage. When VZ drops to the LED's reverse breakdown threshold, leakage current increases, and in severe cases, the entire LED chip fails and ultimately leaks completely. Furthermore, due to the epitaxial structure and material properties of conventional reverse-polarity LEDs, some epitaxial layers must switch between arsenide and phosphide, leading to incomplete or residual pre-reaction between Group III and Group V sources at the switching interface. Lattice point defects between arsenide and phosphide also exist, which easily proliferate and amplify at high temperatures, ultimately forming leakage channels and increasing leakage. Therefore, improving the leakage performance of reverse-polarity LEDs under harsh environments such as high temperatures and high currents is of great significance. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides a reverse polarity LED epitaxial wafer with improved leakage and a preparation method thereof. The reverse polarity LED epitaxial wafer has good anti-leakage performance and can effectively improve the leakage problem of conventional quaternary AlGaInP reverse polarity LEDs under high temperature and high current operating conditions.

[0005] The first object of the present invention is to provide a reverse polarity LED epitaxial wafer with improved leakage. The LED epitaxial wafer comprises, from bottom to top, a GaAs substrate, a buffer layer, an etching stop layer, an N-type ohmic contact layer, an electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-side waveguide layer, a multi-quantum well light-emitting layer, a P-side waveguide layer, a third Zener protection layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer.

[0006] Furthermore, the material of the first Zener protective layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 The value range of P,x1 is 0.80~0.85, and the thickness is 100nm~130nm; the first Zener protection layer adopts a three-stage doping method of high doping-non-doping-high doping, in which the doping concentration of the high doping stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0007] Furthermore, the material of the second Zener protective layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 The value range of P,x2 is 0.85~0.90, and the thickness is 100nm~130nm; the second Zener protection layer adopts a three-stage doping method of high doping-non-doping-high doping, in which the doping concentration of the high doping stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0008] Furthermore, the material of the third Zener protective layer is (Al x3 Ga 1-x3 ) 0.5 In 0.5 The value range of P,x3 is 0.85-0.90, and the thickness is 100nm-130nm; the third Zener protection layer adopts a three-stage doping method of high doping-non-doping-high doping, wherein the doping concentration of the high doping stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0009] Furthermore, the material of the fourth Zener protective layer is (Alx4 Ga 1-x4 ) 0.5 In 0.5 The value range of P,x4 is 0.80-0.85, and the thickness is 100nm-130nm; the fourth Zener protection layer adopts a three-stage doping method of high doping-non-doping-high doping, wherein the doping concentration of the high doping stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0010] Based on a conventional quaternary AlGaInP reverse-polarity LED structure, the present invention introduces a Zener protective layer (epilayer material with a bandgap between the bands of the two functional layers, with each Zener protective layer doped in a pattern of high doping at the beginning, undoped in the middle, and highly doped at the end) between high-barrier-difference epitaxial functional layers. This structural design prevents leakage caused by carrier diffusion narrowing the space charge region of the PN junction, which in turn leads to a drop in the Zener voltage and a reduction in the reverse bias voltage. The Zener protective layer not only suppresses concentration drift under high-current injection by compromising the bandgap, but also exhibits a three-stage doping elasticity effect, enhancing reverse voltage withstand at high temperatures. It also ensures that the presence of the highly doped layer prevents a rise in forward voltage, thus improving the reverse-polarity LED's anti-leakage performance.

[0011] Furthermore, an arsenic-phosphorus interface pre-reaction compound treatment is performed once after the buffer layer is grown; and a second arsenic-phosphorus interface pre-reaction compound treatment is performed after the N-type ohmic contact layer is grown.

[0012] In this technical solution, the arsenic-phosphorus interface pre-reaction compound treatment is performed after the GaAs material is grown. This can avoid the problems of uneven lattice atoms and lattice defects caused by the deposition of pre-reaction compounds of Ga source and AsH3 on the surface of the epitaxial wafer at the arsenic-phosphorus interface of the grown GaAs and GaInP, thereby eliminating the hidden danger of leakage channels formed by lattice defects at the arsenic-phosphorus interface.

[0013] A second object of the present invention is to provide a method for preparing a reverse polarity LED epitaxial wafer with improved leakage current, comprising growing a buffer layer on a GaAs substrate from bottom to top using MOCVD equipment, then performing a primary arsenic-phosphorus interface pre-reaction compound treatment, growing an etching stop layer and an N-type ohmic contact layer, then performing a secondary arsenic-phosphorus interface pre-reaction compound treatment, and then growing an electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-side waveguide layer, a multi-quantum well light-emitting layer, a P-side waveguide layer, a third Zener protection layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer.

[0014] Furthermore, the steps of the one-time arsenic-phosphorus interface pre-reaction compound treatment are as follows: after the buffer layer is grown, the group III metal source TMGa is turned off, the reaction chamber temperature is set to 750°C~780°C, and the flow rate of the group V source AsH3 is gradually reduced from 400sccm~600sccm to 20sccm~50sccm, with a gradient time of 2min~4min. After the time is up, the temperature is lowered to 700°C~730°C, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the corrosion stop layer GaInP material is grown.

[0015] Furthermore, the steps of the secondary arsenic-phosphorus interface pre-reaction compound treatment are as follows: after the growth of the N-type ohmic contact layer GaAs material, the group III metal source TMGa is turned off, the reaction chamber temperature is set to 750°C~780°C, and the flow rate of the group V source AsH3 is gradually reduced from 400sccm~600sccm to 20sccm~50sccm, and the gradient time is 2min~4min. After the time is reached, the temperature is lowered to 700°C~730°C, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the electrode protection layer GaInP material is grown.

[0016] The present invention introduces an arsenic-phosphorus interface pre-reaction compound volatilization treatment technology after the GaAs material of the buffer layer and the N-type ohmic contact layer is grown. The treatment principle is to make use of the characteristic that As atoms in the As compound material are easily volatile under the action of unsaturated As pressure and high temperature, so as to promote the rapid decomposition of the pre-reaction compound formed by the Ga source residue and AsH3 above the epitaxial wafer into three atoms of Ga, As, and H at high temperature, and carry them out of the MOCVD reaction chamber by means of carrier gas, thereby effectively avoiding the problems of uneven lattice atoms and lattice defects caused by the deposition of the pre-reaction compound of Ga source and AsH3 on the surface of the epitaxial wafer at the arsenic-phosphorus interface of growing GaAs and GaInP.

[0017] Furthermore, the growth step of the first Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the roughened layer, and growing (Al x1 Ga 1-x1 ) 0.5 In 0.5 For P material, the value range of x1 is 0.80-0.85, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm-30nm is highly doped, the middle section with a thickness of 60nm-70nm is non-doped, and the final section with a thickness of 20nm-30nm is highly doped.

[0018] Furthermore, the growth step of the second Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the N-type confinement layer, and growing (Al x2 Ga 1-x2 ) 0.5 In 0.5 For P material, the value range of x2 is 0.85 to 0.90, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm to 30nm is highly doped, the middle section with a thickness of 60nm to 70nm is non-doped, and the final section with a thickness of 20nm to 30nm is highly doped.

[0019] Furthermore, the growth step of the third Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the P-plane waveguide layer, and growing (Al x3 Ga 1-x3 ) 0.5 In 0.5 For P material, the value range of x3 is 0.85 to 0.90, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm to 30nm is highly doped, the middle section with a thickness of 60nm to 70nm is non-doped, and the final section with a thickness of 20nm to 30nm is highly doped.

[0020] Furthermore, the growth step of the fourth Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the P-type confinement layer, and growing (Al x4 Ga 1-x4 ) 0.5 In 0.5 For P material, the value range of x4 is 0.80~0.85, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm~30nm is highly doped, the middle section with a thickness of 60nm~70nm is non-doped, and the final section with a thickness of 20nm~30nm is highly doped.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention introduces first, second, third, and fourth Zener protection layers into a conventional quaternary AlGaInP-based reverse polarity LED structure to prevent leakage caused by a decrease in the Zener voltage due to a narrowing of the space charge region of the PN junction under high-temperature, high-current operating conditions. While improving the reverse voltage withstand capability at high temperatures, the present invention also ensures that the forward voltage does not increase due to the presence of the highly doped layer, thereby improving the anti-leakage performance of the reverse polarity LED.

[0023] 2. The present invention introduces the volatilization treatment technology of the arsenic-phosphorus interface pre-reaction compound after the buffer layer and the N-type ohmic contact layer GaAs material are grown, which can effectively avoid the problems of uneven lattice atoms and lattice defects caused by the deposition of the pre-reaction compound of the Ga source and AsH3 on the surface of the epitaxial wafer at the arsenic-phosphorus interface of the growing GaAs and GaInP, thereby eliminating the hidden danger of leakage channels formed by the lattice defects of the arsenic-phosphorus interface and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the structure of a conventional quaternary AlGaInP reverse polarity LED epitaxial wafer;

[0025] Figure 2 Schematic diagram of the structure of the reverse polarity LED epitaxial wafer of the present invention;

[0026] Figure 3 This is the SEM image of a conventional quaternary AlGaInP reverse polarity LED epitaxial wafer;

[0027] Figure 4 This is the SEM image of the reverse polarity LED epitaxial wafer of the present invention.

[0028] Description of the numbers in the schematic diagram:

[0029] 100. GaAs substrate; 101. buffer layer; 102. corrosion stop layer; 103. N-type ohmic contact layer; 104. electrode protection layer; 105. roughening layer; 106. N-type confinement layer; 107. N-side waveguide layer; 108. multi-quantum well light-emitting layer; 109. P-side waveguide layer; 110. P-type confinement layer; 111. transition layer; 112. P-type window layer; 113. first Zener protection layer; 114. second Zener protection layer; 115. third Zener protection layer; 116. fourth Zener protection layer. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] In the description of this application, it should be understood that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0032] In the description of this application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of this application; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0033] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component can be changed at will, and the component layout may also be more complicated.

[0034] In one embodiment of the present invention, a reverse polarity LED epitaxial wafer with improved leakage current is provided, and its structural schematic diagram is shown as follows: Figure 2 As shown, in accordance with the epitaxial growth sequence, from bottom to top, it includes a GaAs substrate 100, a buffer layer 101, an etching stop layer 102, an N-type ohmic contact layer 103, an electrode protection layer 104, a roughening layer 105, a first Zener protection layer 113, an N-type confinement layer 106, a second Zener protection layer 114, an N-side waveguide layer 107, a multi-quantum well light-emitting layer 108, a P-side waveguide layer 109, a third Zener protection layer 115, a P-type confinement layer 110, a fourth Zener protection layer 116, a transition layer 111, and a P-type window layer 112.

[0035] In some specific embodiments, the buffer layer is made of GaAs, has a thickness of 100 nm to 200 nm, and a doping concentration of 2.0×10 18 cm -3 ~3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0036] In some specific embodiments, after the buffer layer is grown, the group III metal source TMGa is turned off, and at the same time, the flow rate of the group V source AsH3 is gradually reduced from 400sccm to 600sccm to 20sccm to 50sccm, with a gradient time of 2min to 4min, and the temperature of the reaction chamber is set to 750℃ to 780℃. The pre-reaction compound is volatilized under this 2min to 4min. After the time is up, the temperature is set to 700℃ to 730℃, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the corrosion stop layer GaInP material is grown. This treatment method takes advantage of the fact that As atoms in As compound materials are easily volatile under unsaturated As pressure and high temperature. Thus, at high temperature, the pre-reaction compound formed by Ga source residues and AsH3 above the epitaxial wafer is rapidly decomposed into three atoms: Ga, As, and H. The three atoms are then carried out of the MOCVD reaction chamber by means of a carrier gas. This can effectively avoid problems such as uneven lattice atoms and lattice defects at the arsenic-phosphorus interface of the growing GaAs and GaInP due to the deposition of the pre-reaction compound of Ga source and AsH3 on the surface of the epitaxial wafer.

[0037] In some specific embodiments, the material of the corrosion stop layer is Ga 0.5 In 0.5 P, thickness is 50nm~100nm, doping concentration is 1.0×10 18 cm -3 ~3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0038] In some specific embodiments, the material of the N-type ohmic contact layer is GaAs, with a thickness of 40 nm to 80 nm and a doping concentration of 2.0×10 18 cm -3 ~5.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0039] In some specific embodiments, after the N-type ohmic contact layer is grown, the Group III metal source TMGa is turned off, and the flow rate of the Group V source AsH3 is gradually reduced from 400 sccm to 600 sccm to 20 sccm to 50 sccm over a 2-4 minute ramp time. The reaction chamber temperature is set at 750°C to 780°C, and the pre-reaction compound is volatilized over this 2-4 minute period. After the time is up, the temperature is set to 700°C to 730°C, the AsH3 is turned off, and the PH3, TMGa, and TMIn sources are introduced to grow the electrode protection layer GaInP material. This treatment method can also effectively avoid problems such as uneven lattice atoms and lattice defects at the arsenic-phosphorus interface of the growing GaAs and GaInP due to the deposition of the pre-reaction compound of the Ga source and AsH3 on the epitaxial wafer surface.

[0040] In some specific embodiments, the material of the electrode protection layer is Ga 0.5 In 0.5 P, thickness is 100nm~150nm, doping concentration is 2.0×10 18 cm -3 ~5.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0041] In some specific embodiments, the material of the roughening layer is (Al y1 Ga 1-y1 ) 0.5 In 0.5 P, thickness is 2000nm~4000nm, y1 value range is 0.60~0.70, doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0042] In some specific embodiments, the material of the first Zener protection layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 The value range of P,x1 is 0.80~0.85, and the thickness is 100nm~130nm. The doping method of this layer is three-stage, in which the initial stage of 20nm~30nm thickness is highly doped, the middle stage of 60nm~70nm thickness is non-doped, and the final stage of 20nm~30nm thickness is highly doped. The doping concentration of the highly doped stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0043] In some specific embodiments, the material of the N-type confinement layer is Al 0.5 In 0.5 P, thickness is 300nm~500nm, doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0044] In some specific embodiments, the material of the second Zener protection layer is (Al x2 Ga1 -x2 ) 0.5 In 0.5 The value range of P,x2 is 0.85~0.90, and the thickness is 100nm~130nm. The doping method of this layer is three-stage, in which the initial stage of 20nm~30nm thickness is highly doped, the middle stage of 60nm~70nm thickness is non-doped, and the final stage of 20nm~30nm thickness is highly doped. The doping concentration of the highly doped stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0045] In some specific embodiments, the material of the N-side waveguide layer is (Al y2 Ga 1-y2 ) 0.5 In 0.5 P, thickness is 100nm~200nm, the value range of y2 is 0.93~0.95, and this layer is non-doped.

[0046] In some specific embodiments, the multi-quantum well light-emitting layer is a quantum well / quantum barrier structure with 8 to 15 pairs, wherein the materials of the quantum well layer / quantum barrier layer are AlGaInP; specifically, the material of the quantum well layer is (Al y3 Ga 1-y3 ) 0.5 In 0.5 The thickness of the single-layer well is 3nm to 6nm, and the value range of y3 is 0.03 to 0.06; the material of the quantum barrier layer is (Al y4 Ga 1-y4 ) 0.5 In 0.5 The thickness of the single-layer barrier is 8 nm to 10 nm, and the value of y4 ranges from 0.9 to 0.95. The quantum wells / barriers are all undoped.

[0047] In some specific embodiments, the material of the P waveguide layer is (Aly5 Ga 1-y5 ) 0.5 In 0.5 P, thickness is 100nm~200nm, y5 value range is 0.93~0.95, this layer is non-doped.

[0048] In some specific embodiments, the material of the third Zener protection layer is (Al x3 Ga 1-x3 ) 0.5 In 0.5 The value range of P,x3 is 0.85~0.90, and the thickness is 100nm~130nm. The doping method of this layer is three-stage, in which the initial stage of 20nm~30nm thickness is highly doped, the middle stage of 60nm~70nm thickness is non-doped, and the final stage of 20nm~30nm thickness is highly doped. The doping concentration of the highly doped stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0049] In some specific embodiments, the material of the P-type confinement layer is Al 0.5 In 0.5 P, thickness is 300nm~500nm, doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , Cp2Mg is used as the P-type dopant.

[0050] In some specific embodiments, the material of the fourth Zener protection layer is (Al x4 Ga 1-x4 ) 0.5 In 0.5 The value range of P,x4 is 0.80~0.85, and the thickness is 100nm~130nm. The doping method of this layer is three-stage, in which the initial stage of 20nm~30nm thickness is highly doped, the middle stage of 60nm~70nm thickness is non-doped, and the final stage of 20nm~30nm thickness is highly doped. The doping concentration of the highly doped stage is 1×10 18 cm -3 ~2×10 18 cm -3, and both use Cp2Mg as the P-type dopant. The design of the Zener protection layer can prevent the Zener voltage from decreasing due to carrier diffusion in the space charge region of the PN junction when operating at high temperature and high current, which in turn leads to leakage caused by the reduced reverse bias voltage. At the same time, the compromised bandgap width can suppress concentration drift under high current injection. The three-stage doping has a elastic effect, which can improve the reverse voltage withstand capability at high temperature and ensure that the presence of the highly doped layer does not increase the forward voltage, thereby improving the anti-leakage performance of the reverse polarity LED.

[0051] In some specific embodiments, the transition layer material is (Al y6 Ga 1-y6 ) 0.5 In 0.5 P, thickness is 20nm~50nm, dopant is Cp2Mg, doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , the value range of y6 is 0.16~0.40.

[0052] In some specific embodiments, the material of the P-type window layer is GaP, with a thickness of 1000nm to 2000nm and a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 .

[0053] In another embodiment, the present invention also provides a method for preparing a reverse polarity LED epitaxial wafer with improved leakage current, using MOCVD equipment to sequentially grow a buffer layer from bottom to top on a GaAs substrate, then perform a primary arsenic-phosphorus interface pre-reaction compound treatment, grow an etching stop layer, an N-type ohmic contact layer, then perform a secondary arsenic-phosphorus interface pre-reaction compound treatment, and then grow an electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-side waveguide layer, a multi-quantum well light-emitting layer, a P-side waveguide layer, a third Zener protection layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer. Specifically, the method comprises the following steps:

[0054] (1) Growth of buffer layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMGa and AsH3, and grow GaAs material with a thickness of 100nm~200nm, with a doping concentration of 2.0×10 18 cm -3 ~3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0055] (2) Primary arsenic-phosphorus interface pre-reaction compound treatment: After the buffer layer is grown, the III metal source TMGa is turned off, and at the same time, the flow rate of the V source AsH3 is gradually reduced from 400sccm to 600sccm to 20sccm to 50sccm, with a gradient time of 2min to 4min, and the reaction chamber temperature is set to 750℃ to 780℃. The pre-reaction compound volatilization treatment is carried out under this 2min to 4min. After the time is up, the temperature is set to 700℃ to 730℃, AsH3 is turned off, and PH3, TMGa, and TMIn sources are introduced to grow the corrosion stop layer GaInP material.

[0056] (3) Growth of corrosion stop layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMGa, TMIn, and PH3, and grow Ga with a thickness of 50nm~100nm. 0.5 In 0.5 P material, doping concentration is 1.0×10 18 cm -3 ~3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0057] (4) Growth of N-type ohmic contact layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMGa and AsH3, and grow GaAs material with a thickness of 40nm~80nm, with a doping concentration of 2.0×10 18 cm -3 ~5.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0058] (5) Secondary arsenic-phosphorus interface pre-reaction compound treatment: After the N-type ohmic contact layer is grown, the III-metal source TMGa is turned off, and at the same time, the flow rate of the V-source AsH3 is gradually reduced from 400sccm to 600sccm to 20sccm to 50sccm, with a gradient time of 2min to 4min, and the temperature of the reaction chamber is set to 750℃ to 780℃. The pre-reaction compound volatilization treatment is carried out under this 2min to 4min. After the time is up, the temperature is set to 700℃ to 730℃, AsH3 is turned off, and PH3, TMGa, and TMIn sources are introduced to grow the electrode protection layer GaInP material.

[0059] (6) Growth of electrode protective layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMGa, TMIn, and PH3, and grow Ga with a thickness of 100nm~150nm. 0.5 In 0.5 P material, doping concentration is 2.0×10 1 8cm -3 ~5.0×1018 cm -3 , SiH4 is used as the N-type dopant.

[0060] (7) Growth of roughening layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3, and grow a roughening layer with a thickness of 2000nm~4000nm (Al y1 Ga 1-y1 ) 0.5 In 0.5 For P material, the value range of y1 is 0.60~0.70, and the doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0061] (8) Growth of the first Zener protective layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3 into the roughened layer, and grow a (Al2O3) layer with a thickness of 100nm to 130nm. x1 Ga 1-x1 ) 0.5 In 0.5 For P material, the value range of x1 is 0.80-0.85. The doping method of this layer is three-stage, in which the initial stage of 20nm-30nm thickness is highly doped, the middle stage of 60nm-70nm thickness is non-doped, and the final stage of 20nm-30nm thickness is highly doped. The doping concentration of the highly doped stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0062] (9) Growth of N-type confinement layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 300nm~500nm. 0.5 In 0.5 P material, doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0063] (10) Growth of the second Zener protective layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3 into the N-type confinement layer, and grow (Al) with a thickness of 100nm~130nm. x2 Ga 1-x2 )0.5 In 0.5 For P material, the value of x2 ranges from 0.85 to 0.90. The doping method of this layer is three-stage, in which the initial stage of 20nm to 30nm thickness is highly doped, the middle stage of 60nm to 70nm thickness is non-doped, and the final stage of 20nm to 30nm thickness is highly doped. The doping concentration of the highly doped stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0064] (11) Growth of N-side waveguide layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMIn, and PH3, and grow (Al) with a thickness of 100nm~200nm. y2 Ga 1-y2 ) 0.5 In 0.5 P material, the value range of y2 is 0.93~0.95, and this layer is undoped.

[0065] (12) Growth of multi-quantum well light-emitting layer: Set the temperature of the reaction chamber to 700℃±20℃, introduce TMGa, TMAl, TMIn, and PH3, and grow wells and barriers respectively (Al y3 Ga 1-y3 ) 0.5 In 0.5 P、(Al y4 Ga 1-y4 ) 0.5 In 0.5 The material is P. The thickness of the single-layer well is 3nm to 6nm, the value of y3 ranges from 0.03 to 0.06, the thickness of the single-layer barrier is 8nm to 10nm, the value of y4 ranges from 0.9 to 0.95, the number of periods is 8 pairs to 15 pairs, and the quantum wells / quantum barriers are all non-doped.

[0066] (13) Growth of P-side waveguide layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3, and grow (Al) with a thickness of 100nm~200nm. y5 Ga 1-y5 ) 0.5 In 0.5 P material, the value range of y5 is 0.93~0.95, and this layer is undoped.

[0067] (14) Growth of the third Zener protective layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3 into the P-side waveguide layer, and grow (Al) with a thickness of 100nm~130nm. x3 Ga1-x3 ) 0.5 In 0.5 For P material, the value of x3 ranges from 0.85 to 0.90. The doping method of this layer is three-stage, in which the initial stage with a thickness of 20nm to 30nm is highly doped, the middle stage with a thickness of 60nm to 70nm is non-doped, and the final stage with a thickness of 20nm to 30nm is highly doped. The doping concentration of the highly doped stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0068] (15) Growth of P-type confinement layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 300nm~500nm. 0.5 In 0.5 P material, doping concentration is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , Cp2Mg is used as the P-type dopant.

[0069] (16) Growth of the fourth Zener protective layer: Set the reaction chamber temperature to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3 into the P-type confinement layer, and grow (Al) with a thickness of 100nm~130nm. x4 Ga 1-x4 ) 0.5 In 0.5 For P material, the value of x4 ranges from 0.80 to 0.85. The doping method of this layer is three-stage, in which the initial stage of 20nm to 30nm thickness is highly doped, the middle stage of 60nm to 70nm thickness is non-doped, and the final stage of 20nm to 30nm thickness is highly doped. The doping concentration of the highly doped stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0070] (17) Growth of transition layer: Set the temperature of the reaction chamber to 700℃±20℃, introduce TMAl, TMGa, TMIn, and PH3, and grow (Al y6 Ga 1-y6 ) 0.5 In 0.5 P material, the value range of y6 is 0.16~0.40, and the doping concentration is 2×10 18 cm -3~3×10 18 cm -3 , Cp2Mg is used as the P-type dopant.

[0071] (18) Growth of P-type window layer: The reaction chamber temperature was set to 740℃±20℃, TMGa and PH3 were introduced, and GaP material with a thickness of 1000nm to 2000nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 .

[0072] (19) Wafer removal: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110°C, and then the pressure is adjusted to 1000 mbar. The reaction chamber is opened and the epitaxial wafer is removed.

[0073] In order to further illustrate the present invention, the present invention is described in detail below with reference to specific embodiments.

[0074] Example 1

[0075] A method for preparing a reverse polarity LED epitaxial wafer with improved leakage, specifically comprising the following steps:

[0076] (1) The MOCVD was pumped down to 50 mbar in a pure H2 atmosphere, and the reaction chamber temperature was set at 400°C. The N-type GaAs substrate was then transferred to the reaction chamber through a robot transfer bin, and then the temperature was rapidly raised to 700°C and maintained at 700°C for 5 minutes.

[0077] (2) Growth of buffer layer: The reaction chamber temperature was set to 700°C, TMGa and AsH3 were introduced, and GaAs material with a thickness of 200 nm was grown with a doping concentration of 3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0078] (3) Primary arsenic-phosphorus interface pre-reaction compound treatment: After the buffer layer is grown, the group III metal source TMGa is turned off, and the flow rate of the group V source AsH3 is gradually reduced from 600sccm to 50sccm. The gradient time is 4 minutes, and the reaction chamber temperature is set to 780℃. The pre-reaction compound volatilization treatment is carried out under these 4 minutes. After the time is up, the temperature is set to 700℃, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the corrosion stop layer GaInP material is grown.

[0079] (4) Growth of corrosion stop layer: Set the reaction chamber temperature to 700℃, introduce TMGa, TMIn, and PH3, and grow Ga with a thickness of 100nm. 0.5 In0.5 P material, doping concentration is 2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0080] (5) Growth of N-type ohmic contact layer: The reaction chamber temperature was set to 700°C, TMGa and AsH3 were introduced, and GaAs material with a thickness of 40 nm was grown with a doping concentration of 5.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0081] (6) Secondary arsenic-phosphorus interface pre-reaction compound treatment: After the N-type ohmic contact layer is grown, the III-metal source TMGa is turned off, and at the same time, the flow rate of the V-source AsH3 is gradually reduced from 600sccm to 50sccm, with a gradient time of 4 minutes, and the reaction chamber temperature is set to 780℃. The pre-reaction compound volatilization treatment is carried out under these 4 minutes. After the time is up, the temperature is set to 700℃, the AsH3 is turned off, and the PH3, TMGa, and TMIn sources are introduced to grow the electrode protection layer GaInP material.

[0082] (7) Growth of electrode protective layer: Set the reaction chamber temperature to 700℃, introduce TMGa, TMIn, and PH3, and grow Ga with a thickness of 100nm. 0.5 In 0.5 P material, doping concentration is 3.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0083] (8) Growth of roughening layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3, and grow a 3000nm thick (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P material, doping concentration is 2.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0084] (9) Growth of the first Zener protective layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3 on the roughened layer, and grow a 100nm thick (Al 0.85 Ga 0.15 ) 0.5 In 0.5 P material, the doping method of this layer is three-stage, in which the initial 20nm thickness is highly doped, the middle 60nm thickness is non-doped, and the final 20nm thickness is highly doped. The doping concentration of the highly doped section is 2×1018 cm -3 , and both use SiH4 as the N-type dopant.

[0085] (10) Growth of N-type confinement layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 300nm. 0.5 In 0.5 P material, doping concentration is 1.0×10 18 cm -3 , SiH4 is used as the N-type dopant.

[0086] (11) Growth of the second Zener protective layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3 on the N-type confinement layer, and grow a 100nm thick (Al 0.9 Ga 0.1 ) 0.5 In 0.5 P material, the doping method of this layer is three-stage, in which the initial 20nm thickness is highly doped, the middle 60nm thickness is non-doped, and the final 20nm thickness is highly doped. The doping concentration of the highly doped section is 2×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0087] (12) Growth of N-side waveguide layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMIn, and PH3, and grow a 100nm thick (Al 0.95 Ga 0.05 ) 0.5 In 0.5 P material, this layer is undoped.

[0088] (13) Growth of multi-quantum well light-emitting layer: Set the temperature of the reaction chamber to 700℃, introduce TMGa, TMAl, TMIn, and PH3, and grow wells and barriers respectively (Al 0.05 Ga 0.95 ) 0.5 In 0.5 P、(Al 0.95 Ga 0.05 ) 0.5 In 0.5 The material is P. The thickness of a single well is 4 nm, the thickness of a single barrier is 8 nm, the number of periods is 12 pairs, and both quantum wells and quantum barriers are non-doped.

[0089] (14) Growth of P-side waveguide layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3, and grow a 100nm thick (Al 0.95 Ga 0.05 )0.5 In 0.5 P material, this layer is undoped.

[0090] (15) Growth of the third Zener protective layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3 into the P-side waveguide layer, and grow a 100nm thick (Al 0.9 Ga 0.1 ) 0.5 In 0.5 P material, the doping method of this layer is three-stage, in which the initial 20nm thickness is highly doped, the middle 60nm thickness is non-doped, and the final 20nm thickness is highly doped. The doping concentration of the highly doped section is 1×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0091] (16) Growth of P-type confinement layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 300nm. 0.5 In 0.5 P material, doping concentration is 1.0×10 18 cm -3 , Cp2Mg is used as the P-type dopant.

[0092] (17) Growth of the fourth Zener protective layer: Set the reaction chamber temperature to 700℃, introduce TMAl, TMGa, TMIn, and PH3 into the P-type confinement layer, and grow a 100nm thick (Al 0.8 Ga 0.2 ) 0.5 In 0.5 P material, the doping method of this layer is three-stage, in which the initial 20nm thickness is highly doped, the middle 60nm thickness is non-doped, and the final 20nm thickness is highly doped. The doping concentration of the highly doped section is 1×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0093] (18) Growth of transition layer: Set the temperature of the reaction chamber to 700℃, introduce TMAl, TMGa, TMIn, and PH3, and grow (Al 0.19 Ga 0.81 ) 0.5 In 0.5 P material, doping concentration is 3×10 18 cm -3 , Cp2Mg is used as the P-type dopant.

[0094] (19) Growth of P-type window layer: The reaction chamber temperature was set to 760°C, TMGa and PH3 were introduced, and GaP material with a thickness of 2000 nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 5×10 18 cm -3 .

[0095] (20) Wafer removal: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110°C, and then the pressure is adjusted to 1000 mbar. The reaction chamber is opened and the epitaxial wafer is removed.

[0096] Comparative Example 1

[0097] A conventional quaternary AlGaInP reverse polarity LED epitaxial wafer is prepared using conventional methods, and its structural diagram is shown in FIG. Figure 1 shown.

[0098] Test example

[0099] 1. The reverse polarity LED epitaxial wafer obtained in Comparative Example 1 and the reverse polarity LED epitaxial wafer obtained in Example 1 were observed under a scanning electron microscope (magnification of 10,000 times). The results were as follows: Figure 3 and Figure 4 As shown. Figure 3 It can be seen that the conventional quaternary AlGaInP reverse polarity LED epitaxial wafer has lattice defects at the interface (marked by the blue dotted line), which grow and amplify to form leakage channels and cause leakage; Figure 4 The crystal growth quality of the reverse polarity LED epitaxial layer obtained in Example 1 of the present invention is improved, and the epitaxial layer is clear and complete without leakage channels caused by defects.

[0100] 2. The reverse polarity LED obtained in Comparative Example 1 and the reverse polarity LED obtained in Example 1 were tested for leakage current at different high temperatures. The test conditions and results are shown in Table 1, where IR refers to leakage current and VZ refers to Zener voltage.

[0101] Table 1

[0102]

[0103] From the results in Table 1, it can be seen that the conventional quaternary AlGaInP reverse polarity LED sample has a leakage current of 1.405uA at 65°C, and as the temperature rises, the leakage current gradually increases, and finally reaches 5uA at 105°C; while the improved reverse polarity LED of the present invention still guarantees no leakage at 105°C, and the tested leakage current is only 0.003uA, indicating that the anti-leakage performance of the reverse polarity LED prepared by the method of the present invention is greatly improved.

[0104] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A reverse polarity LED epitaxial wafer with improved leakage current, characterized in that: The LED epitaxial wafer includes, from bottom to top, a GaAs substrate, a buffer layer, an etching stop layer, an N-type ohmic contact layer, an electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-side waveguide layer, a multi-quantum well light-emitting layer, a P-side waveguide layer, a third Zener protection layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer; The first Zener protection layer and the second Zener protection layer are both doped in a three-stage doping method of high doping-non-doping-high doping, wherein the doping concentration of the high doping stage is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as N-type dopant; The third Zener protection layer and the fourth Zener protection layer are both doped in a three-stage doping method of high doping-non-doping-high doping, wherein the doping concentration of the high doping stage is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

2. The reverse polarity LED epitaxial wafer with improved leakage according to claim 1, characterized in that: The material of the first Zener protective layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 The value range of P, x1 is 0.80~0.85, and the thickness is 100nm~130nm.

3. The reverse polarity LED epitaxial wafer with improved leakage according to claim 1, characterized in that: The material of the second Zener protective layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 The value range of P,x2 is 0.85~0.90, and the thickness is 100nm~130nm.

4. The reverse polarity LED epitaxial wafer with improved leakage according to claim 1, characterized in that: The material of the third Zener protection layer is (Al x3 Ga 1-x3 ) 0.5 In 0.5 The value range of P,x3 is 0.85~0.90, and the thickness is 100nm~130nm.

5. The reverse polarity LED epitaxial wafer with improved leakage according to claim 1, characterized in that: The material of the fourth Zener protection layer is (Al x4 Ga 1-x4 ) 0.5 In 0.5 The value range of P,x4 is 0.80~0.85, and the thickness is 100nm~130nm.

6. The method for preparing a reverse polarity LED epitaxial wafer with improved leakage according to any one of claims 1 to 5, characterized in that: A buffer layer is grown on a GaAs substrate from bottom to top using MOCVD equipment, and then an arsenic-phosphorus interface pre-reaction compound treatment is performed to grow an etching stop layer and an N-type ohmic contact layer. Then, a secondary arsenic-phosphorus interface pre-reaction compound treatment is performed to grow an electrode protection layer, a roughening layer, a first Zener protection layer, an N-type confinement layer, a second Zener protection layer, an N-side waveguide layer, a multi-quantum well light-emitting layer, a P-side waveguide layer, a third Zener protection layer, a P-type confinement layer, a fourth Zener protection layer, a transition layer, and a P-type window layer.

7. The method for preparing a reverse polarity LED epitaxial wafer with improved leakage according to claim 6, characterized in that: The steps of the one-time arsenic-phosphorus interface pre-reaction compound treatment are as follows: after the buffer layer is grown, the group III metal source TMGa is turned off, the reaction chamber temperature is set to 750°C to 780°C, and the flow rate of the group V source AsH3 is gradually reduced from 400sccm to 600sccm to 20sccm to 50sccm, with a gradient time of 2min to 4min. After the time is up, the temperature is lowered to 700°C to 730°C, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the corrosion stop layer GaInP material is grown.

8. The method for preparing a reverse polarity LED epitaxial wafer with improved leakage according to claim 6, characterized in that: The steps of the secondary arsenic-phosphorus interface pre-reaction compound treatment are as follows: after growing the N-type ohmic contact layer GaAs material, turning off the Group III metal source TMGa, setting the reaction chamber temperature to 750°C to 780°C, and gradually reducing the flow rate of the Group V source AsH3 from 400sccm to 600sccm to 20sccm to 50sccm, with a gradient time of 2min to 4min. After the time is up, the temperature is lowered to 700°C to 730°C, AsH3 is turned off, PH3, TMGa, and TMIn sources are introduced, and the electrode protection layer GaInP material is grown.

9. The method for preparing a reverse polarity LED epitaxial wafer with improved leakage according to claim 6, characterized in that: The growth step of the first Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the roughened layer, and growing (Al x1 Ga 1-x1 ) 0.5 In 0.5 For P material, the value of x1 ranges from 0.80 to 0.85, and a three-stage doping method is used, wherein the initial stage of 20nm to 30nm thickness is highly doped, the middle stage of 60nm to 70nm thickness is non-doped, and the final stage of 20nm to 30nm thickness is highly doped; The growth step of the second Zener protective layer is as follows: setting the reaction chamber temperature to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the N-type confinement layer, and growing (Al) with a thickness of 100nm to 130nm. x2 Ga 1-x2 ) 0.5 In 0.5 For P material, the value range of x2 is 0.85 to 0.90, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm to 30nm is highly doped, the middle section with a thickness of 60nm to 70nm is non-doped, and the final section with a thickness of 20nm to 30nm is highly doped.

10. The method for preparing a reverse polarity LED epitaxial wafer with improved leakage according to claim 6, characterized in that: The growth steps of the third Zener protective layer are as follows: setting the temperature of the reaction chamber to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the P-plane waveguide layer, and growing (Al x3 Ga 1-x3 ) 0.5 In 0.5 For P material, the value of x3 ranges from 0.85 to 0.90, and a three-stage doping method is used, wherein the initial stage of 20nm to 30nm thickness is highly doped, the middle stage of 60nm to 70nm thickness is non-doped, and the final stage of 20nm to 30nm thickness is highly doped; The growth steps of the fourth Zener protective layer are as follows: setting the temperature of the reaction chamber to 700°C ± 20°C, introducing TMAl, TMGa, TMIn, and PH3 on the P-type confinement layer, and growing (Al) with a thickness of 100nm to 130nm. x4 Ga 1-x4 ) 0.5 In 0.5 For P material, the value range of x4 is 0.80~0.85, and a three-stage doping method is adopted, in which the initial section with a thickness of 20nm~30nm is highly doped, the middle section with a thickness of 60nm~70nm is non-doped, and the final section with a thickness of 20nm~30nm is highly doped.

Images